TWI734455B - 多晶片封裝件及其製造方法 - Google Patents

多晶片封裝件及其製造方法 Download PDF

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TWI734455B
TWI734455B TW109114287A TW109114287A TWI734455B TW I734455 B TWI734455 B TW I734455B TW 109114287 A TW109114287 A TW 109114287A TW 109114287 A TW109114287 A TW 109114287A TW I734455 B TWI734455 B TW I734455B
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Taiwan
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interposer
connection conductor
chip
semiconductor
chip package
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TW109114287A
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TW202115836A (zh
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陳昭蓉
林育民
吳昇財
黃馨儀
林昂櫻
倪梓瑄
羅元听
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財團法人工業技術研究院
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Priority to TW109114287A priority Critical patent/TWI734455B/zh
Priority to US17/005,310 priority patent/US11424190B2/en
Publication of TW202115836A publication Critical patent/TW202115836A/zh
Priority to CN202110417910.XA priority patent/CN113571496A/zh
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Publication of TWI734455B publication Critical patent/TWI734455B/zh

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    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

一種多晶片封裝件及其製造方法。多晶片封裝件包括：中介層，包括介電主體、被所述介電主體隔開的多個半導體主體、貫穿所述介電主體的貫穿通路以及位於所述多個半導體主體中的每一者中的佈線結構；多個半導體晶片，並排地位於所述中介層的第一表面上且電性連接至所述佈線結構；包封體，位於所述中介層的所述第一表面上且包封所述多個半導體晶片的至少部分；以及重配置線路結構，位於所述中介層的第二表面上，所述中介層的所述第二表面與所述中介層的所述第一表面相對，所述重配置線路結構通過所述貫穿通路電性連接至所述多個半導體晶片。

Description

多晶片封裝件及其製造方法
本發明是有關於一種半導體封裝件及其製造方法，且特別是有關於一種多晶片封裝件及其製造方法。
為了使半導體封裝件同時具有輕薄體積以及高性能，目前的封裝技術已嘗試將多個半導體晶片整合於單一半導體封裝件中而形成多晶片封裝件或是以3維堆疊技術堆疊多個半導體封裝件而形成堆疊式封裝件（Package on package，PoP）或系統級封裝件（System in Package）。然而，現有的多晶片封裝件中的多個半導體晶片之間的訊號溝通速度受限，因此半導體封裝件的整體效能仍有待進一步的提升。
本發明之目的係提供一種效能良好的多晶片封裝件。
本發明提供一種多晶片封裝件，包括中介層、多個半導體晶片、包封體及重配置線路結構。所述中介層包括介電主體、被所述介電主體隔開的多個半導體主體、貫穿所述介電主體的貫穿通路以及位於所述多個半導體主體中的每一者中的佈線結構。所述多個半導體晶片並排地位於所述中介層的第一表面上且電性連接至所述佈線結構。所述包封體位於所述中介層的所述第一表面上且包封所述多個半導體晶片的至少部分。所述重配置線路結構位於所述中介層的第二表面上且通過所述貫穿通路電性連接至所述多個半導體晶片，所述中介層的所述第二表面與所述中介層的所述第一表面相對。
本發明提供一種多晶片封裝件，包括中介層、多個半導體晶片及重配置線路結構。所述中介層包括介電主體、半導體主體、貫穿所述介電主體的貫穿通路以及位於所述半導體主體中的佈線結構，所述貫穿通路與所述佈線結構彼此間隔開。所述多個半導體晶片並排地位於所述中介層的第一表面上且所述多個半導體晶片中的每一者同時電性連接至所述佈線結構與所述貫穿通路。所述重配置線路結構位於所述中介層的第二表面上且與所述貫穿通路電性連接，所述中介層的所述第二表面與所述中介層的所述第一表面相對。
本發明提供一種製造多晶片封裝件的方法，包括以下步驟。於半導體基底的第一表面上提供多個半導體晶片以使所述多個半導體晶片中的每一者電性連接至所述半導體基底中的佈線結構。於所述半導體基底的所述第一表面上形成包封體以包封所述多個半導體晶片。從所述半導體基底的與所述第一表面相對的第二表面移除所述半導體基底的至少部分以使所述半導體基底的剩餘部分彼此隔開。在所述半導體基底移除後產生的空間形成介電主體。在所述介電主體中形成貫穿所述介電主體且連接至所述多個半導體晶片的貫穿通路。在所述半導體基底的所述剩餘部分及所述介電主體上形成重配置線路結構，所述重配置線路結構電性連接至所述貫穿通路。
基於上述，本發明的多晶片封裝件可提升多晶片封裝件的整體效能。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
下文列舉實施例並配合所附圖式來進行詳細地說明，但所提供之實施例並非用以限制本發明所涵蓋的範圍。此外，圖式僅以說明為目的，並未依照原尺寸作圖，且可能放大或縮小不同的膜層或區域來顯示於單一圖式中。而且，雖然文中使用如「第一」、「第二」等來描述不同的元件、區域及/或構件，但是這些元件、區域及/或構件不應當受限於這些用語。而是，這些用語僅用於區別一元件、區域或構件與另一元件、區域或構件。因此，以下所討論之第一元件、區域或構件可以被稱為第二元件、區域或構件而不違背實施例的教示。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。
在本文中，參照附圖定義諸如「上」及「下」的空間相對用語。因此，應該理解，用語「上表面」可與術語「下表面」互換使用，並且當諸如層或膜的元件被描述為配置在另一個元件上時，所述元件可直接放置在另一個元件上，或者在這兩個元件間可存在中介元件。另一方面，當一個元件被描述為直接配置在另一個元件上時，這兩個元件間之間沒有中介元件。類似地，當元件被描述為與另一個元件連接或接合時，所述元件可與另一個元件直接連接或直接接合，或者在這兩個元件間可存在中介元件。另一方面，當一個元件被描述為與另一個元件直接連接或直接接合時，這兩個元件間之間沒有中介元件。
圖1是繪示根據本發明的一實施例的多晶片封裝件的剖面示意圖。圖2是沿圖1的多晶片封裝件的剖線I-I’的平面示意圖。
參照圖1，根據本發明的一實施例的多晶片封裝件100包括中介層150、在中介層150的第一表面150A上的半導體晶片120以及在中介層150的與第一表面150A相對的第二表面150B上的重配置線路結構110。參照圖2，中介層150的主體可由介電主體150R以及被介電主體150R隔開的多個半導體主體150S組成。介電主體150R中形成有貫穿介電主體150R的貫穿通路153。半導體主體150S中形成有佈線結構150W。佈線結構150W可用於在並排的半導體晶片120間傳輸訊號，尤其是高頻寬訊號。貫穿通路153可作為在半導體晶片120與重配置佈線結構110之間的接地路徑或電源路徑以用於傳輸大電流。
在目前的系統級封裝件（System in Package）中，使用重配置線路結構傳輸並排的半導體晶片間的訊號。然而，隨著高效能運算應用的增加，對於高頻寬訊號的傳輸需求也在不斷提高。重配置線路結構受限於線寬線距與有機介電層曝光顯影能力，聯線用層數並不多，因此仍需要具有更高線路密度的連接結構以滿足例如高頻寬記憶體(High Bandwidth Memory，HBM)的頻寬要求。本發明的多晶片封裝件藉由使用相較於重配置佈線結構具有更高線路密度（即更小的線寬線距與更多層數）的佈線結構150W來傳輸半導體晶片120之間的訊號以實現更快的訊號傳輸。
舉例而言，重配置線路結構的層數一般為3層，且重配置線路結構的線寬大小一般約為2微米，線距大小一般約為2微米，通路（via）的大小一般約為2微米，而根據本發明的多晶片封裝件中的佈線結構150W的層數可為4層以上，且其線寬大小可介於約0.01微米至1微米（例如約0.2微米、約0.4微米、約0.6微米或約0.8微米）的範圍內，其線距大小可介於約0.01微米至1微米（例如約0.2微米、約0.4微米、約0.6微米或約0.8微米）的範圍，其通路（via）大小可介於約0.01微米至1微米（例如約0.2微米、約0.4微米、約0.6微米或約0.8微米）的範圍。由於本發明的多晶片封裝件中使用線寬小於或等於1微米的佈線結構150W連接半導體晶片120，因此，可在不同的半導體晶片120間進行高頻寬的訊號傳輸。
此外，根據本發明的多晶片封裝件中的中介層150由介電主體150R與半導體主體150S組成，而貫穿通路153形成於介電主體150R中，因此根據本發明的多晶片封裝件的中介層150可省去矽穿孔而降低成本並提高良率。
詳言之，中介層150的主體可由介電主體150R以及被介電主體150R隔開的多個半導體主體150S組成。多個半導體主體150S可彼此實體隔開。半導體主體150S的材料可例如為矽（Si）、鍺（Ge）、砷化鎵（GaAs）等半導體材料。介電主體150R的材料可包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、雙馬來醯亞胺-三氮雜苯樹脂(Bismaleimide-trazine resin，BT resin)或任何其他合適的聚合物系介電材料以及氧化矽層、氮化矽層、氮氧化矽層或其他合適的矽介電材料。在一些實施例中，介電主體150R的材料可包括感光性絕緣樹脂。介電主體150R與半導體主體150S間的界面可不垂直於中介層150的表面。舉例來說，半導體主體150S的側壁與第二表面150B間的夾角α可大於90°。換句話說，半導體主體150S的寬度隨著與半導體晶片120的距離增大而減小，介電主體150R的寬度隨著與半導體晶片120的距離增大而增大。但本說明書不以此為限，舉例來說，介電主體150R與半導體主體150S間的界面也可垂直於中介層150的表面。當用於本文時，「寬度」是指所描述的部件在根據本發明的多晶片封裝件的縱剖面示意圖（如圖1）中在水平方向上的長度。
半導體主體150S中形成有佈線結構150W。佈線結構150W可用於在半導體晶片120間傳輸訊號，尤其是高頻寬訊號。佈線結構150W的材料可包括例如銅（Cu）、銀（Ag）、鈀（Pd）、鋁（Al）、鎳（Ni）、鈦（Ti）、金（Au）、鉑（Pt）、鎢（W）或其合金等導電材料或其他電特性優異的金屬或其合金。如上所述，佈線結構150W具有高線路密度。在一些實施例中，佈線結構150W的層數可為例如4層以上的多層，且其線寬大小可介於約0.01微米至1微米（例如約0.2微米、約0.4微米、約0.6微米或約0.8微米）的範圍內，其線距大小可介於約0.01微米至1微米（例如約0.2微米、約0.4微米、約0.6微米或約0.8微米）的範圍，其通路（via）大小可介於約0.01微米至1微米（例如約0.2微米、約0.4微米、約0.6微米或約0.8微米）的範圍。
介電主體150R中形成有貫穿第一表面150A與第二表面150B的貫穿通路153。貫穿通路153的材料可包括銅（Cu）、銀（Ag）、鈀（Pd）、鋁（Al）、鎳（Ni）、鈦（Ti）、金（Au）、鉑（Pt）、鎢（W）或其合金等導電材料。貫穿通路153可用於使半導體晶片120與重配置線路結構110彼此連接。貫穿通路153的上部寬度可小於下部寬度。也就是說，貫穿通路153的寬度隨著與半導體晶片120的距離增大而增加。由於貫穿通路153形成於介電主體150R中，因此本發明的多晶片封裝件100可省去形成矽穿孔的製程而降低成本並提高良率。
在中介層150的第一表面150A上形成有中介層連接導體150P。中介層連接導體150P連接至中介層150的佈線結構150W及貫穿通路153。中介層連接導體150P可用於將中介層150連接至其他裝置。中介層連接導體150P的材料可包括例如銅（Cu）、銀（Ag）、鈀（Pd）、鋁（Al）、鎳（Ni）、鈦（Ti）、金（Au）、鉑（Pt）、鎢（W）或其合金等導電材料或其他電特性優異的金屬或其合金。中介層連接導體150P的形狀可包括柱狀或圖釘狀凸塊（Stud bump）等各種形狀。中介層連接導體150P可具有不同的大小。舉例而言，中介層連接導體150P可包括大小較大的第一中介層連接導體150P1與大小較小的第二中介層連接導體150P2。也就是說，第一中介層連接導體150P1的寬度DA 大於第二中介層連接導體150P2的寬度DB 。較大的第一中介層連接導體150P1可連接至中介層150的貫穿通路153，且較小的第二中介層連接導體150P2可連接至佈線結構150W。在其他的實施例中，中介層連接導體150P可具有相同的大小。
半導體晶片120可為任何合適的積體電路（IC）晶片，例如記憶體晶片、邏輯晶片、數位晶片、類比晶片、感測器晶片（sensor chip）、人工智慧晶片（AI chip）、無線射頻晶片（wireless and radio frequency chip）或電壓調節器晶片等。其中感測器晶片可為影像感測器晶片，至少包括電荷耦合元件（CCD）或互補金氧半導體影像感測器(CMOS image sensor)。雖然在圖1的多晶片封裝件100中包括兩個半導體晶片120，但本發明不限於此。舉例而言，本發明的多晶片封裝件可包括三個或多於三個半導體晶片。
半導體晶片120在主動面上具有晶片連接導體120P。晶片連接導體120P的材料可包括例如銅（Cu）、銀（Ag）、鈀（Pd）、鋁（Al）、鎳（Ni）、鈦（Ti）、金（Au）、鉑（Pt）、鎢（W）或其合金等導電材料或其他電特性優異的金屬或其合金。晶片連接導體120P的形狀可包括柱狀或圖釘狀凸塊（Stud bump）等各種形狀。晶片連接導體120P可具有不同的大小。舉例而言，晶片連接導體120P可包括大小較大的第一晶片連接導體120P1與大小較小的第二晶片連接導體120P2。也就是說，第一晶片連接導體120P1的寬度D1 大於第二晶片連接導體120P2的寬度D2 。晶片連接導體120P與至少一部分的中介層連接導體150P彼此接合。在一些實施例中，彼此相應地接合的晶片連接導體120P與中介層連接導體150P可具有相應的大小。舉例來說，較大的第一晶片連接導體120P1可接合到較大的第一中介層連接導體150P1，較小的第二晶片連接導體120P2可接合到較小的第二中介層連接導體150P2。在這種情況下，較大的第一晶片連接導體120P1與第一中介層連接導體150P2可用於傳輸大電流（例如接地），而較小的第二晶片連接導體120P2與第二中介層連接導體150P2可用於傳輸高頻寬訊號。晶片連接導體120P與中介層連接導體150P的接合面可為無焊料接合面。由於中介層150與半導體晶片120是經由晶片連接導體120P與中介層連接導體150P而非重配置線路結構彼此連接，因此可縮短中介層150與半導體晶片120之間的電源及/或訊號的傳遞路徑，而提高電源及/或訊號的傳遞速度與品質。在一些實施例中，晶片連接導體120P與中介層連接導體150P可使用諸如Cu/Sn、Cu/Ni/Sn、Cu/Ni/SnBi等焊錫合金的焊料接合。在一些實施例中，晶片連接導體120P與中介層連接導體150P之間可進一步包括凸塊（如圖4B所示）。
另外，並排的多個半導體晶片120可經由中介層150中的佈線結構150W而彼此連接。如上所述，佈線結構150W具有小於或等於1微米的線寬，佈線結構150W可在半導體晶片120之間進行高頻寬訊號的傳輸。另外，視所欲傳輸的訊號或電流而定，需要較快傳輸速度的高頻寬訊號可經由第二晶片連接導體120P2、第二中介層連接導體150P2與佈線結構150W傳輸，而其他訊號或接地可經由第一晶片連接導體120P1、第一中介層連接導體150P1、貫穿通路153與重配置佈線結構110傳輸。也就是說，在本發明的多晶片封裝件100中，半導體晶片120間的訊號傳輸可視訊號的性質而定而經由不同的路徑傳輸。
根據本發明的多晶片封裝件100在半導體晶片120與中介層150之間可包括底膠（Underfill）170。底膠170可填充半導體晶片120與中介層150之間的空間並包封中介層連接導體150P與晶片連接導體120P。底膠170具有傾斜側壁，且底膠170的上部寬度會小於底膠170的下部寬度。在一些實施例中，底膠170的寬度是漸變的，且底膠170的寬度從較靠近中介層150的一端朝著較靠近半導體晶片120的另一端逐漸縮減。底膠170的材料沒有特別限制，且例如可為環氧樹脂等絕緣材料。在其他實施例中，根據本發明的多晶片封裝件100在半導體晶片120與中介層150之間也可以保護層175取代底膠170（參見圖5B）。
根據本發明的多晶片封裝件100在中介層150上可包括包封體（encapsulant）180以包封半導體晶片120與中介層150。包封體180的材料可包括模塑化合物、模塑底部填料、樹脂或環氧模製化合物（epoxy molding compound，EMC）等。視需要，包封體180中可摻雜有無機填料。包封體180的側壁、中介層150的側壁與重配置線路結構110的側壁可彼此對準。
重配置線路結構110位於中介層150的第二表面150B上且可用於將半導體晶片120的輸出輸入端子重佈線。舉例而言，重配置線路結構110可用於扇出（fan-out）半導體晶片120的輸出輸入端子以連接半導體晶片120與印刷線路板（PCB）（未繪示）。重配置線路結構110包括多個重配置介電層114與多個嵌置於重配置介電層114中且連接至貫穿通路153的重配置佈線層116。重配置介電層114的材料可包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、雙馬來醯亞胺-三氮雜苯樹脂(Bismaleimide-trazine resin，BT resin)或任何其他合適的聚合物系介電材料以及氧化矽層、氮化矽層、氮氧化矽層或其他合適的矽介電材料。在一些實施例中，重配置介電層114的材料可包括感光性絕緣樹脂。重配置佈線層116的材料可包括銅（Cu）、銀（Ag）、鈀（Pd）、鋁（Al）、鎳（Ni）、鈦（Ti）、金（Au）、鉑（Pt）、鎢（W）或其合金等導電材料。
重配置線路結構110可更包括重配置通路118，重配置通路118可用於連接位於不同層的重配置佈線層116。重配置通路118的材料可包括銅（Cu）、銀（Ag）、鈀（Pd）、鋁（Al）、鎳（Ni）、鈦（Ti）、金（Au）、鉑（Pt）、鎢（W）或其合金等導電材料。重配置通路118的上部寬度W1 可小於重配置通路118的下部寬度W2 。也就是說，重配置通路118的傾斜側壁與重配置介電層114的下表面間的夾角β可大於90°。
雖然圖1中的重配置線路結構110繪示為包括三層重配置介電層114與三層重配置佈線層116，但本發明不限於此。根據本發明的多晶片封裝件100可包括比圖中所示更多或更少層數的重配置介電層114與重配置佈線層116。
根據本發明的多晶片封裝件100可更包括導電端子190。導電端子190部分地嵌置於最下重配置介電層114中以連接至最下重配置佈線層116。導電端子190可用於將多晶片封裝件100與例如印刷電路板等外部裝置連接。導電端子190可例如為焊球，但本發明不限於此。
在根據本發明的多晶片封裝件100中，並排的多個半導體晶片120可藉由具有高密度與高層數的佈線結構150W彼此連接而實現高效率的訊號傳遞。此外，根據本發明的多晶片封裝件100也提供用於傳輸高電流的其他電性路徑，以提高本發明的多晶片封裝件100的可靠性。同時，根據本發明的多晶片封裝件100可藉由重配置線路結構110對半導體晶片120重佈線而實現扇出型封裝。
圖3A至圖3H是根據本發明的一實施例的製造多晶片封裝件的製造流程步驟的剖面示意圖。圖4A及圖4B是繪示根據本發明的一實施例的接合晶片的方法的剖面示意圖。圖5A及圖5B是繪示依照本發明的另一實施例的接合晶片的方法的剖面示意圖。
參照圖3A，提供具有佈線結構150W的半導體基底15。半導體基底15可例如為矽基底。雖然在圖式中僅繪示使用半導體基底15形成一個多晶片封裝件的製程，但在一些實施例中，可使用具有大尺寸的半導體基底15以同時形成多個多晶片封裝件。舉例而言，可使用矽晶圓或面板級矽基底作為半導體基底15。半導體基底15在第一表面150A上具有中介層連接導體150P，中介層連接導體150P與佈線結構150W電性連接。中介層連接導體150P包括具有不同大小的第一中介層連接導體150P1與第二中介層連接導體150P2。也就是說，第一中介層連接導體150P1的寬度DA 可大於第二中介層連接導體150P2的寬度DB 。
參照圖3B，提供多個半導體晶片120至半導體基底15上以使晶片連接導體120P與中介層連接導體150P彼此接合。晶片連接導體120P包括具有不同大小的第一晶片連接導體120P1與第二晶片連接導體120P2。也就是說，第一晶片連接導體120P1的寬度D1 可大於第二晶片連接導體120P2的寬度D2 。在一些實施例中，大小較大的第一晶片連接導體120P1與第一中介層連接導體150P1彼此接合，大小較小的第二晶片連接導體120P2與第二中介層連接導體150P2彼此接合。晶片連接導體120P與中介層連接導體150P的接合方法可例如為藉由加熱及/或壓力而直接接合。在晶片連接導體120P與中介層連接導體150P接合之後，可在半導體基底15上施加底膠170以包封晶片連接導體120P與中介層連接導體150P。
在一些實施例中，晶片連接導體120P與中介層連接導體150P可藉由凸塊彼此接合。參見圖4A，可在中介層連接導體150P上形成第一凸塊155並在晶片連接導體120P上形成第二凸塊165。接著再利用熱能及/或壓力將第一凸塊155與第二凸塊165接合。第一凸塊155與第二凸塊165的材料可例如為焊錫合金（如Cu/Sn、Cu/Ni/Sn、Cu/Ni/SnBi）、銅、金、銀、銦、鈀、鈦、錳、鈷、或其合金（如Ni/Au、Cu/Ni/Au、Cu/Ni/In）等接合金屬。第一凸塊155與第二凸塊165的材料可彼此不同。舉例而言，第一凸塊155的材料可為經表面處理的純銅、Ni/Au合金、Cu/Ni/Au合金或Cu/Ni/In合金等且第二凸塊165的材料可為Cu/Sn、Cu/Ni/Sn或Cu/Ni/SnBi合金等。在一些實施例中，第一凸塊155與第二凸塊165的材料不含焊錫成分。在一些實施例中，第一凸塊155與第二凸塊165的材料可為熔點低於200℃的低溫接合金屬。舉例來說，低溫接合金屬可包括雙晶銅、雙晶銀或其他奈米雙晶材料、銦錫合金、錫鉍合金、多孔金或其組合。相對於傳統焊球或焊料所需回焊溫度多高於或等於250℃，使用低溫接合金屬可在相對較低的加熱溫度下（例如，在低於200℃或低於150℃的溫度下）使得連接結構達到穩定接合，且滿足電性連接要求的可靠度要求。在一些實施例中，可僅形成第一凸塊155與第二凸塊165中的一者。舉例來說，可僅在中介層連接導體150P上形成第一凸塊155並將第一凸塊155與晶片連接導體120P接合。
接著參見圖4B，在第一凸塊155與第二凸塊165接合之後，可在半導體基底15上施加底膠170以包封晶片連接導體120P、中介層連接導體150P、第一凸塊155與第二凸塊165。底膠170可填充半導體晶片120與半導體基底15之間的空間並包封中介層連接導體150P、晶片連接導體120P、第一凸塊155與第二凸塊165。
參照圖5A及圖5B，在一些實施例中，可在半導體晶片120上形成保護層175。保護層175的材料可為例如樹脂、非導電性膠膜、介電材料等有機材料。晶片連接導體120P的表面與半導體晶片120之間的保護層175的表面可共面。當晶片連接導體120P與中介層連接導體150P彼此接合時，由於晶片連接導體120P被保護層175包封而只有表面露出進行連接，因此可避免受到外力衝擊而受損，如此一來，可提高良率。
返回參照圖3C，在半導體基底15上形成包封體180。形成包封體180的方法包括以下步驟。通過合適的製程（例如模塑製程或沉積製程）在半導體基底15之上形成覆蓋半導體基底15與半導體晶片120的包封材料層，此後，執行表面研磨拋光製程（grinding）或者表面平坦化製程（surface planarization）使得半導體晶片120的上表面暴露出來。
接著共同參照圖3C與圖3D，將圖3C所得的結構上下倒置，並對半導體基底15的背面進行例如研磨製程或蝕刻製程等減薄製程以減小半導體基底15的厚度。使半導體基底15的厚度減小的目的在於使最終多晶片封裝件小型化及薄型化。此外，半導體基底15的厚度減小亦有助於接下來的介電主體150R的形成。視需要，可省略此步驟。
參照圖3E，藉由例如蝕刻製程移除部分的半導體基底15，以形成彼此實體隔開的多個半導體主體150S並暴露出部分的中介層連接導體150P、底膠170、及/或包封體180。至少一個半導體主體150S在與第一表面150A垂直的方向上同時交疊至少2個半導體晶片120的至少部分以同時連接到所述至少2個半導體晶片120。其他半導體主體150S在與第一表面150A垂直的方向上可不與半導體晶片120交疊。在一些實施例中，其他半導體主體150S在與第一表面150A垂直的方向上可與半導體晶片120部分交疊，但半導體主體150S中的每一者是彼此實體間隔開的。
參照圖3F，介電主體150R可利用例如旋轉塗佈等任何合適的方式形成於包封體180上的半導體主體150S之間。介電主體150R可形成超過半導體主體150S的第二表面150B，接著再利用平坦化製程移除部分介電主體150R，以使介電主體150R的表面與半導體主體150S的表面實質上共面而完成中介層150的主體的製備。接著，可在介電主體150R中形成貫穿通路153及在中介層150的第二表面150B上形成重配置佈線層116。首先，在介電主體150R中形成貫穿中介層的第二表面150B與第一表面150A的貫穿通路孔洞以暴露出中介層連接導體150P，其中於介電主體150R中形成通路孔洞的方法可取決於介電主體150R的材料而採用不同的製程。當介電主體150R為包括感光性絕緣樹脂的感光性絕緣層時，介電主體150R可藉由微影製程進行圖案化以形成貫穿通路孔洞。當介電主體150R為非感光性絕緣層時，可藉由微影/蝕刻製程、雷射鑽孔製程或機械鑽孔製程在介電主體150R中形成貫穿通路孔洞。重配置佈線層116與貫穿通路153可整合地形成。舉例而言，形成重配置佈線層116與貫穿通路153的製程包括以下步驟。首先在中介層150的第二表面150B與貫穿通路孔洞的表面上濺鍍或沉積晶種層，其中晶種層的材料可例如為鈦/銅等導電材料。接著，於晶種層上形成圖案化光阻層以暴露出晶種層。藉由電鍍製程於被圖案化光阻層所暴露出的晶種層上形成導電材料，所述導電材料可包括銅（Cu）、銀（Ag）、鈀（Pd）、鋁（Al）、鎳（Ni）、鈦（Ti）、金（Au）、鉑（Pt）、鎢（W）或其合金。接著，移除光阻層以及未被導電材料所覆蓋的部分晶種層而形成重配置佈線層116與貫穿通路153。
參照圖3G，可在重配置佈線層116上與貫穿通路153上以與形成介電主體150R類似的方法形成重配置介電層114，從而形成重配置線路結構(redistribution circuit structure)110。
重配置線路結構110可包括多層或單層重配置佈線層116。當重配置線路結構110包括多層重配置佈線層116時，形成上層之重配置佈線層116的製程包括以下步驟。首先，在重配置介電層114中形成通路孔洞以暴露出其下之重配置佈線層116，其中於重配置介電層114中形成通路孔洞的方法可取決於重配置介電層114的材料而採用不同的製程。當重配置介電層114為包括感光性絕緣樹脂的感光性絕緣層時，重配置介電層114可藉由微影製程進行圖案化以形成通路孔洞。當重配置介電層114為非感光性絕緣層時，重配置介電層114可藉由微影/蝕刻製程、雷射鑽孔製程或機械鑽孔製程進行圖案化以形成通路孔洞。接著以與上述形成重配置佈線層116的方法相同的方法形成上層之重配置佈線層116與填充通路孔洞的重配置通路118以連接到經由通路孔洞所暴露出的重配置佈線層116。雖然在圖式中，重配置線路結構110繪示為包括三層重配置介電層114與三層重配置佈線層116，但本發明不以此為限，重配置線路結構110可包括較圖式更多層或更少層的重配置介電層114與重配置佈線層116。
參照圖3H，可在重配置線路結構110上形成多個導電端子190而完成如圖1所示的本發明的多晶片封裝件100。可使用大尺寸的半導體基底15同時形成多個本發明的多晶片封裝件100，接著，再藉由切割等製程以分離個別多晶片封裝件100。因此本發明的多晶片封裝件100中的中介層150的側壁、包封體180的側壁可與重配置線路結構110的側壁對準。
綜上所述，本發明提供一種多晶片封裝件及其製造方法。本發明的多晶片封裝件能夠縮短多晶片封裝件中的電源及/或訊號的傳遞路徑而提升多晶片封裝件的整體效能，同時本發明的多晶片封裝還具有重佈線結構而具有扇出型封裝的設計自由度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
15: 半導體基底 100:多晶片封裝件 110:重配置線路結構 114:重配置介電層 116:重配置佈線層 118:重配置通路 120:半導體晶片 120P:晶片連接導體 120P1:第一晶片連接導體 120P2:第二晶片連接導體 150:中介層 150A:第一表面 150B:第二表面 150P:中介層連接導體 150P1:第一中介層連接導體 150P2:第二中介層連接導體 150R:介電主體 150S:半導體主體 150W:佈線結構 153:貫穿通路 155:第一凸塊 165:第二凸塊 170:底膠 175:保護層 180:包封體 190:導電端子 I-I':剖線 D1 :寬度 D2 :寬度 DA :寬度 DB :寬度 W1 :寬度 W2 :寬度 α:夾角 β:夾角
圖1是繪示根據本發明的一實施例的多晶片封裝件的剖面示意圖。 圖2是沿圖1的多晶片封裝件的剖線I-I’的平面示意圖。 圖3A至圖3H是根據本發明的一實施例的製造多晶片封裝件的製造流程步驟的剖面示意圖。 圖4A及圖4B是繪示根據本發明的一實施例的接合晶片的方法的剖面示意圖。 圖5A及圖5B是繪示根據本發明的另一實施例的接合晶片的方法的剖面示意圖。
100:多晶片封裝件
110:重配置線路結構
114:重配置介電層
116:重配置佈線層
118:重配置通路
120:半導體晶片
120P:晶片連接導體
120P1:第一晶片連接導體
120P2:第二晶片連接導體
150:中介層
150A:第一表面
150B:第二表面
150P:中介層連接導體
150P1:第一中介層連接導體
150P2:第二中介層連接導體
150R:介電主體
150S:半導體主體
150W:佈線結構
153:貫穿通路
170:底膠
180:包封體
190:導電端子
I-I':剖線
D1 :寬度
D2 :寬度
DA :寬度
DB :寬度
W1 :寬度
W2 :寬度
α:夾角
β:夾角

Claims (21)

  1. 一種多晶片封裝件，包括：中介層，包括介電主體、被所述介電主體隔開的多個半導體主體、貫穿所述介電主體的貫穿通路以及位於所述多個半導體主體中的每一者中的佈線結構；多個半導體晶片，並排地位於所述中介層的第一表面上且電性連接至所述佈線結構；包封體，位於所述中介層的所述第一表面上且包封所述多個半導體晶片的至少部分；以及重配置線路結構，位於所述中介層的第二表面上，所述中介層的所述第二表面與所述中介層的所述第一表面相對，所述重配置線路結構通過所述貫穿通路電性連接至所述多個半導體晶片，其中所述介電主體與所述半導體主體間的界面不垂直於所述中介層的所述第一表面。
  2. 如請求項1所述的多晶片封裝件，其中所述佈線結構的線寬小於1微米。
  3. 如請求項1所述的多晶片封裝件，其中所述中介層的所述第一表面上配置有中介層連接導體，所述多個半導體晶片中的每一者的緊鄰所述中介層的表面上配置有晶片連接導體，所述中介層連接導體與所述晶片連接導體彼此接合。
  4. 如請求項3所述的多晶片封裝件，其中所述中介層連接導體與所述晶片連接導體之間的接合面為無焊料接合面。
  5. 如請求項3所述的多晶片封裝件，其中所述中介層連接導體與所述晶片連接導體藉由焊料接合。
  6. 如請求項3所述的多晶片封裝件，其中所述中介層連接導體與所述晶片連接導體藉由熔點低於200℃的接合金屬接合。
  7. 如請求項3所述的多晶片封裝件，更包括位於所述中介層連接導體與所述晶片連接導體之間的第一凸塊。
  8. 如請求項7所述的多晶片封裝件，更包括位於所述第一凸塊與所述晶片連接導體之間的第二凸塊。
  9. 如請求項3所述的多晶片封裝件，更包括：保護層，配置於所述中介層與所述多個半導體晶片之間且包封所述中介層連接導體與所述晶片連接導體。
  10. 如請求項3所述的多晶片封裝件，其中所述中介層連接導體包括第一中介層連接導體與第二中介層連接導體，所述第一中介層連接導體的寬度大於所述第二中介層連接導體的寬度。
  11. 如請求項10所述的多晶片封裝件，其中所述晶片連接導體包括第一晶片連接導體與第二晶片連接導體，所述第一晶片連接導體的寬度大於所述第二晶片連接導體的寬度。
  12. 如請求項11所述的多晶片封裝件，其中所述第一中介層連接導體與所述第一晶片連接導體彼此接合，且所述第二中介層連接導體與所述第二晶片連接導體彼此接合。
  13. 如請求項10所述的多晶片封裝件，其中所述貫穿通 路連接至所述第一中介層連接導體，且所述佈線結構連接至所述第二中介層連接導體。
  14. 如請求項1所述的多晶片封裝件，其中所述介電主體的寬度隨著與所述多個半導體晶片的距離增大而增加。
  15. 如請求項1所述的多晶片封裝件，其中所述重配置線路結構包括重配置介電層與重配置佈線層，且所述重配置佈線層的線寬大於所述佈線結構的線寬。
  16. 如請求項1所述的多晶片封裝件，其中所述包封體的側壁、所述中介層的側壁以及所述重配置線路結構的側壁彼此對準。
  17. 如請求項1所述的多晶片封裝件，更包括：底膠，配置於所述中介層與所述多個半導體晶片之間，其中所述底膠的寬度隨著與所述多個半導體晶片的距離增大而增加。
  18. 如請求項1所述的多晶片封裝件，其中所述多個半導體主體中的至少一個半導體主體在與所述第一表面垂直的方向上交疊所述多個半導體晶片中的至少兩者。
  19. 一種多晶片封裝件，包括：中介層，包括介電主體、半導體主體、貫穿所述介電主體的貫穿通路以及位於所述半導體主體中的佈線結構，所述貫穿通路與所述佈線結構彼此間隔開；多個半導體晶片，並排地位於所述中介層的第一表面上且所述多個半導體晶片中的每一者同時電性連接至所述佈線結構與所 述貫穿通路；以及重配置線路結構，位於所述中介層的第二表面上且與所述貫穿通路電性連接，所述中介層的所述第二表面與所述中介層的所述第一表面相對，其中所述介電主體與所述半導體主體間的界面不垂直於所述中介層的所述第一表面。
  20. 如請求項19所述的多晶片封裝件，其中所述佈線結構的線寬小於1微米。
  21. 一種製造多晶片封裝件的方法，包括：於半導體基底的第一表面上提供多個半導體晶片以使所述多個半導體晶片中的每一者電性連接至所述半導體基底中的佈線結構；於所述半導體基底的所述第一表面上形成包封體以包封所述多個半導體晶片；從所述半導體基底的與所述第一表面相對的第二表面移除所述半導體基底的至少部分以使所述半導體基底的剩餘部分彼此隔開；在所述半導體基底移除後產生的空間形成介電主體；在所述介電主體中形成貫穿所述介電主體且連接至所述多個半導體晶片的貫穿通路；以及在所述半導體基底的所述剩餘部分及所述介電主體上形成重配置線路結構，所述重配置線路結構電性連接至所述貫穿通路。
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