CN111952268A - 多模块集成内插器和由此形成的半导体器件 - Google Patents

多模块集成内插器和由此形成的半导体器件 Download PDF

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Publication number
CN111952268A
CN111952268A CN201910403773.7A CN201910403773A CN111952268A CN 111952268 A CN111952268 A CN 111952268A CN 201910403773 A CN201910403773 A CN 201910403773A CN 111952268 A CN111952268 A CN 111952268A
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China
Prior art keywords
semiconductor
module
interposer
bond pads
wafer
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CN201910403773.7A
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English (en)
Inventor
张聪
邱进添
杨旭一
张亚舟
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Western Digital Technologies Inc
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Western Digital Technologies Inc
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Priority to CN201910403773.7A priority Critical patent/CN111952268A/zh
Priority to US16/818,817 priority patent/US11257785B2/en
Publication of CN111952268A publication Critical patent/CN111952268A/zh
Pending legal-status Critical Current

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Abstract

本发明题为“多模块集成内插器和由此形成的半导体器件”。本发明公开了一种半导体器件，包括用于实现所述器件内的一个或多个半导体管芯与上面安装有所述半导体器件的主机设备之间的通信的多模块内插器。所述多模块内插器可以在所述晶圆级形成，并且提供到所述器件中的所述一个或多个管芯的扇出信号路径以及自所述器件中的所述一个或多个管芯的扇出信号路径。另外，所述多模块内插器允许在所述晶圆级形成任何各种不同的半导体封装构型，包括例如引线键合封装、倒装芯片封装和硅通孔(TSV)封装。

Description

多模块集成内插器和由此形成的半导体器件
背景技术
便携式消费电子器件需求的强劲增长推动了对高容量存储设备的需求。非易失性半导体存储装置，诸如闪存存储卡，已广泛用于满足对数字信息存储和交换的日益增长的需求。它们的便携性、多功能性和坚固耐用的设计以及它们的高可靠性和大容量，使得此类存储装置理想地用于多种电子设备中，包括例如数字相机、数字音乐播放器、视频游戏控制台、PDA和蜂窝电话。
虽然已知许多不同的封装配置，但是闪存半导体产品通常可以被制造为系统级封装(SIP)或多芯片模块(MCM)，其中多个半导体管芯被安装并互连到衬底的上表面。衬底通常可以包括刚性的电介质基部，其具有在一侧或两侧上蚀刻的导电层。焊球通常安装在形成在衬底下表面上的接触焊盘上，以允许衬底焊接到主机设备，诸如印刷电路板。一旦安装，信号可以经由衬底在半导体管芯和主机设备之间传输。
一直存在在较小的整体形状因数半导体封装中提供更大的存储容量的需求。探索的一个领域是提供没有衬底的半导体封装，但是迄今为止，已经证明提供不具有衬底的多芯片半导体封装的此类努力是困难的。
附图说明
图1是根据本发明技术的实施方案的用于形成半导体器件的流程图。
图2是根据本发明技术的实施方案的包括多模块内插器的半导体晶圆的顶视图。
图3是根据本发明技术的实施方案的包括表面接合焊盘的第一构型的多模块内插器的顶视图。
图4是根据本发明技术的实施方案的包括表面接合焊盘的第二构型的多模块内插器的顶视图。
图5是根据本发明技术的实施方案的包括表面接合焊盘的第三构型的多模块内插器的顶视图。
图6是根据本发明技术的实施方案的在第一制造阶段包括多个多模块内插器的晶圆的横截面边缘视图。
图7是根据本发明技术的实施方案的在第二制造阶段包括多个多模块内插器和半导体管芯的晶圆的横截面边缘视图。
图8是根据本发明技术的实施方案的在第三制造阶段包括多个多模块内插器和封装的半导体管芯的晶圆的横截面边缘视图。
图9是根据本发明技术的实施方案的在第四制造阶段包括多个多模块内插器和封装的半导体管芯的减薄晶圆的横截面边缘视图。
图10是根据本发明技术的实施方案的在第五制造阶段包括多个多模块内插器、封装的半导体管芯和重新分布层的减薄晶圆的横截面边缘视图。
图11是根据本发明技术的实施方案的包括多模块内插器的多个完成的半导体器件的横截面边缘视图。
图12是根据本发明技术的实施方案的包括多模块内插器的半导体器件的底部透视图。
具体实施方式
现在将参考附图来描述本发明的技术，在实施方案中，这些附图涉及一种包括多模块内插器的半导体器件，该多模块内插器用于实现器件内的一个或多个半导体管芯与安装有半导体器件的主机设备之间的通信。多模块内插器可以在晶圆级形成，并且提供到器件中的一个或多个管芯的扇出信号路径以及自器件中的一个或多个管芯的扇出信号路径。另外，多模块内插器允许在晶圆级形成任何各种不同的半导体封装构型，包括例如引线键合封装、倒装芯片封装和硅通孔(TSV)封装。
可以理解，本发明可体现为许多不同形式并且不应解释为限于本文所阐述的实施方案。相反，提供了这些实施方案，使得本公开将是彻底的和完整的，并且将充分地将本发明传达给本领域的技术人员。实际上，本发明旨在覆盖这些实施方案的另选方案、修改和等同物，这些均包括在由所附权利要求书所限定的本发明的范围和实质内。此外，在本发明的以下详细描述中，给出了许多具体细节，以便提供对本发明的彻底理解。然而，对本领域的普通技术人员将显而易见的是，本发明可在没有此类具体细节的情况下被实施。
本文所用的术语“顶部”和“底部”、“上”和“下”以及“垂直”和“水平”及其形式，如可仅以举例方式和出于示例性目的用于本文，并且不旨在限制技术的描述，因为所引用的项目可在位置和取向上交换。另外，如本文所用，术语“基本上”和/或“约”是指指定的尺寸或参数可在给定应用的可接受的制造公差内变化。在一个实施方案中，可接受的制造公差为给定尺寸的±2.5％。
现在将参考图1的流程图以及图2至图12的视图解释本发明技术的实施方案。在步骤200和步骤202中，可以将半导体晶圆100处理成多个多模块内插器102，如图2所示。半导体晶圆100开始时可以是晶圆材料的晶锭，晶圆材料可以是根据Czochralski(CZ)或浮区(FZ)工艺生长的单晶硅。然而，在另外的实施方案中，晶片100可由其他材料并通过其他工艺形成。
可以从晶锭切割出半导体晶圆100并在第一主平坦表面104和与该表面104相对的第二主平坦表面105(图6)两者上抛光，以提供平滑表面。第一主表面104可以经历各种处理步骤以将晶圆100分成相应的多模块内插器102。具体地，在步骤200中，可以在实施方案中处理多模块内插器102以包括形成在包括层114和层116的电介质衬底中的内部电连接件，如图6的横截面边缘视图所示。图2中的晶圆100上示出的多模块内插器102的数量是为了进行示意性的说明，并且晶圆100可以包括比其他实施方案中示出的更多的多模块内插器102。
每个内插器102内的内部电连接件可以包括顺序地形成穿过介电膜116的层的多层金属互连件110和通孔112。金属互连件110、通孔112和介电膜层116可以使用光刻和薄膜沉积工艺一次形成一层。光刻工艺可包括例如图案定义、等离子体、化学或干法蚀刻和抛光。薄膜沉积工艺可包括例如溅射和/或化学气相沉积。金属互连件110可以由各种导电金属形成，包括例如本领域中已知的铜和铜合金，并且通孔112可以衬有和/或填充有各种导电金属，包括例如本领域已知的钨、铜和铜合金。
在步骤202中，可以在多模块内插器102的主平坦表面104上形成接合焊盘120。如图3、图4和图5所示，在本技术的不同实施方案中，接合焊盘120可以在平坦表面104中以各种不同的图案形成。图3示出了接合焊盘120的行和列的均匀图案。虽然行和列被示出为彼此对准，但是应当理解，在其他实施方案中，行和/或列彼此有偏移。图4示出了接合焊盘120的类似构型，其中内插器102的中心部分没有接合焊盘。图5示出了具有单列焊盘的构型。应当理解，图3至图5中所示的接合焊盘120的数量和接合焊盘120的图案是为了进行例示性的说明，可以以其他数量和各种其他构型在多模块内插器102的主平坦表面104中提供接合焊盘120。
此外，应当理解，单个晶圆100上的各种内插器102可各自具有相同图案的接合焊盘120。另选地，单个晶圆100上的不同内插器102可具有不同图案的接合焊盘120。在此类实施方案中，可以开发晶圆图，限定要在各个内插器102(例如，引线键合、倒装芯片、TSV)上形成的不同类型的半导体封装，并且可以根据该晶圆图定制各个内插器102上的接合焊盘120的图案。
为了形成接合焊盘120，可以在主平坦表面104上形成钝化层122(图6)。可以蚀刻钝化层122，并且可以在钝化层的蚀刻区域中的衬垫124上形成每个接合焊盘120。如本领域中已知的，接合焊盘120可由例如铜、铝及其合金形成，并且衬垫124可由例如钛/氮化钛叠堆(诸如，例如，Ti/TiN/Ti)形成，但这些材料在另外的实施方案中可变化。可以通过气相沉积和/或电镀技术施加接合焊盘120和衬垫124。接合焊盘和衬垫一起可以具有720nm的厚度，但是在其他实施方案中该厚度可以更大或更小。不同组的接合焊盘120可以通过金属互连件110和通孔112彼此电连接。
内部金属连接件还包括从最底部金属互连件110向下延伸到晶圆100的介电层114中的一系列通孔130。如下所述，介电层114在背面研磨工艺中变薄，从而使通孔130的一端暴露在晶圆100的后表面(相对表面104)处。
在步骤208中，半导体管芯132可以固定到晶圆100上的相应多模块内插器102上，如图7所示。管芯132安装在相应的内插器102的表面104上，如通过最下面的半导体管芯上的管芯附接膜(DAF)，并且电耦合至相应的内插器102的接合焊盘120。电连接件的类型取决于半导体封装构型。
例如，左边的图7示出了一堆被引线键合到一行接合焊盘120(诸如图5中所示的一排接合焊盘120)的半导体管芯132。引线键合的半导体管芯132可以以偏移的阶梯式构型堆叠，以在堆叠的每个级别处留下在管芯132上暴露的一行接合焊盘。然后可以形成引线键合134，其中引线键合毛细管(未示出)将半导体管芯132中的每一者彼此电耦合并且电耦合至晶圆100的内插器102。图7的左侧还示出了无源器件135，诸如例如电阻器、电容器和/或电感器，这些无源器件与引线键合的管芯堆叠相关联地安装。任何封装构型还可以包括无源器件135。
图7的中间部分示出了倒装芯片半导体管芯132形式的第二半导体封装构型。倒装芯片半导体管芯132可以包括在半导体管芯132的下表面上(面向晶圆100的表面104)的球形接合图案，该球形接合图案与内插器102上的接合焊盘120的图案(诸如图4中所示的焊盘120的图案)接合。
图7的右侧示出了垂直堆叠的半导体管芯形式的第三半导体封装构型，其通过硅通孔136电耦合至接合焊盘120。
在实施方案中，单个晶圆100可以具有图7中所示的一些或所有封装构型(引线键合、倒装芯片和/或TSV)。如上所述，可以准备晶圆图，示出要在晶圆100上的哪个内插器102上形成哪种类型的封装构型。还如上所述，用于给定内插器102的接合焊盘120的图案可以针对要在该内插器102上形成的封装构型的类型而定制。另选地，可以在所有内插器102上使用单个图案的接合焊盘120，但是根据封装构型仅使用那些接合焊盘中的一些。
在另一实施方案中，给定晶圆100上的所有内插器102可以接纳相同类型的封装构型。因此，晶圆100上的所有内插器102可以接纳引线键合的半导体管芯封装构型，晶圆100上的所有内插器102可以接纳倒装芯片半导体管芯封装构型，或者晶圆100上的所有内插器102可以接纳TSV半导体管芯封装构型。虽然示出了引线键合、倒装芯片和TSV封装构型，但是应当理解，可以使用其他类型的封装构型来代替图7中所示的那些，或者除了在该图中所示的那些之外可以使用其他类型的封装构型。
任何配置中的半导体管芯132可以是各种半导体管芯中的任何一种，包括例如存储器管芯，诸如2D NAND闪存或3D BiCS(位成本缩放)、V-NAND或其他3D闪存。然而，可以使用其他类型的半导体管芯，包括例如控制器管芯，诸如ASIC，或者RAM，诸如SDRAM、DDRSDRAM、LPDDR和GDDR。堆叠管芯封装中的管芯132的数量可以在例如2、4、8、16、32和64个管芯之间变化，但是在其他实施方案中可以存在其他数量的管芯。
再次参见图1，在将半导体管芯132安装到它们各自的内插器102之后，可以在步骤210中将半导体管芯132封装在模塑化合物140中，如图8所示。模塑化合物140可包括例如固体环氧树脂、酚醛树脂、熔融二氧化硅、结晶二氧化硅、炭黑和/或金属氢氧化物。还设想了来自其他制造商的其他模塑化合物。模塑化合物可通过各种已知工艺施加，包括通过压塑、FFT(无流动薄)模塑、传递模塑或注塑成型技术。
一旦管芯132被封装，晶圆100就可以在背面研磨工艺步骤214中减薄，如图9所示。背面研磨步骤214可以实现两个目标。首先，背面研磨步骤使晶圆100的介电层114变薄，以提供最终的晶圆厚度。在一个示例中，背面研磨步骤可以将晶圆从约760μm减薄至30μm，但是在其他实施方案中这些厚度可以变化。其次，背面研磨步骤可以在晶圆100的底表面105处暴露通孔130，如图9所示。
在步骤216中，可以在晶圆100的表面105上形成重新分布层(RDL)144，如图10所示。RDL 144可以将通孔130的图案电重新分布到RDL144的底表面上的接触焊盘146的图案。焊球148可以在步骤220中安装在接触焊盘146上。因此，根据本发明技术的方面，使用多模块内插器102，所选择的接合焊盘120电耦合至所选择的焊球148。
在步骤224中，可以切割晶圆100以将相应的多模块内插器102和安装在其上的半导体管芯分离成独立的半导体器件150，如图11所示。可以通过各种方法切割器件150，包括通过锯条、激光和水射流切割方法。图12是示出包括焊球148的图案的半导体器件150的底部透视图。所示的焊球148的特定图案是以举例的方式，并且焊球的图案和数量可以在其他实施方案中变化。然后，通过将焊球148焊接到主机设备的接触焊盘上，可以将半导体器件150安装在主机设备(未示出)上。此后，可以通过多模块内插器102完成半导体器件150和主机设备之间的通信。
应当理解，在其他实施方案中，关于图1的流程图描述的处理步骤可以以不同的顺序形成。在一个此类示例中，晶圆100可以变薄(步骤214)，RDL 144附连到晶圆(步骤216)并且焊球148可以附接到RDL144，所有这些都在连接半导体管芯和无源部件的步骤208之前。这种步骤排序的一个优点是可以将制造完全的晶圆100运送到半导体封装制造厂。在封装制造工厂，所需要的只是附连半导体管芯和无源部件(步骤208)、封装管芯和无源部件(步骤210)，以及切割晶圆(步骤224)以形成完整的半导体器件150。与半导体封装制造工厂的传统制造步骤相比，这极大地简化了半导体封装制造工厂所需的处理步骤。
在实施方案中，多模块内插器102提供有效的晶圆级解决方案，用于提供半导体器件内的半导体管芯与可安装器件的主机设备之间的通信路径。内插器102还提供高度的柔韧性，因为各种半导体封装构型中的任何一种都可以在晶圆级电耦合至内插器102。此外，内插器102提供扇出信号路径，使得电连接件(例如焊球148)不限于在半导体器件150内使用的半导体管芯的尺寸内。
此外，与传统衬底相比，多模块内插器102可以制造得非常薄，以便在整个半导体器件150中占据非常小的高度。如上所述，在实施方案中，晶圆100的最终厚度可以例如是30μm，并且RDL可以具有约20μm的厚度，以提供约50μm的内插器102的最终厚度。应当理解，内插器102的厚度可以比其他实施方案中的厚度更多或更少。
概括地说，本发明技术的示例涉及一种半导体晶圆，包括：多个多模块内插器，多个多模块内插器各自包括：每个多模块内插器的第一表面上的多个接合焊盘；重新分布层，该重新分布层包括在每个多模块内插器的与第一表面相对的第二表面上的多个接触焊盘，该第二表面上的多个接触焊盘电耦合至第一表面上的多个接合焊盘中的所选择的接合焊盘；以及多个半导体管芯，这些多个半导体管芯安装在多个多模块内插器上并且电耦合至多个多模块内插器，这些多个多模块内插器的不同多模块内插器接纳多个半导体管芯的不同构型。
在另一示例中，本发明技术涉及一种半导体晶圆，包括：多个多模块内插器，这些多个多模块内插器中的每个多模块内插器包括：多模块内插器的第一表面上的多个接合焊盘、至少一个介电层、形成在介电层上的重新分布层，该重新分布层包括在多模块内插器的与第一表面相对的第二表面上的多个接触焊盘，以及在至少一个介电层中形成的用于将多个管芯焊盘与多个接触焊盘电互连的电互连件和通孔；以及安装到多个多模块内插器的多个半导体管芯，多个半导体管芯中的一个或多个电耦合至多模块内插器上的多个接合焊盘。
在另一示例中，本发明技术涉及多个半导体器件，每个半导体器件包括：多模块内插器，包括：多模块内插器的第一表面上的多个接合焊盘，包括位于多模块内插器的与第一表面相对的第二表面上的多个接触焊盘的重新分布层，第二表面上的多个接触焊盘电耦合至第一表面上的多个接合焊盘中所选择的接合焊盘；以及安装在多模块内插器上并电耦合至多个接合焊盘的一个或多个管芯；其中多个半导体器件被配置为接纳一个或多个半导体管芯的不同构型。
在另一示例中，本发明技术涉及一种制造半导体晶圆的方法，包括：(a)在半导体晶圆的第一表面上形成多个接合焊盘；(b)形成多个通孔，电耦合至多个接合焊盘，远离半导体晶圆的第一表面朝向与第一表面相对的半导体晶圆的第二表面延伸；(c)在第二表面处减薄晶圆，使得多个通孔在第二表面处暴露；以及(d)将重新分布层附连到晶圆的第二表面，重新分布层将重新分布层的第一表面处的多个通孔的位置电重新分布到重新分布层的与第一表面相对的第二表面处的多个接触焊盘。
在另一示例中，本发明技术涉及一种半导体晶圆，包括：用于传输电信号的插入装置，包括：在内插器装置的第一表面上的接合焊盘装置用于电耦合至半导体管芯，重新分配装置包括接触焊盘装置，该重新分配装置用于将接合焊盘装置的位置重新分配到接触焊盘装置的不同位置；以及安装在内插器装置上并且电耦合至内插器装置的多个半导体管芯，不同的内插器装置接纳多个半导体管芯的不同构型。
已出于例证和描述的目的提出本发明的上述详细描述。它并非旨在是穷尽的或将本发明限制为所公开的精确形式。根据以上教导内容，很多修改形式和变型形式都是可能的。选择所述实施方案是为了最佳地阐明本发明的原理以及其实际应用，以由此使得本领域的其他技术人员能够最佳地使用具有适合于所构想的特定用途的各种修改的本发明以及各种实施方案。本发明的范围旨在由所附权利要求书限定。

Claims (25)

1.一种半导体晶圆，包括：
多个多模块内插器，所述多个多模块内插器各自包括：
每个多模块内插器的第一表面上的多个接合焊盘，
重新分布层，所述重新分布层包括在每个多模块内插器的与所述第一表面相对的第二表面上的多个接触焊盘，所述第二表面上的所述多个接触焊盘电耦合至所述第一表面上的所述多个接合焊盘中所选择的接合焊盘；以及
多个半导体管芯，所述多个半导体管芯被安装到所述多个多模块内插器上并且电耦合至所述多个多模块内插器，所述多个多模块内插器的不同多模块内插器接纳所述多个半导体管芯的不同构型。
2.根据权利要求1所述的半导体晶圆，其中所述多个半导体管芯的不同构型包括以下各项中的至少两者：i)一组引线键合半导体管芯，ii)倒装芯片半导体管芯，以及iii)通过硅通孔彼此电连接的一组半导体管芯。
3.根据权利要求1所述的半导体晶圆，其中每个多模块内插器的所述第一表面上的所述多个接合焊盘的图案与每个其他多模块内插器的所述第一表面上的所述多个接合焊盘的图案相同。
4.根据权利要求1所述的半导体晶圆，其中所述多个多模块内插器的第一多模块内插器的所述第一表面上的所述多个接合焊盘的第一图案，不同于所述多个多模块内插器的第二多模块内插器的所述第一表面上的所述多个接合焊盘的第二图案。
5.根据权利要求4所述的半导体晶圆，其中所述多个接合焊盘的所述第一图案被配置为接纳所述多个半导体管芯的第一构型，并且所述多个接合焊盘的所述第二图案被配置为接纳所述多个半导体管芯的与所述第一构型不同的第二构型。
6.根据权利要求1所述的半导体晶圆，其中所述多模块内插器中的每一者包括扇出信号路径，其中具有所述多个接触焊盘的每个多模块内插器的所述第二表面的面积大于具有所述多个接合焊盘的每个多模块内插器的所述第一表面的面积。
7.根据权利要求1所述的半导体晶圆，还包括多个焊球，所述多个焊球附连到所述多个多模块内插器中的每一者的所述第二表面上的所述多个接触焊盘。
8.一种半导体晶圆，包括：
多个多模块内插器，所述多个多模块内插器中的每个多模块内插器包括：
所述多模块内插器的第一表面上的多个接合焊盘，
至少一个介电层，
形成在所述介电层上的重新分布层，所述重新分布层包括位于所述多模块内插器的与所述第一表面相对的第二表面上的多个接触焊盘，以及
在所述至少一个介电层中形成的电互连件和通孔，用于将所述多个管芯接合焊盘与所述多个接触焊盘电互连；以及
安装到所述多个多模块内插器的多个半导体管芯，所述多个半导体管芯中的一个或多个电耦合至所述多模块内插器上的所述多个接合焊盘。
9.根据权利要求8所述的半导体晶圆，其中所述多个多模块内插器中的不同多模块内插器被配置为接纳所述多个半导体管芯的不同构型。
10.根据权利要求9所述的半导体晶圆，其中所述多个半导体管芯的不同构型包括以下各项中的至少两者：i)一组引线键合半导体管芯，ii)倒装芯片半导体管芯，以及iii)通过硅通孔彼此电连接的一组半导体管芯。
11.根据权利要求9所述的半导体晶圆，其中被配置为接纳所述多个半导体管芯的第一构型的所述多个多模块内插器中的所述第一多模块内插器的所述多个接合焊盘，具有与所述多个多模块内插器的第二多模块内插器上的所述多个接合焊盘不同的图案，所述多个多模块内插器被配置为接纳与所述多个半导体管芯的所述第一构型不同的所述多个半导体管芯的第二构型。
12.根据权利要求9所述的半导体晶圆，其中被配置为接纳所述多个半导体管芯的第一构型的所述多个多模块内插器中的所述第一多模块内插器的所述多个接合焊盘，具有与所述多个多模块内插器的第二多模块内插器上的所述多个接合焊盘相同的图案，所述多个多模块内插器被配置为接纳与所述多个半导体管芯的所述第一构型不同的所述多个半导体管芯的第二构型。
13.根据权利要求8所述的半导体晶圆，其中所述多模块内插器中的每一者包括扇出信号路径，其中具有所述多个接触焊盘的每个多模块内插器的所述第二表面的面积大于具有所述多个接合焊盘的每个多模块内插器的所述第一表面的面积。
14.多个半导体器件，每个半导体器件包括：
一种多模块内插器，包括：
所述多模块内插器的第一表面上的多个接合焊盘，
重新分布层，所述重新分布层包括在所述多模块内插器的与所述第一表面相对的第二表面上的多个接触焊盘，所述第二表面上的所述多个接触焊盘电耦合至所述第一表面上的所述多个接合焊盘中所选择的接合焊盘；以及
一个或多个管芯，所述一个或多个管芯被安装在所述多模块内插器上并且被电耦合至所述多个接合焊盘；
其中所述多个半导体器件被配置为接纳所述一个或多个半导体管芯的不同构型。
15.根据权利要求14所述的多个半导体器件，其中所述一个或多个半导体管芯的所述不同构型包括以下各项中的至少两者：i)一组引线键合半导体管芯，ii)倒装芯片半导体管芯，以及iii)通过硅通孔彼此电连接的一组半导体管芯。
16.根据权利要求14所述的多个半导体器件，其中所述多个半导体器件中的每一者的所述多个接合焊盘的图案彼此相同。
17.根据权利要求14所述的多个半导体器件，其中所述多个半导体器件中的每一者的所述多个接合焊盘的图案彼此不同。
18.一种制造半导体晶圆的方法，包括：
(a)在所述半导体晶圆的第一表面上形成多个接合焊盘；
(b)形成多个通孔，电耦合至所述多个接合焊盘，远离所述半导体晶圆的所述第一表面朝向所述半导体晶圆的与所述第一表面相对的第二表面延伸；
(c)在所述第二表面处减薄所述晶圆，使得所述多个通孔在所述第二表面处暴露；
(d)将重新分布层附连到所述晶圆的所述第二表面，所述重新分布层将所述重新分布层的第一表面处的所述多个通孔的位置电重新分布到所述重新分布层的与所述第一表面相对的第二表面处的多个接触焊盘。
19.根据权利要求18所述的方法，还包括步骤(e)：将多个半导体管芯附连到所述晶圆的所述第一表面，以及将所述多个半导体管芯电耦合至所述多个接合焊盘。
20.根据权利要求19所述的方法，还包括步骤(f)：将所述多个半导体管芯封装在所述晶圆的所述第一表面上。
21.根据权利要求20所述的方法，还包括步骤(g)：将所述晶圆切割成分立的半导体器件，每个半导体器件包括所述多个半导体管芯中的一个或多个。
22.根据权利要求19所述的方法，其中所述附连多个半导体管芯的步骤(e)在所述减薄所述晶圆的步骤(c)之前进行。
23.根据权利要求19所述的方法，其中所述附连多个半导体管芯的步骤(e)在所述附连重新分布层的步骤(d)之后进行。
24.根据权利要求19所述的方法，其中所述附连多个半导体管芯的步骤(e)在所述附连重新分布层的步骤(d)之后进行。
25.一种半导体晶圆，包括：
用于传输电信号的内插器装置，包括：
在所述内插器装置的第一表面上的接合焊盘装置，用于被电耦合至半导体管芯，
包括接触焊盘装置的重新分配装置，所述重新分配装置用于将所述接合焊盘装置的位置重新分配到所述接触焊盘装置的不同位置；以及
安装在所述内插器装置上并电耦合至所述内插器装置的多个半导体管芯，不同的内插器装置接纳所述多个半导体管芯的不同构型。
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