CN109935562B - 包括可选垫互连件的半导体装置 - Google Patents

包括可选垫互连件的半导体装置 Download PDF

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CN109935562B
CN109935562B CN201811284045.0A CN201811284045A CN109935562B CN 109935562 B CN109935562 B CN 109935562B CN 201811284045 A CN201811284045 A CN 201811284045A CN 109935562 B CN109935562 B CN 109935562B
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die bond
bond pad
die
semiconductor
pad
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CN109935562A (zh
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陈含笑
廖致钦
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Western Digital Technologies Inc
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Western Digital Technologies Inc
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Abstract

本发明题为“包括可选垫互连件的半导体装置”。本发明公开了一种半导体装置，该半导体装置包括半导体管芯，该半导体管芯由功能冗余的主管芯接合焊盘和可选管芯接合焊盘形成。在示例中，可选管芯接合焊盘被配置为通过形成具有电隔离的第一部分和第二部分的可选管芯接合焊盘以及将主管芯接合焊盘与第二管芯接合焊盘的第一部分电互连而任选地对主管芯接合焊盘冗余。根据是否将导电材料沉积在可选管芯接合焊盘的第一部分和第二部分上，第二管芯接合焊盘可对或可不对第一管芯接合焊盘冗余。

Description

包括可选垫互连件的半导体装置
背景技术
便携式消费电子器件需求的强劲增长推动了对高容量存储装置的需求。非易失性半导体存储装置，诸如闪存存储卡，已广泛用于满足对数字信息存储和交换的日益增长的需求。它们的便携性、多功能性和坚固耐用的设计以及它们的高可靠性和大容量，使得此类存储装置理想地用于多种电子设备中，包括例如数字相机、数字音乐播放器、视频游戏控制台、PDA和蜂窝电话。
半导体存储器可设置在半导体封装内，该半导体封装保护半导体存储器并实现存储器与主机装置之间的通信。半导体封装的示例包括系统级封装(SiP)或多芯片模块(MCM)，其中多个管芯安装并互连在小占用面积衬底上。多个半导体管芯可安装在一个偏移叠堆中使得每个管芯上的管芯接合焊盘被暴露于管芯的边缘。随后叠堆中相应管芯的管芯接合焊盘通常可彼此丝焊并丝焊到衬底以允许信号交换至/自管芯叠堆中的选择管芯。
经常需要在管芯冗余上制备管芯接合焊盘中的一者或多者。例如，用于芯片启用信号的管芯接合焊盘可具有主管芯接合焊盘和冗余，或可选管芯接合焊盘，该管芯接合焊盘与衬底上的相同接触焊盘电连接。
有两种传统方法用于丝焊到主管芯接合焊盘和可选管芯接合焊盘。第一种是所谓的“Y”形焊线。使用安装在衬底上的第一管芯D1和安装在管芯D1上的第二管芯D2的简单示例，可能有利的是在第二管芯D2上制造第一和第二冗余管芯接合焊盘。焊线可从衬底到第一管芯接合焊盘的D1形成，并且第二焊线从第一管芯接合焊盘的D1直接向上到第一管芯接合焊盘的D2形成。然后，为了形成冗余“Y”形焊接，第三焊线也从第一管芯接合焊盘的D1到第二管芯接合焊盘的D2沿对角线形成(从而形成包括第一管芯接合焊盘的D1以及第一管芯接合焊盘和第二管芯接合焊盘的D2的“Y”形焊接)。这种传统的焊接方法是有问题的，因为三个焊线在第一管芯接合焊盘的D1上形成(一个来自衬底并且两个至管芯2)。在同一接合焊盘上的三个焊接存在可靠性风险，诸如电短路或失效(其中焊线可与焊盘分离)。
用于冗余丝焊的第二传统方法是形成从衬底直接到管芯D2的冗余焊线。焊线可从衬底上的第一接触焊盘到第一管芯接合焊盘的D1形成，并且第二焊线从第一管芯接合焊盘的D1直接向上到第一管芯接合焊盘的D2形成。然后，为了形成冗余焊线，将第三焊线从衬底上的第一接触焊盘到第二管芯接合焊盘的D2沿对角线形成(越过管芯D1)。在该简单的示例中，第三焊线从衬底到第二管芯，但半导体装置更通常将具有更大数量的管芯(4、8、16或甚至32个管芯)。形成从衬底直接到上部层级管芯的焊线导致长焊线存在可靠性风险，诸如对其他焊线的短路或长焊线的塌缩。
附图说明
图1是根据本技术的实施方案的用于形成半导体管芯的流程图。
图2是半导体晶片的前视图，其示出了该晶片的第一主表面。
图3是晶片的一部分的放大视图，其示出了在晶片的一部分上形成的接合焊盘管芯。
图4是根据本技术的实施方案的半导体管芯的顶视图。
图5是图4所示的半导体管芯的一部分的放大顶视图。
图6是根据本技术的实施方案的用于形成半导体装置的流程图。
图7是包括堆叠的半导体管芯的半导体装置的透视图，该堆叠的半导体管芯具有根据本技术实施方案的未连接的可选管芯接合焊盘。
图8是图7所示的半导体管芯的一部分的放大顶视图。
图9是包括堆叠的半导体管芯的半导体装置的透视图，该堆叠的半导体管芯具有根据本技术实施方案的连接的可选管芯接合焊盘。
图10是图9所示的半导体管芯的一部分的放大顶视图。
图11是根据本技术实施方案的完成的半导体装置的横截面侧视图。
图12是本技术的另选实施方案的透视图。
具体实施方式
现在将参照附图描述本发明的技术，所述附图在实施方案中涉及半导体装置，该半导体装置包括半导体管芯，该半导体管芯由功能冗余的主管芯接合焊盘和可选管芯接合焊盘形成。在实施方案中，半导体管芯上的可选管芯接合焊盘可形成为第一部分，该第一部分与半导体管芯内的集成电路电连接。可选管芯接合焊盘可进一步形成有第二部分，该第二部分包围第一部分但与之电气隔离。导电金属互连件可形成于半导体管芯上，该半导体管芯在可选管芯接合焊盘的第二部分与主管芯接合焊盘之间延伸并将二者电耦合。
当期望使用主管芯接合焊盘和可选管芯接合焊盘作为冗余管芯接合焊盘时，可选管芯接合焊盘的第一部分和第二部分可彼此电耦合，例如通过在可选管芯接合焊盘上形成的球状凸块越过可选管芯接合焊盘的第一部分和第二部分两者。当期望让主管芯接合焊盘和可选管芯接合焊盘不电连接时，可从可选管芯接合焊盘中省略球状凸块。
可以理解，本发明可体现为许多不同形式并且不应解释为限于本文所阐述的实施方案。相反，提供了这些实施方案，使得本公开将是彻底和完整的，并且将充分地将本发明传达给本领域的技术人员。实际上，本发明旨在覆盖这些实施方案的另选方案、修改和等同物，这些均包括在由所附权利要求所限定的本发明的范围和实质内。此外，在本发明的以下详细描述中，给出了许多具体细节，以便提供对本发明的彻底理解。然而，对本领域的普通技术人员将显而易见的是，本发明可在没有这些具体细节的情况下被实施。
本文所用的术语“顶部”和“底部”、“上”和“下”以及“垂直”和“水平”及其形式，如可仅以举例方式和出于示例性目的用于本文的，并且不旨在限制技术的描述，因为所引用的项目可在位置和取向上交换。另外，如本文所用，术语“基本上”和/或“约”是指指定的尺寸或参数可在给定应用的可接受的制造公差内变化。在一个实施方案中，可接受的制造公差为限定尺寸的±0.25％。
现在将参考图1和图6的流程图以及图2至图5和图7至图12的视图解释本技术的实施方案。最初参见图1的流程图，半导体晶片100可作为可在步骤200中形成的晶片材料的铸块开始。在一个示例中，形成晶片100的铸块可以是根据柴可拉斯基法(CZ)或浮区法(FZ)生长的单晶硅。然而，在另外的实施方案中，晶片100可由其他材料并通过其他方法形成。
在步骤204中，半导体晶片100可从铸块切割下来，并且在第一主表面102(图2)和第二主表面两者相对的表面102上抛光以提供平滑表面。在步骤206中，第一主表面102可经历各种处理步骤以将晶片100分成相应的半导体管芯106(图2和图3)，并且在第一主表面102上和/或中形成相应半导体管芯106的集成电路。这些各种处理步骤可包括金属化步骤，在晶片内沉积金属互连层和通孔。这些金属互连层和通孔可被提供用于将信号传输至每个半导体管芯内的集成电路以及从每个半导体管芯内的集成电路传输信号，从而为集成电路提供结构支撑。
在实施方案中，集成电路可被操作为NAND闪存存储器半导体管芯，但设想了其他类型的集成电路。图2中晶片100上所示的半导体管芯106的数目是为了进行示意性的说明，并且晶片100可包括比在另外的实施方案中所示更多的半导体管芯106。
金属化步骤206还可包括沉积金属触点，该金属触点包括管芯接合焊盘108，该管芯接合焊盘暴露在第一主表面102上。每个半导体管芯106上的接合焊盘108的数目为了进行示意性的说明而示出，并且每个管芯106可包括比另外的实施方案中所示的更多管芯接合焊盘。每个管芯接合焊盘108可包括在衬垫上方形成的上部接触层。如本领域已知的，接触层可由例如铜、铝及其合金形成，并且衬垫可由例如钛/氮化钛叠堆(例如Ti/TiN/Ti)形成，但这些材料在另外的实施方案中可变化。接合焊盘108(接触层加衬垫)可具有720nm的厚度，但在另外的实施方案中，该厚度可能更大或更小。在实施方案中，每个管芯接合焊盘108可具有50μm至70μm的长度和宽度，但在另外的实施方案中焊盘108的长度和宽度可彼此成比例地或不成比例地变化。另外，虽然显示为矩形或正方形，但管芯接合焊盘可为多种其他形状，包括圆形、椭圆形、长方形和多边形。如图3所示，根据本技术的各方面，这些管芯接合焊盘108中的一者或多者可为被构造成如下所述的可选管芯接合焊盘108a。
半导体管芯106在晶片100上形成为行和列，所述行和列通过在晶片100上的半导体管芯106之间提供的垂直和水平划线112彼此间隔开。划线112被保留为半导体管芯的有源区域周围的边界，其中可进行切割以将半导体管芯彼此分离以及与晶片100分离。
根据例如图3所示的本技术的各方面，可选管芯接合焊盘108a可通过金属互连件110电耦合到另一个(主)管芯接合焊盘108b。图3示出了虚线形式的金属互连件110，因为金属互连件110可被埋在形成于晶片100的上表面上的钝化层下面。图3还示出了从管芯接合焊盘108延伸的电迹线114。这些电迹线可连接到半导体管芯106内的集成电路和其他部件(仅示出这些迹线114的部分)。
金属互连件110可以多种方法中的任一种在晶片层级形成。在一个实施方案中，在形成接合焊盘108之前，当金属互连层和通孔在晶片内沉积时可形成金属互连件110。在这种实施方案中，金属互连件将形成在半导体管芯106的比管芯接合焊盘108更远离主表面102的层级处。
在另一个实施方案中，金属互连件110可以与形成管芯接合焊盘108和迹线114相同的工艺限定。具体地讲，可在晶片100上铺设铝层，例如通过薄膜沉积，然后可使用例如各种光刻工艺将铝层蚀刻到限定图案中。该图案可包括管芯接合焊盘108、金属互连件110和电迹线114。在该实施方案中，金属互连件110将处于与管芯接合焊盘108相同的层级。
在另一个实施方案中，金属互连件110可在形成接合焊盘108之后形成为在主管芯焊盘108b和可选管芯焊盘108a之间的RDL(再分布层)迹线。该再分布层可通过将钝化层沉积在晶片的表面上，并且蚀刻该钝化层以暴露该管芯接合焊盘108而形成。此后，金属互连件110可光刻形成或印刷在钝化层的顶部上，在主管芯接合焊盘108b与可选管芯接合焊盘108a之间。在实施方案中，另外的钝化层可形成在金属互连件110的顶部上。在该实施方案中，金属互连件110将处于比管芯接合焊盘108高的层级(更接近表面102)。
根据本技术的另一个方面，可选管芯接合焊盘108a可用彼此电隔离的第一导电部分和第二导电部分形成。这些第一导电部分和第二导电部分的功能解释如下，但是当在步骤206中形成接合焊盘108时，可在可选接合焊盘108a中限定第一导电部分和第二导电部分。具体地讲，当将铝层沉积在晶片上并蚀刻到管芯接合焊盘和迹线的图案中时，焊盘108a可被图案化以包括两个电隔离部分。
当将完成的半导体管芯组装到半导体封装中时将形成可选管芯接合焊盘和主管芯接合焊盘108a、108b的管芯接合焊盘的位置在晶片层级是已知的，并且可以是用于在晶片100内限定集成电路和金属层的地图的一部分。图1示出了晶片中每个半导体管芯上相同位置处的主管芯接合焊盘和可选管芯接合焊盘。可以设想，在另外的实施方案中，主管芯接合焊盘和可选管芯接合焊盘(由金属互连件110连接)可设置在晶片100上的不同半导体管芯106上的不同管芯接合对处。
虽然附图示出了每个半导体管芯上的单对主管芯接合焊盘和可选管芯接合焊盘，但半导体管芯中的一者或多者可不包括或包括不止一对主管芯接合焊盘和可选管芯接合焊盘。还应当理解，形成图中所示的主管芯接合焊盘和可选管芯接合焊盘的特定对的管芯接合焊盘仅以举例的方式示出，并且在另外的实施方案中，其他对的管芯接合焊盘可以是主管芯接合焊盘和可选管芯接合焊盘。
在步骤206中，在晶片100中形成金属焊盘和互连件之后，晶片100可通过在步骤210中磨削晶片的非活性表面而被翻转并支撑在承载器上以使晶片100变薄。此后，晶片可在步骤212中被切块。晶片通过多种切割装置包括通过锯片被切块。在另外的实施方案中，可在磨削步骤之前使用隐形切块将晶片切块。在此类实施方案中，晶片100可在回磨削步骤210之前在步骤212中被切块。
图4示出了半导体管芯106从晶片100分离之后的顶视图。管芯106包括管芯接合焊盘108，该管芯接合焊盘具有可选管芯接合焊盘108a，该可选管芯接合焊盘通过金属互连件110连接到主管芯接合焊盘108b。半导体管芯106可例如为存储器管芯诸如NAND闪存存储器管芯，但是可使用其他类型的管芯106。这些其他类型的半导体管芯包括但不限于控制器管芯诸如ASIC，或RAM诸如SDRAM。
图5为示出可选管芯接合焊盘108a的附加细节的放大视图。焊盘108a包括第一内部部分120，该第一内部部分电耦合到从焊盘108a延伸的迹线114。焊盘108a还包括围绕内部部分120的第二外部部分122。外部部分122通过围绕内部部分120的间隙124与内部部分120电隔离。虽然显示为圆形，但内部和/或外部部分120、124可为多种其他形状，包括正方形、矩形、椭圆形、长方形和多边形。外部部分122通过金属互连件110电耦合至具有主管芯接合焊盘108b的公共电压状态。
这些图示出了与主管芯接合焊盘108b紧紧相邻(紧挨)的可选管芯接合焊盘108a。然而，在另外的实施方案中，可选管芯接合焊盘108a可通过一个或多个其他管芯接合焊盘108与主管芯接合焊盘108b分开。在此类实施方案中，可选管芯接合焊盘和主管芯接合焊盘108a、108b仍将通过金属互连件110彼此连接。
单独的半导体管芯106可被封装在一起形成半导体装置130，如现在将参考图6的流程图和图7至图12的示意图所阐述的。在步骤230中，可将多个半导体管芯106堆叠在衬底140上，如图7的透视图中所示。半导体管芯106可在偏移的阶梯形构型中彼此堆叠以形成管芯叠堆152。实施方案可包括管芯叠堆152中不同数目的半导体管芯106，包括例如1、2、4、8、16、32或64管芯。在叠堆152的另外的实施方案中可存在其他数目的管芯。使用每个管芯106的底表面上的DAF(管芯粘附膜)层，可将该管芯固定于衬底和/或彼此。
虽然未示出，一个或多个无源部件可另外地固定于衬底140。所述一个或多个无源部件可包括例如一个或多个电容器、电阻器和/或电感器，尽管也设想了其他部件。
半导体管芯106和衬底140之间的电互连可在步骤232中形成。如图7所示，半导体管芯106经由焊线154(其中一个在图7中编号)电耦合到彼此以及衬底140，所述焊线固定到叠堆152中每个管芯106上的管芯接合焊盘108。焊线154可根据一些方案形成。然而，在一个实施方案中，焊线毛细管(未示出)在第一管芯106-1的第一管芯接合焊盘108上形成球状凸块156。从那里，该焊线毛细管铺展线迹并在衬底140的接触焊盘148上形成针脚式接合。然后，焊线毛细管使线迹断裂，向上移动到第二管芯106-2的第一管芯接合焊盘108，并形成球状凸块156。从那里，该焊线毛细管铺展线迹，并在管芯106-1的第一管芯接合焊盘上的球状凸块156顶部形成针脚式接合。
此过程沿着管芯叠堆继续直到管芯106-1、106-2、106-3、106-4等上的第一管芯接合焊盘108彼此丝焊并且丝焊到衬底140。然后对半导体装置130中的管芯106上的其他管芯接合焊盘中的每一者(除了如下文所述的可选管芯接合焊盘108a之外)重复该过程。如上所述，焊线154可通过在另外的实施方案中的其他方法形成。焊线154和球状凸块156可由金形成，但在另外的实施方案中可由其他材料形成。
如上所述，本技术允许冗余电连接到一对管芯接合焊盘108a和108b。在没有至一对冗余接合焊盘中的可选管芯接合焊盘108a焊线或来自一对冗余接合焊盘中的可选管芯接合焊盘的焊线的情况下完成此冗余。如例如图7中所示，不形成至可选管芯接合焊盘108a或来自该可选管芯接合焊盘的焊线。虽然图7示出了可选管芯接合焊盘108a(其中没有一个具有焊线)的整个列，但应当理解，可选管芯接合焊盘108a可占据小于整个列的管芯接合焊盘。此外，可选管芯接合焊盘108a可在另外的实施方案中处于不同管芯上的不同列中。
在实施方案中，本技术提供了使管芯接合焊盘在功能上冗余或没有冗余的选项。在图7和图8的实施方案中，可选管芯接合焊盘108a未被使用(非冗余)。即，假定内部部分120和外部部分122在焊盘108a上彼此电隔离，则至主管芯接合焊盘108b的信号或来自该主管芯接合焊盘的信号不由可选管芯接合焊盘108a共享。
根据本技术的各方面，可选管芯接合焊盘108a可通过使可选管芯焊盘108a的内部部分120与外部部分122电耦合而变得对于管芯接合焊盘108b冗余。具体地讲，通过电耦合内部部分和外部部分120、122，可选管芯接合焊盘和主管芯接合焊盘108a、108b可凭借其通过金属互连件110的连接来共享相同的电压状态。这可通过在内部部分和外部部分120、122两者上沉积导电材料来完成。
虽然内部部分和外部部分120、122可通过多种方案电耦合，但在一个实施方案中，导电材料包括球状凸块156，该球状凸块在可选管芯接合焊盘108a上形成，如图9和图10所示。球状凸块156覆盖可选管芯接合焊盘108a的很大一部分，并且物理接触焊盘108a的内部部分120(在图9和图10中被覆盖)和外部部分122两者。
使用球状凸块156来使可选管芯接合焊盘108a冗余，其具有如下优点：其在上述球状凸块和丝焊过程期间可沉积，以将另一个管芯接合焊盘108彼此丝焊并丝焊到衬底140。具体地讲，当焊线毛细管到达可选管芯接合焊盘108a时，毛细管可在可选管芯接合焊盘108a上沉积球状凸块156，然后拉离使线迹断裂并且仅留下球状凸块156。因此，可选管芯接合焊盘108a可被制成冗余而不增加额外的工艺步骤。球状凸块156是由可选管芯接合焊盘108a上的毛细管形成(从而提供冗余)还是通过毛细管跳过(从而省略冗余)是针对给定半导体装置130预先确定的，并且被编程到控制器中以用于焊线毛细管。
如所指出的，可选管芯接合焊盘108a的内部部分和外部部分120、122可使用除球状凸块156之外的导电材料电耦合。在另外的实施方案中，焊料可被施加到可选管芯接合焊盘108a作为糊剂、球或凸块，以将内部部分和外部部分120、122电耦合。这可在丝焊其他管芯接合焊盘的步骤之前或之后进行。
图7至图10所示的半导体装置130还可包括丝焊到衬底140上以用于控制半导体管芯106的控制器管芯160(图11)诸如ASIC。在如图10所示的步骤234中，装置130可被封装在模具化合物162中。在步骤236中，可任选地将焊料球(未示出)固定到衬底140的下表面。在步骤238中，半导体装置130的制造可通过从此类装置的面板中分离出相应的半导体装置来完成。
上述实施方案显示了使一对管芯接合焊盘对于彼此冗余的能力。在另外的实施方案中，可使两个以上的管芯接合焊盘对彼此冗余。在此类实施方案中，三个或更多个管芯接合焊盘可通过共同金属互连件110彼此电耦合，并且这些管芯接合焊盘中的一者或多者可包括电隔离部分，该电隔离部分可例如与球状凸块156联接在一起以增加冗余。
根据本技术的各方面，两个或更多个管芯接合焊盘可被制成冗余的，而无需脱离单个管芯接合焊盘的多条焊线。与形成例如脱离单个管芯接合焊盘的三条焊线的常规系统相比，这提高了冗余管芯接合焊盘的可靠性。另外，使用金球状凸块而不是金焊线减少了所使用的金的量，并且可降低制造成本。另外，使用金属互连件110和球状凸块156提供了一种牢固且高度可靠的方法，该方法与常规的丝焊技术相比提供冗余管芯接合焊盘。
在上述实施方案中，可选管芯接合焊盘的内部部分和外部部分提供了使可选管芯接合焊盘108a冗余或非冗余的灵活性。然而，可设想的是，不需要这种灵活性，并且已知在晶片层级一对管芯接合焊盘将对于彼此冗余。在此类实施方案中，可选管芯接合焊盘108a的内部部分和外部部分可被省略，并且可选管芯接合焊盘108a可简单地包括与在其他管芯接合焊盘108中一样的导体的均匀表面层。此类实施方案例如在图12中示出。在该实施方案中，可选管芯接合焊盘108a通过如上所述的金属互连件110连接到主管芯接合焊盘108b。
总之，本技术涉及一种半导体管芯，包括：多个管芯接合焊盘，该多个管芯接合焊盘包括第一管芯接合焊盘和第二管芯接合焊盘，该第二管芯接合焊盘被配置为向第一管芯接合焊盘提供功能冗余；以及金属互连件，该金属互连件具有第一端和第二端，该第一端连接至第一管芯接合焊盘，该第二端与第一端相对并且连接至第二管芯接合焊盘的至少一部分。
在又一示例中，本技术涉及半导体管芯，包括：第一主表面；第二主表面，该第二主表面与第一主表面相对；集成电路，该集成电路与第一主表面相邻形成；多个管芯接合焊盘，该多个管芯接合焊盘包括：第一管芯接合焊盘和第二管芯接合焊盘，该第一管芯接合焊盘电耦合至第一集成电路，该第二管芯接合焊盘被配置为任选地充当第一管芯接合焊盘的冗余管芯接合焊盘，该第二管芯接合焊盘包括：第一部分和第二部分，该第一部分电耦合至第一管芯接合焊盘，该第二部分与第一部分电隔离。
在另一示例中，本技术涉及半导体装置，包括：衬底；安装到衬底上的多个堆叠半导体管芯，所述堆叠半导体管芯的半导体管芯包括：第一管芯接合焊盘、第二管芯接合焊盘以及导电材料，该第二管芯接合焊盘被配置为任选地充当第一管芯接合焊盘的冗余管芯接合焊盘，其中第二管芯接合焊盘在导电材料被施加在第二管芯接合焊盘的表面上时充当第一管芯接合焊盘的冗余管芯接合焊盘。
在又一示例中，本技术涉及使用一对管芯接合焊盘制造半导体装置的方法，所述一对管芯接合焊盘位于半导体管芯上且任选地对彼此冗余，所述方法包括以下步骤：(a)在半导体管芯上形成该对管芯接合焊盘的第一管芯接合焊盘；(b)在半导体管芯上形成该一对管芯接合焊盘的具有电隔离的第一部分和第二部分的第二管芯接合焊盘；以及(c)将第一管芯接合焊盘电耦合至第二管芯接合焊盘的第一部分。
在另一示例中，本技术涉及半导体管芯，该半导体管芯由半导体晶片形成，该半导体晶片包括：第一主表面；第二主表面，该第二主表面与第一主表面相对；集成电路，该集成电路与第一主表面相邻形成；第一焊盘装置和第二焊盘装置，该第一焊盘装置用于接纳第一球状凸块，该第二焊盘装置用于任选地充当第一焊盘装置的冗余管芯接合焊盘。
已出于例证和描述的目的提出本发明的上述详细描述。它并非旨在是穷尽的或将本发明限制为所公开的精确形式。根据以上教导内容，很多修改形式和变型形式都是可能的。选择所述实施方案是为了最佳地阐明本发明的原理及其实际应用，以便由此使得本领域的其他技术人员能够最佳地使用具有适合于所构想的特定用途的各种修改的本发明以及各种实施方案。本发明的范围旨在由所附权利要求书限定。

Claims (19)

1.一种半导体管芯，包括：
多个管芯接合焊盘，包括：
第一管芯接合焊盘，和
第二管芯接合焊盘，所述第二管芯接合焊盘被配置为向所述第一管芯接合焊盘提供功能冗余；和
金属互连件，所述金属互连件具有第一端和第二端，所述第一端连接至所述第一管芯接合焊盘，所述第二端与所述第一端相对且连接至所述第二管芯接合焊盘的至少一部分。
2.根据权利要求1所述的半导体管芯，其中所述第二管芯接合焊盘包括第一部分和第二部分，所述第二部分与所述第一部分电隔离。
3.根据权利要求2所述的半导体管芯，其中所述第一管芯接合焊盘电耦合至所述第二管芯接合焊盘的所述第一部分。
4.根据权利要求1所述的半导体管芯，其中所述第二管芯接合焊盘具有单个均匀表面层。
5.根据权利要求1所述的半导体管芯，其中所述第一管芯接合焊盘和所述第二管芯接合焊盘沿所述半导体管芯的边缘彼此相邻。
6.一种半导体管芯，包括：
第一主表面；
第二主表面，所述第二主表面与所述第一主表面相对；
集成电路，所述集成电路与所述第一主表面相邻形成；
多个管芯接合焊盘，所述多个管芯接合焊盘包括：
第一管芯接合焊盘，所述第一管芯接合焊盘电耦合至第一集成电路，和
第二管芯接合焊盘，所述第二管芯接合焊盘被配置为任选地充当所述第一管芯接合焊盘的冗余管芯接合焊盘，所述第二管芯接合焊盘包括：
第一部分，所述第一部分电耦合至所述第一管芯接合焊盘，和
第二部分，所述第二部分与所述第一部分电隔离，所述第二部分具有圆形占用面积并具有从其延伸的电引线，除了所述第一部分与从所述第二部分延伸的所述电引线电隔离之外，所述第一部分围绕所述第二部分。
7.根据权利要求6所述的半导体管芯，其中当电连接所述第二管芯接合焊盘的所述第一部分和所述第二部分时，所述第二管芯接合焊盘充当所述第一管芯接合焊盘的冗余管芯接合焊盘。
8.根据权利要求6所述的半导体管芯，其中在所述第二管芯接合焊盘的所述第一部分和所述第二部分保持彼此电隔离的情况下，所述第二管芯接合焊盘不充当所述第一管芯接合焊盘的冗余管芯接合焊盘。
9.根据权利要求6所述的半导体管芯，还包括金属互连件，所述金属互连件在所述第一管芯接合焊盘与所述第二管芯接合焊盘的所述第一部分之间延伸、用于将所述第一管芯接合焊盘电耦合至所述第二管芯接合焊盘的所述第一部分。
10.根据权利要求9所述的半导体管芯，其中所述金属互连件由相同的材料形成，且与所述第一管芯接合焊盘和所述第二管芯接合焊盘相对于所述半导体管芯的第一主表面处于相同的层级。
11.根据权利要求9所述的半导体管芯，其中所述金属互连件由再分布层形成。
12.根据权利要求6所述的半导体管芯，其中所述半导体管芯是NAND闪存半导体管芯。
13.一种半导体装置，包括：
衬底；
安装到所述衬底上的多个堆叠半导体管芯，所述堆叠半导体管芯的半导体管芯包括：
第一管芯接合焊盘，
第二管芯接合焊盘，所述第二管芯接合焊盘被配置为任选地充当所述第一管芯接合焊盘的冗余管芯接合焊盘，以及
导电材料，其中当所述导电材料被施加在所述第二管芯接合焊盘的表面上时，所述第二管芯接合焊盘充当所述第一管芯接合焊盘的冗余管芯接合焊盘。
14.根据权利要求13所述的半导体装置，所述第二管芯接合焊盘包括：
第一部分，所述第一部分电耦合至所述第一管芯接合焊盘，和
第二部分，所述第二部分通过间隙与所述第一部分电隔离。
15.根据权利要求14所述的半导体装置，其中所述导电材料是沉积在所述第二管芯接合焊盘上的球状凸块。
16.根据权利要求14所述的半导体装置，其中所述导电材料是焊料糊剂、焊料球和焊料凸块中的一种。
17.根据权利要求14所述的半导体装置，还包括多个焊线和多个球状凸块，所述多个焊线和所述多个球状凸块将所述多个半导体管芯和所述衬底电互连，所述导电材料包括所述多个球状凸块中的球状凸块。
18.一种使用一对管芯接合焊盘制造半导体装置的方法，所述一对管芯接合焊盘位于半导体管芯上且任选地彼此冗余，所述方法包括以下步骤：
(a)在所述半导体管芯上形成所述一对管芯接合焊盘的第一管芯接合焊盘；
(b)在所述半导体管芯上形成所述一对管芯接合焊盘的第二管芯接合焊盘，所述第二管芯接合焊盘具有电隔离的第一部分和第二部分；以及
(c)将所述第一管芯接合焊盘电耦合至所述第二管芯接合焊盘的所述第一部分。
19.根据权利要求18所述的方法，还包括以下步骤：通过将导电材料沉积在所述第二管芯接合焊盘的所述第一部分和所述第二部分上来使所述第二管芯接合焊盘对所述第一管芯接合焊盘冗余。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10923462B2 (en) 2018-05-01 2021-02-16 Western Digital Technologies, Inc. Bifurcated memory die module semiconductor device
US10522489B1 (en) * 2018-06-28 2019-12-31 Western Digital Technologies, Inc. Manufacturing process for separating logic and memory array
KR20200073643A (ko) * 2018-12-14 2020-06-24 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
KR102677593B1 (ko) * 2019-05-28 2024-06-24 에스케이하이닉스 주식회사 인터커넥트 구조를 포함한 스택 패키지
KR20210090521A (ko) * 2020-01-10 2021-07-20 에스케이하이닉스 주식회사 본딩 와이어 분지 구조를 포함한 반도체 패키지
US11527508B2 (en) * 2020-03-03 2022-12-13 Micron Technology, Inc. Apparatuses and methods for coupling a plurality of semiconductor devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101964333A (zh) * 2009-05-26 2011-02-02 马维尔国际贸易有限公司 引线接合结构
CN102487021A (zh) * 2010-12-03 2012-06-06 新科金朋有限公司 形成用于倒装半导体管芯的焊盘布局的半导体器件和方法
CN103887191A (zh) * 2012-12-20 2014-06-25 新科金朋有限公司 半导体器件和制作无凸块倒装芯片互连结构的方法
CN106298715A (zh) * 2015-06-25 2017-01-04 台湾积体电路制造股份有限公司 混合接合焊盘结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4982892A (en) * 1989-11-09 1991-01-08 International Business Machines Corporation Solder interconnects for selective line coupling
US6991970B2 (en) * 2001-08-30 2006-01-31 Micron Technology, Inc. Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of semiconductor device
JP3865055B2 (ja) 2001-12-28 2007-01-10 セイコーエプソン株式会社 半導体装置の製造方法
KR100690922B1 (ko) * 2005-08-26 2007-03-09 삼성전자주식회사 반도체 소자 패키지
KR101604605B1 (ko) * 2009-09-24 2016-03-21 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR20130042210A (ko) 2011-10-18 2013-04-26 삼성전자주식회사 멀티-칩 패키지 및 그의 제조 방법
US9613914B2 (en) * 2011-12-07 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure
KR102108325B1 (ko) * 2013-10-14 2020-05-08 삼성전자주식회사 반도체 패키지
KR102299673B1 (ko) * 2014-08-11 2021-09-10 삼성전자주식회사 반도체 패키지

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101964333A (zh) * 2009-05-26 2011-02-02 马维尔国际贸易有限公司 引线接合结构
CN102487021A (zh) * 2010-12-03 2012-06-06 新科金朋有限公司 形成用于倒装半导体管芯的焊盘布局的半导体器件和方法
CN103887191A (zh) * 2012-12-20 2014-06-25 新科金朋有限公司 半导体器件和制作无凸块倒装芯片互连结构的方法
CN106298715A (zh) * 2015-06-25 2017-01-04 台湾积体电路制造股份有限公司 混合接合焊盘结构

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