CN102487021A - 形成用于倒装半导体管芯的焊盘布局的半导体器件和方法 - Google Patents
形成用于倒装半导体管芯的焊盘布局的半导体器件和方法 Download PDFInfo
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Abstract
本发明涉及形成用于倒装半导体管芯的焊盘布局的半导体器件和方法。一种半导体器件具有带有管芯焊盘布局的半导体管芯。管芯焊盘布局中的信号焊盘主要位于半导体管芯周边附近,并且功率焊盘和接地焊盘主要位于自信号焊盘的内侧。信号焊盘被布置成大体上平行于半导体管芯边缘的周边行或周边阵列。在信号焊盘、功率焊盘和接地焊盘上形成凸块。凸块可以具有可熔部分和非可熔部分。在基底上形成具有互连点的导电迹线。凸块比互连点宽。所述凸块被结合到互连点,使得凸块覆盖互连点的顶面和侧面。在半导体管芯与基底之间的凸块周围沉积密封剂。
Description
国内优先权要求
本申请是2009年4月29日提交的美国申请No. 12/432,137的部分继续申请,并根据美国法典第35条120款要求前述申请的优先权。
技术领域
本发明涉及半导体器件,并且更特别地涉及形成用于倒装(flipchip)半导体管芯的焊盘布局的半导体器件和方法。
背景技术
在现代电子产品中常常发现半导体器件。半导体器件在电气组件的数目和密度方面不同。分立半导体器件通常包含一种类型的电气组件,例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包括几百个至几百万个电气组件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳电池和数字微镜器件(DMD)。
半导体器件执行大范围的功能,诸如信号处理、高速计算、传送和接收电磁信号、控制电子器件、将日光变换成电和产生用于电视显示的可视投影。半导体器件被用于娱乐、通信、功率转换、网络、计算机和消费者产品领域。半导体器件还被用于军事应用、航空、汽车、工业控制器和办公室设备。
半导体器件利用半导体材料的电气性质。半导体材料的原子结构允许通过施加电场或基电流或通过掺杂的过程来操纵其导电性。掺杂向半导体材料中引入杂质以操纵并控制半导体器件的导电性。
半导体器件包含有源和无源电气结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂的水平和电场或基电流的施加,晶体管促进或限制电流的流动。包括电阻器、电容器和电感器的无源结构产生执行多种电功能所需的电压与电流之间的关系。无源和有源结构被电连接以形成电路,该电路使得半导体器件能够执行高速计算及其它有用功能。
通常使用每个包括可能几百个步骤的两个复杂的制造过程、即前端制造和后端制造来制造半导体器件。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常是相同的并包含通过将有源和无源组件电连接而形成的电路。后端制造包括从成品晶片单颗化单独的管芯并将该管芯封装以提供结构支撑和环境隔离。
半导体制造的一个目的是生产较小的半导体器件。较小的器件通常消耗较少的功率,具有较高的性能,并且能够更高效地生产。另外,较小的半导体器件具有较小的覆盖区,这对于较小的最终产品是期望的。可以通过前端过程的改进来实现更小的管芯尺寸,导致管芯具有更小、更高密度的有源和无源组件。后端过程可以通过电互连和封装材料的改进来产生具有更小覆盖区的半导体器件封装。
在倒装式封装中,半导体管芯通常被安装到封装基底,管芯的有源侧与基底相对。以凸块的方式来实现半导体管芯中的电路与基底中的电路的互连,所述凸块被附着于管芯上的互连焊盘阵列,并被结合到基底上的互连焊盘的相应互补阵列。
用于信号、功率和接地功能的半导体管芯上的焊盘按照惯例遍布于阵列分布,并且基底上的相应焊盘被连接到适当的电路至外部二级互连。二级互连具有比倒装互连更大的节距,并且因此基底上的布线按照惯例呈扇形展开。在封装基底内的多个金属层上形成半导体管芯上的焊盘与封装的外部管脚之间的扇形展开布线。
多个层基底是昂贵的,并且在常规倒装结构中,基底通常单独地占了一大半的封装成本。多层基底的高成本已经是限制主流产品中的倒装技术发展的因素。在常规倒装构造中,逸出布线图案通常引入附加的电寄生,因为布线包括信号传输路径中的配线层之间的短行程的非屏蔽配线和过孔(via)。电寄生能够显著地限制封装性能。
在常规倒装封装中,如在图1中的10处大体上在平面图中所示,半导体管芯13上的共同称为信号焊盘的输入/输出焊盘被布置成基本上覆盖管芯的有源表面12的面积阵列。分别针对半导体管芯13的信号、功率和接地功能的信号焊盘18和19、功率焊盘14和接地焊盘16遍布于阵列内的多个行和列。特别地,某些信号焊盘18被布置在阵列的周边上,而其它信号焊盘19没有。通常,进行某些设计努力以布置焊盘,使得各种信号焊盘被功率焊盘和/或接地焊盘围绕或至少邻近于功率焊盘和/或接地焊盘。
许多常规倒装封装是使用陶瓷基底制造的。可以相对经济地用许多层来制造陶瓷基底,并且可以容易地在陶瓷层中制造盲孔。在为了与常规陶瓷基底一起使用而制造的常规芯片中,焊盘节距通常在150微米(μm)至250μm范围内,并且225μm的栅距是许多芯片的典型。
在被图案化的多个金属层中实现基底中的扇形展开布线、亦即将基底上的相应焊盘与封装的外部端子相连的基底上的配线,以提供信号配线及功率和接地配线。在图2中的20处大体上以平面图示出与管芯焊盘布局10相对应的基底焊盘的布置。信号焊盘28和29、功率焊盘24和接地焊盘26被布置成基底表面22上的互补阵列,使得其能够接纳并分别被结合到被附着于管芯上的相应焊盘的信号、功率和接地凸块。在常规布置中,与信号布线相关联的某些焊盘28位于阵列的周边处,而其它焊盘29不是。用于阵列周边上的信号焊盘的逸出布线可以直接在管芯边缘23下面穿过作为基底的最高金属层中的迹线30。不在阵列周边处的基底上的焊盘被经由短迹线和过孔连接到基底中的更深金属层。信号焊盘29经由短迹线(信号支柱或凸出部分(jog))32通过信号过孔34连接到下面的多个金属层之一中的信号迹线。同样地,功率焊盘24经由短迹线(功率支柱或凸出部分)36通过功率过孔38连接到下面的金属层中的功率迹线,并且接地焊盘26经由短迹线(接地支柱或凸出部分)40通过接地过孔42连接到下面的金属层中的功率迹线。
在具有约1000个外部端子的典型常规封装中,在基底中存在至少2或3层信号配线和至少4或5层功率和接地配线,这产生总量约6或8个或更多层。通常,信号配线层的数目的增加由于需要保持封装中的传输线电气环境而要求伴随的功率和接地层的增加,这进一步增加总层计数。对附加层的需要还导致更长的信号路径和许多层间过孔,增加不期望的电寄生并性能劣化。
发明内容
需要一种管芯焊盘布局以容纳对于倒装半导体管芯所需要的信号焊盘以及功率焊盘和接地焊盘,同时增加布线密度并使互连层的必需数目最小化。因此,在一个实施例中,本发明是一种制造半导体器件的方法,包括步骤:提供半导体管芯,该半导体管芯具有信号焊盘主要位于半导体管芯的周边区域中且功率焊盘和接地焊盘主要位于半导体管芯的自信号焊盘的内侧区域中的管芯焊盘布局;在信号焊盘、功率焊盘和接地焊盘上形成多个凸块;提供基底;以及在该基底上形成具有互连点的多个导电迹线。凸块比互连点宽。所述方法还包括步骤:将凸块结合到互连点,使得凸块覆盖互连点的顶面和侧面、以及在半导体管芯与基底之间的凸块周围沉积密封剂。
在另一实施例中,本发明是一种制造半导体器件的方法,包括步骤:提供半导体管芯、提供基底、在基底上形成具有以信号点位于基底周边附近且功率点和接地点位于自信号点的内侧的布局布置的互连点的多个导电迹线、以及在半导体管芯与基底之间形成互连结构,使得互连结构覆盖互连点的顶面和侧面。
在另一实施例中,本发明是制造半导体器件的方法,包括步骤:提供半导体管芯、提供基底、在基底上形成具有以信号点主要位于基底的周边区域中且功率点和接地点主要位于基底的自信号焊盘的内侧区域中的布局布置的互连点的多个导电迹线、将半导体管芯结合到互连点、以及在半导体管芯与基底之间沉积密封剂。
在另一实施例中,本发明是一种包括半导体管芯的半导体器件,所述半导体管芯具有信号焊盘主要位于半导体管芯的周边区域中且功率焊盘和接地焊盘主要位于半导体管芯的自信号焊盘的内侧区域中的管芯焊盘布局。在基底上形成具有互连点的多个导电迹线。将半导体管芯结合到互连点。在半导体管芯与基底之间沉积密封剂。
附图说明
图1在平面图中举例说明用于倒装封装的管芯上的常规焊盘布局;
图2在平面图中举例说明倒装基底上的焊盘和布线的布置;
图3举例说明具有安装到其表面的不同类型的封装的PCB;
图4a—4c举例说明被安装到PCB的半导体封装的更多细节;
图5举例说明用于倒装封装的管芯上的焊盘布局;
图6举例说明倒装基底上的焊盘和布线的布置;
图7举例说明具有管芯焊盘布局和基底焊盘布置的安装在基底上的倒装的一部分;
图8a—8b举例说明用于倒装封装的管芯上的第一焊盘布局;
图9a~9b举例说明用于倒装封装的管芯上的第二焊盘布局;
图10a~10b举例说明用于倒装封装的管芯上的第三焊盘布局;
图11a~11b举例说明用于倒装封装的管芯上的第四焊盘布局;
图12a~12h举例说明在半导体管芯上形成以便结合到基底上的导电迹线的各种互连结构;
图13a~13g举例说明被结合到导电迹线的半导体管芯和互连结构;
图14a~14d举例说明具有被结合到导电迹线的楔形互连结构的半导体管芯;
图15a~15d举例说明被结合到导电迹线的半导体管芯和互连结构的另一实施例;
图16a~16c举例说明被结合到导电迹线的台阶式凸块和支柱凸块互连结构;
图17a~17b举例说明具有导电过孔的导电迹线;
图18a~18c举例说明半导体管芯与基底之间的模底部填充;
图19举例说明半导体管芯与基底之间的另一模底部填充;
图20举例说明模底部填充之后的半导体管芯和基底;
图21a~21g举例说明具有开放焊料套准(registration)的导电迹线的各种布置;
图22a~22b举例说明与导电迹线之间的贴片的开放焊料套准;以及
图23举例说明具有掩蔽层屏障(dam)以在模底部填充期间限制密封剂的POP。
具体实施方式
在以下说明中参考附图在一个或多个实施例中描述本发明,在附图中相同的附图标记表示相同或类似的元件。虽然依照用于实现本发明的目的的最佳方式描述了本发明,但本领域的技术人员应认识到意图在与覆盖可以被包括在由所附权利要求和由以下公开和附图支持的其等价物限定的本发明的精神和范围内的替换、修改和等价物。
通常使用两个复杂的制造过程:前端制造和后端制造来制造半导体器件。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电气组件,其被电连接而形成功能电路。诸如晶体管和二极管的有源电气组件具有控制电流流动的能力。诸如电容器、电感器、电阻器和变压器的无源电气组件产生执行电路功能所需的电压与电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻和平面化的一系列过程步骤在半导体晶片的表面上形成无源和有源组件。掺杂通过诸如离子注入或热扩散的技术向半导体材料中引入杂质。掺杂过程修改有源器件中的半导体材料的导电性,将半导体材料变换成绝缘体、导体,或响应于电场或基电流来动态地改变半导体材料导电性。晶体管包含根据需要来改变所布置的掺杂的类型和程度的区域以使晶体管能够在施加电场或基电流时促进或限制电流的流动。
有源和无源组件由具有不同电气性质的材料层形成。可以通过部分地由正在沉积的材料的类型确定的多种沉积技术来形成该层。例如,薄膜沉积可以包括化学汽相沉积(CVD)、物理汽相沉积(PVD)、电解镀覆和化学镀覆过程。每个层通常被图案化以形成有源组件、无源组件或组件之间的电连接的一部分。
可以使用光刻法对层进行图案化,光刻法包括例如光致抗蚀剂的感光材料在要图案化的层上的沉积。使用光将图案从光掩膜转印到光致抗蚀剂。使用溶剂来去除经历光的光致抗蚀剂图案的一部分,使要图案化的底层的一部分暴露。去除其余的光致抗蚀剂,留下被图案化的层。可替换地,通过将材料直接沉积到由使用诸如化学或电解镀覆的技术的前述沉积/蚀刻过程形成的区域或空隙中来对某些类型的材料进行图案化。
在现有图案上沉积材料薄膜能够将底层图案放大并产生非均匀平面。要求均匀平面以产生更小且更密集地封装的有源和无源组件。可以使用平面化来从晶片的表面去除材料并产生均匀平面。平面化包括用抛光垫对晶片的表面进行抛光。可以在抛光期间向晶片的表面添加研磨材料和腐蚀性化学制品。化学制品的研磨和腐蚀动作的组合机械动作去除了任何不规则外貌(topography),产生均匀平面。
后端制造指的是将成品晶片切割或单颗化成单独管芯并随后将管芯封装以进行结构支撑和环境隔离。为了单颗化管芯,沿着称为锯道(saw streets)或划线的晶片的非功能区域刻划并折断晶片。使用激光切割工具或锯条来单颗化晶片。在单颗化之后,将单独管芯安装到封装基底,该封装基底包括用于与其它系统组件互连的引脚或接触焊盘。然后将半导体管芯上形成的接触焊盘连接到封装内的接触焊盘。可以用焊料凸块、支柱凸块、导电膏、或引线结合来实现电连接。在封装上沉积密封剂或其它成型材料以提供物理支撑和电隔离。然后将成品封装插入电气系统中并使得半导体器件的功能可用于其它系统组件。
图3举例说明具有芯片载体基底的电子器件50或具有安装在其表面上的多个半导体封装的印刷电路板(PCB)52。根据应用,电子器件50具有一种类型的半导体封装,或多种类型的半导体封装。出于举例说明的目的,在图3中示出不同类型的半导体封装。
电子器件50可以是使用半导体封装来执行一个或多个电功能的独立系统。可替换地,电子器件50可以是较大系统的子组件。例如,电子器件50可以是蜂窝式电话、个人数字助理(PDA)、数字视频照相机(DVC)或其它电子通信设备的一部分。可替换地,电子器件50可以是图形卡、网络接口卡或可以被插入计算机中的其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电气组件。小型化和重量减小对于这些产品被市场接受而言是必不可少的。必须减小半导体器件之间的距离以实现较高的密度。
在图3中,PCB 52提供用于安装在PCB上的半导体封装的电互连和支撑结构的一般基底。使用蒸发、电解镀覆、化学镀覆、丝网印刷或其它适当的金属沉积过程在PCB 52的表面上或层内形成导电信号迹线54。信号迹线54提供半导体封装、安装组件与其它外部系统组件中的每一个之间的电通信。迹线54还向每个半导体封装提供功率和接地连接。
在某些实施例中,半导体器件具有两个封装级。一级封装是用于将半导体管芯机械地和电气地附着于中间载体的技术。二级封装包括将中间载体机械地和电气地附着于PCB。在其它实施例中,半导体器件可以仅具有一级封装,其中管芯被机械地和电气地直接安装到PCB。
出于举例说明的目的,在PCB 52上示出了多种类型的一级封装,包括引线结合封装56和倒装58。另外,示出了安装在PCB 52上的多种类型的二级封装,包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、基板格栅阵列(LGA)66、多芯片模块(MCM)68、四方扁平无引线封装(QFN)70和四方扁平封装72。根据系统要求,可以将配置有一级和二级封装样式的任何组合的半导体封装的任何组合以及其它电子组件连接到PCB 52。在某些实施例中,电子器件50包括单个附着半导体封装,而其它实施例要求多个互连封装。通过在单个基底上将一个或多个半导体封装组合,制造商可以将预制组件结合到电子器件和系统中。由于半导体封装包括精密功能,所以可以使用更廉价的组件和流水线制造过程来制造电子器件。结果得到的器件很少会出现故障,并且制造起来价格比较低廉,为消费者产生较低的成本。
图4a~4c示出了示例性半导体封装。图4a举例说明安装在PCB 52上的DIP 64的其它细节。半导体管芯74包括有源区,该有源区包含被实现为有源器件、无源器件、导电层、和电介质层的模拟或数字电路,其在管芯内形成并根据管芯的电气设计被电互连。例如,电路可以包括在半导体管芯74的有源区内形成的一个或多个晶体管、二极管、电感器、电容器、电阻器及其它电路元件。接触焊盘76是一层或多层导电材料,诸如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag),并被电连接到在半导体管芯74内形成的电路元件。在DIP 64的组装期间,使用金硅共熔层或诸如热环氧物或环氧树脂的粘合材料将半导体管芯74安装到中间载体78。封装主体包括诸如聚合物或陶瓷的绝缘封装材料。导体引线80和结合引线82提供半导体管芯74与PCB 52之间的电互连。通过防止水分和颗粒进入封装并污染管芯74或结合引线82来在封装上沉积密封剂84以进行环境保护。
图4b举例说明安装在PCB 52上的BCC 62的其它细节。使用底部填充或环氧树脂粘合材料92来将半导体管芯88安装在载体90上。结合引线94提供接触焊盘96与98之间的一级封装互连。在半导体管芯88和结合引线94上沉积成型化合物或密封剂100以便为器件提供物理支撑和电绝缘。使用诸如电解镀覆或化学镀覆的适当金属沉积过程来在PCB 52的表面上形成接触焊盘102以防止氧化。接触焊盘102被电连接到PCB 52中的一个或多个导电信号迹线54。在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间形成凸块104。
在图4c中,用倒装样式的一级封装将半导体管芯58安装为面向下朝向中间载体106。半导体管芯58的有源区108包含被实现为根据管芯的电气设计形成的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如,该电路可以在有源区108内包括一个或多个晶体管、二极管、电感器、电容器、电阻器及其它电路元件。半导体管芯58通过凸块110被电气地和机械地连接到载体106。
BGA 60使用凸块112以BGA样式的二级封装被电气地和机械地连接到PCB 52。半导体管芯58通过凸块110、信号线114和凸块112被电连接到PCB 52中的导电信号迹线54。在半导体管芯58和载体106上沉积成型化合物或密封剂116以便为器件提供物理支撑和电隔离。倒装半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离,降低电容,并改善总电路性能。在另一实施例中,可以在没有中间载体106的情况下使用倒装样式的一级封装将半导体管芯58机械地和电气地直接连接到PCB 52。
在倒装互连焊盘布局中,所有或基本上所有信号焊盘位于半导体管芯的边缘部分和相应的封装基底中。管芯信号焊盘被布置在半导体管芯周边附近的管芯表面上,并且管芯功率和接地焊盘被布置在自信号焊盘的内侧的管芯表面上。以与管芯焊盘布局互补的方式来布置相应封装基底上的信号焊盘。从远离管芯覆盖区的管芯边缘下面的信号焊盘为信号线布线,并且将功率和接地线布线到管芯覆盖区下面的过孔。
焊盘布局在芯片边缘处提供高信号迹线逸出布线密度。封装基底具有较少金属层,使得可以以明显更低的成本实现使用焊盘布局构造的封装。由于存在较少的金属层,并且由于减少了过孔的数目或从信号传输路径完全去除,所以减少了电寄生且封装能够具有改善的性能。
用于倒装互连的管芯焊盘布局可以具有主要位于半导体管芯周边附近的信号焊盘和主要位于自信号焊盘的内侧的接地和功率焊盘。可以将信号焊盘布置成大体上与管芯边缘平行的行。可替换地,将信号焊盘布置成与管芯边缘平行的两行或更多行阵列。在某些实施例中,使相邻行中的焊盘交错。将上面设置有信号焊盘的行或阵列的半导体管芯的区域称为管芯的周边区域。
在其它实施例中,将接地和功率焊盘布置成半导体管芯中心附近的矩形阵列。可替换地,半导体管芯的中心区域不具有焊盘。还可以将功率和接地焊盘布置成与信号焊盘附近的管芯边缘平行的行,或与信号焊盘附近的管芯边缘平行的两行或更多行阵列。将上面设置有功率和接地焊盘的行或阵列的半导体管芯区域称为管芯的内侧区域。
图5示出管芯焊盘布局120的实施例。信号焊盘122以与管芯边缘126平行的行布置在半导体管芯周边附近的管芯表面124上。信号焊盘122具有比图1的常规混合焊盘阵列中的焊盘更精细的节距。功率焊盘128和接地焊盘130在管芯表面124的内侧区域上被布置成阵列。管芯表面124的中心区域132没有任何焊盘,包括功率焊盘128和接地焊盘130。
在图6中的134处大体上在平面图中示出对应于图5的管芯焊盘布局120的基底焊盘布置。信号焊盘136、功率焊盘138和接地焊盘140被布置成基底表面142上的互补阵列,使得其能够接纳并分别被结合到被附着于半导体管芯上的相应焊盘的信号、功率和接地凸块。在此布置中,与信号布线相关联的所有焊盘136位于阵列周边处,并且用于阵列周边上的信号焊盘的逸出布线可以直接在管芯边缘144下面穿过作为基底的最高金属层中的迹线146。不在阵列周边处的基底上的信号焊盘136和功率焊盘138经由短迹线和过孔连接到基底中的更深金属层。功率焊盘138经由短迹线(功率支柱或凸出部分)148通过功率过孔150连接到下面的金属层中的功率迹线,并且接地焊盘140经由短迹线(接地支柱或凸出部分)152通过接地过孔154连接到下面的金属层中的功率迹线。
在图5和6中,从信号线焊盘136开始为所有信号线布线,从管芯覆盖区离开,并且将所有功率和接地线布线到管芯覆盖区下面的过孔中。因此,在信号路径中不要求支柱或过孔,并且避免了信号传输中的寄生。可以将信号迹线布线为如用于迹线形成的可用技术所允许的那样靠近在一起,虽然如果使其过于密集,在相邻线中可能发生信号干扰。可以使信号焊盘136如用于迹线形成和凸块结合的可用技术所允许的那样靠近在一起。
图7示出具有安装在基底158的表面的管芯附着区上的半导体管芯157的倒装封装156的一部分。在半导体管芯157的有源侧155上或中形成管芯焊盘,包括信号焊盘159、功率焊盘160和接地焊盘161。导电球或凸块被附着于管芯焊盘,并且可以通过将球或凸块结合到基底的上金属层162中的相应图案化迹线上的互连点来实现到基底158的倒装互连。信号凸块163被附着到信号焊盘159并结合到信号迹线164上的互连点。功率凸块165被附着到功率焊盘160并结合到功率迹线166上的互连点,并且接地凸块167被附着于接地焊盘161并结合到接地迹线168上的互连点。
基底158可以是组合式基底,具有一个或或多个较薄的交替电介质和金属层,其被固定于称为芯的较厚的中间双层基底的上和下表面中的每一个上。组合式基底158在顶部上通常具有与在底部上相同数目的单金属层。因此,1-2-1组合式基底具有一个较薄的单金属层,其与电介质层一起被固定于芯的顶部和底部中的每一个,总共形成四个金属层。2-2-2组合式基底具有两个较薄的单金属层,其与电介质层一起被固定于芯的顶部和底部中的每一个,总共形成六个金属层。3-2-3组合式基底具有三个较薄的单金属层基底,其与电介质层一起被固定于芯的顶部和底部中的每一个,总共形成八个金属层。每个附加组的组合式层显著地提高组合式基底的成本,并且因此期望要求较少层的电路布局。
组合过程可能使得需要通过旋涂工艺在芯的表面上或先前建立的组合层的表面上的层中施加电介质材料,然后对电介质的表面进行金属化并用掩膜和蚀刻工艺对金属化进行图案化。
基底158包括在电介质的顶面和底面上具有图案化金属层(即两个金属层基底)的印刷电路板作为芯。印刷电路板中的电介质的厚度通常约为500μm。实际上,芯上的金属层中的特征节距具有在约100μm范围内的下限,并且过孔捕获焊盘直径具有在约300μm范围内的下限。相反,较薄单组合层中的电介质的厚度通常约为50μm。组合层上的金属层通常比较厚芯上的那些更薄。组合层中的金属层中的特征节距具有在约50μm范围内的下限,并且过孔捕获焊盘直径具有在约120μm范围内的下限。
图7的实施例中的基底158是组合1-2-1式的四金属层基底。也就是说,基底158包括在中间较厚的两个金属层基底172上形成的上和下薄单金属层基底170和171。两个金属层基底172具有图案化的上和下金属层173和174。单金属层基底170和171具有图案化金属层162和176。每个图案化金属层162、173、174和176具有用于信号、功率和接地电路的迹线。例如,金属层173包括专用于接地电路的迹线177和专用于功率电路的迹线178,并且金属层174包括功率迹线179和接地迹线180。
下金属层176被图案化以在诸如器件母板的印刷电路板上的安装时提供用于封装的二级焊料凸块互连的结合点。特别地,接地凸块181、信号凸块182和功率凸块183被附着于布置在封装基底158的下侧边缘上的接地凸块点184、信号凸块点185和功率凸块点186。芯接地凸块187和芯功率凸块188被附着于布置在封装基底158下侧的管芯下面的芯接地凸块点189和芯功率凸块点190。
上接地迹线168和功率迹线166包括用于接地和功率凸块167、165的倒装附着的点,并通过管芯覆盖区下面的过孔191和192被连接到金属层173中的迹线177和178。迹线177和178通过过孔198和193连接到金属层174中的迹线180和194。迹线180和194又通过过孔连接到二级互连点189和190(芯接地和芯功率)及184和186(接地和功率)。
管芯信号焊盘159被布置在半导体管芯的周边附近,并且在远离管芯覆盖区的管芯边缘195下面布线基底158上的相应信号迹线164。信号迹线164被直接布线到通常覆盖二级信号凸块点185的基底158的区域,使得能够主要经由过孔196和197来缩短并实现上金属层162中的信号迹线到凸块点185的连接,在下金属层173、174和176内具有最少的信号电路。二级信号凸块和向下行进的过孔可以位于接地和功率凸块和过孔之间和附近。
通常,封装基底中的接地线优选地与信号线分离相当于至少与作为相邻信号线之间的距离的相同量级的距离,使得由信号产生的场线转到地而不与其它信号相干扰。优选地,因此,第二金属层173主要充当接地平面,并且上金属层中的电介质的厚度约等于或小于上层上的相邻信号线之间的最小间距。因此,用于封装156的大部分扇形展开接地电路在第二金属层173中形成,其仅仅通过薄上层电介质与上金属层162分离。上和下单金属层基底中的电介质的厚度可以约为50μm,并且因此在相邻信号线之间的标称距离约为50μm或更大的情况下,获得地和信号线的期望间距而为信号提供稳定的微带控制阻抗传输线。
如下文所讨论的,存在其中少数所选信号焊盘位于管芯的内侧区域中的接地和功率焊盘之间、亦即在管芯的芯电路区域内的情况。在设计需要的情况下或在管芯电路使得更优选的情况下,位于半导体管芯的芯电路区域内的接地或功率焊盘之间的信号焊盘可以在管芯的芯电路区域的覆盖区内的基底上具有相应的焊盘,并且可以直接在过孔中向下通过基底芯布线更多至底层。
可以采用其它组合式基底,虽然如上所述,成本随着附加层的添加而提高,并且具有较少层的基底可能是有利的。在使用2-2-2基底的情况下,可以正如上文针对1-2-1基底所述的对顶部和底部组合层进行图案化。可以将中间基底上的金属层主要用于功率布线,并且可以将中间基底之上和之下的组合层上的金属层主要用作接地平面。在组合基底中采用更大数目的层的情况下,可以将基底层上的布局布置为使得在切合实际的限度内,信号过孔被接地和功率过孔围绕,以减少由于电寄生而引起的信号的劣化。
在没有组合层的情况下,可以使用四层组合式0-4-0层压基底,在芯基底的粗设计规则内提供特征节距和过孔捕获焊盘设计适配。避免组合的需要能够提供层压制备中的显著的成本降低。
可以实现其它管芯焊盘布局,其中管芯信号焊盘被布置在管芯周边附近且管芯功率和接地焊盘被布置在自信号焊盘的内侧。在其它布局布置中,以与管芯焊盘布局互补的方式来布置信号焊盘,或者其中从远离管芯覆盖区的管芯边缘下面的信号焊盘布线信号线并将功率和接地线布线到管芯覆盖区下面的过孔。图8a—8b、9a—9b、10a—10b和11a—11b示出了具有相应基底的焊盘布局的四个说明性示例。
在图8a的管芯焊盘布局200中,信号焊盘202被以平行于管芯边缘206的两个交错行的阵列布置在半导体管芯周边附近的管芯表面204上。示出了信号焊盘202,其具有与诸如图5中的单行实施例中的焊盘大约相同的节距,结果,在半导体管芯的周边上能够容纳数目大得多的信号焊盘。可替换地,可以在两行中容纳与在单行实施例中相同数目的焊盘并进行交错,使得焊盘节距和焊盘直径及相应的互连凸块或球可以更大,降低制造成本。类似于图5,功率焊盘208和接地焊盘210被布置成在管芯表面的内侧区域上具有无焊盘的中心区域的阵列。应注意的是与图中所示的相比,在典型的管芯中可以存在更多的管芯焊盘,某些管芯具有几百个焊盘。例如,半导体管芯可以具有总共500个焊盘,包括150个功率和接地焊盘及350个信号焊盘。
在图8b中的212处大体上在平面图中示出与图8a的管芯焊盘布局200相对应的基底焊盘的布置。信号焊盘214、功率焊盘216和接地焊盘218在基底表面220上被布置成与图8a的管芯焊盘布局互补的阵列,使得其能够接纳并分别被结合到被附着于半导体管芯204上的相应焊盘的信号、功率和接地凸块。在此布置中,与信号布线相关联的所有焊盘214被以两个交错行的阵列布置在阵列周边处,并且用于阵列周边上的信号焊盘的逸出布线可以直接在管芯边缘222下面穿过作为基底的最高金属层中的迹线224。虽然信号焊盘214具有与图6中的焊盘大约相同的节距,但信号迹线224具有大约为信号迹线146的一半的节距。也就是说,对于给定焊盘节距而言,可以将逸出密度加倍。不在阵列周边处的基底220上的信号焊盘214和功率焊盘216经由短迹线和过孔连接到基底中的更深金属层。在图8b中,功率焊盘216经由功率支柱或凸出部分226通过功率过孔228连接到下面的金属层中的功率迹线。接地焊盘218经由接地支柱或凸出部分230通过接地过孔232连接到下面金属层中的功率迹线。
图9a示出了管芯焊盘布局234,其中信号焊盘236以平行于管芯边缘240的行布置在管芯周边附近的管芯表面238上。示出了具有与图5中的焊盘大约相等的节距的信号焊盘236。功率焊盘242和接地焊盘244还被布置成行,平行于管芯边缘240并在信号焊盘236的行的内侧。在行中,功率焊盘242与接地焊盘244交替。可以通过使内侧行中的焊盘与外侧行中的信号焊盘交错来更紧密地形成所有焊盘。
通常,在一个或多个边缘附近,沿着管芯周边来配置管芯的有源层中的输入/输出电路。将所有焊盘限制成半导体管芯周边附近的行从而形成焊盘环,其允许通过减少管芯上布线的量来降低管芯成本,并且在构造管芯时可以采用芯片设计工具。
在图9b中的250处大体上在平面图中示出与图9a的管芯焊盘布局234相对应的基底焊盘的布置。信号焊盘252、功率焊盘254和接地焊盘256在基底表面258上被布置成与图9a的管芯焊盘布局234互补的阵列,使得其能够接纳并分别被结合到被附着于半导体管芯238上的相应焊盘的信号、功率和接地凸块。在此布置中,与信号布线相关联的所有焊盘252在阵列周边处被布置成行,并且用于阵列周边上的信号焊盘的逸出布线可以直接在管芯边缘260下面穿过作为基底的最高金属层中的迹线262。在阵列周边附近的信号焊盘内侧的基底258上的接地焊盘256和功率焊盘254经由短接线和过孔连接到基底中的更深的金属层。在图9b中,功率焊盘254经由功率支柱或凸出部分264通过功率过孔266连接到下面的金属层中的功率迹线。接地焊盘256经由接地支柱或凸出部分268通过接地过孔269连接到下面金属层中的功率迹线。
在图9a和9b中,可以将少量接地焊盘和/或少量功率焊盘设置在更靠近管芯边缘的外侧行中。在基底中,可以以相应的方式来布置接地焊盘和/或功率焊盘。配置具有的接地和功率焊盘可以是外侧行中的接地和功率焊盘的多达10%、更一般地小于约5%、更一般地为0%或小于约2%,但是将功率或接地焊盘设置在外侧行中导致信号焊盘逸出密度的降低。可以通过使焊盘周边中的功率或接地焊盘的数目最小化来使信号焊盘逸出密度最大化。在某些实施例中,在外侧行中不存在功率焊盘或接地焊盘。同样地,可以在管芯周边内侧的功率和接地焊盘之间设置少量信号焊盘,并且在基底中,可以以相应的方式来布置信号焊盘。然而,此类布置可能要求采用下基底层,使得需要使用过孔并增加信号路径长度。
如上所述,使信号焊盘逸出密度最大化,其中,外侧行中的接地和/或功率焊盘的数目被最小化,并且因此,逸出密度可以处于最大值,其中,在外侧行中不存在接地焊盘或功率焊盘。然而,服务于射频(RF)信号的信号焊盘可以在一侧具有邻近的接地焊盘,或者,可以由信号焊盘和接地焊盘在两侧夹着该信号焊盘以进行信号的电磁屏蔽。可以协调信号焊盘逸出密度达到有限的程度,并且在管芯周边附近的信号焊盘的两侧或三侧上布置功率和/或接地焊盘能够提供有用的折衷。
在图10a的管芯焊盘布局270中,信号焊盘271以平行于管芯边缘273的行布置在管芯周边附近的管芯表面272上。示出了具有与图5中的焊盘大约相等的节距的信号焊盘271。功率焊盘274和接地焊盘275被布置成行,平行于管芯边缘273并在信号焊盘271的行的内侧。功率焊盘274和接地焊盘275数目已经减少。也就是说,存在约为如图9a所示的一半的功率和接地焊盘。在行中,功率焊盘274与接地焊盘275交替。可以通过使内侧行中的焊盘与外侧行中的信号焊盘交错来更紧密地形成所有焊盘。
减少功率和接地焊盘数目允许有在半导体管芯阴影下具有多得多的接地过孔和功率过孔的布局,如图10b所示,大体上在276处以平面图示出了与图10a的管芯焊盘布局270相对应的基底焊盘布置。信号焊盘278、功率焊盘279和接地焊盘280在基底表面281上被布置成与图10a的管芯焊盘布局互补的阵列,使得其能够接纳并分别被结合到被附着于半导体管芯272上的相应焊盘的信号、功率和接地凸块。在此布置中,与信号布线相关联的所有焊盘278在阵列周边处被布置成行,并且用于阵列周边上的信号焊盘的逸出布线可以直接在管芯边缘282下面穿过作为基底281的最高金属层中的迹线283。在阵列周边附近的信号焊盘内侧的基底281上的接地焊盘280和功率焊盘279经由短接线和过孔连接到基底中的更深的金属层。功率焊盘279经由功率支柱或凸出部分284通过功率过孔285连接到下面的金属层中的功率迹线。接地焊盘280经由接地支柱或凸出部分286通过接地过孔287连接到下面金属层中的功率迹线。
通常使接地和功率过孔的直径约为线间距的2至3倍。对于更大的功率和接地过孔尺寸而言,交替的支柱可以具有不同的长度,使得功率和接地过孔被布置成交错阵列,如图10b所示。对于约100μm的信号线逸出节距而言,接地过孔和功率过孔之间的有效过孔节距可以约为220μm,并且过孔直径可以大到约250μm。具有较大过孔的基底可能不那么昂贵,并且此类配置能够提供成品封装的成本的显著降低。
在图11a的管芯焊盘布局288中,信号焊盘289被以平行于管芯边缘291的两个行的大体正交阵列布置在半导体管芯周边附近的管芯表面290上。示出了每行中的信号焊盘289,其具有大约与图8a的外侧行中的焊盘相同的节距,并且内侧和外侧行的间隔略远于如图5中的单行中的相邻焊盘的间隔。也就是说,如在图8a的交错周边阵列中一样,在图11a的正交周边阵列中存在相同数目的信号焊盘289。在图11a中,正交周边信号节距阵列比图8a的交错周边信号节距阵列占据略大的面积;然而,正交阵列中的最邻近焊盘之间的节距小于交错阵列中的最邻近焊盘之间的节距,使得互连几何结构、即焊盘节距和焊盘直径及相应的互连凸块和球可以更大,降低制造成本。类似于图5和8a,功率焊盘292和接地焊盘293被布置成在管芯表面的内侧区域上具有无焊盘的中心区域的阵列。
在图11b中大体上在294处以平面图示出与管芯焊盘布局288相对应的基底焊盘的布置。信号焊盘295、功率焊盘296和接地焊盘297在基底表面298上被布置成与图11a的管芯焊盘布局288互补的阵列,使得其能够接纳并分别被结合到被附着于半导体管芯290上的相应焊盘的信号、功率和接地凸块。在此布置中,与信号布线相关联的所有焊盘295被以两个行的正交阵列布置在阵列周边处,并且用于阵列周边上的信号焊盘的逸出布线可以直接在管芯边缘300下面穿过作为基底的最高金属层中的迹线302。不在阵列周边处的基底298上的信号焊盘295和功率焊盘296经由短迹线和过孔连接到基底中的更深金属层。功率焊盘296经由功率支柱或凸出部分304通过功率过孔306连接到下面的金属层中的功率迹线。接地焊盘297经由接地支柱或凸出部分310通过接地过孔312连接到下面金属层中的功率迹线。
从信号线焊盘开始布线图8b、9b、10b和11b的实施例中的信号线,从管芯覆盖区离开,并且将所有功率和接地线布线到管芯覆盖区下面的过孔中。可以在基底上的单个上金属层中布线所有信号迹线。因此,在信号路径中不要求支柱或过孔,并且避免了信号传输中的寄生。可以使信号迹线形成为如用于迹线形成可用技术所允许的那样靠近在一起。可以使信号焊盘形成为如用于迹线形成和凸块结合的可用技术所允许的那样靠近在一起。
前述示例举例说明其中没有接地或功率互连位于距离基底上的管芯覆盖区和管芯周边最近的信号互连之间的实施例。没有信号互连位于充分地在管芯和管芯覆盖区中间周围的芯矩阵内的功率和接地互连之间。在某些情况下,一个或几个信号互连可以位于芯阵列内,通常邻近于接地互连,并且因此将基底中的一个或几个信号线布线到管芯覆盖区下面的过孔,与基底中的下金属层相连或从管芯边缘下面外侧的管芯覆盖区的充分内部开始在基底的上金属层中布线此类信号线。在某些情况下,信号互连之中的一个或几个功率互连、或者更通常为更加在外围的一个或几个接地互连可以位于管芯周边附近,并因此在基底上的管芯覆盖区的周边附近。某些电路设计将时钟信号互连设置为更靠近接地互连。
所有或基本上所有管芯信号焊盘在管芯周边附近被布置成行或阵列。所有或基本上所有管芯功率和接地焊盘位于基本上所有管芯信号焊盘内侧。特别地,将周边附近的信号焊盘与芯中的接地和功率焊盘分离的优点可能随着未分离焊盘的数目或比例的增加而显著劣化。不在周边行或周边阵列中的信号焊盘的比例通常小于所有信号焊盘的约10%,更一般地小于所有信号焊盘的约5%,并且更一般地为0%或在所有信号焊盘的0%至约2%范围内。不在信号焊盘的周边行或周边阵列内侧的接地或功率焊盘的比例通常小于所有功率和接地焊盘的约10%,更一般地小于所有功率和接地焊盘的约5%,并且更一般地为0%或在所有信号焊盘的0%至约2%范围内。
信号焊盘被沿着管芯的整个周边、亦即沿着矩形管芯的全部四个边缘布置成行或阵列。在某些实施例中,信号焊盘被沿着比全部的管芯边缘少的边缘布置,并且特别地在其中信号焊盘被沿着四个管芯边缘中的任何两个或更多个布置成周边行或周边阵列的实施例中,能够实现该优点。
可以使用具有很少层的基底来进行倒装封装,并且可以根据功能有效地分配各种层上的电路,降低基底成本以及改善性能。
图12—17描述了具有可以与管芯焊盘布局相组合地使用的各种互连结构的其它实施例,包括信号焊盘、功率焊盘和接地焊盘,如图5—11所述。更具体而言,半导体管芯接触焊盘和相应的互连导电迹线可以对应于管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。图12a示出具有底部基底材料322的半导体晶片320,底部基底材料320诸如硅、锗、砷化镓、磷化铟、或碳化硅,用于结构支撑。在如上所述被锯道326分离的晶片320上形成多个半导体管芯或组件324。
图12b示出半导体晶片320的一部分的横截面图。每个半导体管芯324具有背面328和有源表面330,有源表面330包含被实现为有源器件、无源器件、导电层和电介质层的模拟或数字电路,其在管芯内形成并被根据管芯的电气设计和功能电互连。例如,该电路可以包括在有源表面330内形成的一个或多个晶体管、二极管及其它电路元件以实现模拟电路或数字电路,诸如数字信号处理器(DSP)、ASIC、存储器或其它信号处理电路。半导体管芯324还可以包含集成无源器件(IPD),诸如电感器、电容器和电阻器,以进行RF信号处理。在一个实施例中,半导体管芯324是倒装式半导体管芯。
使用PVD、CVD、电解镀覆、化学镀覆工艺或其它适当的金属沉积工艺在有源表面330上形成导电层332。导电层332可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层332充当被电连接到有源表面330上的电路的接触焊盘或凸块焊盘。
图12c示出具有在接触焊盘332上形成的互连结构的半导体晶片320的一部分。使用蒸发、电解镀覆、化学镀覆、球滴或丝网印刷工艺在接触焊盘332上沉积导电凸块材料334。凸块材料334可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合,具有可选助焊剂溶液。例如,凸块材料334可以是共熔Sn/Pb、高铅焊料或无铅焊料。凸块材料334通常是具有柔顺性的,并且在等效于约200克的垂直载荷的力下经历大于约25μm的塑性变形。使用适当的附着或结合工艺将凸块材料334结合到接触焊盘332。例如,可以将凸块材料334压缩结合到接触焊盘332。如图12d所示,还可以通过将材料加热至其熔点之上以形成球状球或凸块336来对凸块材料334进行回流。在某些应用中,第二次对凸块336进行回流以改善到接触焊盘332的电连接。凸块336表示可以在接触焊盘332上形成的一种类型的互连结构。互连结构还可以使用支柱凸块、微型凸块或其它电互连。
图12e示出在接触焊盘332上形成作为包括不可熔或不可拆卸部分340和可熔或可拆卸部分342的复合凸块338的互连结构的另一实施例。相对于回流条件,针对凸块338来限定可熔或可拆卸和不可熔或不可拆卸属性。不可熔部分340可以是Au、Cu、Ni、高铅焊料或铅锡合金。可熔部分342可以是Sn、无铅合金、Sn-Ag合金、Sn-Ag-Cu合金、Sn-Ag-铟(In)合金、共熔焊料、具有Ag、Cu或Pb的锡合金或其它相对低温熔化焊料。在一个实施例中,给定100μm的宽度或直径的接触焊盘332,不可熔部分340在高度上约45μm且可熔部分342在高度上约35μm。
图12f示出了作为导电柱346上的凸块344的接触焊盘332上形成的互连结构的另一示例。凸块344是可熔或可拆卸的且导电柱346是不可熔或不可拆卸的。相对于回流条件来定义可熔或可拆卸及不可熔或不可拆卸属性。凸块344可以是Sn、无铅合金、Sn-Ag合金、Sn-Ag-Cu合金、Sn-Ag-In合金、共熔焊料、具有Ag、Cu或Pb的锡合金或其它相对低温熔化焊料。导电柱346可以是Au、Cu、Ni、高铅焊料或铅锡合金。在一个实施例中,导电柱346是Cu柱且凸块344是焊料盖。给定100μm的宽度或直径的接触焊盘332,导电柱346在高度上约45μm且凸块344在高度上约35μm。
图12g示出了作为具有凸起物(asperities)350的凸块材料348的在接触焊盘332上形成的互连结构的另一实施例。凸块材料348是软的且在回流条件下是可变形的,具有低屈服强度和高断裂伸长率,与凸块材料334类似。凸起物350形成有镀覆的表面面层(finish),并且在图中出于举例说明的目的被放大地示出。凸起物350的尺度通常约为1-25μm量级。该凸起物还可以在凸块336、复合凸块338和凸块344上形成。
在图12h中,使用锯条或激光切割工具352通过锯道326将半导体晶片320单颗化成单独的半导体管芯324。
图13a示出具有导电迹线356的基底或PCB 354。基底354可以是单面FR5层压件或双面BT树脂层压件。半导体管芯324被定位为使得凸块材料334与导电迹线356上的互连点对准,参见图21a-21g。可替换地,可以使凸块材料334与在基底354上形成的导电焊盘或其它互连点对准。凸块材料334比导电迹线356宽。在一个实施例中,对于150μm的凸块节距而言,凸块材料334具有小于100μm的宽度且导电迹线或焊盘356具有35μm的宽度。接触焊盘332和导电迹线356可以对应于图5—11的管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。
向半导体管芯324的背面328施加压力或力F以将凸块材料334压紧到导电迹线356上。可以在提高温度的情况下施加力F。由于凸块材料334的柔顺性,凸块材料在导电迹线356的顶面和侧面周围变形或压出,称为引线上凸块(BOL)。特别地,压力的施加促使凸块材料334在等效于约200克的垂直载荷的力F下经历大于约25μm的塑性变形并覆盖导电迹线的顶面和侧面,如图13b所示。还可以通过使凸块材料与导电迹线进行物理接触并随后在回流温度下对凸块材料进行回流来以冶金方式将凸块材料334连接到导电迹线356。
通过使得导电迹线356比凸块材料334窄,可以缩小导电迹线节距以增加布线密度和I/O计数。较窄的导电迹线356减小使导电迹线周围的凸块材料334变形所需的力F。例如,必需的力F可以是针对比凸块材料宽的导电迹线或焊盘使凸块材料变形所需的力的30-50%。较低的压缩力F对细节距互连和小管芯以指定公差保持共面性并实现均匀的z方向变形和高可靠性互连联合有用。另外,使导电迹线356周围的凸块材料334变形机械地将凸块锁定到迹线以防止回流期间的管芯移位或管芯浮置。
图13c示出在半导体管芯324的接触焊盘332上形成的凸块336。半导体管芯324被定位为使得凸块336与导电迹线356上的互连点对准。可替换地,凸块336可以与在基底354上形成的导电焊盘或其它互连点对准。凸块336比导电迹线356宽。接触焊盘332和导电迹线356可以对应于图5—11的管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。
向半导体管芯324的背面328施加压力或力F以将凸块336压紧到导电迹线356上。可以在提高温度的情况下施加力F。由于凸块336的柔顺性,凸块在导电迹线356的顶面和侧面周围变形或压出。特别地,压力的施加促使凸块材料336经历塑性变形并覆盖导电迹线356的顶面和侧面。还可以通过在回流温度下使凸块与导电迹线进行物理接触来以冶金方式将凸块336连接到导电迹线356。
通过使得导电迹线356比凸块336窄,可以缩小导电迹线节距以增加布线密度和I/O数目。较窄的导电迹线356减小使导电迹线周围的凸块336变形所需的力F。例如,必需的力F可以是针对比凸块宽的导电迹线或焊盘使凸块变形所需的力的30-50%。较低的压缩力F对细节距互连和小管芯而将共面性保持在指定公差内并实现均匀的z方向变形和高可靠性互连联合有用。另外,使导电迹线356周围的凸块336变形机械地将凸块锁定到迹线以防止回流期间的管芯移位或管芯浮置。
图13d示出在半导体管芯324的接触焊盘332上形成的复合凸块338。半导体管芯324被定位为使得复合凸块338与导电迹线356上的互连点对准。可替换地,复合凸块338可以与在基底354上形成的导电焊盘或其它互连点对准。复合凸块338比导电迹线356宽。接触焊盘332和导电迹线356可以对应于图5—11的管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。
向半导体管芯324的背面328施加压力或力F以将可熔部分342压紧到导电迹线356上。可以在提高温度的情况下施加力F。由于可熔部分342的柔顺性,可熔部分在导电迹线356的顶面和侧面周围变形或压出。特别地,压力的施加促使可熔部分342经历塑性变形并覆盖导电迹线356的顶面和侧面。还可以通过在回流温度下使可熔部分342与导电迹线进行物理接触来以冶金方式将复合凸块338连接到导电迹线356。不可熔部分340在施加压力或温度期间不熔化或变形,并且保持其高度和形状作为半导体管芯324与基底354之间的垂直基准距。半导体管芯324与基底354之间的附加位移提供配合表面之间的较大共面性公差。
在回流过程期间,半导体管芯324上的大量(例如几千个)复合凸块338被附着于基底354的导电迹线356上的互连点。某些凸块338可能未能适当地连接到导电迹线356,特别是如果管芯324发生翘曲。回想复合凸块338可以比导电迹线356宽。在施加适当力的情况下,可熔部分342在导电迹线356的顶面和侧面周围变形或压出并将复合凸块338机械地锁定到导电迹线。通过可熔部分342比导电迹线356更软且更具有柔顺性的性质并因此在导电迹线的顶面之上和侧面周围变形以有更大的接触表面面积来形成机械互锁。复合凸块338与导电迹线356之间的机械互锁在回流期间将凸块保持到导电迹线,即凸块和导电迹线不失去接触。因此,配合到导电迹线356的复合凸块338减少凸块互连故障。
图13e示出在半导体管芯324的接触焊盘332上形成的导电柱346和凸块344。半导体管芯324被定位为使得凸块344与导电迹线356上的互连点对准。可替换地,可以使凸块344与在基底354上形成的导电焊盘或其它互连点对准。凸块344比导电迹线356宽。接触焊盘332和导电迹线356可以对应于图5—11的管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。
向半导体管芯324的背面328施加压力或力F以将凸块344压紧到导电迹线356上。可以在提高温度的情况下施加力F。由于凸块344的柔顺性,凸块在导电迹线356的顶面和侧面周围变形或压出。特别地,压力的施加促使凸块344经历塑性变形并覆盖导电迹线356的顶面和侧面。还可以通过在回流温度下使凸块与导电迹线进行物理接触来以冶金方式将导电柱346和凸块344连接到导电迹线356。导电柱346在施加压力或温度期间不熔化或变形,并且保持其高度和形状作为半导体管芯324与基底354之间的垂直基准距。半导体管芯324与基底354之间的附加位移提供配合表面之间的较大共面性公差。较宽的凸块344和较窄的导电迹线356具有上文针对凸块材料334和凸块336所述的类似低必需压缩力和机械锁定特征和优点。
图13f示出了具有在半导体管芯324的接触焊盘332上形成的凸起物350的凸块材料348。半导体管芯324被定位为使得凸块材料348与导电迹线356上的互连点对准。可替换地,可以使凸块材料348与在基底354上形成的导电焊盘或其它互连点对准。凸块材料348比导电迹线356宽。向半导体管芯324的背面328施加压力或力F以将凸块材料348压紧到导电迹线356上。可以在提高温度的情况下施加力F。由于凸块材料348的柔顺性,凸块在导电迹线356的顶面和侧面周围变形或压出。特别地,压力的施加促使凸块材料348经历塑性变形并覆盖导电迹线356的顶面和侧面。另外,凸起物350被以冶金方式连接到导电迹线356。凸起物350的尺寸被确定为约为1-25μm量级。
图13g示出具有带有成角度或倾斜边的梯形导电迹线360的基底或PCB 358。凸块材料361在半导体管芯324的接触焊盘332上形成。半导体管芯324被定位为使得凸块材料361与导电迹线360上的互连点对准。可替换地,可以使凸块材料361与在基底358上形成的导电焊盘或其它互连点对准。凸块材料361比导电迹线360宽。接触焊盘332和导电迹线360可以对应于图5—11的管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。
向半导体管芯324的背面328施加压力或力F以将凸块材料361压紧到导电迹线360上。可以在提高温度的情况下施加力F。由于凸块材料361的柔顺性,凸块材料在导电迹线360的顶面和侧面周围变形或压出。特别地,压力的施加促使凸块材料361在力F下经历塑性变形而覆盖导电迹线360的顶面和成角度的侧面。还可以通过使凸块材料与导电迹线进行物理接触并随后在回流温度下对凸块材料进行回流来以冶金方式将凸块材料361连接到导电迹线360。
图14a-14d示出半导体管芯324和具有不可熔或不可拆卸部分364和可熔或可拆卸部分366的细长复合凸块362的BOL实施例。不可熔部分364可以是Au、Cu、Ni、高铅焊料或铅锡合金。可熔部分366可以是Sn、无铅合金、Sn-Ag合金、Sn-Ag-Cu合金、Sn-Ag-铟(In)合金、共熔焊料、具有Ag、Cu或Pb的锡合金或其它相对低温熔化焊料。不可熔部分364构成比可熔部分366大的复合凸块362的更大部分。不可熔部分364被固定于半导体管芯324的接触焊盘332。
如图14a所示,半导体管芯324被定位为使得复合凸块362与在基底370上形成的导电迹线368上的互连点对准。复合凸块362沿着导电迹线368逐渐缩减,即复合凸块具有楔形形状,沿着导电迹线368的长度较长且跨越导电迹线较窄。复合凸块362的锥形方位沿着导电迹线368的长度发生。图14a中的视图示出与导电迹线368共线的较短方位或缩窄的锥形。与图14a垂直的图14b中的视图示出楔形形状的复合凸块362的较长方位。复合凸块362的较短方位比导电迹线368宽。如图14c和14d所示,可熔部分366在施加压力和/或具有热量的回流时在导电迹线368周围拆卸。不可熔部分364在回流期间不熔化或变形并保持其外形和形状。可以将不可熔部分364的尺寸确定为提供半导体管芯324与基底370之间的基准距距离。可以向基底370施加诸如Cu OSP的面层。接触焊盘332和导电迹线368可以对应于图5—11的管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。
在回流过程期间,半导体管芯324上的大量(例如几千个)复合凸块362被附着于基底370的导电迹线368上的互连点。某些凸块362可能未能适当地连接到导电迹线368,特别是如果半导体管芯324发生翘曲。回想复合凸块362可以比导电迹线368宽。在施加适当力的情况下,可熔部分366在导电迹线368的顶面和侧面周围变形或压出并将复合凸块362机械地锁定到导电迹线。通过可熔部分366比导电迹线368更软且更具有柔顺性的性质并因此在导电迹线的顶面和侧面周围变形以有更大的接触面积来形成机械互锁。复合凸块362的楔形形状增加凸块与导电迹线之间的接触面积,例如沿着图14b和14d的较长方位,而不牺牲沿着图14a和14c的较短方位的节距。复合凸块362与导电迹线368之间的机械互锁在回流期间将凸块保持到导电迹线,即凸块和导电迹线之间不失去接触。因此,配合到导电迹线368的复合凸块362减少凸块互连故障。
类似于图12c,图15a—15d示出在凸块材料374形成于接触焊盘332上的情况下的半导体管芯324的BOL实施例。在图15a中,凸块材料374通常是具有柔顺性的,并且在等效于约200克的垂直载荷的力下经历大于约25μm的塑性变形。凸块材料374比基底378上的导电迹线376宽。在导电迹线376上形成具有约1—25μm量级的高度的多个凸起物380。
半导体管芯324被定位为使得凸块材料374与导电迹线376上的互连点对准。可替换地,可以使凸块材料374与在基底378上形成的导电焊盘或其它互连点对准。如图15b所示,向半导体管芯324的背面328施加压力或力F以将凸块材料374压紧到导电迹线376和凸起物380上。可以在提高温度的情况下施加力F。由于凸块材料374的柔顺性,凸块材料在凸起物380和导电迹线376的顶面和侧面周围变形或压出。特别地,压力的施加促使凸块材料374经历塑性变形并覆盖凸起物380和导电迹线376的顶面和侧面。凸块材料374的塑性流动在凸块材料与凸起物380和导电迹线376的顶面和侧面之间产生宏观机械互锁点。凸块材料374的塑性流动在凸起物380和导电迹线376的顶面和侧面周围发生,但是不过度地延伸到基底378上,这可能引起电短路及其它缺陷。凸块材料与凸起物380和导电迹线376的顶面和侧面之间的机械互锁提供与各表面之间的较大接触面积的稳健连接,而不显著地增加结合力。凸块材料与凸起物380和导电迹线376的顶面和侧面之间的机械互锁还减少诸如密封的后续制造过程期间的横向管芯移位。接触焊盘332和导电迹线376可以对应于图5—11的管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。
图15c示出凸块材料374比导电迹线376窄的情况下的另一BOL实施例。向半导体管芯324的背面328施加压力或力F以将凸块材料374压紧到导电迹线376和凸起物380上。可以在提高温度的情况下施加力F。由于凸块材料374的柔顺性,凸块材料在凸起物380和导电迹线376的顶面之上变形或压出。特别地,压力的施加促使凸块材料374经历塑性变形并覆盖凸起物380和导电迹线376的顶面。凸块材料374的塑性流动在凸块材料与凸起物380和导电迹线376的顶面之间产生宏观机械互锁点。凸块材料与凸起物380和导电迹线376的顶面之间的机械互锁提供与各表面之间的较大接触面积的稳健连接,而不显著地增加结合力。凸块材料与凸起物380和导电迹线376的顶面之间的机械互锁还减少诸如密封的后续制造过程期间的横向管芯移位。
图15d示出在凸块材料374形成于导电迹线376的边缘上的情况下的另一BOL实施例,即,凸块材料的一部分在导电迹线上且凸块材料的另一部分不在导电迹线上。向半导体管芯324的背面328施加压力或力F以将凸块材料374压紧到导电迹线376和凸起物380上。可以在提高温度的情况下施加力F。由于凸块材料374的柔顺性性质,凸块材料在凸起物380和导电迹线376的顶面和侧面上变形或压出。特别地,压力的施加促使凸块材料374经历塑性变形并覆盖凸起物380和导电迹线376的顶面和侧面。凸块材料374的塑性流动在凸块材料与凸起物380和导电迹线376的顶面和侧面之间产生宏观机械互锁。凸块材料与凸起物380和导电迹线376的顶面和侧面之间的机械互锁提供与各表面之间的较大接触面积的稳健连接,而不显著地增加结合力。凸块材料与凸起物380和导电迹线376的顶面和侧面之间的机械互锁还减少诸如密封的后续制造过程期间的横向管芯移位。
类似于图12c,图16a—16c示出具有形成于接触焊盘332上的凸块材料384的半导体管芯324的BOL实施例。如图16a所示,尖端386从凸块材料384的主体伸出作为台阶式凸块,尖端386比凸块材料384的主体窄。半导体管芯324被定位为使得凸块材料384与基底390上的导电迹线388上的互连点对准。更具体而言,尖端386在导电迹线388上的互连点上位于中心。可替换地,可以使凸块材料384和尖端386与在基底390上形成的导电焊盘或其它互连点对准。凸块材料384比基底390上的导电迹线388宽。
导电迹线388通常是柔顺性的,并且在等效于约200克的垂直载荷的力下经历大于约25 μm的塑性变形。向半导体管芯324的背面328施加压力或力F以将尖端384压紧到导电迹线388上。可以在提高温度的情况下施加力F。由于导电迹线388的柔顺性性质,如图16b所示,导电迹线在尖端386周围变形。特别地,压力的施加促使导电迹线388经历塑性变形并覆盖尖端386的顶面和侧面。接触焊盘332和导电迹线388可以对应于图5—11的管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。
图16c示出圆形凸块材料394在接触焊盘332上形成的另一BOL实施例。尖端396从凸块材料394的主体伸出而形成具有比凸块材料394的主体窄的尖端的支柱凸块。半导体管芯324被定位为使得凸块材料394与基底400上的导电迹线398上的互连点对准。更具体而言,尖端396在导电迹线398上的互连点上位于中心。可替换地,可以使凸块材料394和尖端396与在基底400上形成的导电焊盘或其它互连点对准。凸块材料394比基底400上的导电迹线398宽。
导电迹线398通常是柔顺性的,并且在等效于约200克的垂直载荷的力下经历大于约25μm的塑性变形。向半导体管芯324的背面328施加压力或力F以将尖端396压紧到导电迹线398上。可以在提高温度的情况下施加力F。由于导电迹线398的柔顺性性质,导电迹线在尖端396周围变形。特别地,压力的施加促使导电迹线398经历塑性变形并覆盖尖端396的顶面和侧面。接触焊盘332和导电迹线398可以对应于图5—11的管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。
如图16a—16c所述,在图13a—13g、14a—14d和15a—15d中描述的导电迹线也可以是柔顺性材料。
类似于图11c,图17a—17b示出具有形成于接触焊盘332上的凸块材料404的半导体管芯324的BOL实施例。凸块材料404通常是柔顺性的,并且在等效于约200克的垂直载荷的力下经历大于约25μm的塑性变形。凸块材料404比基底408上的导电迹线406宽。如图17a所示,通过导电迹线406形成具有开口412和导电侧壁414的导电过孔410。接触焊盘332和导电迹线406可以对应于图5—11的管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。
半导体管芯324被定位为使得凸块材料404与导电迹线406上的互连点对准,参见图21a—21g。可替换地,可以使凸块材料404与在基底408上形成的导电焊盘或其它互连点对准。向半导体管芯324的背面328施加压力或力F以将凸块材料404压紧到导电迹线406上并到达导电过孔410的开口412中。可以在提高温度的情况下施加力F。由于凸块材料404的柔顺性性质,如图17b所示,凸块材料在导电迹线406的顶面和侧面周围变形或压出并到达导电过孔410的开口412中。特别地,压力的施加促使凸块材料404经历塑性变形并覆盖导电迹线406的顶面和侧面并到达导电过孔410的开口412中。凸块材料404因此被电连接到导电迹线406和导电侧壁414以便通过基底408进行z方向垂直互连。凸块材料404的塑性流动产生凸块材料与导电迹线406的顶面和侧面及导电过孔410的开口412之间的机械互锁。凸块材料与导电迹线406的顶面和侧面及导电过孔410的开口412之间的机械互锁提供与各表面之间的较大接触面积的稳健连接,而不显著地增加结合力。凸块材料与导电迹线406的顶面和侧面及导电过孔410的开口412之间的机械互锁还减少诸如密封的后续制造过程期间的横向管芯移位。由于导电过孔410在具有凸块材料404的互连点内形成,所以总基底互连面积减小。
在图13a—13g、14a—14d、15a—15d、16a—16c和17a—17b的BOL实施例中,通过使导电迹线比互连结构窄,可以减小导电迹线节距以增加布线密度和I/O计数。较窄的导电迹线减小使导电迹线周围的互连结构变形所需的力F。例如,必需的力F可以是针对比凸块宽的导电迹线或焊盘使凸块变形所需的力的30—50%。较低的压缩力F对细节距互连和小管芯将共面性保持在指定公差内并实现均匀的z方向变形和高可靠性互连联合有用。另外,使导电迹线周围的互连结构变形机械地将凸块锁定到迹线以防止回流期间的管芯移位或管芯浮置。
图18a—18c示出在半导体管芯与基底之间的凸块周围沉积密封剂的模底部填充(MUF)过程。图18a示出使用来自图13b的凸块材料334安装到基底354并被放置在模套模具(chase mold)420的上模支撑体416和下模支撑体418之间。可以将来自图13a—13g、14a—14d、15a—15d、16a—16c和17a—17b的其它半导体管芯和基底组合放置在模套模具420的上模支撑体416和下模支撑体418之间。上模支撑体416包括可压缩释放膜422。
在图18b中,上模支撑体416和下模支撑体418被放在一起以便用在基底之上和半导体管芯与基底之间的开放空间来封闭半导体管芯324和基底354。可压缩释放膜422与半导体管芯324的背面328和侧面一致以阻止密封剂在这些表面上的形成。用喷嘴426将处于液体状态的密封剂424注入到模套模具420的一侧中,同时可选真空帮助428从相对侧吸取压力以用密封剂均匀地填充基底354之上的开放空间和半导体管芯324与基底354之间的开放空间。密封剂424可以是聚合物复合材料,诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或具有适当填料的聚合物。密封剂424是不导电的且在环境上保护半导体器件免受外部元件和污染物的影响。可压缩材料422防止密封剂424在背面328上和半导体管芯324的侧面周围流动。密封剂424被固化。半导体管芯324的背面328和侧面仍从密封剂424暴露。
图18c示出MUF和模过量填充(MOF)、即没有可压缩材料422的实施例。半导体管芯324和基底354被放置在模套模具420的上模支撑体416与下模支撑体418之间。上模支撑体416和下模支撑体418被放在一起以便用在基底之上、半导体管芯周围和半导体管芯与基底之间的开放空间来封闭半导体管芯324和基底354。用喷嘴426将处于液体状态的密封剂424注入到模套模具420的一侧中,同时可选真空帮助428从相对侧吸取压力以用密封剂均匀地填充半导体管芯324周围和基底354之上的开放空间和半导体管芯324与基底354之间的开放空间。密封剂424被固化。
图19示出在半导体管芯324周围和半导体管芯324与基底354之间的间隙中沉积密封剂的另一实施例。半导体管芯324和基底354被屏障430封闭。密封剂432在液态下被从喷嘴434分配到屏障430中以填充基底354之上的开放空间和半导体管芯324与基底354之间的开放空间。控制从喷嘴434分配的密封剂432的体积以在不覆盖半导体管芯324的背面328或侧面的情况下填充屏障430。密封剂432被固化。
图20示出来自图18a、18c和19的MUF过程之后的半导体管芯324和基底354。密封剂424被均匀地分布在基底354上和半导体管芯324与基底354之间的凸块材料334周围。
图21a—21g示出基底或PCB 440上的各种导电迹线布局的顶视图。在图21a中,导电迹线442是具有在基底440上形成的集成凸块焊盘或互连点444的直导体。基底凸块焊盘444的侧边与导电迹线442共线。在现有技术中,通常在互连点上形成焊料套准开口(SRO)以在回流期间包含凸块材料。SRO增加互连节距并减少I/O计数。相反,可以在基底440的一部分上形成掩蔽层446;然而,不在导电迹线442的基底凸块焊盘444周围形成掩蔽层。也就是说,被设计为与凸块材料配合的导电迹线442的一部分缺少将被用于回流期间的凸块包含的掩蔽层446的任何SRO。
半导体管芯324被放置在基底440上且凸块材料与基底凸块焊盘444对准。通过使凸块材料与凸块焊盘进行物理接触并随后在回流温度下对凸块材料进行回流来将凸块材料以电气方式和冶金方式连接到基底凸块焊盘444。
在另一实施例中,使用蒸发、电解镀覆、化学镀覆、球滴或丝网印刷工艺在基底凸块焊盘444上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合,具有可选助焊剂溶液。例如,凸块材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。使用适当的附着或结合工艺将凸块材料结合到基底凸块焊盘444。在一个实施例中,如图21b所示,通过将材料加热至其熔点以上对凸块材料进行回流以形成凸块或互连448。在某些应用中,第二次对凸块448进行回流以改善与基底凸块焊盘444的电接触。窄基底凸块焊盘444周围的凸块材料保持回流期间的管芯放置。
在高布线密度应用中,期望的是使导电迹线442的逸出节距最小化。通过出于回流包含的目的去除掩蔽层、即通过在没有掩蔽层的情况下对凸块材料进行回流来减小导电迹线442之间的逸出节距。由于未在管芯凸块焊盘332或基底凸块焊盘444周围形成SRO,所以可以以更精细的节距形成导电迹线442,即将导电迹线442更近地设置在一起或接近于附近结构。在基底凸块焊盘444周围没有SRO的情况下,导电迹线442之间的节距被给定为P = D + PLT + W/2,其中,D是凸块448的底部直径,PLT是管芯放置公差,并且W是导电迹线442的宽度。在一个实施例中,给定100μm的凸块底部直径、10μm的PLT和30μm的迹线线宽,导电迹线442的最小逸出节距是125μm。如在现有技术中发现的,无掩膜凸块形成消除了考虑相邻开口之间的掩蔽材料的带状间隔(ligament spacing)、焊料掩膜套准公差(SRT)和最小可分辨SRO的需要。
当在没有掩蔽层的情况下对凸块材料进行回流以便以冶金和电气方式将管芯凸块焊盘332连接到基底凸块焊盘444时,润湿和表面张力促使凸块材料保持自限制,并被保持在管芯凸块焊盘332和基底凸块焊盘444与直接邻近于基本上在凸块焊盘覆盖区内的导电迹线442的那部分基底440之间的空间内。
为了实现期望的自限制性质,可以在放置到管芯凸块焊盘332或基底凸块焊盘444上之前将凸块材料浸入助焊剂溶液中以选择性地使得被凸块材料接触的区域比导电迹线442的周围区域更加可润湿。熔融凸块材料由于助焊剂溶液的可润湿性质而仍基本上被限制在由凸块焊盘限定的区域内。凸块材料未流出到可润湿性较低的区域。可以在凸块材料并不意图使该区域具有较低可润湿性的区域上形成薄氧化层或其它绝缘层。因此,在管芯凸块焊盘332或基底凸块焊盘444周围不需要掩蔽层440。
图21c示出作为直导体的平行导电迹线452的另一实施例,其具有在基底450上形成的集成矩形凸块焊盘或互连点454。在这种情况下,基底凸块焊盘454比导电迹线452宽,但是小于配合凸块的宽度。基底凸块焊盘454的侧边可以平行于导电迹线452。可以在基底450的一部分上形成掩蔽层456;然而,未在导电迹线452的基底凸块焊盘454周围形成掩蔽层。也就是说,被设计为与凸块材料配合的导电迹线452的一部分缺少将被用于回流期间的凸块包含(containment)的掩蔽层456的任何SRO。
图21d示出具有被布置成多排阵列的导电迹线460和462的另一实施例,其具有在基底466上形成以用于最大互连逸出布线密度和容量的偏移集成凸块焊盘或互连点464。交替的导电迹线460和462包括用于布线至凸块焊盘464的转弯处。每个基底凸块焊盘464的侧边与导电迹线460和462共线。可以在基底466的一部分上形成掩蔽层468;然而,未在导电迹线460和462的基底凸块焊盘464周围形成掩蔽层468。也就是说,被设计为与凸块材料配合的导电迹线460和462的一部分缺少将被用于回流期间的凸块包含的掩蔽层468的任何SRO。
图21e示出具有被布置成多排阵列的导电迹线470和472的另一实施例,其具有在基底476上形成以用于最大互连密度和容量的偏移集成凸块焊盘或互连点474。交替的导电迹线470和472包括用于布线至凸块焊盘474的转弯处。在这种情况下,基底凸块焊盘474是圆形的,并且比导电迹线470和472宽,但是小于配合互连凸块材料的宽度。可以在基底476的一部分上形成掩蔽层478;然而,未在导电迹线470和472的基底凸块焊盘474周围形成掩蔽层478。也就是说,被设计为与凸块材料配合的导电迹线470和472的一部分缺少将被用于回流期间的凸块包含的掩蔽层478的任何SRO。
图21f示出具有被布置成多排阵列的导电迹线480和482的另一实施例,其具有在基底486上形成以用于最大互连密度和容量的偏移集成凸块焊盘或互连点484。交替的导电迹线480和482包括用于布线至凸块焊盘484的转弯处。在这种情况下,基底凸块焊盘484是矩形的,并且比导电迹线480和482宽,但是小于配合互连凸块材料的宽度。可以在基底486的一部分上形成掩蔽层488;然而,未在导电迹线480和482的基底凸块焊盘484周围形成掩蔽层488。也就是说,被设计为与凸块材料配合的导电迹线480和482的一部分缺少将被用于回流期间的凸块包含的掩蔽层488的任何SRO。
作为互连过程的一个示例,半导体管芯324被放置在基底466上且凸块材料334与来自图21d的基底凸块焊盘464对准。如针对图13a—13g、14a—14d、15a—15d、16a—16c和17a—17b所述,通过压紧凸块材料或通过使凸块材料与凸块焊盘进行物理接触并随后在回流温度下对凸块材料进行回流以电气和冶金方式将凸块材料334连接到基底凸块焊盘464。
在另一实施例中,使用蒸发、电解镀覆、化学镀覆、球滴或丝网印刷工艺在基底凸块焊盘464上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合,具有可选助焊剂溶液。例如,凸块材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。使用适当的附着或结合工艺将凸块材料结合到基底凸块焊盘464。在一个实施例中,如图21g所示,通过将材料加热至其熔点以上对凸块材料进行回流以形成凸块或互连490。在某些应用中,第二次对凸块490进行回流以改善与基底凸块焊盘464的电接触。窄基底凸块焊盘464周围的凸块材料保持回流期间的管芯放置。还可以在图21a—21g的基底凸块焊盘配置上形成凸块材料334或凸块490。
在高布线密度应用中,期望的是使图21a—21g的导电迹线460和462或其它导电迹线配置的逸出节距最小化。通过出于回流包含的目的去除掩蔽层、即通过在没有掩蔽层的情况下对凸块材料进行回流来减小导电迹线460和462之间的逸出节距。由于未在管芯凸块焊盘332或基底凸块焊盘464周围形成SRO,所以可以以更精细的节距形成导电迹线460和462,即将导电迹线460和462更近地设置在一起或接近于附近结构。在基底凸块焊盘464周围没有SRO的情况下,导电迹线460和462之间的节距被给定为P = D/2 + PLT + W/2,其中,D是凸块490的底部直径,PLT是管芯放置公差,并且W是导电迹线460和462的宽度。在一个实施例中,给定100μm的凸块底部直径、10μm的PLT和30μm的迹线线宽,导电迹线460和462的最小逸出节距是125μm。如在现有技术中发现的,无掩膜凸块形成消除了考虑相邻开口之间的掩蔽材料的带状间隔、SRT和最小可分辨SRO的需要。
当在没有掩蔽层的情况下对凸块材料进行回流以便以冶金和电气方式将管芯凸块焊盘332连接到基底凸块焊盘464时,润湿和表面张力促使凸块材料保持自限制,并被保持在管芯凸块焊盘332和基底凸块焊盘464与直接邻近于基本上在凸块焊盘覆盖区内的导电迹线460和462的那部分基底466之间的空间内。
为了实现期望的自限制性质,可以在放置到管芯凸块焊盘332或基底凸块焊盘464上之前将凸块材料浸入助焊剂溶液中以选择性地使得被凸块材料接触的区域比导电迹线460和462的周围区域更加可润湿。熔融凸块材料由于助焊剂溶液的可润湿性性质而仍基本上被限制在由凸块焊盘限定的区域内。凸块材料未流出到可润湿性较低的区域。可以在凸块材料并不意图使该区域具有较低可润湿性的区域上形成薄氧化层或其它绝缘层。因此,在管芯凸块焊盘332或基底凸块焊盘464周围不需要掩蔽层468。
在图22a中,在导电迹线494和496的一部分上沉积掩蔽层492。然而,未在集成凸块焊盘498上形成掩蔽层492。因此,在基底500上不存在用于每个凸块焊盘498的SRO。在以填隙方式在集成凸块焊盘498的阵列内的基底500上、即在相邻凸块焊盘之间形成不可润湿掩蔽贴片502。还可以以填隙方式在管芯凸块焊盘498的阵列内的半导体管芯324上形成掩蔽贴片502。更一般而言,以任何布置与集成凸块焊盘紧密接近地形成掩蔽贴片以防止流出至可润湿性较低的区域。
半导体管芯324被放置在基底500上且凸块材料与基底凸块焊盘498对准。如针对图13a—13g、14a—14d、15a—15d、16a—16c和17a—17b所述,通过压紧凸块材料或通过使凸块材料与凸块焊盘进行物理接触并随后在回流温度下对凸块材料进行回流以电气和冶金方式将凸块材料连接到基底凸块焊盘498。
在另一实施例中,使用蒸发、电解镀覆、化学镀覆、球滴或丝网印刷工艺在管芯集成凸块焊盘498上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合,具有可选助焊剂溶液。例如,凸块材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。使用适当的附着或结合工艺将凸块材料结合到集成凸块焊盘498。在一个实施例中,通过将材料加热至其熔点以上形成球状球或凸块504来对凸块材料进行回流。在某些应用中,第二次对凸块504进行回流以改善与集成凸块焊盘498的电接触。还可以将凸块压缩结合到集成凸块焊盘498。凸块504表示可以在集成凸块焊盘498上形成的一种互连结构。互连结构还可以使用支柱凸块、微型凸块或其它电互连。
在高布线密度应用中,期望的是使逸出节距最小化。为了减小导电迹线494与496之间的节距,在集成凸块焊盘498周围没有掩蔽层的情况下对凸块材料进行回流。通过出于回流包含的目的去除掩蔽层和集成凸块焊盘周围的相关SRO、即通过在没有掩蔽层的情况下对凸块材料进行回流来减小导电迹线494和496之间的逸出节距。可以远离集成凸块焊盘498在导电迹线494和496的一部分和基底500上形成掩蔽层492;然而,不在集成凸块焊盘498周围形成掩蔽层492。也就是说,被设计为与凸块材料配合的导电迹线494和496的一部分缺少将被用于回流期间的凸块包含的掩蔽层492的任何SRO。
另外,以填隙方式在集成凸块焊盘498的阵列内的基底500上形成掩蔽贴片502。掩蔽贴片502是不可润湿材料。掩蔽贴片502可以是与掩蔽层492相同的材料,并且在同一处理步骤期间施加,或者是在不同处理步骤期间的不同材料。可以在集成凸块焊盘498的阵列内通过迹线或焊盘的一部分的选择性氧化、镀覆或其它处理来形成掩蔽贴片502。掩蔽贴片502限制到集成凸块焊盘498的凸块材料流动并防止导电凸块焊盘浸出到相邻结构。
当用填隙方式设置在集成凸块焊盘498的阵列内的掩蔽贴片502对凸块材料进行回流时,润湿和表面张力促使凸块材料被限制并保持在管芯凸块焊盘332和集成凸块焊盘498与直接邻近于导电迹线494和496且基本上在集成凸块焊盘498的覆盖区内的那部分基底500之间的空间内。
为了实现期望的限制性质,可以在放置到管芯凸块焊盘332或集成凸块焊盘498上之前将凸块材料浸入助焊剂溶液中以选择性地使得被凸块材料接触的区域比导电迹线494和496的周围区域更加可润湿。熔融凸块材料由于助焊剂溶液的可润湿性性质而仍基本上被限制在由凸块焊盘限定的区域内。凸块材料未流出到可润湿性较低的区域。可以在凸块材料并不意图使该区域具有较低可润湿性的区域上形成薄氧化层或其它绝缘层。因此,在管芯凸块焊盘332或集成凸块焊盘498周围不需要掩蔽层492。
由于未在管芯凸块焊盘332或集成凸块焊盘498周围形成SRO,所以可以以更精细的节距形成导电迹线494和496,即可以在不进行接触和形成电短路的情况下将导电迹线设置为更加接近于相邻结构。采取相同的焊料套准设计规则,将导电迹线494和496之间的节距给定为P = (1.1D + W)/2,其中,D是凸块504的底部直径且W是导电迹线494和496的宽度。在一个实施例中,给定100μm的凸块直径和20μm的迹线线宽,导电迹线494和496的最小逸出节距是65μm。如在现有技术中发现的,凸块形成消除了考虑相邻开口之间的掩蔽材料的带状间隔和最小可分辨SRO的需要。
图23示出使用管芯附着粘合剂510将半导体管芯506堆叠在半导体管芯508上的情况下的封装上封装(PoP)505。半导体管芯506和508每个具有有源表面,该有源表面包含被实现为有源器件、无源器件、导电层和电介质层的模拟或数字电路,其在管芯内形成并被根据管芯的电气设计和功能电互连。例如,该电路可以包括在有源表面内形成的一个或多个晶体管、二极管及其它电路元件以实现模拟电路或数字电路,诸如DSP、ASIC、存储器或其它信号处理电路。半导体管芯506和508还可以包含IPD,诸如电感器、电容器和电阻器,以进行RF信号处理。
使用来自图13a—13g、14a—14d、15a—15d、16a—16c和17a—17b的任何实施例,使用在接触焊盘518上形成的凸块材料516将半导体管芯506安装到在基底514上形成的导电迹512。接触焊盘518和导电迹线512可以对应于图5—11的管芯焊盘布局中的信号焊盘、功率焊盘或接地焊盘。使用结合引线522将半导体管芯508电连接到在基底514上形成的接触焊盘520。结合引线522的相对末端被结合到半导体管芯506上的接触焊盘524。
掩蔽层526在基底514上形成并打开超过半导体管芯506的覆盖区。虽然掩蔽层526在回流期间不将凸块材料516限制于导电迹线512,但开放式掩膜可以充当屏障以防止密封剂528在MUF期间迁移至接触焊盘520或结合引线522。类似于图18a—18c,在半导体管芯508与基底514之间沉积密封剂528。掩蔽层526阻止MUF密封剂528到达接触焊盘520和结合引线522,这可能引起缺陷。掩蔽层526允许将较大的半导体管芯放置在给定基底上,而没有密封剂528流到接触焊盘520上的风险。
虽然已详细地举例说明了本发明的一个或多个实施例,但技术人员将认识到在不脱离以下权利要求所阐述的本发明的范围的情况下可以对那些实施例进行修改和改动。
Claims (25)
1. 一种制造半导体器件的方法,包括:
提供半导体管芯,该半导体管芯具有信号焊盘主要位于半导体管芯的周边区域中且功率焊盘和接地焊盘主要位于半导体管芯的自信号焊盘的内侧区域中的管芯焊盘布局;
在信号焊盘、功率焊盘和接地焊盘上形成多个凸块;
提供基底;
在所述基底上形成具有互连点的多个导电迹线,所述凸块比所述互连点宽;
将所述凸块结合到所述互连点,使得凸块覆盖互连点的顶面和侧面;以及
在半导体管芯与基底之间的凸块周围沉积密封剂。
2. 权利要求1的方法,其中,所述凸块包括可熔部分和不可熔部分。
3. 权利要求1的方法,还包括将信号焊盘布置成大体上与半导体管芯边缘平行的周边行或周边阵列。
4. 权利要求1的方法,还包括以交错布置或正交布置将信号焊盘布置成相邻行。
5. 根据权利要求1的方法,其中,少于10%的功率焊盘和接地焊盘位于周边区域内且少于10%的信号焊盘位于内侧区域内。
6. 权利要求1的方法,还包括在远离互连点的基底区域上形成掩蔽层。
7. 一种制造半导体器件的方法,包括:
提供半导体管芯;
提供基底;
在所述基底上形成具有以信号点位于基底的周边附近且功率点和接地点位于自信号点的内侧的布局布置的互连点的多个导电迹线;以及
在半导体管芯与基底之间形成互连结构,使得互连结构覆盖互连点的顶面和侧面。
8. 权利要求7的方法,还包括在半导体管芯与基底之间沉积密封剂。
9. 权利要求7的方法,其中,所述互连结构包括可熔部分和不可熔部分。
10. 权利要求7的方法,还包括将信号点布置成大体上与基底边缘平行的周边行或周边阵列。
11. 权利要求7的方法,还包括以交错布置或正交布置将信号点布置成相邻行。
12. 权利要求7的方法,还包括在基底的中心附近将功率和接地点布置成阵列。
13. 权利要求7的方法,其中,所述半导体管芯的中心区域不具有焊盘。
14. 一种制造半导体器件的方法,包括:
提供半导体管芯;
提供基底;
在所述基底上形成具有以信号点主要位于基底的周边区域中且功率点和接地点主要位于基底的自信号焊盘的内侧区域中的布局布置的互连点的多个导电迹线;
将半导体管芯结合到互连点;以及
在半导体管芯与基底之间沉积密封剂。
15. 权利要求14的方法,还包括在半导体管芯上形成互连结构,所述互连结构包括可熔部分和不可熔部分。
16. 权利要求14的方法,其中,少于10%的功率点和接地点位于周边区域内。
17. 权利要求14的方法,其中,少于10%的信号点位于内侧区域内。
18. 权利要求14的方法,还包括将信号点布置成大体上与基底边缘平行的周边行或周边阵列。
19. 权利要求14的方法,还包括在基底的中心附近将功率点和接地点布置成阵列。
20. 权利要求14的方法,还包括以交错布置或正交布置将信号点布置成相邻行。
21. 一种半导体器件,包括:
半导体管芯,该半导体管芯具有信号焊盘主要位于半导体管芯的周边区域中且功率焊盘和接地焊盘主要位于半导体管芯的自信号焊盘的内侧区域中的管芯焊盘布局;
基底;
所述基底上形成的具有互连点的多个导电迹线,其中,所述半导体管芯被结合到互连点;以及
沉积在所述半导体管芯与基底之间的密封剂。
22. 权利要求21的半导体器件,还包括在半导体管芯上形成的互连结构,所述互连结构包括可熔部分和不可熔部分。
23. 权利要求21的半导体器件,其中,少于10%的功率焊盘和接地焊盘位于周边区域内。
24. 权利要求21的半导体器件,其中,少于10%的信号焊盘位于内侧区域内。
25. 权利要求21的半导体器件,还包括以交错布置或正交布置将信号焊盘布置成相邻行。
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TWI667759B (zh) | 2019-08-01 |
SG181206A1 (en) | 2012-06-28 |
US8853001B2 (en) | 2014-10-07 |
US20150054167A1 (en) | 2015-02-26 |
CN102487021B (zh) | 2015-10-07 |
US20120241984A9 (en) | 2012-09-27 |
US9780057B2 (en) | 2017-10-03 |
KR101798657B1 (ko) | 2017-11-16 |
TW201614789A (en) | 2016-04-16 |
JP2012119648A (ja) | 2012-06-21 |
US20110074047A1 (en) | 2011-03-31 |
TWI528515B (zh) | 2016-04-01 |
SG10201402301RA (en) | 2014-07-30 |
TW201250958A (en) | 2012-12-16 |
KR20120061712A (ko) | 2012-06-13 |
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