CN102468197B - 半导体器件以及形成倒装芯片互连结构的方法 - Google Patents

半导体器件以及形成倒装芯片互连结构的方法 Download PDF

Info

Publication number
CN102468197B
CN102468197B CN201110058357.1A CN201110058357A CN102468197B CN 102468197 B CN102468197 B CN 102468197B CN 201110058357 A CN201110058357 A CN 201110058357A CN 102468197 B CN102468197 B CN 102468197B
Authority
CN
China
Prior art keywords
interconnection
substrate
semiconductor element
conductive trace
projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110058357.1A
Other languages
English (en)
Other versions
CN102468197A (zh
Inventor
R·D·彭德塞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stats Chippac Shanghai Co Ltd
Stats Chippac Pte Ltd
Original Assignee
Stats Chippac Shanghai Co Ltd
Stats Chippac Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Shanghai Co Ltd, Stats Chippac Pte Ltd filed Critical Stats Chippac Shanghai Co Ltd
Publication of CN102468197A publication Critical patent/CN102468197A/zh
Application granted granted Critical
Publication of CN102468197B publication Critical patent/CN102468197B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/64—Manufacture or treatment of solid state devices other than semiconductor devices, or of parts thereof, not peculiar to a single device provided for in groups H01L31/00 - H10K99/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141—Guiding structures both on and outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134—Bonding interfaces of the bump connector
    • H01L2224/81345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及半导体器件以及形成倒装芯片互连结构的方法。一种半导体器件具有半导体管芯，该半导体管芯具有形成在半导体管芯的有源表面上的多个凸块或互连结构。凸块可以具有可熔部分和非可熔部分，例如导电柱和形成在导电柱上的凸块。具有互连部位的多个导电迹线形成在衬底上。凸块宽于互连部位。掩蔽层形成在衬底的远离互连部位的区域上。凸块在压力或回流温度下被结合到互连部位，使得凸块覆盖互连部位的顶面和侧面。密封剂沉积在管芯与衬底之间的凸块周围。掩蔽层可以形成坝状物以阻挡密封剂延伸到半导体管芯之外。凸起体可以形成在互连部位或凸块上。

Description

半导体器件以及形成倒装芯片互连结构的方法
要求本国优先权
本申请是2004年5月20日提交的美国申请No.10/849,947的部分延续，并且依据35U.S.C.§120要求在先申请的优先权。
技术领域
本发明总体上涉及半导体器件，并且更具体地涉及半导体器件以及形成倒装芯片互连结构的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池、以及数字微镜器件(DMD)。
半导体器件执行多种功能，例如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流(base current)或者通过掺杂工艺来操纵(manipulated)它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构(包括双极和场效应晶体管)控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构(包括电阻器、电容器、和电感器)产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化(singulating)单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占用空间(footprint)，其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占用空间的半导体器件封装。
在电子封装组件中通常会发现半导体管芯与衬底之间的倒装芯片互连。在最普通的形式中，通常通过使用回流工艺熔化凸块材料，半导体管芯上的互连凸块冶金接合到形成于衬底上的焊盘。在凸块材料的回流提供鲁棒连接的同时，在回流和固化工艺期间由于桥接的风险(即相邻连接之间的短路)导致难以减小互连的间距。在替换方法中，使用颗粒膜或膏剂来形成附连，由此该膏剂或膜中的导电颗粒连同树脂的收缩力一起实现电连接。颗粒膜方法适合于减小互连间距，但要承受由于颗粒互连随时间退化的敏感性而导致的有限的长期可靠性。
发明内容
在微间距应用中存在一种在半导体管芯及衬底之间形成可靠且鲁棒的互连接合的需求。因此，在一个实施例中，本发明提供一种制造半导体器件的方法，该方法包括以下步骤：提供半导体管芯，该半导体管芯具有形成在半导体管芯的有源表面上的多个凸块，提供衬底，以及在衬底上形成具有互连部位(interconnect site)的多个导电迹线。凸块宽于互连部位。该方法进一步包括以下步骤：在衬底的远离互连部位的区域上形成掩蔽层，将凸块结合到互连部位使得凸块覆盖互连部位的顶面及侧面，以及在半导体管芯与衬底间的凸块的周围沉积密封剂。
在另一个实施例中，本发明提供一种制造半导体器件的方法，该方法包括以下步骤：提供半导体管芯，该半导体管芯具有形成在半导体管芯表面上的多个互连结构，提供衬底，在衬底上形成具有互连部位的多个导电迹线，将互连结构结合至没有掩模开口的互连部位使得互连结构覆盖互连部位的顶面及侧面，以及在半导体管芯与衬底间的凸块的周围沉积密封剂。互连结构宽于互连部位。
在另一个实施例中，本发明提供一种制造半导体器件的方法，该方法包括以下步骤：提供半导体管芯，该半导体管芯具有形成在半导体管芯表面上的多个互连结构，提供衬底，在衬底上形成具有互连部位的多个导电迹线，以及将互连结构结合至没有掩模开口的互连部位使得互连结构覆盖互连部位的顶面及侧面。互连部位窄于互连结构。
在另一个实施例中，本发明提供一种包括半导体管芯的半导体器件，该半导体管芯具有形成在半导体管芯表面上的多个互连结构。具有互连部位的多个导电迹线形成在衬底上。互连部位窄于互连结构。互连结构被结合在互连部位上使得互连结构覆盖互连部位的顶面及侧面。密封剂沉积在半导体管芯与衬底间的互连结构周围。
附图说明
图1示出具有安装到其表面的不同类型封装的PCB；
图2a-2c示出安装到所述PCB的半导体封装的更多细节；
图3a-3h示出了形成在半导体管芯上的用于结合到衬底上的导电迹线的各种互连结构；
图4a-4g示出了半导体管芯及结合到导电迹线的互连结构；
图5a-5d示出了具有结合到导电迹线的楔形互连结构的半导体管芯；
图6a-6d示出了半导体管芯及结合到导电迹线的互连结构的另一个实施例；
图7a-7c示出了结合到导电迹线的阶梯状凸块及柱形凸块(stud bump)互连结构；
图8a-8b示出了具有导电通路的导电迹线；
图9a-9c示出了在半导体管芯和衬底之间的模塑底层填充；
图10示出了在半导体管芯和衬底之间的另一种模塑底层填充；
图11示出了模塑底层填充后的半导体管芯及衬底；
图12a-12g示出了具有开放的焊料对准(open solder registration)的导电迹线的各种排列；
图13a-13b示出了在导电迹线之间具有补片(patch)的开放的焊料对准；以及
图14示出了具有在模塑底层填充期间限制密封剂的掩蔽层坝状物(maskinglayer dam)的POP。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积(CVD)、物理汽相沉积(PVD)、电解电镀、以及无电极电镀(electroless plating)工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌(topography)，产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区(saw street)或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块、导电胶、或线结合(wirebond)来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图1示出具有芯片载体衬底或印刷电路板(PCB)52的电子器件50，所述芯片载体衬底或印刷电路板(PCB)52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理(PDA)、数字摄像机(DVC)或其它电子通信设备的一部分。可替换地，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。小型化及重量减轻对于这些将被市场所接受的产品是必要的。半导体器件之间的距离必须被减小以实现更高的密度。
在图1中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括线结合封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、岸面栅格阵列(land grid array，LGA)66、多芯片模块(MCM)68、四侧无引脚扁平封装(quad flat non-leaded package，QFN)70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料(例如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、或银(Ag))的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料(例如热的环氧或环氧树脂)将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或结合线82来进行环境保护。
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。结合线94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和结合线94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图2c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
图3a示出了具有基本衬底材料122的半导体晶片120，所述基本衬底材料例如是硅、锗、砷化镓、磷化铟或碳化硅，用于结构支撑。多个半导体管芯或元件124形成在晶片120上，如上所述那样被划片街区126分开。
图3b示出了半导体晶片120的一部分的截面图。每个半导体管芯124具有后表面128和有源表面130，该有源表面130包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面130内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器(DSP)、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括集成无源器件(IPD)，例如电感器、电容器、和电阻器，用于RF信号处理。在一个实施例中，半导体管芯124是倒装芯片类型的半导体管芯。
利用PVD、CVD、电解电镀、无电极电镀工艺或其它适当的金属沉积工艺将导电层132形成在有源表面130上。导电层132可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层132用作电连接到有源表面130上的电路的接触焊盘。
图3c示出了具有形成在接触焊盘132上的互连结构的半导体晶片120的一部分。使用蒸发、电解电镀、无电极电镀、球滴(ball drop)或丝网印刷工艺将导电凸块材料134沉积在接触焊盘132上。凸块材料134可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，或其组合，以及可选的焊剂溶液。例如，凸块材料134可以是共晶Sn/Pb、高铅焊料、或无铅焊料。凸块材料134通常是顺从的(compliant)并且在等价于约250克的垂直负荷的力下经受大于约25微米(μm)的塑性变形。利用合适的附着或结合工艺将凸块材料134结合到接触焊盘132。例如，凸块材料134可以被压缩结合到接触焊盘132。也可以通过将凸块材料134加热到它的熔点以上，所述凸块材料134回流以形成球形球或凸块136，如图3d所示。在一些应用中，凸块136被二次回流以改善到接触焊盘132的电接触。凸块136表示一种可以形成在接触焊盘132上的互连结构。所述互连结构也可以使用柱形凸块、微凸块、或其它电互连。
图3e示出了形成在接触焊盘132上的互连结构的另一个实施例，如包括非可熔或非可坍陷部分140以及可熔或可坍陷部分142的复合凸块138。关于回流条件来针对凸块138限定可熔或可坍陷以及非可熔或非可坍陷属性。非可熔部分140可以是金、铜、镍、高铅焊料或铅锡合金。可熔部分142可以是锡、无铅合金、锡银合金、锡银铜合金、锡银铟(In)合金、共晶焊料、具有银、铜或铅的锡合金、或其它相对低温熔化的焊料。在一个实施例中，给定接触焊盘132的宽度或直径为100微米，则非可熔部分140大约45微米高，且可熔部分142大约35微米高。
图3f示出了形成在接触焊盘132上的互连结构的另一个实施例，如导电柱146上的凸块144。凸块144是可熔或可坍陷的并且导电柱146是非可熔或非可坍陷的。可熔或可坍陷以及非可熔或非可坍陷属性是关于回流条件来限定的。凸块144可以是锡、无铅合金、锡银合金、锡银铜合金、锡银铟合金、共晶焊料、具有银、铜或铅的锡合金、或其它相对低温熔化的焊料。导电柱146可以是金、铜、镍、高铅焊料或铅锡合金。在一个实施例中，导电柱146是铜柱并且凸块144是焊料帽。给定接触焊盘132的宽度或直径为100微米，则导电柱146大约45微米高，且凸块144大约35微米高。
图3g示出了形成在接触焊盘132上的互连结构的另一个实施例，如具有凸起体(asperities)150的凸块材料148。类似于凸块材料134，凸块材料148是软的且在回流条件下以低屈服强度和高失效伸长性(high elongation to failure)可变形。凸起体150使用电镀表面加工形成并且被夸大地显示在图中用以说明。凸起体150的数值范围一般在约1-25微米的量级。凸起体也可以形成在凸块136、复合凸块138及凸块144上。
在图3h中，使用锯条或激光切割工具152通过划片街区126将半导体晶片120单体化为单个半导体管芯124。
图4a示出了具有导电迹线156的衬底或PCB 154。衬底154可以是单面FR5叠层或者双面BT树脂叠层。半导体管芯124被放置为使得凸块材料134对准导电迹线156上的互连部位，参见图12a-12g。可替换地，凸块材料134可以对准形成在衬底154上的导电焊盘或其它互连部位。凸块材料134比导电迹线156更宽。在另一个实施例中，对于150微米的凸块间距，凸块材料134具有80微米的宽度且导电迹线或焊盘156具有35微米的宽度。压力或力F施加到半导体管芯124的后表面128以将凸块材料134压制到导电迹线156上。力F可以在升高的温度下施加。由于凸块材料134的顺从性质，凸块材料在导电迹线156的顶面及侧面周围变形或突出，称为引线上凸块(bump-on-lead，BOL)。特别地，压力的施加引起凸块材料134在等价于约250克的垂直负荷的力F下经受大于约25μm的塑性变形，并且覆盖导电迹线的顶面及侧面，如图4b所示。也可以通过将凸块材料134与导电迹线156在回流温度下物理接触，然后回流凸块材料134，来将凸块材料134冶金连接到导电迹线156。
通过使导电迹线156窄于凸块材料134，导电迹线间距可以被降低，以提高布线密度和I/O数目。较窄的导电迹线156降低了使导电迹线周围的凸块材料134变形所需的力F。例如，必需的力F可以是使凸块材料相对于宽于凸块材料的导电迹线或焊盘变形所需的力的30-50％。更小的压缩力F用于细间距互连和小管芯，以便在规定的容限下维持共面性并实现均匀Z方向变形及高可靠性互连结合(union)。另外，使导电迹线156周围的凸块材料134变形会将凸块机械锁定到迹线以防止回流期间管芯移动或管芯浮动。
图4c示出了形成在半导体管芯124的接触焊盘132上的凸块136。半导体管芯124被定位成使得凸块136与导电迹线156上的互连部位对准。可替换地，凸块136可以与形成在衬底154上的导电焊盘或其它互连部位对准。凸块136比导电迹线156宽。压力或力F施加到半导体管芯124的后表面128以将凸块136压制到导电迹线156上。力F可以在升高的温度下施加。由于凸块136的顺从性质，凸块在导电迹线156的顶面及侧面周围变形或突出。特别地，压力的施加引起凸块材料136经受塑性变形并且覆盖导电迹线156的顶面及侧面。也可以通过将凸块136与导电迹线156在回流温度下物理接触来将凸块136冶金连接到导电迹线156。
通过使导电迹线156窄于凸块136，导电迹线间距可以被降低，以提高布线密度和I/O数目。更窄的导电迹线156降低了使导电迹线周围的凸块136变形所需的力F。例如，必需的力F可以是使凸块相对于宽于凸块的导电迹线或焊盘变形所需的力的30-50％。更小的压缩力F用于细间距互连和小管芯，以便在规定的容限下维持共面性并实现均匀Z方向变形及高可靠性互连结合。另外，使导电迹线156周围的凸块136变形会将凸块机械锁定到迹线以防止回流期间管芯移动或管芯浮动。
图4d示出了形成在半导体管芯124的接触焊盘132上的复合凸块138。半导体管芯124被定位成使得复合凸块138与导电迹线156上的互连部位对准。可替换地，复合凸块138可以与形成在衬底154上的导电焊盘或其它互连部位对准。复合凸块138比导电迹线156宽。压力或力F施加到半导体管芯124的后表面128以将可熔部分142压制到导电迹线156上。力F可以在升高的温度下施加。由于可熔部分142的顺从性质，可熔部分在导电迹线156的顶面及侧面周围变形或突出。特别地，压力的施加引起可熔部分142经受塑性变形并且覆盖导电迹线156的顶面及侧面。也可以通过将可熔部分142与导电迹线156在回流温度下物理接触来将复合凸块138冶金连接到导电迹线156。非可熔部分140在施加压力或温度期间不熔化或变形，并且保持它的高度和形状而作为半导体管芯124和衬底154之间的垂直支座。半导体管芯124和衬底154之间的附加位移提供配合表面间的更大共面性容限。
在回流工艺期间，半导体管芯124上的大量(例如成千个)复合凸块138被附连到衬底154的导电迹线156上的互连部位。复合凸块138中的一些可能没有正确地连接到导电迹线156，特别是如果管芯124翘曲的话。回想复合凸块138宽于导电迹线156。在施加正确力的情况下，可熔部分142在导电迹线156的顶面及侧面周围变形或突出并且机械锁定复合凸块138到导电迹线。通过可熔部分142比导电迹线156更软和更顺从并因此在导电迹线的顶面上及侧面周围变形以获得更大的接触表面积的性质来形成机械互锁。复合凸块138与导电迹线156之间的机械互锁在回流期间将凸块保持在导电迹线，也就是，凸块及导电迹线不会失去接触。因此，与导电迹线156配合的复合凸块138降低了凸块互连失效。
图4e示出了形成在半导体管芯124的接触焊盘132上的导电柱146和凸块144。半导体管芯124被定位成使得凸块144对准导电迹线156上的互连部位。可替换地，凸块144可以与形成在衬底154上的导电焊盘或其它互连部位对准。凸块144宽于导电迹线156。压力或力F施加到半导体管芯124的后表面128以将凸块144压制到导电迹线156上。力F可以在升高的温度下施加。由于凸块144的顺从性质，凸块在导电迹线156的顶面及侧面周围变形或突出。特别地，压力的施加引起凸块144经受塑性变形，并且覆盖导电迹线156的顶面及侧面。也可以通过将凸块144与导电迹线156在回流温度下物理接触来将导电柱146和凸块144冶金连接到导电迹线156。导电柱146在施加压力或温度期间不熔化或变形，并且保持它的高度和形状而作为半导体管芯124和衬底154之间的垂直支座。半导体管芯124和衬底154之间的附加位移提供配合表面间的更大共面性容限。更宽的凸块144和更窄的导电迹线156具有以上针对凸块材料134和凸块136描述的相似的低的必需的压缩力和机械锁特征和优点。
图4f示出形成半导体管芯124的接触焊盘132上的具有凸起体150的凸块材料148。半导体管芯124被定位成使得凸块材料148与导电迹线156上的互连部位对准。可替换地，凸块材料148可以对准形成在衬底154上的导电焊盘或其它互连部位。凸块材料148宽于导电迹线156。压力或力F施加到半导体管芯124的后表面128以将凸块材料148压制到导电迹线156上。力F可以在升高的温度下施加。由于凸块材料148的顺从性质，凸块在导电迹线156的顶面及侧面周围变形或突出。特别地，压力的施加引起凸块材料148经受塑性变形，并且覆盖导电迹线156的顶面及侧面。此外，凸起体150冶金地连接到导电迹线156。凸起体150的尺寸在约1-25微米的量级。
图4g示出了包括具有有角度的或倾斜的边的梯形导电迹线160的衬底或PCB 158。凸块材料161形成在半导体管芯124的接触焊盘132上。半导体管芯124被定位成使得凸块材料161对准导电迹线160上的互连部位。可替换地，凸块材料161可以对准形成在衬底158上的导电焊盘或其它互连部位。凸块材料161宽于导电迹线160。压力或力F施加到半导体管芯124的后表面128以将凸块材料161压制到导电迹线160上。力F可以在升高的温度下施加。由于凸块材料161的顺从性质，凸块材料在导电迹线160的顶面及侧面周围变形或突出。特别地，压力的施加引起凸块材料161在力F下经受塑性变形以覆盖导电迹线160的顶面及有角度的侧面。也可以通过将凸块材料161与导电迹线156在回流温度下物理接触，然后回流凸块材料，来将凸块材料161冶金连接到导电迹线160。
图5a-5d示出了半导体管芯124及具有非可熔或非可坍陷部分164和可熔或可坍陷部分166的拉长的复合凸块162的BOL实施例。非可熔部分164可以是金、铜、镍、高铅焊料或铅锡合金。可熔部分166可以是锡、无铅合金、锡银合金、锡银铜合金、锡银铟合金、共晶焊料、具有银、铜或铅的锡合金、或其它相对低温熔化的焊料。非可熔部分164构成复合凸块162的比可熔部分166更大的部分。非可熔部分164固定到半导体管芯124的接触焊盘132。
半导体管芯124被定位成使得复合凸块162对准形成在衬底170上的导电迹线168的互连部位，如图5a所示。复合凸块162沿着导电迹线168逐渐变细，也就是，复合凸块具有楔形形状，沿着导电迹线168的长度较长并且跨过导电迹线较窄。复合凸块162的锥形平面形状(aspect)沿导电迹线168的长度出现。图5a的视图示出了与导电迹线168共线的较短平面形状或变窄的锥形。图5b的视图，垂直于图5a，示出了楔形复合凸块162的较长平面形状。复合凸块162的较短平面形状宽于导电迹线168。在施加压力和/或利用热回流时可熔部分166在导电迹线168周围塌陷，如图5c和5d中所示。非可熔部分164在回流期间不熔化或变形并且保持它的高度和形状。非可熔部分164可以被定尺寸成在半导体管芯124和衬底170之间提供支座距离。抛光，如铜OSP，可以被应用于衬底170。
在回流工艺期间，半导体管芯124上的大量(例如成千个)复合凸块162被附连到衬底170的导电迹线168上的互连部位。复合凸块162中的一些可能没有正确地连接到导电迹线168，特别是如果管芯124翘曲的话。回想复合凸块162宽于导电迹线168。在施加正确力的情况下，可熔部分166在导电迹线168的顶面及侧面周围变形或突出并且机械锁定复合凸块162到导电迹线。通过可熔部分166比导电迹线168更软和更顺从并因此在导电迹线的顶面及侧面周围变形以获得更大的接触表面积的性质来形成机械互锁。复合凸块162的楔形形状提高了凸块和导电迹线之间的接触面积，例如，沿着图5b和5d的较长平面形状，而没有牺牲沿图5a和5c的较短平面形状的间距。复合凸块162与导电迹线168之间的机械互锁在回流期间将凸块保持在导电迹线，也就是，凸块及导电迹线不会失去接触。因此，与导电迹线168配合的复合凸块162降低了凸块互连失效。
图6a-6d示出了具有形成在接触焊盘132上的凸块材料174的半导体管芯124的BOL实施例，类似于图3c。凸块材料174通常是顺从的并且在等价于约250克的垂直负荷的力下经受大于约25μm的塑性变形。凸块材料174宽于衬底178上的导电迹线176。多个凸起体180形成在导电迹线176上且高度在约1-25微米的量级。
在图6a中，半导体管芯124被定位成使得凸块材料174对准导电迹线176上的互连部位。可替换地，凸块材料174可以对准形成在衬底178上的导电焊盘或其它互连部位。压力或力F施加到半导体管芯124的后表面128以将凸块材料174压制到导电迹线176及凸起体180上，如图6b所示。力F可以在升高的温度下施加。由于凸块材料174的顺从性质，凸块材料在导电迹线176及凸起体180的顶面及侧面周围变形或突出。特别地，压力的施加引起凸块材料174经受塑性变形，并且覆盖导电迹线176及凸起体180的顶面及侧面。凸块材料174的塑性流动在凸块材料与导电迹线176及凸起体180的顶面及侧面之间生成宏观的机械互锁点。凸块材料174的塑性流动发生在导电迹线176及凸起体180的顶面及侧面周围，但是没有过度地延伸到衬底178上，这可能引起电短路和其它缺陷。凸块材料与导电迹线176及凸起体180的顶面及侧面之间的机械互锁提供相应表面间的更大接触面积的鲁棒连接，而没有显著地提高结合力。凸块材料与导电迹线176及凸起体180的顶面及侧面之间的机械互锁也降低了在后续制造工艺(如密封)期间的横向管芯移动。
图6c示出了凸块材料174窄于导电迹线176的另一个BOL实施例。压力或力F施加到半导体管芯124的后表面128以将凸块材料174压制到导电迹线176及凸起体180上。力F可以在升高的温度下施加。由于凸块材料174的顺从性质，凸块材料在导电迹线176及凸起体180的顶面及侧面周围变形或突出。特别地，压力的施加引起凸块材料174经受塑性变形，并且覆盖导电迹线176及凸起体180的顶面。凸块材料174的塑性流动在凸块材料与导电迹线176及凸起体180的顶面之间生成宏观的机械互锁点。凸块材料与导电迹线176及凸起体180的顶面之间的机械互锁提供相应表面间的更大接触面积的鲁棒连接，而没有显著地提高结合力。凸块材料与导电迹线176及凸起体180的顶面之间的机械互锁也降低了在后续制造工艺(如密封)期间的横向管芯移动。
图6d示出了凸块材料174形成在导电迹线176的边缘上的另一个BOL实施例，即凸块材料的一部分在导电迹线上以及凸块材料的一部分没有在导电迹线上。压力或力F施加到半导体管芯124的后表面128以将凸块材料174压制到导电迹线176及凸起体180上。力F可以在升高的温度下施加。由于凸块材料174的顺从性质，凸块材料在导电迹线176及凸起体180的顶面及侧面周围变形或突出。特别地，压力的施加引起凸块材料174经受塑性变形，并且覆盖导电迹线176及凸起体180的顶面及侧面。凸块材料174的塑性流动在凸块材料与导电迹线176及凸起体180的顶面及侧面之间生成宏观的机械互锁点。凸块材料与导电迹线176及凸起体180的顶面及侧面之间的机械互锁提供相应表面间的更大接触面积的鲁棒连接，而没有显著地提高结合力。凸块材料与导电迹线176及凸起体180的顶面及侧面之间的机械互锁也降低了在后续制造工艺(如密封)期间的横向管芯移动。
图7a-7c示出了具有形成在接触焊盘132上的凸块材料184的半导体管芯124的BOL实施例，类似于图3c。末端(tip)186从凸块材料184的本体延伸作为阶梯状凸块且末端186窄于凸块材料184的本体，如图7a所示。半导体管芯124被定位成使得凸块材料184对准衬底190上的导电迹线188上的互连部位。更具体地，末端186中心位于导电迹线188上的互连部位上。可替换地，凸块材料184和末端186可以对准形成在衬底190上的导电焊盘或其它互连部位。凸块材料184宽于衬底190上的导电迹线188。
导电迹线188通常是顺从的并且在等价于约250克的垂直负荷的力下经受大于约25μm的塑性变形。压力或力F施加到半导体管芯124的后表面128以将末端186压制到导电迹线188上。力F可以在升高的温度下施加。由于导电迹线188的顺从性质，导电迹线在末端186的周围变形，如图7b所示。特别地，压力的施加引起导电迹线188经受塑性变形，并且覆盖末端186的顶面及侧面。
图7c示出了圆形的凸块材料194形成在接触焊盘132上的另一个BOL实施例。末端196从凸块材料194的本体延伸以形成具有末端窄于凸块材料194的本体的柱形凸块。半导体管芯124被定位成使得凸块材料194对准衬底200上的导电迹线198上的互连部位。更具体地，末端196的中心在导电迹线198上的互连部位上。可替换地，凸块材料194和末端196可以对准形成在衬底200上的导电焊盘或其它互连部位。凸块材料194宽于衬底200上的导电迹线198。
导电迹线198通常是顺从的并且在等价于约250克的垂直负荷的力下经受大于约25μm的塑性变形。压力或力F施加到半导体管芯124的后表面128以将末端196压制到导电迹线198上。力F可以在升高的温度下施加。由于导电迹线198的顺从性质，导电迹线在末端196的周围变形。特别地，压力的施加引起导电迹线198经受塑性变形，并且覆盖末端196的顶面及侧面。
图4a-4g、5a-5d及6a-6d中描述的导电迹线也可以是如图7a-7c所描述的顺从材料。
图8a-8b示出了具有形成在接触焊盘132上的凸块材料204的半导体管芯124的BOL实施例，类似于图3c。凸块材料204通常是顺从的并且在等价于约250克的垂直负荷的力下经受大于约25μm的塑性变形。凸块材料204宽于衬底208上的导电迹线206。导电通路210被形成为穿过具有开口212和导电侧壁214的导电迹线206，如图8a所示。
半导体管芯124被定位成使得凸块材料204对准导电迹线206上的互连部位，参见图12a-12g。可替换地，凸块材料204可以对准形成在衬底208上的导电焊盘或其它互连部位。压力或力F施加到半导体管芯124的后表面128以将凸块材料204压制到导电迹线206上并且进入导电通路210的开口212中。力F可以在升高的温度下施加。由于凸块材料204的顺从性质，凸块材料在导电迹线176的顶面及侧面周围变形或突出并且进入导电通路210的开口212中，如图8b所示。特别地，压力的施加引起凸块材料204经受塑性变形，并且覆盖导电迹线206的顶面及侧面及进入导电通路210的开口212中。凸块材料204因此电连接到导电迹线206及导电侧壁214，用于穿过衬底208的z方向垂直互连。凸块材料204的塑性流动在凸块材料与导电迹线206及导电通路210的开口212的顶面及侧面之间生成机械互锁。凸块材料与导电迹线206及导电通路210的开口212的顶面及侧面之间的机械互锁提供相应表面间的更大接触面积的鲁棒连接，而没有显著地提高结合力。凸块材料与导电迹线206及导电通路210的开口212的顶面及侧面之间的机械互锁也降低了在后续制造工艺(如密封)期间的横向管芯移动。由于导电通路210形成在具有凸块材料204的互连部位中，因此总的衬底互连面积降低。
在图4a-4g、5a-5d、6a-6d、7a-7c及8a-8b的BOL实施例中，通过使导电迹线窄于互连结构，导电迹线的间距可以降低以提高布线密度和I/O数目。较窄的导电迹线降低了使导电迹线周围的互连结构变形所需的力F。例如，必需的力F可以是使凸块相对于宽于凸块的导电迹线或焊盘变形所需的力的30-50％。更小的压缩力F用于细间距互连和小管芯，以便在规定的容限下维持共面性并实现均匀Z方向变形及高可靠性互连结合。另外，使导电迹线周围的互连结构变形会将凸块机械锁定到迹线以防止回流期间管芯移动或管芯浮动。
图9a-9c示出了围绕半导体管芯和衬底之间的凸块沉积密封剂的模塑底层填充(MUF)工艺。图9a示出了使用来自图4b的凸块材料134安装到衬底154的并且放置在模塑槽(chase mold)220的上模塑支撑216与下模塑支撑218之间的半导体管芯124。来自图4a-4g、5a-5d、6a-6d、7a-7c及8a-8b的其它半导体管芯和衬底组合可以被放置在模塑槽220的上模塑支撑216与下模塑支撑218之间。上模塑支撑216包括可压缩释放膜222。
在图9b中，上模塑支撑216与下模塑支撑218放到一起以围住半导体管芯124和衬底154，且在衬底上、半导体管芯与衬底之间具有开放空间。可压缩释放膜222与半导体管芯124的后表面128及侧面一致以阻止这些表面上的密封剂的形成。液体状态的密封剂224使用喷嘴226注入模塑槽220的一侧中，同时可选的真空辅助设备(vacuum assist)228从相对侧汲取压力以利用密封剂均匀填充衬底154上的开放空间和半导体管芯124与衬底154之间的开放空间。密封剂224可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂224不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。可压缩材料222防止密封剂224流到半导体管芯124的后表面128上以及半导体管芯124的侧面周围。密封剂224被固化。半导体管芯124的后表面128和侧面保持从密封剂224暴露出来。
图9c示出了MUF及没有可压缩材料222的模塑过填充(mold overfill，MOF)的一个实施例。半导体管芯124和衬底154放置在模塑槽220的上模塑支撑216与下模塑支撑218之间。上模塑支撑216与下模塑支撑218放到一起以围住半导体管芯124和衬底154，且在衬底上、半导体管芯周围、半导体管芯与衬底之间具有开放空间。液体状态的密封剂224使用喷嘴226注入模塑槽220的一侧中，同时可选的真空辅助设备228从相对侧汲取压力以利用密封剂均匀填充半导体管芯124周围的开放空间、衬底154上的开放空间、半导体管芯124与衬底154之间的开放空间。密封剂224被固化。
在另一个实施例中，喷嘴也可以放置在模塑槽或管芯带的中央区域中以将密封剂分布到半导体管芯和衬底的边缘以外。
图10示出了在半导体管芯124周围及半导体管芯124和衬底154之间的间隙中沉积密封剂的另一个实施例。半导体管芯124和衬底154由坝状物230围住。密封剂232以液体状态从喷嘴234分配到坝状物230中以填充衬底154上的开放空间及半导体管124芯与衬底154之间的开放空间。从喷嘴234分配的密封剂232的体积被控制以填充坝状物230而不覆盖半导体管芯124的后表面128或侧面。密封剂232被固化。
图11示出了在图9a、9c及10的MUF工艺后的半导体管芯124和衬底154。密封剂224均匀地分布在衬底154上及半导体管芯124与衬底154之间的凸块材料134周围。
图12a-12g示出了衬底或PCB 240上的各种导电迹线布局的顶视图。在图12a中，导电迹线242是具有形成在衬底240上的集成凸块焊盘或互连部位244的直线导体。衬底凸块焊盘244的侧边与导电迹线242共线。在现有技术中，焊料对准开口(solder registrationopening，SRO)典型地形成在互连部位上以在回流期间包含凸块材料。SRO增加了互连间距并减少了I/O数目。相比之下，掩蔽层246可以形成在衬底240的一部分上；但是，掩蔽层不形成在导电迹线242的衬底凸块焊盘244的周围。也就是，被设计为与凸块材料配合的导电迹线242的一部分没有用于回流期间凸块保留的掩蔽层246的任何SRO。
半导体管芯124放置在衬底240上并且凸块材料134对准衬底凸块焊盘244。也可以通过将凸块材料134与凸块焊盘在回流温度下物理接触，然后回流凸块材料134，来将凸块材料134电学地和冶金地连接到衬底凸块焊盘244。
在另一个实施例中，利用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺将导电凸块材料形成在衬底凸块焊盘244上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，或其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到衬底凸块焊盘244。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成凸块或互连248，如图12b所示。在一些应用中，凸块248被二次回流以改善到衬底凸块焊盘244的电接触。窄衬底凸块焊盘244周围的凸块材料在回流期间维持管芯位置。
在高布线密度的应用中，期望最小化导电迹线242的出口间距(escape pitch)。导电迹线242之间的出口间距可以通过消除用于回流维持的掩蔽层，即通过在没有掩蔽层的情况下回流凸块材料，而被降低。由于没有SRO形成在管芯凸块焊盘132或衬底凸块焊盘244周围，因此导电迹线242可以形成为具有更细的间距，即导电迹线242可以更接近地被放置在一起或放置得更接近相邻结构。在没有SRO围绕衬底凸块焊盘244的情况下，导电迹线242之间的间距被给定为P＝D+PLT+W/2，其中D为凸块248的基底直径，PLT是管芯位移容差，以及W是导电迹线242的宽度。在一个实施例中，给定凸块基底直径是100微米，PLT是10微米，且迹线宽度是30微米，则导电迹线242的最小出口间距是125微米。无掩模(mask-less)凸块形成消除了对考虑如在现有技术中发现的相邻开口、焊料掩模对准(SRT)及最小可溶SRO之间的掩蔽材料的连接间隔(ligament spacing)的需要。
当凸块材料在没有掩蔽层的情况下被回流以冶金及电学地连接管芯凸块焊盘132到衬底凸块焊盘244时，润湿和表面张力引起凸块材料维持自限制并保持在管芯凸块焊盘132和衬底凸块焊盘244间的空间以及衬底240的紧邻基本上在凸块焊盘的占用空间中的导电迹线242的部分中。
为了实现期望的自限制特性，在放置在凸块焊盘132或衬底凸块焊盘244上之前，凸块材料可以浸入焊剂溶液中以选择性地致使被凸块材料接触的区域比导电迹线242的周围区域更可湿润。由于焊剂溶液的可湿润特性，熔化的凸块材料保持基本上被限制在由凸块焊盘限定的区域内。凸块材料不会跑出至不太可湿润的区域。薄氧化物层或其它绝缘层可以形成在凸块材料并不打算形成不太可湿润的区域的区域上。因此，在管芯凸块焊盘132或衬底凸块焊盘244周围不需要掩蔽层240。
图12c示出了作为具有形成在衬底250上的集成矩形凸块焊盘或互连部位254的直线导体的平行导电迹线252的另一个实施例。在该情况下，衬底凸块焊盘254宽于导电迹线242，但是小于配合凸块的宽度。衬底凸块焊盘254的侧边可以平行于导电迹线252。掩蔽层256形成在衬底250的一部分上；但是，掩蔽层没有形成在导电迹线252的衬底凸块焊盘254的周围。也就是，被设计为与凸块材料配合的导电迹线252的一部分没有用于回流期间凸块保留的掩蔽层256的任何SRO。
图12d示出了排列成多行阵列的、具有形成在衬底266上的偏移集成凸块焊盘或互连部位264的导电迹线260和262的另一个实施例，用于最大互连密度和容量。交替的导电迹线260和262包括用于通到凸块焊盘264的弯部。每个衬底凸块焊盘264的侧边与导电迹线260和262共线。掩蔽层268可以形成在衬底266的一部分上；但是，掩蔽层268没有形成在导电迹线260和262的衬底凸块焊盘264的周围。也就是，被设计为与凸块材料配合的导电迹线260和262的一部分没有用于回流期间凸块保留的掩蔽层268的任何SRO。
图12e示出了排列成多行阵列的、具有形成在衬底276上的偏移集成凸块焊盘或互连部位274的导电迹线270和272的另一个实施例，用于最大互连密度和容量。交替的导电迹线270和272包括用于通到凸块焊盘274的弯部。在该情况下，衬底凸块焊盘274是圆形的并且宽于导电迹线270和272，但是小于配合互连凸块材料的宽度。掩蔽层278可以形成在衬底276的一部分上；但是，掩蔽层278没有形成在导电迹线270和272的衬底凸块焊盘274的周围。也就是，被设计为与凸块材料配合的导电迹线270和272的一部分没有用于回流期间凸块保留的掩蔽层278的任何SRO。
图12f示出了排列成多行阵列的、具有形成在衬底286上的偏移集成凸块焊盘或互连部位284的导电迹线280和282的另一个实施例，用于最大互连密度和容量。交替的导电迹线280和282包括用于通到凸块焊盘284的弯部。在该情况下，衬底凸块焊盘254是矩形的并且宽于导电迹线280和282，但是小于配合互连凸块材料的宽度。掩蔽层288可以形成在衬底286的一部分上；但是，掩蔽层288没有形成在导电迹线280和282的衬底凸块焊盘284的周围。也就是，被设计为与凸块材料配合的导电迹线280和282的一部分没有用于回流期间凸块保留的掩蔽层288的任何SRO。
作为互连工艺的例子，半导体管芯124放置在衬底266上并且凸块材料134与图12d的衬底凸块焊盘264对准。通过对凸块材料加压或者通过将凸块材料与衬底凸块焊盘264在回流温度下物理接触，然后回流凸块材料，来将凸块材料电学地和冶金地连接到衬底凸块焊盘264，如针对图4a-4g、5a-5d、6a-6d、7a-7c及8a-8b所描述的。
在另一个实施例中，利用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺将导电凸块材料形成在衬底凸块焊盘264上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，或其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到衬底凸块焊盘264。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成凸块或互连290，如图12g所示。在一些应用中，凸块290被二次回流以改善到衬底凸块焊盘264的电接触。窄衬底凸块焊盘264周围的凸块材料在回流期间维持管芯位置。凸块材料134或凸块290也可以形成在图12a-12g的衬底凸块焊盘配置上。
在高布线密度的应用中，期望最小化导电迹线260和262或图12a-12g的其它导电迹线配置的出口间距。导电迹线260和262之间的出口间距可以通过消除用于回流维持的掩蔽层，即通过在没有掩蔽层的情况下回流凸块材料，而被降低。由于没有SRO形成在管芯凸块焊盘132或衬底凸块焊盘264周围，因此导电迹线260和262可以形成为具有更细的间距，即导电迹线260和262可以更接近地被放置在一起或放置得更接近相邻结构。在没有SRO围绕衬底凸块焊盘264的情况下，导电迹线260和262之间的间距被给定为P＝D+PLT+W/2，其中D为凸块290的基底直径，PLT是管芯位移容差，以及W是导电迹线260和262的宽度。在一个实施例中，给定凸块基底直径是100微米，PLT是10微米，且迹线宽度是30微米，则导电迹线260和262的最小出口间距是125微米。无掩模凸块形成消除了对考虑如在现有技术中发现的相邻开口、SRT及最小可溶SRO之间的掩蔽材料的连接间隔的需要。
当凸块材料在没有掩蔽层的情况下被回流以冶金及电学地连接管芯凸块焊盘132到衬底凸块焊盘264时，润湿和表面张力引起凸块材料维持自限制并保持在管芯凸块焊盘132和衬底凸块焊盘264间的空间以及衬底266的紧邻基本上在凸块焊盘的占用空间中的导电迹线260和262的部分中。
为了实现期望的自限制特性，在放置在管芯凸块焊盘132或衬底凸块焊盘264上之前，凸块材料可以浸入焊剂溶液中以选择性地致使被凸块材料接触的区域比导电迹线260和262的周围区域更可湿润。由于焊剂溶液的可湿润特性，熔化的凸块材料保持基本上被限制在由凸块焊盘限定的区域内。凸块材料不会跑出至不太可湿润的区域。薄氧化物层或其它绝缘层可以形成在凸块材料并不打算形成不太可湿润的区域的区域上。因此，在管芯凸块焊盘132或衬底凸块焊盘264周围不需要掩蔽层268。
在图13a中，掩蔽层292沉积在导电迹线294和296的一部分上。但是，掩蔽层292不形成在集成凸块焊盘298上。因此，对于衬底300上的每个凸块焊盘298不存在SRO。非可湿润的掩蔽补片(patch)302形成在衬底300上，填隙地(interstitially)处于集成凸块焊盘298的阵列中，即在相邻的凸块焊盘之间。掩蔽补片302也可以形成在半导体管芯124上，填隙地处于管芯凸块焊盘132的阵列中。更一般地，掩蔽补片被形成为极接近采用任何排列的集成凸块焊盘以防止跑出至不太可湿润的区域。
半导体管芯124放置在衬底300上并且凸块材料134对准衬底凸块焊盘298。通过对凸块材料134加压或者通过将凸块材料134与衬底凸块焊盘298在回流温度下物理接触，然后回流凸块材料，来将凸块材料134电学地和冶金地连接到衬底凸块焊盘298，如针对图4a-4g、5a-5d、6a-6d、7a-7c及8a-8b所描述的。
在另一个实施例中，利用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺将导电凸块材料形成在管芯集成凸块焊盘298上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，或其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到集成凸块焊盘298。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块304。在一些应用中，凸块304被二次回流以改善到集成凸块焊盘298的电接触。凸块也可以被压缩结合到集成凸块焊盘298。凸块304表示一种可以形成在集成凸块焊盘298上的互连结构。所述互连结构也可以使用柱形凸块、微凸块、或其它电互连。
在高布线密度的应用中，期望最小化出口间距。为了降低导电迹线294和296之间的间距，在集成凸块焊盘298周围没有掩蔽层的情况下回流凸块材料。导电迹线294和296之间的出口间距可以通过消除用于回流维持的掩蔽层和在集成凸块焊盘周围的相关SRO，即通过在没有掩蔽层的情况下回流凸块材料，而被降低。掩蔽层292可以形成在导电迹线294和296及衬底300的一部分上，远离集成凸块焊盘298；但是，掩蔽层292没有形成在集成凸块焊盘298的周围。也就是，被设计为与凸块材料配合的导电迹线294和296的一部分没有用于回流期间凸块保留的掩蔽层292的任何SRO。
另外，掩蔽补片302形成在衬底300上，填隙地处于集成凸块焊盘298的阵列中。掩蔽补片302是非可湿润的材料。掩蔽补片302可以是与掩蔽层292相同的材料并且在相同的工艺步骤期间被施加，或者也可以是在不同工艺步骤期间的不同材料。掩蔽补片302也可以通过对集成凸块焊盘298的阵列中的迹线或焊盘的部分进行选择性氧化、电镀或其它处理而被形成。掩蔽补片302限制凸块材料流动到集成凸块焊盘298并且防止导电凸块材料流失到相邻结构。
当采用填隙地置于集成凸块焊盘298的阵列中的掩蔽补片302来回流凸块材料时，润湿和表面张力引起凸块材料被限制并保持在管芯凸块焊盘132和集成凸块焊盘298之间的空间以及衬底300的紧邻导电迹线294和296的部分中，并且基本上在集成凸块焊盘298的占用空间中。
为了实现期望的限制特性，在放置在凸块焊盘132或衬底凸块焊盘298上之前，凸块材料可以浸入焊剂溶液中以选择性地致使被凸块材料接触的区域比导电迹线294和296的周围区域更可湿润。由于焊剂溶液的可湿润特性，熔化的凸块材料保持基本上被限制在由凸块焊盘限定的区域内。凸块材料不会跑出至不太可湿润的区域。薄氧化物层或其它绝缘层可以形成在凸块材料并不打算形成不太可湿润的区域的区域上。因此，在管芯凸块焊盘132或集成凸块焊盘298周围不需要掩蔽层292。
由于没有SRO形成在管芯凸块焊盘132或集成凸块焊盘298周围，因此导电迹线294和296可以形成为具有更细的间距，即导电迹线可以放置得更接近相邻结构而不会形成接触以及形成电短路。采用相同的焊料对准设计规则，导电迹线294和296之间的间距被给定为P＝(1.1D+W)/2，其中D为凸块304的基底直径并且W是导电迹线294和296的宽度。在一个实施例中，给定凸块的直径是100微米且迹线宽度是20微米，则导电迹线294和296的最小出口间距是65微米。凸块形成消除了对考虑如在现有技术中发现的相邻开口及最小可溶SRO之间的掩蔽材料的连接间隔的需要。
图14示出了具有使用管芯附着粘合剂310堆叠在半导体管芯308上的半导体管芯306的层叠封装(PoP)305。半导体管芯306和半导体管芯308均具有有源表面，所述有源表面包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯306和308也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。
采用图4a-4g、5a-5d、6a-6d、7a-7c或8a-8b的任何实施例，使用形成在接触焊盘318上的凸块材料316将半导体管芯306安装到形成在衬底314上的导电迹线312。半导体管芯308使用结合线322电连接到形成在衬底314上的接触焊盘320。结合线322的相反端结合到半导体管芯306上的接触焊盘324。
掩蔽层326形成在衬底314上并且在半导体管芯306的占用空间以外被开口。在掩蔽层326在回流期间不将凸块材料316限制到导电迹线312的同时，开口掩模可以用作坝状物以防止密封剂328在MUF期间移动至接触焊盘320或结合线322。密封剂328沉积在半导体管芯308与衬底314之间，类似于图9a-9c。掩蔽层326阻挡MUF密封剂328到达接触焊盘320以及结合线322，这可能引起缺陷。掩蔽层326允许更大的半导体管芯放置在所给衬底上，而不会有密封剂328渗出至接触焊盘320的风险。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (14)

1.一种制造半导体器件的方法，包括：
提供半导体管芯，该半导体管芯包括形成在半导体管芯的表面上的多个凸块；
提供衬底；
在衬底上形成包括互连部位的多个导电迹线，所述凸块宽于所述互连部位；
在衬底的远离互连部位的区域上形成掩蔽层；
在所述导电迹线的一部分上填隙地在互连部位之间形成多个掩蔽补片且该多个掩蔽补片在物理上与所述互连部位分离，其中所述多个掩蔽补片由非可湿润材料形成；
将凸块结合到互连部位，使得凸块覆盖互连部位的顶面和侧面；以及
在半导体管芯与衬底之间的凸块周围沉积密封剂。
2.根据权利要求1所述的方法，进一步包括在互连部位或凸块上形成凸起体。
3.根据权利要求1所述的方法，其中凸块包括可熔部分和非可熔部分。
4.根据权利要求1所述的方法，其中掩蔽层形成坝状物以阻挡密封剂延伸到半导体管芯的占用空间以外。
5.一种制造半导体器件的方法，包括：
提供半导体管芯，该半导体管芯包括形成在半导体管芯的表面上的多个互连结构；
提供衬底；
在衬底上形成包括互连部位的多个导电迹线，所述互连结构宽于所述互连部位；
形成掩蔽层，所述掩蔽层包括在所述导电迹线的一部分上由非可湿润材料制成的多个掩蔽补片，其中所述掩蔽补片填隙地布置在所述互连部位之间并且在物理上与所述互连部位分离；
将互连结构结合到没有掩模开口的互连部位，使得互连结构覆盖互连部位的顶面和侧面；以及
在半导体管芯与衬底之间的互连结构周围沉积密封剂。
6.根据权利要求5所述的方法，进一步包括在压力或回流温度下将互连结构结合到互连部位。
7.根据权利要求5所述的方法，进一步包括在衬底的远离互连部位的区域上形成掩蔽层。
8.根据权利要求5所述的方法，其中互连结构包括可熔部分和非可熔部分。
9.根据权利要求5所述的方法，其中互连结构包括导电柱和形成在导电柱上的凸块。
10.一种半导体器件，包括：
半导体管芯，其包括形成在半导体管芯的表面上的多个互连结构；
衬底；
形成在衬底上的包括互连部位的多个导电迹线，所述互连部位窄于所述互连结构，互连结构被结合到互连部位，使得互连结构覆盖互连部位的顶面和侧面；
多个掩蔽补片，其在所述导电迹线的一部分上在所述互连部位之间填隙地形成并且在物理上与所述互连部位分离；以及
沉积在半导体管芯与衬底之间的互连结构周围的密封剂。
11.根据权利要求10所述的半导体器件，其中互连结构在压力或回流温度下被结合到互连部位。
12.根据权利要求10所述的半导体器件，其中互连结构包括可熔部分和非可熔部分。
13.根据权利要求10所述的半导体器件，其中互连结构包括导电柱和形成在导电柱上的凸块。
14.根据权利要求10所述的半导体器件，进一步包括形成在互连部位或互连结构上的凸起体。
CN201110058357.1A 2010-11-16 2011-02-21 半导体器件以及形成倒装芯片互连结构的方法 Active CN102468197B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/947,414 US10388626B2 (en) 2000-03-10 2010-11-16 Semiconductor device and method of forming flipchip interconnect structure
US12/947414 2010-11-16

Publications (2)

Publication Number Publication Date
CN102468197A CN102468197A (zh) 2012-05-23
CN102468197B true CN102468197B (zh) 2017-04-26

Family

ID=43779387

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110058357.1A Active CN102468197B (zh) 2010-11-16 2011-02-21 半导体器件以及形成倒装芯片互连结构的方法

Country Status (6)

Country Link
US (1) US10388626B2 (zh)
JP (1) JP5952523B2 (zh)
KR (1) KR101785729B1 (zh)
CN (1) CN102468197B (zh)
SG (3) SG181205A1 (zh)
TW (1) TWI541916B (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9029196B2 (en) * 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US9659893B2 (en) 2011-12-21 2017-05-23 Mediatek Inc. Semiconductor package
US8633588B2 (en) 2011-12-21 2014-01-21 Mediatek Inc. Semiconductor package
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
KR101492603B1 (ko) * 2012-07-25 2015-02-12 모글루(주) 전자문서 제작 시스템과 그 제어 방법
US9461008B2 (en) * 2012-08-16 2016-10-04 Qualcomm Incorporated Solder on trace technology for interconnect attachment
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
CN104599978B (zh) * 2014-12-31 2017-08-01 广州兴森快捷电路科技有限公司 一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法
DE102015105752B4 (de) * 2015-04-15 2021-08-05 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Halbleiteranordnung mit Reservoir für Markermaterial
US10141287B2 (en) * 2015-07-14 2018-11-27 Goertek, Inc. Transferring method, manufacturing method, device and electronic apparatus of micro-LED
US20170271175A1 (en) * 2016-03-16 2017-09-21 Qualcomm Incorporated Exposed die mold underfill (muf) with fine pitch copper (cu) pillar assembly and bump density
TWI641097B (zh) * 2016-08-12 2018-11-11 南茂科技股份有限公司 半導體封裝
US10050021B1 (en) * 2017-02-16 2018-08-14 Nanya Technology Corporation Die device, semiconductor device and method for making the same
KR102446203B1 (ko) 2017-12-12 2022-09-23 삼성디스플레이 주식회사 구동칩 및 이를 포함하는 표시 장치
TW202042359A (zh) * 2019-05-02 2020-11-16 南茂科技股份有限公司 薄膜覆晶封裝結構
CN112687629B (zh) * 2020-12-25 2024-02-23 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101690434A (zh) * 2007-06-26 2010-03-31 株式会社村田制作所 元器件内置基板的制造方法

Family Cites Families (133)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3665590A (en) 1970-01-19 1972-05-30 Ncr Co Semiconductor flip-chip soldering method
JPS54105774A (en) 1978-02-08 1979-08-20 Hitachi Ltd Method of forming pattern on thin film hybrid integrated circuit
US4813129A (en) 1987-06-19 1989-03-21 Hewlett-Packard Company Interconnect structure for PC boards and integrated circuits
JPH01226160A (ja) 1988-03-07 1989-09-08 Nippon Telegr & Teleph Corp <Ntt> 電子部品接続用の端子装置および端子の製造方法
US5323035A (en) 1992-10-13 1994-06-21 Glenn Leedy Interconnection structure for integrated circuits and method for making same
US4937653A (en) 1988-07-21 1990-06-26 American Telephone And Telegraph Company Semiconductor integrated circuit chip-to-chip interconnection scheme
US5634267A (en) 1991-06-04 1997-06-03 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
JPH0797597B2 (ja) 1989-06-02 1995-10-18 松下電器産業株式会社 半導体装置
JPH0429338A (ja) 1990-05-24 1992-01-31 Nippon Mektron Ltd Ｉｃの搭載用回路基板及びその搭載方法
US5011066A (en) 1990-07-27 1991-04-30 Motorola, Inc. Enhanced collapse solder interconnection
JPH04355933A (ja) 1991-02-07 1992-12-09 Nitto Denko Corp フリツプチツプの実装構造
US5865365A (en) 1991-02-19 1999-02-02 Hitachi, Ltd. Method of fabricating an electronic circuit device
US5686317A (en) 1991-06-04 1997-11-11 Micron Technology, Inc. Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die
JP3225062B2 (ja) 1991-08-05 2001-11-05 ローム株式会社 熱硬化性樹脂シート及びそれを用いた半導体素子の実装方法
US5219117A (en) 1991-11-01 1993-06-15 Motorola, Inc. Method of transferring solder balls onto a semiconductor device
JP2678958B2 (ja) 1992-03-02 1997-11-19 カシオ計算機株式会社 フィルム配線基板およびその製造方法
US5314651A (en) 1992-05-29 1994-05-24 Texas Instruments Incorporated Fine-grain pyroelectric detector material and method
JP3086081B2 (ja) 1992-08-20 2000-09-11 日本特殊陶業株式会社 配線基板とその製造方法
US5346857A (en) 1992-09-28 1994-09-13 Motorola, Inc. Method for forming a flip-chip bond from a gold-tin eutectic
JP2518508B2 (ja) 1993-04-14 1996-07-24 日本電気株式会社 半導体装置
US5386624A (en) 1993-07-06 1995-02-07 Motorola, Inc. Method for underencapsulating components on circuit supporting substrates
US5592736A (en) * 1993-09-03 1997-01-14 Micron Technology, Inc. Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads
US5326428A (en) 1993-09-03 1994-07-05 Micron Semiconductor, Inc. Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability
JP3283977B2 (ja) 1993-10-18 2002-05-20 三菱電機株式会社 半導体装置およびその製造方法
JPH07122846A (ja) 1993-10-21 1995-05-12 Advantest Corp 微小表面実装部品のハンダ付け方法
JPH07142488A (ja) 1993-11-15 1995-06-02 Nec Corp バンプ構造及びその製造方法並びにフリップチップ実装 構造
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US6835898B2 (en) * 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
JPH07201917A (ja) 1993-12-28 1995-08-04 Matsushita Electric Ind Co Ltd 回路形成基板とその製造方法
JP2664878B2 (ja) 1994-01-31 1997-10-22 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体チップパッケージおよびその製造方法
JP2830734B2 (ja) 1994-04-04 1998-12-02 松下電器産業株式会社 配線基板とその製造方法
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
US5519580A (en) 1994-09-09 1996-05-21 Intel Corporation Method of controlling solder ball size of BGA IC components
FR2726397B1 (fr) 1994-10-28 1996-11-22 Commissariat Energie Atomique Film conducteur anisotrope pour la microconnectique
DE19524739A1 (de) 1994-11-17 1996-05-23 Fraunhofer Ges Forschung Kernmetall-Lothöcker für die Flip-Chip-Technik
JP3353508B2 (ja) 1994-12-20 2002-12-03 ソニー株式会社 プリント配線板とこれを用いた電子装置
JPH08236654A (ja) * 1995-02-23 1996-09-13 Matsushita Electric Ind Co Ltd チップキャリアとその製造方法
JP3209875B2 (ja) 1995-03-23 2001-09-17 株式会社日立製作所 基板の製造方法及び基板
JP2796070B2 (ja) 1995-04-28 1998-09-10 松下電器産業株式会社 プローブカードの製造方法
US5650595A (en) * 1995-05-25 1997-07-22 International Business Machines Corporation Electronic module with multiple solder dams in soldermask window
JP2770821B2 (ja) 1995-07-27 1998-07-02 日本電気株式会社 半導体装置の実装方法および実装構造
US5874780A (en) 1995-07-27 1999-02-23 Nec Corporation Method of mounting a semiconductor device to a substrate and a mounted structure
DE19527661C2 (de) 1995-07-28 1998-02-19 Optrex Europ Gmbh Elektrische Leiter aufweisender Träger mit einem elektronischen Bauteil und Verfahen zum Kontaktieren von Leitern eines Substrates mit Kontaktwarzen eines elektronischen Bauteils
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
KR19990044151A (ko) 1995-08-29 1999-06-25 스프레이그 로버트 월터 견고하게 접착된 변형가능한 전자장치용 기판조립장치
US5710071A (en) 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
KR0182073B1 (ko) 1995-12-22 1999-03-20 황인길 반도체 칩 스케일 반도체 패키지 및 그 제조방법
JP3558459B2 (ja) 1996-02-08 2004-08-25 沖電気工業株式会社 インナーリード接続方法
US5889326A (en) * 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
JPH09237802A (ja) 1996-02-28 1997-09-09 Fujitsu Ltd 電子部品
JPH09260552A (ja) 1996-03-22 1997-10-03 Nec Corp 半導体チップの実装構造
KR100216839B1 (ko) 1996-04-01 1999-09-01 김규현 Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조
US5940729A (en) 1996-04-17 1999-08-17 International Business Machines Corp. Method of planarizing a curved substrate and resulting structure
JP2828021B2 (ja) 1996-04-22 1998-11-25 日本電気株式会社 ベアチップ実装構造及び製造方法
US5755909A (en) 1996-06-26 1998-05-26 Spectra, Inc. Electroding of ceramic piezoelectric transducers
JP2870497B2 (ja) 1996-08-01 1999-03-17 日本電気株式会社 半導体素子の実装方法
JPH1098075A (ja) 1996-09-20 1998-04-14 Toshiba Corp 半導体実装方法、半導体実装装置および半導体実装構造
US6121689A (en) 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US5729896A (en) * 1996-10-31 1998-03-24 International Business Machines Corporation Method for attaching a flip chip on flexible circuit carrier using chip with metallic cap on solder
US5796590A (en) 1996-11-05 1998-08-18 Micron Electronics, Inc. Assembly aid for mounting packaged integrated circuit devices to printed circuit boards
JP2924830B2 (ja) 1996-11-15 1999-07-26 日本電気株式会社 半導体装置及びその製造方法
US5952840A (en) * 1996-12-31 1999-09-14 Micron Technology, Inc. Apparatus for testing semiconductor wafers
US5931371A (en) 1997-01-16 1999-08-03 Ford Motor Company Standoff controlled interconnection
JPH10233413A (ja) 1997-02-21 1998-09-02 Nec Kansai Ltd 半導体装置およびその製造方法並びに配線基板
JP3500032B2 (ja) 1997-03-13 2004-02-23 日本特殊陶業株式会社 配線基板及びその製造方法
JP3346263B2 (ja) 1997-04-11 2002-11-18 イビデン株式会社 プリント配線板及びその製造方法
JPH10303252A (ja) * 1997-04-28 1998-11-13 Nec Kansai Ltd 半導体装置
JP3070514B2 (ja) 1997-04-28 2000-07-31 日本電気株式会社 突起電極を有する半導体装置、半導体装置の実装方法およびその実装構造
WO1999000842A1 (en) 1997-06-26 1999-01-07 Hitachi Chemical Company, Ltd. Substrate for mounting semiconductor chips
JPH1126919A (ja) 1997-06-30 1999-01-29 Fuji Photo Film Co Ltd プリント配線板
US6337522B1 (en) 1997-07-10 2002-01-08 International Business Machines Corporation Structure employing electrically conductive adhesives
US5985456A (en) 1997-07-21 1999-11-16 Miguel Albert Capote Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits
US6335571B1 (en) 1997-07-21 2002-01-01 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
JP3028791B2 (ja) 1997-08-06 2000-04-04 日本電気株式会社 チップ部品の実装方法
US6121143A (en) 1997-09-19 2000-09-19 3M Innovative Properties Company Abrasive articles comprising a fluorochemical agent for wafer surface modification
US6448665B1 (en) 1997-10-15 2002-09-10 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
SG71734A1 (en) 1997-11-21 2000-04-18 Inst Materials Research & Eng Area array stud bump flip chip and assembly process
JP3381593B2 (ja) 1997-12-22 2003-03-04 松下電器産業株式会社 バンプ付電子部品の実装方法
JP3819576B2 (ja) 1997-12-25 2006-09-13 沖電気工業株式会社 半導体装置及びその製造方法
US6200143B1 (en) 1998-01-09 2001-03-13 Tessera, Inc. Low insertion force connector for microelectronic elements
JPH11204913A (ja) 1998-01-09 1999-07-30 Sony Corp 回路基板及び実装方法並びにプリント配線板
US6037192A (en) 1998-01-22 2000-03-14 Nortel Networks Corporation Process of assembling an integrated circuit and a terminal substrate using solder reflow and adhesive cure
US6426636B1 (en) 1998-02-11 2002-07-30 International Business Machines Corporation Wafer probe interface arrangement with nonresilient probe elements and support structure
US5953814A (en) 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability
US6324754B1 (en) 1998-03-25 2001-12-04 Tessera, Inc. Method for fabricating microelectronic assemblies
US6329605B1 (en) 1998-03-26 2001-12-11 Tessera, Inc. Components with conductive solder mask layers
JP2000031204A (ja) 1998-07-07 2000-01-28 Ricoh Co Ltd 半導体パッケージの製造方法
US6189208B1 (en) 1998-09-11 2001-02-20 Polymer Flip Chip Corp. Flip chip mounting technique
JP2000133672A (ja) 1998-10-28 2000-05-12 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP3346320B2 (ja) 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
SG88747A1 (en) 1999-03-01 2002-05-21 Motorola Inc A method and machine for underfilling an assembly to form a semiconductor package
US6483195B1 (en) 1999-03-16 2002-11-19 Sumitomo Bakelite Company Limited Transfer bump street, semiconductor flip chip and method of producing same
US6225206B1 (en) * 1999-05-10 2001-05-01 International Business Machines Corporation Flip chip C4 extension structure and process
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6173887B1 (en) 1999-06-24 2001-01-16 International Business Machines Corporation Method of making electrically conductive contacts on substrates
JP2001068836A (ja) 1999-08-27 2001-03-16 Mitsubishi Electric Corp プリント配線基板及び半導体モジュール並びに半導体モジュールの製造方法
TW429492B (en) 1999-10-21 2001-04-11 Siliconware Precision Industries Co Ltd Ball grid array package and its fabricating method
ATE459099T1 (de) 2000-03-10 2010-03-15 Chippac Inc Flipchip-verbindungsstruktur und dessen herstellungsverfahren
JP2001339011A (ja) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
EP1223612A4 (en) * 2000-05-12 2005-06-29 Matsushita Electric Ind Co Ltd PCB FOR SEMICONDUCTOR COMPONENTS, THEIR MANUFACTURING METHOD AND MANUFACTURING OF THE FITTING PLANT FOR THE PCB
US6573610B1 (en) 2000-06-02 2003-06-03 Siliconware Precision Industries Co., Ltd. Substrate of semiconductor package for flip chip package
US6201305B1 (en) 2000-06-09 2001-03-13 Amkor Technology, Inc. Making solder ball mounting pads on substrates
JP3554533B2 (ja) 2000-10-13 2004-08-18 シャープ株式会社 チップオンフィルム用テープおよび半導体装置
JP2002134541A (ja) 2000-10-23 2002-05-10 Citizen Watch Co Ltd 半導体装置とその製造方法ならびに半導体装置の実装構造
US8158508B2 (en) 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US7242099B2 (en) 2001-03-05 2007-07-10 Megica Corporation Chip package with multiple chips connected by bumps
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US6808958B2 (en) * 2001-03-07 2004-10-26 Tessera, Inc. Methods of bonding microelectronic elements
US6893901B2 (en) 2001-05-14 2005-05-17 Fairchild Semiconductor Corporation Carrier with metal bumps for semiconductor die packages
JP4663165B2 (ja) 2001-06-27 2011-03-30 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP3787295B2 (ja) 2001-10-23 2006-06-21 ローム株式会社 半導体装置
TW507341B (en) 2001-11-01 2002-10-21 Siliconware Precision Industries Co Ltd Substrate capable of preventing delamination of chip and semiconductor encapsulation having such a substrate
US6952047B2 (en) * 2002-07-01 2005-10-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US6969914B2 (en) * 2002-08-29 2005-11-29 Micron Technology, Inc. Electronic device package
JP4114483B2 (ja) 2003-01-10 2008-07-09 セイコーエプソン株式会社 半導体チップの実装方法、半導体実装基板、電子デバイスおよび電子機器
US7271497B2 (en) 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
US7005751B2 (en) * 2003-04-10 2006-02-28 Formfactor, Inc. Layered microelectronic contact and method for fabricating same
US7758351B2 (en) 2003-04-11 2010-07-20 Neoconix, Inc. Method and system for batch manufacturing of spring elements
TWI225701B (en) * 2003-09-17 2004-12-21 Advanced Semiconductor Eng Process for forming bumps in adhesive layer in wafer level package
US20060216860A1 (en) 2005-03-25 2006-09-28 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
WO2005048311A2 (en) 2003-11-10 2005-05-26 Chippac, Inc. Bump-on-lead flip chip interconnection
US20070145548A1 (en) * 2003-12-22 2007-06-28 Amkor Technology, Inc. Stack-type semiconductor package and manufacturing method thereof
US7368695B2 (en) * 2004-05-03 2008-05-06 Tessera, Inc. Image sensor package and fabrication method
US7576427B2 (en) 2004-05-28 2009-08-18 Stellar Micro Devices Cold weld hermetic MEMS package and method of manufacture
JP2007064841A (ja) 2005-08-31 2007-03-15 Advantest Corp 電子部品試験装置用のキャリブレーションボード
KR100691443B1 (ko) 2005-11-16 2007-03-09 삼성전기주식회사 플립칩 패키지 및 그 제조방법
JP2007214230A (ja) 2006-02-08 2007-08-23 Cmk Corp プリント配線板
US7829998B2 (en) 2007-05-04 2010-11-09 Stats Chippac, Ltd. Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
WO2009090896A1 (ja) 2008-01-17 2009-07-23 Murata Manufacturing Co., Ltd. 電子部品
JP2009177061A (ja) * 2008-01-28 2009-08-06 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
JP2010141055A (ja) 2008-12-10 2010-06-24 Sanyo Electric Co Ltd 半導体モジュール、半導体モジュールの製造方法および携帯機器
US8338945B2 (en) * 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods
US9599665B2 (en) 2013-05-21 2017-03-21 Advantest Corporation Low overdrive probes with high overdrive substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101690434A (zh) * 2007-06-26 2010-03-31 株式会社村田制作所 元器件内置基板的制造方法

Also Published As

Publication number Publication date
SG10201809052TA (en) 2018-11-29
US20110074022A1 (en) 2011-03-31
US20120241945A9 (en) 2012-09-27
TWI541916B (zh) 2016-07-11
US10388626B2 (en) 2019-08-20
SG181205A1 (en) 2012-06-28
TW201225193A (en) 2012-06-16
KR20120052844A (ko) 2012-05-24
KR101785729B1 (ko) 2017-11-06
JP5952523B2 (ja) 2016-07-13
CN102468197A (zh) 2012-05-23
SG10201402214VA (en) 2014-09-26
JP2012109507A (ja) 2012-06-07

Similar Documents

Publication Publication Date Title
CN102468197B (zh) 半导体器件以及形成倒装芯片互连结构的方法
US9899286B2 (en) Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
CN102487020B (zh) 形成引线上凸块互连的半导体器件和方法
US8349721B2 (en) Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US9865556B2 (en) Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9679811B2 (en) Semiconductor device and method of confining conductive bump material with solder mask patch
US9345148B2 (en) Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
US8896133B2 (en) Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
US8877567B2 (en) Semiconductor device and method of forming uniform height insulating layer over interposer frame as standoff for semiconductor die
CN102403239B (zh) 半导体器件及形成用于在Fo‑WLCSP中安装半导体小片的引线上键合互连的方法
US8399305B2 (en) Semiconductor device and method of forming dam material with openings around semiconductor die for mold underfill using dispenser and vacuum assist
US8836097B2 (en) Semiconductor device and method of forming pre-molded substrate to reduce warpage during die molding
US9258904B2 (en) Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant