JP5952523B2 - 半導体素子およびフリップチップ相互接続構造を形成する方法 - Google Patents
半導体素子およびフリップチップ相互接続構造を形成する方法 Download PDFInfo
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- JP5952523B2 JP5952523B2 JP2011009327A JP2011009327A JP5952523B2 JP 5952523 B2 JP5952523 B2 JP 5952523B2 JP 2011009327 A JP2011009327 A JP 2011009327A JP 2011009327 A JP2011009327 A JP 2011009327A JP 5952523 B2 JP5952523 B2 JP 5952523B2
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Description
(項目1)
半導体ダイの能動表面上に形成された複数のバンプを有する、半導体ダイを提供するステップと、
基板を提供するステップと、
上記基板上に相互接続部位を伴う複数の伝導性トレースを形成するステップであって、上記バンプは、上記相互接続部位よりも幅広い、ステップと、
上記接続部位から離れた上記基板の領域上にマスキング層を形成するステップと、
上記バンプが上記相互接続部位の頂面および側面を覆うように、上記バンプを上記相互接続部位に接着するステップと、
上記半導体ダイと基板との間で上記バンプの周囲に封入材を堆積させるステップと、
を含む、半導体素子を作製する方法。
(項目2)
圧力またはリフロー温度下で、上記バンプを上記相互接続部位に接着するステップをさらに含む、上記項目のいずれかに記載の方法。
(項目3)
上記伝導性トレースの周囲のパッチとして上記マスキング層を形成するステップをさらに含む、上記項目のいずれかに記載の方法。
(項目4)
上記相互接続部位またはバンプ上に凹凸を形成するステップをさらに含む、上記項目のいずれかに記載の方法。
(項目5)
上記バンプは、可融部分と、非可融部分とを含む、上記項目のいずれかに記載の方法。
(項目6)
上記マスキング層は、上記封入材が上記半導体ダイの設置面積を越えて延在することを防止するようにダムを形成する、上記項目のいずれかに記載の方法。
(項目7)
半導体ダイの表面上に形成された複数の相互接続構造を有する、半導体ダイを提供するステップと、
基板を提供するステップと、
上記基板上に相互接続部位を伴う複数の伝導性トレースを形成するステップであって、上記相互接続構造は、上記相互接続部位よりも幅広い、ステップと、
上記相互接続構造が上記相互接続部位の頂面および側面を覆うように、マスク開口部を欠いて上記相互接続構造を上記相互接続部位に接着するステップと、
上記半導体ダイと基板との間で上記相互接続構造の周囲に封入材を堆積させるステップと
を含む、半導体素子を作製する方法。
(項目8)
圧力またはリフロー温度下で、上記相互接続構造を上記相互接続部位に接着するステップをさらに含む、上記項目のいずれかに記載の方法。
(項目9)
上記接続部位から離れた上記基板の領域上にマスキング層を形成するステップをさらに含む、上記項目のいずれかに記載の方法。
(項目10)
上記相互接続構造は、バンプまたはバンプ材料を含む、上記項目のいずれかに記載の方法。
(項目11)
上記相互接続構造は、可融部分と、非可融部分とを含む、上記項目のいずれかに記載の方法。
(項目12)
上記相互接続構造は、伝導柱と、上記伝導柱上に形成されるバンプとを含む、上記項目のいずれかに記載の方法。
(項目13)
上記相互接続部位または相互接続構造上に凸凹を形成するステップをさらに含む、上記項目のいずれかに記載の方法。
(項目14)
半導体ダイの表面上に形成された複数の相互接続構造を有する、半導体ダイを提供するステップと、
基板を提供するステップと、
上記基板上に相互接続部位を伴う複数の伝導性トレースを形成するステップであって、上記相互接続部位は、上記相互接続構造よりも狭い、ステップと、
上記相互接続構造が上記相互接続部位の頂面および側面を覆うように、マスク開口部を欠いて上記相互接続構造を上記相互接続部位に接着するステップと、
を含む、半導体素子を作製する方法。
(項目15)
圧力またはリフロー温度下で、上記相互接続構造を上記相互接続部位に接着するステップをさらに含む、上記項目のいずれかに記載の方法。
(項目16)
上記半導体ダイと基板との間で上記相互接続構造の周囲に封入材を堆積させるステップと、上記項目のいずれかに記載の方法。
(項目17)
上記接続部位から離れた上記基板の領域上にマスキング層を形成するステップをさらに含む、上記項目のいずれかに記載の方法。
(項目18)
上記マスキング層は、上記封入材が上記半導体ダイの設置面積を越えて延在することを防止するようにダムを形成する、上記項目のいずれかに記載の方法。
(項目19)
上記相互接続構造は、可融部分と、非可融部分とを含む、上記項目のいずれかに記載の方法。
(項目20)
上記相互接続部位または相互接続構造上に凸凹を形成するステップをさらに含む、上記項目のいずれかに記載の方法。
(項目21)
半導体ダイの表面上に形成された複数の相互接続構造を有する、半導体ダイと、
基板と、
上記基板上に形成された相互接続部位を伴う複数の伝導性トレースあって、上記相互接続部位は、上記相互接続構造よりも狭く、上記相互接続構造は、上記相互接続構造が上記相互接続部位の頂面および側面を覆うように、上記相互接続部位に接着される、伝導性トレースと、
上記半導体ダイと基板との間で上記相互接続構造の周囲に堆積させられる、封入材と、
を備える、半導体素子。
(項目22)
上記相互接続構造は、圧力またはリフロー温度下で上記相互接続部位に接着される、上記項目のいずれかに記載の半導体素子。
(項目23)
上記相互接続構造は、可融部分と、非可融部分とを含む、上記項目のいずれかに記載の半導体素子。
(項目24)
上記相互接続構造は、伝導柱と、上記伝導柱上に形成されるバンプとを含む、上記項目のいずれかに記載の半導体素子。
(項目25)
上記相互接続部位または相互接続構造上に凸凹を形成するステップをさらに含む、上記項目のいずれかに記載の半導体素子。
半導体素子は、金型の能動表面上に形成された複数のバンプまたは相互接続構造を伴う半導体金型を有する。バンプは、伝導柱および伝導柱上に形成されるバンプ等の、可溶部分および非可溶部分を有することができる。相互接続部位を伴う伝導性トレースが、基板上に形成される。バンプは、相互接続部位よりも幅広い。マスキング層が、相互接続部位から離れた基板の領域上に形成される。バンプは、バンプが相互接続部位の頂面および側面を覆うように、圧力またはリフロー温度下で相互接続部位に接着される。封入材が、金型と基板との間でバンプの周囲に堆積させられる。マスキング層は、封入材が半導体金型を越えて延在することを阻止するようにダムを形成することができる。凸凹を、相互接続部位またはバンプ上に形成することができる。
非可融部分140は、Au、Cu、Ni、鉛の含有量が高いはんだ、または鉛スズ合金となり得る。可融部分142は、Sn、無鉛合金、Sn−Ag合金、Sn−Ag−Cu合金、Sn−Ag−インジウム(In)合金、共晶はんだ、Ag、Cu、またはPbを伴うスズ合金、または比較的低温溶融のはんだとなり得る。一実施形態では、100μmの接触パッド132の幅または直径を考慮すると、非可融部分140は、高さが約45μmであり、可融部分142は、高さが約35μmである。
いくつかの用途では、バンプ248は、基板バンプパッド244への電気接触を向上させるように、2回リフローされる。より狭い基板バンプパッド244の周囲のバンプ材料は、リフロー中にダイの配置を維持する。
マスキングパッチ302は、マスキング層292と同じ材料であり、同じ処理ステップ中に塗布することができるか、または異なる処理ステップ中に異なる材料となり得る。マスキングパッチ302は、集積バンプパッド298のアレイ内のトレースまたはパッドの部分の選択的酸化、めっき、または他の処理によって形成することができる。マスキングパッチ302は、集積バンプパッド298にバンプ材料流動を閉じ込め、隣接構造への伝導性バンプ材料の浸出を防止する。
Claims (13)
- 半導体素子を作製する方法であって、前記方法は、
半導体ダイの表面上に形成された複数のバンプを含む半導体ダイを提供することと、
基板を提供することと、
前記基板上に複数の相互接続部位のアレイを含む複数の伝導性トレースを形成することであって、前記バンプは、前記相互接続部位よりも幅広い、ことと、
前記複数の相互接続部位から離れた前記基板の領域上にマスキング層を形成することと、
前記複数の伝導性トレース上に、かつ、前記複数の相互接続部位のアレイ内に介在して、複数のマスキングパッチを形成することであって、前記マスキング層および前記複数のマスキングパッチは、はんだ位置合わせ開口部を欠いており、前記複数のマスキングパッチの各マスキングパッチは、前記複数の伝導性トレースのうちの単一の伝導性トレース上に形成される、ことと、
前記複数のバンプが前記複数の相互接続部位の頂面および側面を覆うように、前記複数のバンプを前記複数の相互接続部位に接着することと、
前記半導体ダイと前記基板との間で前記複数のバンプの周囲に封入材を堆積させることと
を含む、方法。 - 前記相互接続部位またはバンプ上に凹凸を形成することをさらに含む、請求項1に記載の方法。
- 前記バンプは、可融部分と、非可融部分とを含む、請求項1に記載の方法。
- 前記マスキング層は、前記封入材が前記半導体ダイの設置面積を越えて延在することを防止するようにダムを形成する、請求項1に記載の方法。
- 半導体素子を作製する方法であって、前記方法は、
半導体ダイの表面上に形成された複数の相互接続構造を含む半導体ダイを提供することと、
基板を提供することと、
前記基板上に複数の相互接続部位を含む複数の伝導性トレースを形成することであって、前記相互接続構造は、前記相互接続部位よりも幅広い、ことと、
前記基板上に、かつ、前記複数の相互接続部位の間に、複数のマスキングパッチを含むマスキング層を形成することであって、前記複数のマスキングパッチは、はんだ位置合わせ開口部を欠いており、前記複数のマスキングパッチの各マスキングパッチは、前記複数の伝導性トレースのうちの単一の伝導性トレース上に形成される、ことと、
前記複数の相互接続構造が前記複数の相互接続部位の頂面および側面を覆うように、前記マスキング層を有しない位置において前記複数の相互接続構造を前記複数の相互接続部位に接着することと、
前記半導体ダイと前記基板との間で前記複数の相互接続構造の周囲に封入材を堆積させることと
を含む、方法。 - 前記複数の相互接続構造を前記複数の相互接続部位に接着することは、圧力またはリフロー温度下で、前記複数の相互接続構造を前記複数の相互接続部位に接着することをさらに含む、請求項5に記載の方法。
- 前記複数の相互接続部位から離れた前記基板の領域上に前記マスキング層を形成することをさらに含む、請求項5に記載の方法。
- 前記相互接続構造は、可融部分と、非可融部分とを含む、請求項5に記載の方法。
- 前記相互接続構造は、伝導柱と、前記伝導柱上に形成されたバンプとを含む、請求項5に記載の方法。
- 半導体ダイの表面上に形成された複数の相互接続構造を含む半導体ダイと、
基板と、
前記基板上に形成された複数の相互接続部位のアレイを含む複数の伝導性トレースであって、前記相互接続部位は、前記相互接続構造よりも狭く、前記複数の相互接続構造は、前記複数の相互接続構造が前記複数の相互接続部位の頂面および側面を覆うように、前記複数の相互接続部位に接着されている、複数の伝導性トレースと、
前記基板上に、かつ、前記複数の相互接続部位のアレイ内に介在して形成された複数のマスキングパッチであって、前記複数のマスキングパッチの各マスキングパッチは、前記複数の伝導性トレースのうちの単一の伝導性トレース上に形成される、複数のマスキングパッチと、
前記半導体ダイと前記基板との間で前記複数の相互接続構造の周囲に堆積させられた封入材と
を備える、半導体素子。 - 前記相互接続構造は、可融部分と、非可融部分とを含む、請求項10に記載の半導体素子。
- 前記相互接続構造は、伝導柱と、前記伝導柱上に形成されたバンプとを含む、請求項10に記載の半導体素子。
- 前記相互接続部位または前記相互接続構造上に凸凹を形成することをさらに含む、請求項10に記載の半導体素子。
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US10388626B2 (en) | 2019-08-20 |
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US20120241945A9 (en) | 2012-09-27 |
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