WO2009090896A1 - 電子部品 - Google Patents
電子部品 Download PDFInfo
- Publication number
- WO2009090896A1 WO2009090896A1 PCT/JP2009/050028 JP2009050028W WO2009090896A1 WO 2009090896 A1 WO2009090896 A1 WO 2009090896A1 JP 2009050028 W JP2009050028 W JP 2009050028W WO 2009090896 A1 WO2009090896 A1 WO 2009090896A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- land
- insulating film
- electronic component
- common substrate
- alignment mark
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/058—Holders; Supports for surface acoustic wave devices
- H03H9/059—Holders; Supports for surface acoustic wave devices consisting of mounting pads or bumps
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
- H03H9/1085—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a non-uniform sealing mass covering the non-active sides of the BAW device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/70—Multiple-port networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source
- H03H9/72—Networks using surface acoustic waves
- H03H9/725—Duplexers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/0558—Plural external layers being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to an electronic component, and more particularly to an electronic component in which a plurality of elements are mounted on a common substrate via solder bumps.
- the surface acoustic wave filter for reception 102 and the surface acoustic wave filter for transmission 103 are electrically connected to the multilayer ceramic substrate 101 with solder or gold bumps 105. Yes.
- the solder bumps are joined by reflow, and the gold bumps are joined by ultrasonic joining (see, for example, Patent Document 1). JP 2003-198325 A
- an insulating film 50x having an opening 52x is formed on a conductive pattern 42x formed on a common substrate using a solder resist. A portion of the conductive pattern 42k exposed from the opening 52x of the insulating film 50x becomes a land on the common substrate side for connection to the elements 10a and 10b.
- the conductive film needs to be formed larger than the opening of the insulating film in consideration of the positional deviation between the insulating film and the conductive pattern. Therefore, it is disadvantageous for narrowing the pitch of the bumps and becomes a design constraint.
- the solder bumps when solder bumps are melted by the reflow process, the solder bumps are wet and spread in a state of being confined in the opening of the insulating film, and the element mounting height is reduced. Determined by size. Increasing the opening of the insulating film increases the tolerance range of the solder bump size, but increases the mounting position of the element. On the other hand, when the opening of the insulating film is reduced, the variation in the mounting position of the element is reduced, but the allowable range of the variation in the size of the solder bump is reduced.
- the opening size of the insulating film must be reduced.
- the opening is small, it is necessary to increase the processing accuracy of the opening and reduce the variation in the size of the opening, which makes processing difficult and increases the processing cost.
- the present invention aims to provide an electronic component that can reduce the variation in the mounting position of the element even if there is a variation in the size of the solder bump, and can easily cope with a narrow pitch. To do.
- the present invention provides an electronic component configured as follows.
- the electronic component includes (a) a common substrate, (b) at least two elements mounted on one main surface of the common substrate, and (c) a conductive pattern formed on the one main surface of the common substrate.
- the elements mounted on the one main surface of the common substrate extend in the same direction as the adjacent directions and correspond to the terminals of the elements mounted on the one main surface of the common substrate, respectively.
- a conductive pattern including a plurality of lands formed on the land, and (d) at least the conductive pattern separated from both side edges in the direction perpendicular to the extending direction of the land and adjacent to both ends in the extending direction of the land.
- the direction in which the land extends and the direction in which the elements mounted on the common substrate are adjacent to each other are the same direction.
- Insulating films are arranged on both sides of the land extending direction, and insulating films are formed away from the side edges on both sides in the direction perpendicular to the land extending direction. It can wrap around the space on both sides in the direction perpendicular to. Therefore, even if there is variation in the size of the solder bumps, it is possible to mount with a constant spacing between adjacent elements.
- the portion of the conductive pattern adjacent to both ends in the extending direction of the land is formed so as to extend in the same direction as the land with the same width as the land.
- the allowable range can be increased.
- the insulating film extends from the side edge of the land with a predetermined interval and surrounds the land.
- a distance between the insulating film and the side edge of the land is smaller than a diameter of the solder bump.
- the conductive pattern includes an alignment mark forming portion extending in parallel with a direction in which the land extends.
- the insulating film includes alignment mark end portions formed at intervals on both sides in the extending direction of the alignment mark forming portion.
- an alignment mark is formed by a portion exposed at the interval provided at the end portion of the alignment mark.
- the one main surface of the common substrate further includes a resin covering the element.
- the elements are a surface acoustic wave filter for transmission and a surface acoustic wave filter for reception.
- a small duplexer can be provided.
- the electronic component of the present invention can reduce the variation in the mounting position of the element even if there is a variation in the size of the solder bump, and can easily cope with a narrow pitch.
- Example 1 It is a top view of one main surface of a common substrate.
- Example 1 It is a principal part enlarged plan view of a land vicinity.
- Example 1 It is a graph which shows the dispersion
- Example 1 It is a principal part expanded sectional view of alignment mark vicinity.
- Example 2 It is a top view of one main surface of a common substrate.
- Example 3 It is a principal part enlarged plan view of a land vicinity.
- Example 3) It is a principal part expanded sectional view near a land.
- Comparative example It is sectional drawing of an electronic component. (Conventional example)
- Example 1 An electronic component 30 of Example 1 will be described with reference to FIGS.
- two elements 10a and 10b are mounted on the upper surface 40a side which is one main surface of the common substrate 40. That is, the conductive pattern 42 formed on the upper surface 40 a of the common substrate 40 and the elements 10 a and 10 b are electrically connected via the solder bumps 18.
- a resin 32 is disposed around the elements 10 a and 10 b, and the elements 10 a and 10 b are covered with the resin 32.
- an external electrode 46 for mounting the electronic component 30 on another circuit substrate or the like is exposed.
- the common substrate 40 via conductors and internal wiring patterns that electrically connect the conductive patterns 42 and the external electrodes 46 are formed.
- the electronic component 30 is a duplexer, and surface acoustic wave filters for transmission and reception are mounted on the common substrate 40 as the elements 10a and 10b.
- a conductive pattern 42 is formed on the upper surface 40a of the common substrate 40, and an insulating film 50 with hatched lines is formed on the solder resist. It is formed using.
- a slit 53 is formed in the insulating film 50, and a land 44 bonded to the solder bump 18 is formed by a portion of the conductive pattern 42 exposed from the slit 53.
- the land 44 extends in the direction in which the elements 10a and 10b mounted on the upper surface 40a of the common substrate 40 are adjacent to each other, that is, in the same direction as the X direction (left and right direction in the drawing).
- the slit 53 of the insulating film 50 extends in a direction perpendicular to the extending direction (X direction) of the land 44, that is, the Y direction.
- the insulating film 50 is separated from the side edges 44s on both sides of the land 44 in the Y direction. Is formed.
- the pitch of the lands 44 does not change, so that mounting defects of the elements 10a and 10b are unlikely to occur.
- the insulating film 50 is formed away from the side edge 44s of the land 44, there is a space where the solder bumps 18 spread in the Y direction in the reflow process. Therefore, compared to the case where the solder bumps are arranged in the closed space in the opening between the insulation, the solder bumps 18 are less likely to be stressed, so that the bonding reliability of the elements 10a and 10b is high.
- a piezoelectric element having at least one vibration part and an element wiring connected to the vibration part on the piezoelectric substrate 11 is manufactured.
- the support layer 12 is formed so as not to reach the vibration part.
- a photosensitive polyimide resin was used for the support layer 12.
- a cover layer 14 is formed on the support layer 12 by lamination or the like, and a via hole is formed by a laser.
- the cover layer 14 was made of a non-photosensitive epoxy resin.
- an under bump mental layer 17 is formed by electrolytic plating (Cu, Ni, etc.), and Au (thickness of about 0.05 to 0.1 ⁇ m) for preventing oxidation is formed on the surface.
- a solder paste such as Sn—Ag—Cu is printed directly on the under bump mental layer 17 through a metal mask and heated at a temperature at which the solder paste dissolves, for example, about 260 ° C.
- the solder is fixed to the layer 17 and the flux is removed by a flux cleaning agent to form spherical solder bumps 18. Thereafter, the chip is cut out by a method such as dicing, and the preparation of the element is completed.
- a conductive pattern 42 obtained by patterning Cu foil by etching is provided on the surface 40a by a general printed wiring board manufacturing method, and an insulating film 50 is formed thereon by a photolithography etching method using a solder resist.
- a printed wiring board on which Ni (thickness of about 3 to 6 ⁇ m) and Au (thickness of about 0.05 to 0.1 ⁇ m) are formed by electroless plating is prepared.
- the land 44 constituted by the conductive pattern 42 and the insulating film 50 on the printed wiring board surface 40a extends in the direction in which the two elements 10a and 10b are adjacent, that is, in the X direction.
- the conductive pattern 42 and the insulating film 50 are formed.
- the elements 10 a and 10 b are mounted on the lands 44 on the surface of the printed wiring board 40 a, embedded in the resin 32, and then divided to produce a plurality of electronic components 30. .
- FIG. 4 is a graph showing the results of measuring the mounting positions of the elements 10a and 10b before embedding the elements 10a and 10b in the resin 32, that is, variations in the mounting positions of the elements.
- Table 1 below shows the average value, standard deviation, maximum value, and minimum value of the measured values in FIG.
- Example 2 The electronic component of Example 2 will be described with reference to FIG.
- the electronic component of the second embodiment has the following configuration added to the same configuration as the electronic component 30 of the first embodiment.
- an alignment mark forming part 42a extending in the X direction is formed on the conductive pattern in the same manner as the land.
- an alignment mark end portion 50a is formed by providing a gap 53a on both sides of the alignment mark forming portion 42a in the extending direction.
- the alignment mark 44a is formed by the portion exposed at the interval 53a of the alignment mark end portion 50a of the insulating film.
- the conductive pattern and the insulating film simultaneously form both a portion for forming an alignment mark and a portion for forming a land.
- Example 3 An electronic component of Example 3 will be described with reference to FIGS.
- the electronic component of Example 3 has substantially the same configuration as the electronic component of Example 1.
- the same reference numerals are used for the same components as in the first embodiment, and differences from the first embodiment will be mainly described.
- the insulating film 50 extending in the Y direction is formed to be aligned in the X direction, and the insulating film 50 is not formed on both sides of the land 44 in the Y direction.
- FIG. 7 which is a plan view of FIG. 6 and an enlarged plan view of the main part of the portion denoted by reference numeral A in FIG.
- an insulating film 50b is formed at a distance from the side edge 44t of the land 44b. That is, for each land 44b, a rectangular frame-shaped insulating film 50b is formed so as to surround the land 44b.
- the distance (S) between the side edge 43 of the land 44b and the inner surface 52 of the insulating film 50b is preferably smaller than the diameter (D) of the solder bump 18. If S ⁇ D, even if the mounting positions of the elements 10a and 10b are shifted, if the solder bumps fit in the opening 53b surrounded by the insulating film 50b, the movement of the solder bumps is prevented by the insulating film 50b. The position of the element does not shift greatly due to handling or the like. When the solder balls are melted by reflow in a later process, the elements 10a and 10b can be mounted at normal positions by the self-alignment action due to the surface tension of the solder.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
18 はんだバンプ
20,20a,20b 支持層
30 電子部品
32 樹脂
40 共通基板
40a 上面(一方主面)
40b 下面
42 導電パターン
42a アライメントマーク形成部
43 側縁
44 ランド
44a アライメントマーク
44a,44t 側縁
50 絶縁膜
50a アライメントマーク端部
50b 絶縁膜
53 スリット
53a 間隔
Claims (6)
- 共通基板と、
前記共通基板の一方主面に実装される少なくとも2つの素子と、
前記共通基板の前記一方主面に形成された導電パターンであって、前記共通基板の前記一方主面に実装される前記素子同士が隣接する方向と同方向に延在しかつ前記共通基板の前記一方主面に実装される前記素子の端子にそれぞれ対応する位置に形成された複数のランドを含む、導電パターンと、
前記ランドの延在方向に直角な方向の両側の側縁から離れて、前記ランドの延在方向の両端に隣接して、少なくとも前記導電パターン上に形成された絶縁膜と、
前記ランド上に配置され、前記ランドと前記素子の前記端子とを接合するはんだバンプと、
を備えたことを特徴とする、電子部品。 - 前記絶縁膜は、前記ランドの前記側縁から所定の間隔を設けて延在し、前記ランドのまわりを囲むことを特徴とする、請求項1に記載の電子部品。
- 前記絶縁膜と前記ランドの前記側縁との間の間隔は、前記はんだバンプの直径よりも小さいことを特徴とする、請求項2に記載の電子部品。
- 前記導電パターンは、前記ランドが延在する方向と平行に延在するアライメントマーク形成部を含み、
前記絶縁膜は、前記アライメントマーク形成部の延在方向両側に間隔を設けて形成されたアライメントマーク端部を含み、
前記アライメントマーク形成部のうち、前記アライメントマーク端部に設けられた前記間隔に露出する部分により、アライメントマークが形成されることを特徴とする、請求項1、2又は3に記載の電子部品。 - 前記共通基板の前記一方主面に、前記素子を覆う樹脂をさらに備えたことを特徴とする、請求項1乃至4のいずれか一つに記載の圧電デバイス。
- 前記素子が送信用弾性表面波フィルタと受信用弾性表面波フィルタであることを特徴とする、請求項1乃至5のいずれか一つに記載の電子部品。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2009801021178A CN101911271B (zh) | 2008-01-17 | 2009-01-06 | 电子部件 |
JP2009549999A JP5550102B2 (ja) | 2008-01-17 | 2009-01-06 | 電子部品 |
US12/825,524 US8344265B2 (en) | 2008-01-17 | 2010-06-29 | Electronic component |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008008481 | 2008-01-17 | ||
JP2008-008481 | 2008-01-17 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/825,524 Continuation US8344265B2 (en) | 2008-01-17 | 2010-06-29 | Electronic component |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009090896A1 true WO2009090896A1 (ja) | 2009-07-23 |
Family
ID=40885287
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2009/050028 WO2009090896A1 (ja) | 2008-01-17 | 2009-01-06 | 電子部品 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8344265B2 (ja) |
JP (1) | JP5550102B2 (ja) |
CN (1) | CN101911271B (ja) |
WO (1) | WO2009090896A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012109507A (ja) * | 2010-11-16 | 2012-06-07 | Stats Chippac Ltd | 半導体素子およびフリップチップ相互接続構造を形成する方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5754464B2 (ja) * | 2013-05-21 | 2015-07-29 | 株式会社村田製作所 | モジュールおよびその製造方法 |
KR20170114313A (ko) * | 2016-04-04 | 2017-10-16 | 삼성전기주식회사 | Baw 필터 및 그 제조방법 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0697634A (ja) * | 1992-09-09 | 1994-04-08 | Ibiden Co Ltd | フリップチップ用のプリント配線板 |
JP2003198325A (ja) * | 2001-10-19 | 2003-07-11 | Murata Mfg Co Ltd | 分波器、通信装置 |
JP2003282812A (ja) * | 2002-03-26 | 2003-10-03 | Matsushita Electric Ind Co Ltd | 半導体実装モジュール |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW381328B (en) * | 1994-03-07 | 2000-02-01 | Ibm | Dual substrate package assembly for being electrically coupled to a conducting member |
US5969461A (en) * | 1998-04-08 | 1999-10-19 | Cts Corporation | Surface acoustic wave device package and method |
JP3945968B2 (ja) * | 2000-09-06 | 2007-07-18 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
JP4477213B2 (ja) | 2000-10-04 | 2010-06-09 | 古河電気工業株式会社 | 回路基板及び回路基板の製造方法 |
JP3963655B2 (ja) * | 2001-03-22 | 2007-08-22 | 三洋電機株式会社 | 回路装置の製造方法 |
US6940183B1 (en) * | 2004-06-04 | 2005-09-06 | Lu-Chen Hwan | Compound filled in lead IC packaging product |
KR100850243B1 (ko) * | 2007-07-26 | 2008-08-04 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
-
2009
- 2009-01-06 WO PCT/JP2009/050028 patent/WO2009090896A1/ja active Application Filing
- 2009-01-06 CN CN2009801021178A patent/CN101911271B/zh active Active
- 2009-01-06 JP JP2009549999A patent/JP5550102B2/ja active Active
-
2010
- 2010-06-29 US US12/825,524 patent/US8344265B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0697634A (ja) * | 1992-09-09 | 1994-04-08 | Ibiden Co Ltd | フリップチップ用のプリント配線板 |
JP2003198325A (ja) * | 2001-10-19 | 2003-07-11 | Murata Mfg Co Ltd | 分波器、通信装置 |
JP2003282812A (ja) * | 2002-03-26 | 2003-10-03 | Matsushita Electric Ind Co Ltd | 半導体実装モジュール |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10388626B2 (en) | 2000-03-10 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming flipchip interconnect structure |
JP2012109507A (ja) * | 2010-11-16 | 2012-06-07 | Stats Chippac Ltd | 半導体素子およびフリップチップ相互接続構造を形成する方法 |
Also Published As
Publication number | Publication date |
---|---|
US20100252316A1 (en) | 2010-10-07 |
JPWO2009090896A1 (ja) | 2011-05-26 |
CN101911271A (zh) | 2010-12-08 |
US8344265B2 (en) | 2013-01-01 |
JP5550102B2 (ja) | 2014-07-16 |
CN101911271B (zh) | 2012-05-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9258899B2 (en) | Method of fabricating a wiring board | |
JP5790682B2 (ja) | モジュールおよびその製造方法 | |
US8179689B2 (en) | Printed circuit board, method of fabricating printed circuit board, and semiconductor device | |
JP2006294692A (ja) | 半導体装置およびその製造方法 | |
JP2009200389A (ja) | 電子部品内蔵基板の製造方法 | |
JP2009105139A (ja) | 配線基板及びその製造方法と半導体装置 | |
JP2008091640A (ja) | 電子装置およびその製造方法 | |
US20170047230A1 (en) | Fabrication method of packaging substrate | |
KR101139084B1 (ko) | 다층 프린트 기판 및 그 제조 방법 | |
US7943863B2 (en) | Wiring substrate and manufacturing method thereof, and semiconductor device | |
KR101477818B1 (ko) | 배선 회로 기판 및 그 제조 방법 | |
US9426887B2 (en) | Wiring board and electronic device using the same | |
JP5550102B2 (ja) | 電子部品 | |
JP4061506B2 (ja) | 半導体装置の製造方法 | |
JP6674284B2 (ja) | 実装構造及びモジュール | |
JP2014504034A (ja) | リードクラックが強化された電子素子用テープ | |
JP6323622B2 (ja) | 部品実装基板 | |
JP2011029287A (ja) | プリント配線基板、半導体装置及びプリント配線基板の製造方法 | |
WO2011043102A1 (ja) | 回路基板 | |
JP2007109884A (ja) | 実装基板および半導体装置 | |
JP2006344631A (ja) | 部品内蔵基板 | |
JP2006253253A (ja) | フレキシブル回路基板の製造方法 | |
JP2007103831A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2006066665A (ja) | 配線基板 | |
JP2017188554A (ja) | 回路基板、回路基板装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200980102117.8 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09701834 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2009549999 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 09701834 Country of ref document: EP Kind code of ref document: A1 |