CN101911271A - 电子部件 - Google Patents

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CN101911271A
CN101911271A CN2009801021178A CN200980102117A CN101911271A CN 101911271 A CN101911271 A CN 101911271A CN 2009801021178 A CN2009801021178 A CN 2009801021178A CN 200980102117 A CN200980102117 A CN 200980102117A CN 101911271 A CN101911271 A CN 101911271A
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terminal pad
dielectric film
common substrate
elements
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CN101911271B (zh
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小田哲也
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Murata Manufacturing Co Ltd
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Abstract

本发明提供一种即使存在焊料凸起的尺寸偏差，也能减小元件的安装位置的偏差，且能容易地对应于窄间距化的电子部件。一种电子部件包括：(a)共用基板；(b)安装在共用基板的一个主面上的至少2个元件(10a、10b)；(c)导电图形(42)，其被形成在共用基板的一个主面上，包括多个连接盘(44)，该多个连接盘(44)向与元件(10a、10b)彼此之间相邻的方向的相同方向延伸、且被形成在分别与元件(10a、10b)端子相对应的位置；(d)绝缘膜(50)，其从与连接盘(44)的延伸方向成直角方向的两侧的侧边缘离开，与连接盘(44)的延伸方向的两端相邻，且至少被形成在导电图形(42)上；以及(e)焊料凸起，其被配置在连接盘(44)上，对连接盘(44)和元件(10a、10b)的端子进行接合。

Description

电子部件
技术领域
本发明涉及一种电子部件，详细地涉及一种在共用基板上通过焊料凸起来安装多个元件的电子部件。
背景技术
过去，已提出一种在共用基板上安装多个元件的电子部件。
例如，图10的剖面图所示的电子部件，发送用表面声波滤波器102和接收用表面声波滤波器103通过焊料或金凸起105与多层结构陶瓷基板101电连接。在焊料凸起的情况下，通过回流焊(reflow)，在金凸起的情况下，通过超声波接合来进行接合(例如参照专利文献1)。
专利文献1：JP特开2003-198325号公报
发明内容
在使用焊料凸起的情况下，例如，通常如图9的平面图所示，在形成在共用基板上的导电图形42x上，使用抗焊剂(solder resist)形成具有开口52x的绝缘膜50x，从绝缘膜50x的开口52x露出的部分的导电图形42k成为用于与元件10a、10b连接的共用基板侧的连接盘。
如此，在绝缘膜的开口处露出导电图形而形成连接盘的时候，考虑绝缘膜和导电图形的位置偏移，需要比绝缘膜的开口更大地形成导电膜。因此，在不利于凸起的窄间距化的同时，也会制约设计。
此外，当通过回流焊工序熔化时，焊料凸起就会以封闭在绝缘膜的开口内的状态而浸润扩散，由于元件安装高度降低，所以焊料凸起的尺寸的偏差的允许范围由绝缘膜的开口的大小决定。虽然如果加大绝缘膜的开口，则焊料凸起的尺寸的偏差的允许范围变大，但元件的安装位置的偏差也变大。另一方面，虽然如果减小绝缘膜的开口，则元件的安装位置的偏差会变小，但焊料凸起的尺寸的偏差的允许范围也变小。
如果为了薄型化和窄间距化而减小凸起尺寸，则也不得不减小绝缘膜的开口尺寸。由于开口变小时，就必须提高开口的加工精度、减小开口的尺寸的差异，所以加工变得困难，也会增大加工成本。
本发明鉴于相关的实情，希望提供一种即使存在焊料凸起的尺寸偏差，也能减小元件的安装位置的偏差，且能容易地对应于窄间距化的电子部件。
本发明提供如下这种结构的电子部件。
一种电子部件，包括：(a)共用基板；(b)安装在上述共用基板的一个主面上的至少2个元件；(c)导电图形，其被形成在上述共用基板的上述一个主面上，包括多个连接盘，其中，该多个连接盘向与安装在上述共用基板的上述一个主面上的上述元件彼此之间相邻的方向相同的方向延伸、且被形成在分别与安装在上述共用基板的上述一个主面上的上述元件的端子相对应的位置处；(d)绝缘膜，其从与上述连接盘的延伸方向成直角方向的两侧的侧边缘离开，与上述连接盘的延伸方向的两端相邻，且至少被形成在上述导电图形上；以及(e)焊料凸起，其被配置在上述连接盘上，对上述连接盘和上述元件的上述端子进行接合。
在上述结构中，连接盘延伸的方向和安装在共用基板上的元件彼此之间相邻的方向是相同的方向。在连接盘的延伸方向两侧配置绝缘膜，由于从与连接盘的延伸方向成直角的方向的两侧的侧边缘离开而形成绝缘膜，所以能使焊料凸起在回流焊时蔓延到与连接盘的延伸方向成直角方向的两侧的空间。因此，即使焊料凸起的大小存在偏差，也能够保证相邻的元件彼此之间的间隔固定，从而进行安装。
在上述结构中，通过以与连接盘相同的宽度向与连接盘相同的方向延伸，如此形成导电图形中与连接盘的延伸方向两端相邻的部分，就能够增大绝缘膜和连接盘的位置偏移的允许范围。在实现凸起的窄间距化的情况下，可以仅在元件彼此之间相邻的一方向上提高绝缘膜的尺寸精度。由此，如果与在绝缘膜中设置开口而形成连接盘的情形相比，则能够减少谋求凸起的窄间距化时的设计制约，也容易制造。
优选地，上述绝缘膜按照从上述连接盘的上述侧边缘开始设置规定的间隔的方式进行延伸，且包围上述连接盘的四周。
此情况下，即使元件的搭载位置发生偏移，如果焊料凸起伸入包围连接盘的四周的绝缘膜的内侧，则在此后的操作等时元件的位置也不会进一步偏移。
优选地，上述绝缘膜与上述连接盘的上述侧边缘之间的间隔比上述焊料凸起的直径更小。
此情况下，即使元件的搭载位置发生偏移，也会因为在回流焊工序中，焊料凸起与连接盘相连，从而能够通过自动对准而在正常的位置安装元件。
优选地，上述导电图形包括与上述连接盘延伸的方向平行地延伸的对准标记形成部。上述绝缘膜包括通过在上述对准标记形成部的延伸方向两侧设置间隔而形成的对准标记端部。由上述对准标记形成部中的、在设置在上述对准标记端部的上述间隔中露出的部分来形成对准标记。
此情况下，即使导电图形和绝缘膜的位置对准发生偏移，也由于连接盘和对准标记在相同的方向上偏移几乎相同的量，从而减小了对元件搭载精度的影响。
优选地，在上述共用基板的上述一个主面上还包括覆盖上述元件的树脂。
此情况下，容易对具备多个元件的电子部件进行小型化。
优选地，上述元件是发送用表面声波滤波器和接收用表面声波滤波器。
此情况下，能提供小型的双工器。
发明效果
本发明的电子部件，即使存在焊料凸起的尺寸偏差，也能减小元件的安装位置的偏差，能容易地对应于窄间隙化。
附图说明
图1是电子部件的剖面图。(实施例1)
图2是共用基板的一个主面的平面图。(实施例1)
图3是连接盘(land)附近的主要部位放大平面图。(实施例1)
图4是表示安装位置的X、Y方向的偏差的图表。(实施例1)
图5是对准标记附近的主要部位放大剖面图。(实施例2)
图6是共用基板的一个主面的平面图。(实施例3)
图7是连接盘附近的主要部位放大平面图。(实施例3)
图8是连接盘附近的主要部位放大剖面图。(实施例3)
图9是共用基板的平面图。(比较例)
图10是电子部件的剖面图。(现有例)
符号说明
10a、10b  元件
18  焊料凸起
20、20a、20b  支持层
30  电子部件
32  树脂
40 共用基板
40a  上面(一个主面)
40b  下面
42  导电图形
42a  对准标记形成部
43  侧边缘
44  连接盘
44a  对准标记
44a、44t  侧边缘
50  绝缘膜
50a  对准标记端部
50b  绝缘膜
53  隙缝
53a  间隔
具体实施方式
下面，参照图1～图7说明作为本发明的实施方式的实施例。
<实施例1>
参照图1～图4说明实施例1的电子部件30。
如图1的剖面图所示，实施例1的电子部件30，在共用基板40的一个主面即上面40a侧安装有2个元件10a、10b。即，在形成在共用基板40的上面40a的导电图形42和元件10a、10b之间，通过焊料凸起18进行电连接。在元件10a、10b的周围配置树脂32，用树脂32覆盖元件10a、10b。在共用基板40的另一个主面即下面40b侧露出用于在另一电路基板等上安装电子部件30的外部电极46。在共用基板40的内部形成电连接在导电图形42和外部电极46之间的通路导体和内部布线图形。例如，电子部件30是双工器，作为元件10a、10b，在共用基板40上并列搭载发送用和接收用的表面声波滤波器。
详细地，如图2的平面图及图3的主要部位放大平面图所示，在共用基板40的上面40a形成导电图形42，在其上使用抗焊剂形成带斜线的绝缘膜50。在绝缘膜50中形成隙缝53，由导电图形42中从隙缝53露出的部分形成与焊料凸起18相接合的连接盘44。连接盘44，向与安装在共用基板40的上面40a的元件10a、10b彼此之间相邻的方向、即X方向(在图中左右方向)相同的方向延伸。绝缘膜50的隙缝53向与连接盘44的延伸方向(X方向)成直角的方向即Y方向延伸，从连接盘44的Y方向两侧的侧边缘44s离开而形成绝缘膜50。
像这样，如果在向绝缘膜50的Y方向延伸的隙缝53中露出向X方向延伸的连接盘44，则即使因为元件10a、10b的搭载位置偏移或焊料凸起18的尺寸偏差等导致焊料的浸润性不均匀等，从而在元件10a、10b中产生位置偏移，与Y方向的位置偏移量相比，X方向的位置偏移量会变小。为此，由于能减小在X方向上相邻的元件10a、10b间的间隔来进行设计，所以有利于产品的小型化、成本面。
此外，即使导电图形42和绝缘膜50的位置对准精度变差，也因连接盘44的间距没有改变而很难产生元件10a、10b的安装不良。
此外，由于从连接盘44的侧边缘44s离开而形成绝缘膜50，所以在回流焊工序中，存在焊料凸起18在Y方向上扩展的空间。由此，如果与在绝缘间的开口内的封闭空间内配置焊料凸起的情形相比，则由于难以对焊料凸起18施加应力，而使得元件10a、10b的接合可靠性提高。
接着，参照图1及图2说明具体的制作例。
制作在压电基板11上至少具有1个振动部及连接到振动部的元件布线的压电元件，以作为元件10a、10b。为了形成中空空间13而形成不涉及振动部的支持层12。在支持层12中使用感光性聚酰亚胺类树脂。在支持层12上通过层叠(laminate)等形成覆盖层14，利用激光器形成通孔(viahole)。覆盖层14使用非感光性环氧类树脂。此后，通过电解电镀(Cu、Ni等)形成下凸起(under bump)金属层17，在表面形成用于防止氧化的Au(厚度0.05～0.1μm左右)。在下凸起金属层17的正上方隔着金属掩膜来印刷Sn-Ag-Cu等焊料膏，通过以使焊料膏熔化的温度例如260℃左右进行加热，来使焊料与下凸起金属层17固着，通过焊剂清洗剂去除焊剂，形成球状的焊料凸起18。此后，利用切割(dicing)等方法截出芯片，完成元件制备。
关于共用基板40，利用通常的印刷布线版制造方法，制备印刷布线版，其中，在该印刷布线版中，在表面40a上设置通过蚀刻来对Cu箔进行构图而成的导电图形42，在其上使用抗焊剂通过光刻蚀刻法形成绝缘膜50，利用用于防止导电图形表面氧化的非电解电镀，来形成Ni(厚度3～6μm左右)和Au(厚度0.05～0.1μm左右)。
如图2所示，形成导电图形42和绝缘膜50，以使得由印刷布线版表面40a的导电图形42和绝缘膜50构成的连接盘44向2个元件10a、10b相邻的方向即X方向延伸。
接着，如图1及图2所示，在印刷布线版表面40a的连接盘44上安装元件10a、10b，之后，用树脂32填埋后进行分割，制作出多个电子部件30。
图4是表示在树脂32中填埋元件10a、10b前，测量元件10a、10b的安装位置的结果、即元件的安装位置的偏差的图表。在下面的表1中示出图4的测量值的平均值、标准偏差(standard deviation)、最大值、最小值。
[表1]
  X方向   Y方向
  平均   -0.002   0.008
  σ   0.005   0.012
  最大值   0.009   0.032
  最小值   -0.010   -0.018
基于图4及表1可知，X方向的安装位置的偏差比Y方向的安装位置的偏差更小。认为这是由于虽然在连接盘44的X方向两端形成绝缘膜50，但在连接盘44的Y方向两侧没有形成绝缘膜50，所以在回流焊工序中，焊料凸起18向Y方向比向X方向能更自由地扩展。
<实施例2>
参照图5说明实施例2的电子部件。
实施例2的电子部件在与实施例1的电子部件30相同的结构中追加了以下的结构。
即，如图5的主要部位放大平面图所示，在导电图形中形成与连接盘一样地向X方向延伸的对准标记形成部42a。在绝缘膜中，在对准标记形成部42a的延伸方向两侧上设置间隔53a而形成对准标记端部50a。然后，如导电图形的对准标记形成部42a中用粗线60所表示那样，由在绝缘膜的对准标记端部50a的间隔53a中露出的部分形成对准标记44a。
导电图形及绝缘膜同时形成用于形成对准标记的部分、和用于形成连接盘的部分两者。
如此，一旦使安装时的对准标记44a与连接盘结构相同，即使导电图形和绝缘膜的相对位置发生偏移，也会因为连接盘和对准标记两者向相同的方向偏移相同的量，从而减小了对元件搭载精度的影响。
<实施例3>
参照图6～图8说明实施例3的电子部件。
实施例3的电子部件与实施例1的电子部件的结构大致相同。下面对与实施例1相同的结构部分使用相同的符号，以与实施例1的不同点为中心进行说明。
在实施例1的电子部件中，在X方向上并列地形成向Y方向延伸的绝缘膜50，在连接盘44的Y方向两侧不形成绝缘膜50。相对于此，在实施例3的电子部件中，如图6的平面图及作为图6中赋予符号A的部分的主要部位放大平面图的图7所示，还在连接盘44b的Y方向两侧，从连接盘44b的侧边缘44t开始设置间隔来形成绝缘膜50b。即，按每一连接盘44b来形成矩形的框状的绝缘膜50b，以便包围连接盘44b。
如图8的主要部位放大剖面图所示，优选连接盘44b的侧边缘43和绝缘膜50b的内面52之间的间隔(S)比焊料凸起18的直径(D)更小。如果S＜D，则即使假设元件10a、10b的搭载位置发生偏移，若焊料凸起收缩在绝缘膜50b所围绕的开口53b内，则由于通过绝缘膜50b就能阻止焊料凸起的移动，所以通过处理等，元件的位置也不会大大地偏移。在后面工序的回流焊中，当焊球熔化时，通过焊料的表面张力而产生的自动对准作用，就能将元件10a、10b安装在正常的位置。
<总结>
如上所说明的，如果在向元件彼此之间相邻的方向延伸的连接盘的延伸方向两侧形成绝缘膜，使用焊料凸起安装元件，则即使存在焊料凸起的尺寸偏差，也能减小元件的安装位置的偏差，能容易地对应于窄间距化。
再有，本发明不限于上述实施方式，可追加各种变更来实施。

Claims (6)

1.一种电子部件，包括：
共用基板；
安装在上述共用基板的一个主面上的至少2个元件；
导电图形，其被形成在上述共用基板的上述一个主面上，包括多个连接盘，其中，该多个连接盘向与安装在上述共用基板的上述一个主面上的上述元件彼此之间相邻的方向相同的方向延伸、且被形成在分别与安装在上述共用基板的上述一个主面上的上述元件的端子相对应的位置处；
绝缘膜，其从与上述连接盘的延伸方向成直角的方向的两侧的侧边缘离开，与上述连接盘的延伸方向的两端相邻，且至少被形成在上述导电图形上；以及
焊料凸起，其被配置在上述连接盘上，对上述连接盘和上述元件的上述端子进行接合。
2.根据权利要求1所述的电子部件，其特征在于，
上述绝缘膜按照从上述连接盘的上述侧边缘开始设置规定的间隔的方式进行延伸，且包围上述连接盘的四周。
3.根据权利要求2所述的电子部件，其特征在于，
上述绝缘膜与上述连接盘的上述侧边缘之间的间隔比上述焊料凸起的直径更小。
4.根据权利要求1、2或3所述的电子部件，其特征在于，
上述导电图形包括与上述连接盘延伸的方向平行地延伸的对准标记形成部，
上述绝缘膜包括通过在上述对准标记形成部的延伸方向两侧设置间隔而形成的对准标记端部，
由上述对准标记形成部中的、在设置在上述对准标记端部的上述间隔中露出的部分来形成对准标记。
5.根据权利要求1至4中任一项所述的电子部件，其特征在于，
在上述共用基板的上述一个主面上还包括覆盖上述元件的树脂。
6.根据权利要求1至5中任一项所述的电子部件，其特征在于，
上述元件是发送用表面声波滤波器和接收用表面声波滤波器。
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* Cited by examiner, † Cited by third party
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US10388626B2 (en) * 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
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US5969461A (en) * 1998-04-08 1999-10-19 Cts Corporation Surface acoustic wave device package and method
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US6940183B1 (en) * 2004-06-04 2005-09-06 Lu-Chen Hwan Compound filled in lead IC packaging product
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