KR19990063268A - 전자 부품 장치, 그 제조 방법 및 집합 회로 기판 - Google Patents
전자 부품 장치, 그 제조 방법 및 집합 회로 기판 Download PDFInfo
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- KR19990063268A KR19990063268A KR1019980056724A KR19980056724A KR19990063268A KR 19990063268 A KR19990063268 A KR 19990063268A KR 1019980056724 A KR1019980056724 A KR 1019980056724A KR 19980056724 A KR19980056724 A KR 19980056724A KR 19990063268 A KR19990063268 A KR 19990063268A
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- circuit board
- electronic component
- pattern
- electrode pad
- alignment pattern
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- 238000004519 manufacturing process Methods 0.000 title claims description 41
- 229910000679 solder Inorganic materials 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims description 61
- 239000000463 material Substances 0.000 claims description 38
- 230000015572 biosynthetic process Effects 0.000 claims description 27
- 238000005520 cutting process Methods 0.000 claims description 21
- 238000005192 partition Methods 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 22
- 229910052802 copper Inorganic materials 0.000 description 22
- 239000010949 copper Substances 0.000 description 22
- 238000007747 plating Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 17
- 238000005476 soldering Methods 0.000 description 13
- 238000003909 pattern recognition Methods 0.000 description 9
- 230000004907 flux Effects 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000002390 adhesive tape Substances 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
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- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/181—Encapsulation
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49131—Assembling to base an electrical component, e.g., capacitor, etc. by utilizing optical sighting device
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
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Abstract
Description
Claims (20)
- 전자부품이 실장(實裝)되고, 제1 주표면(主表面) 측에 외부 접속용의 전극 패드가 형성되고, 또한 집합 회로 기판으로부터 절삭(切削) 분리된 회로 기판을 가지는 전자 부품 장치를 제조하는 방법에 있어서,상기 집합 회로 기판의 상기 제1 주표면 측에, 상기 전극 패드의 노출부의 윤곽을 구획하는 동시에, 상기 전극 패드의 노출부 윤곽을 구획하는 구성 부분의 재료와 동일한 재료로 이루어지는 위치 맞춤 패턴의 윤곽을 구획하는 것을 특징으로 하는 전자 부품 장치의 제조 방법.
- 제1항에 있어서, 상기 노출부 윤곽이 상기 전극 패드 자체의 윤곽에 따라서 구획되는 경우에, 상기 전극 패드의 재료와 동일 재료로 이루어지는 상기 위치 맞춤 패턴의 윤곽을 상기 전극 패드의 윤곽의 구획 시에 동시에 구획하는 것을 특징으로 하는 전자 부품 장치의 제조 방법.
- 제1항에 있어서, 상기 노출부 윤곽이 상기 전극 패드의 주변부를 덮는 솔더 레지스트(solder resist)의 개구부의 윤곽에 따라서 구획되는 경우에, 솔더 레지스트로 이루어지는 상기 위치 맞춤 패턴의 윤곽을 상기 개구부 형성 시에 동시에 구획하는 것을 특징으로 하는 전자 부품 장치의 제조 방법.
- 제1항에 있어서, 상기 위치 맞춤 패턴은 상기 집합 회로 기판의 절삭 위치를 나타내기 위한 패턴으로서 형성하는 것을 특징으로 하는 전자 부품 장치의 제조 방법.
- 제1항에 있어서, 상기 위치 맞춤 패턴은 상기 전극 패드로의 돌기 전극의 형성 위치를 결정하기 위한 패턴으로서 형성하는 것을 특징으로 하는 전자 부품 장치의 제조 방법.
- 제1항에 있어서, 상기 위치 맞춤 패턴은 마더 보드로의 상기 전자 부품 장치의 실장위치를 결정하기 위한 인식용 패턴으로서 형성하는 것을 특징으로 하는 전자 부품 장치의 제조 방법.
- 제6항에 있어서, 상기 위치 맞춤 패턴을 1개의 상기 회로 기판 당 2개소씩 형성하는 것을 특징으로 하는 전자 부품 장치의 제조 방법.
- 제6항에 있어서, 상기 위치 맞춤 패턴의 윤곽 형상이 서로 상이하게 한 것을 특징으로 하는 전자 부품 장치의 제조 방법.
- 전자 부품이 실장되고, 제1 주표면 측에 외부 접속용의 전극 패드가 형성된 회로 기판을 가지는 전자 부품 장치에 있어서,상기 회로 기판은 상기 제1 주표면 측에 상기 전극 패드의 노출부의 윤곽을 구획하는 구성 부분의 재료와 동일한 재료로 이루어지고, 상기 노출부 윤곽이 구획되는 동시에 윤곽이 구획된 위치 맞춤 패턴을 배설하여 이루어지는 것을 특징으로 하는 전자 부품 장치.
- 제9항에 있어서, 상기 노출부 윤곽이 상기 전극 패드 자체의 윤곽에 따라서 구획되는 경우, 상기 위치 맞춤 패턴이 상기 전극 패드의 재료와 동일 재료를 상기 전극 패드 형성 시에 동시에 구획한 것인 것을 특징으로 하는 전자 부품 장치.
- 제9항에 있어서, 상기 노출부 윤곽이 상기 전극 패드의 주변부를 덮는 솔더 레지스트의 개구부의 윤곽에 따라서 구획되는 경우, 상기 위치 맞춤 패턴이 솔더 레지스트를 상기 개구부 형성 시에 동시에 구획한 것인 것을 특징으로 하는 전자 부품 장치.
- 제9항에 있어서, 상기 위치 맞춤 패턴은 상기 전극 패드로의 돌기 전극의 형성 위치를 결정하기 위한 패턴인 것을 특징으로 하는 전자 부품 장치.
- 제9항에 있어서, 상기 위치 맞춤 패턴은 마더 보드로의 상기 전자 부품 장치의 실장 위치를 결정하기 위한 인식용 패턴인 것을 특징으로 하는 전자 부품 장치.
- 제13항에 있어서, 상기 위치 맞춤 패턴은 2개소에 배설된 것을 특징으로 하는 전자 부품 장치.
- 제14항에 있어서, 상기 위치 맞춤 패턴의 윤곽 형상이 서로 상이한 것을 특징으로 하는 전자 부품 장치.
- 제9항에 있어서, 상기 전극 패드를 일정 간격의 그리드의 교점에 배치한 경우, 상기 그리드의 위치에 대하여 하프 그리드 어긋난 위치에, 상기 위치 맞춤 패턴을 배치한 것을 특징으로 하는 전자 부품 장치.
- 제1 주표면 측에 외부 접속용의 전극 패드가 형성되는 복수의 회로 기판이 형성된 집합 회로 기판에 있어서,상기 집합 회로 기판은 상기 제1 주표면 측에 상기 전극 패드의 노출부의 윤곽을 구획하는 구성 부분의 재료와 동일한 재료로 이루어지고, 상기 노출부 윤곽이 구획되는 동시에 윤곽이 구획된 위치 맞춤 패턴을 배설하여 이루어지는 것을 특징으로 하는 집합 회로 기판.
- 제17항에 있어서, 상기 위치 맞춤 패턴은 상기 회로 기판 이외의 부분에 상기 집합 회로 기판의 절삭 위치를 나타내기 위한 패턴으로서 배설한 것을 특징으로 하는 집합 회로 기판.
- 제17항에 있어서, 상기 위치 맞춤 패턴은 상기 전극 패드로의 돌기 전극의 형성 위치를 결정하기 위한 패턴으로서 배설한 것을 특징으로 하는 집합 회로 기판.
- 제17항에 있어서, 상기 위치 맞춤 패턴은 상기 집합 회로 기판을 사용하여 제조된 전자 부품 장치의 마더 보드로의 실장 위치를 결정하기 위한 인식용 패턴으로서 배설한 것을 특징으로 하는 집합 회로 기판.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35286797A JP3850967B2 (ja) | 1997-12-22 | 1997-12-22 | 半導体パッケージ用基板及びその製造方法 |
JP97-352867 | 1997-12-22 | ||
JP98-77159 | 1998-03-25 | ||
JP07715998A JP3831109B2 (ja) | 1998-03-25 | 1998-03-25 | 半導体パッケージ |
Publications (2)
Publication Number | Publication Date |
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KR19990063268A true KR19990063268A (ko) | 1999-07-26 |
KR100589530B1 KR100589530B1 (ko) | 2006-11-30 |
Family
ID=26418260
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KR1019980056724A KR100589530B1 (ko) | 1997-12-22 | 1998-12-21 | 전자 부품 장치, 그 제조 방법 및 집합 회로 기판 |
Country Status (3)
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US (2) | US6219912B1 (ko) |
KR (1) | KR100589530B1 (ko) |
TW (1) | TW421980B (ko) |
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JP3614030B2 (ja) * | 1999-04-02 | 2005-01-26 | 株式会社村田製作所 | マザー基板,子基板およびそれを用いた電子部品ならびにその製造方法 |
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JP3827497B2 (ja) | 1999-11-29 | 2006-09-27 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
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JP3636030B2 (ja) * | 2000-04-26 | 2005-04-06 | 株式会社村田製作所 | モジュール基板の製造方法 |
JP4615117B2 (ja) * | 2000-11-21 | 2011-01-19 | パナソニック株式会社 | 半導体ウエハへのバンプ形成方法及びバンプ形成装置 |
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JP2009016397A (ja) * | 2007-06-29 | 2009-01-22 | Toshiba Corp | プリント配線板 |
EP2538439A1 (en) * | 2010-02-19 | 2012-12-26 | Asahi Glass Company, Limited | Substrate for mounting element, and method for manufacturing the substrate |
CN102565518A (zh) * | 2010-12-16 | 2012-07-11 | 鸿富锦精密工业(深圳)有限公司 | 电流平衡测试系统 |
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KR102214512B1 (ko) * | 2014-07-04 | 2021-02-09 | 삼성전자 주식회사 | 인쇄회로기판 및 이를 이용한 반도체 패키지 |
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1998
- 1998-12-16 TW TW087120893A patent/TW421980B/zh not_active IP Right Cessation
- 1998-12-21 US US09/216,932 patent/US6219912B1/en not_active Expired - Lifetime
- 1998-12-21 KR KR1019980056724A patent/KR100589530B1/ko active IP Right Grant
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2000
- 2000-05-11 US US09/569,310 patent/US6324068B1/en not_active Expired - Lifetime
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US6324068B1 (en) | 2001-11-27 |
US6219912B1 (en) | 2001-04-24 |
TW421980B (en) | 2001-02-11 |
KR100589530B1 (ko) | 2006-11-30 |
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