TWI286830B - Electronic carrier board - Google Patents
Electronic carrier board Download PDFInfo
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- TWI286830B TWI286830B TW095101563A TW95101563A TWI286830B TW I286830 B TWI286830 B TW I286830B TW 095101563 A TW095101563 A TW 095101563A TW 95101563 A TW95101563 A TW 95101563A TW I286830 B TWI286830 B TW I286830B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R43/00—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
- H01R43/02—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections
- H01R43/0256—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections for soldering or welding connectors to a printed circuit board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R43/00—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
- H01R43/02—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections
- H01R43/0228—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections without preliminary removing of insulation before soldering or welding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
1286830 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種電子載板,尤指一種應用於表面 黏著技術(Surface Mounted Technology,SMT)之電子載板。 . 【先前技術】 , 隨著積體電路製作技術的進步,電子元件的設計與製 . 作持續朝著細微化的趨勢發展,且由於其具備更大規模、 高積集度的電子線路,因此其產品功能亦更加完整。 • 在此種情況下,傳統利用插入式組裝技術(Through1286830 IX. Description of the Invention: [Technical Field] The present invention relates to an electronic carrier board, and more particularly to an electronic carrier board applied to Surface Mounted Technology (SMT). [Prior Art] With the advancement of integrated circuit fabrication technology, the design and manufacture of electronic components continue to move toward a trend of miniaturization, and because of its larger scale and high integration of electronic circuits, Its product features are also more complete. • In this case, traditional use of plug-in assembly technology (Through
Hole Technology ; THT)進行接置的電子元件,由於尺寸無 法進一步的縮小,因而佔用例如印刷電路板(Printed Circuit Board; PCB)、電路板(circuit board)或基板(substrate) 等電子載板大量的空間,再加上插入式組裝技術需要對應 每個電子元件的每隻腳位置而於電子載板上進行鑽孔,所 以此類型的電子元件接腳實際佔用電子載板兩面的空間, 而且該電子元件與電子載板連接處的銲點也比較大,是 以,現今的電子元件組裝程序中,大量採用表面黏著技術 (Surface Mounted Technology ; SMT),以有效提供電子元 件組裝於電子載板上。 使用表面黏著技術之電子元件,由於其電性連接端(接 腳)係銲結於與該電子元件同一面之電子載板上,因此,不 需如同插入式組裝技術般需在電子載板中大量鑽孔,以供 電子元件之接腳穿設,換言之,使用表面黏著技術將可在 電子載板兩面同時都可組裝電子元件,而大幅提昇電子載 6 19294 1286830 板·^間利用率’此外’由於表面黏著技術之電子元件體 積車X i相較於傳統的插入式組裝技術的電子元件,使用 2黏著技術之電子元件所能設置於電子載板上之數量較 為达、集,加上表面黏著技術之電子元件的造價也較便宜, 因此已躍升為現今電子載板上組裝電子元件的主流。 j者,基於電性及性能上的需求,於電子載板上安置 如電容(capacit0T)、電阻(Resist〇r)或電感㈣如㈣等被動 = (Passive CGmponents)已成為維持電子產品電性品質 穩定不可或缺之步驟。 、請參閱第1A圖,係為顯示於基板上接置表面黏著式 被動凡件之平面示意圖,同時配合參閱第1B及1C圖,係 為對應該第1A圖中之剖面線1β_1Β及剖面線ic_ic所形 成之uj面示思圖。其主要係在基板丨丨上之一預設位置上形 成t -對間隔開的銲塾12,該兩銲墊12係分別外露出用 以覆蓋該基板u上之防銲層(SGlderMask)13之開口 H ^銲墊_12上塗佈適量之錫膏(s〇lderPaste)i^,即可供’ :被動元件14之兩端部分別接黏至錫膏15上,再予回銲 、旱接(Reflow Soldering)處理,該被動元件14便可藉錫膏 15與鲜墊12適當地電性連接。其中,為避免被動元件\ 對應接著於銲墊時,因兩邊之鍚膏15不平衝發生立 (T〇mbstone)’因此在設計上為使錫f 15之潤濕區域 (wettmg area)大小一致,所形成外露出該相對兩銲墊η之 防銲層13的開π尺寸皆相互對稱且大小相同。 惟應用於半導體封裝件時,由於錫膏15的塗佈量以 19294 1286830 及經回銲處理時錫膏 精準控制,加上防銲’致使被動元件14高度難以 導致銲接之被動I: 面並不平整’時有凹陷產生而 (:,)17’此等間隙η多僅有,。至3。:;= =:(形二覆被動元…封裝膠體二 約為50微米,係大於此間隙高度。因 -無=所:r:;r被動元件14底部之間隙 溫作章严产由\ ^ 成有氣洞(void),導致後續高 裝結構:二t生5象(p°pcorn effect),致使整個構 貝13 ’亦或使得熔融錫膏15鑽過間隙17(即毛Hole Technology; THT) The electronic components that are connected are not able to be further reduced in size, and thus occupy a large number of electronic carriers such as printed circuit boards (PCBs), circuit boards, or substrates. Space, plus plug-in assembly technology, requires drilling on the electronic carrier for each foot position of each electronic component, so this type of electronic component pin actually occupies space on both sides of the electronic carrier, and the electron The solder joints between the components and the electronic carrier are also relatively large. Therefore, in today's electronic component assembly process, Surface Mounted Technology (SMT) is widely used to effectively provide electronic components for assembly on an electronic carrier. The electronic component using the surface adhesion technology, since the electrical connection end (pin) is soldered to the electronic carrier board on the same side as the electronic component, it does not need to be in the electronic carrier as the plug-in assembly technology A large number of holes are drilled for the pins of the electronic components. In other words, the surface adhesion technology can be used to assemble electronic components on both sides of the electronic carrier, and the electronic load is greatly improved. 'Because of the surface-adhesive technology, the electronic component volume car X i is compared with the traditional plug-in assembly technology electronic components, the electronic components using the 2 adhesive technology can be placed on the electronic carrier board in a larger amount, set, plus surface Adhesive electronic components are also cheaper to manufacture, and have therefore become the mainstream of today's electronic components on electronic boards. j, based on electrical and performance requirements, such as capacitors (capacit0T), resistors (Resist〇r) or inductors (4) such as (4) passive = (Passive CGmponents) has been maintained on the electronic carrier to maintain the electrical quality of electronic products An indispensable step to stability. Please refer to Figure 1A, which is a schematic plan view showing the surface-attached passive parts on the substrate. Referring to Figures 1B and 1C, it is the corresponding line 1β_1Β and the section line ic_ic in Figure 1A. The formed uj surface is a reflection. The main purpose is to form a t-pair of spaced apart solder pads 12 at a predetermined position on the substrate, the two solder pads 12 are respectively exposed to cover the solder resist layer 13 on the substrate u. Appropriate amount of solder paste (12 〇 P P 上 上 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 被动 被动 被动 被动 被动 被动 被动 被动 被动 被动 被动 被动 被动(Reflow Soldering) processing, the passive component 14 can be appropriately electrically connected to the fresh pad 12 by the solder paste 15. In order to avoid the passive component\ corresponding to the solder pad, the two sides of the paste 15 are not flattened (T〇mbstone)', so the size of the wett area of the tin f 15 is designed to be uniform, The opening π dimensions of the solder resist layer 13 formed to expose the opposing pads η are all symmetrical and the same in size. However, when applied to a semiconductor package, since the solder paste 15 is coated with 19294 1286830 and the solder paste is precisely controlled during reflow processing, and the solder resist is added, the passive component 14 is highly difficult to cause passive I: the surface is not When there is a flattening, there is a depression and (:,) 17'. These gaps are more than η. To 3. :;= =: (Formed two-pass passive element... The encapsulation colloid 2 is about 50 microns, which is greater than the height of this gap. Because - no =: r:; r The gap between the bottom of the passive component 14 is strictly produced by \^ Void, resulting in a subsequent high-load structure: the p°pcorn effect, causing the entire structure 13' or the molten solder 15 to pass through the gap 17 (ie, hair
、、、田:)形成橋接而導致被動元件14短路(如第1B 不),從而影響製成品之良率。 -同和由於受到相鄰被動元件14配置影t,供不同被 動π件14電性導通至銲墊12之熔融錫膏15,亦有可能流 ,銲墊12表面與防銲層13間之間隙,再沿該基板u _ 鮮層13間之間隙而相互擴散、接觸,因而發生銲錫突伸 (solderextrusion)現象,導致相鄰被動元件14發生短路問 題’如第1C圖所示之標號SE。 另請參閱第2A圖,美國專利第6,521,997號所揭露之 技術係在形成相對銲墊22間的防銲層23開口間,增設一 溝槽(Gr〇ove)230,冀藉由開設溝槽230擴大間隙來提供樹 脂穿越。 然而,該溝槽330的開設受限於感光型防銲層33之 解析度(Resolution)較低之限制,其寬度尺寸最小僅能開設 8 19294 1286830 成150微米(μιη),且因銲墊開口之光罩對位精度之限制, 其銲墊防銲層寬度Μ最小需有75微米寬因此,隨著元件 體積逐漸縮小,於有限的銲㈣距_設溝槽將更加困難。, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , - and the molten solder paste 15 for electrically connecting the different passive π members 14 to the bonding pads 12 due to the arrangement of the adjacent passive elements 14 is also likely to flow, and the gap between the surface of the bonding pad 12 and the solder resist layer 13 is Further, the electrodes are diffused and contacted along the gap between the substrate u and the fresh layer 13, so that a solder extrusion phenomenon occurs, causing a short circuit problem between the adjacent passive elements 14 as indicated by reference numeral SE in FIG. 1C. Referring to FIG. 2A, the technique disclosed in US Pat. No. 6,521,997 is to add a trench (Gr〇ove) 230 between the openings of the solder resist layer 23 formed between the opposing pads 22, by opening the trench 230. The gap is enlarged to provide resin traversal. However, the opening of the trench 330 is limited by the lower resolution of the photosensitive solder resist layer 33, and the width dimension can be as small as 8 19294 1286830 to 150 micrometers (μιη), and the opening of the pad is opened. The reticle alignment accuracy is limited, and the solder pad solder mask width Μ is required to be 75 μm wide. Therefore, as the component volume is gradually reduced, it is more difficult to set the trench in a limited solder (four) pitch.
其因為,半導體業界目前使用之被動元件尺寸規格(如 _3型,0402型)-般係由兩組數字分別代表該被動元件 的長和寬,該長、寬單位皆以英制(一般以英吋)為單位, 且以較大的數字排列在前。以刚2型晶片被動元件為例, 〇402係特定規格之被動元件,元件之大小為0.040英吋 (長)x 0.020奂时(覓)’如換算成公制單位則相當於長度 0.040 X 25.4 = 1.016 公厘(約為 1000 微米),寬度 〇 〇2〇 X 4 〇·508公厘(約為500微米),而高度一般為500微米 之晶片型電容、電阻或電感。 如第2B圖所示,隨著半導體產品逐漸朝向輕、薄、 紐、小的方向發展,目前薄型球柵陣列式半導體封裝件 (Thin & Fine Ball Grid Array,TFBGA)的封裝膠體 (EjiCapsulant)厚度已發展至53〇微米,因此,未來薄型 封裝件勢必無法容納厚度500微米之〇4〇2型晶片被動元件 而必/員改採尺寸更小的〇2〇 1型晶片被動元件來降低封裝 件整體厚度。有關0201型晶片被動元件的長、寬、高俱為 04〇2型晶片被動元件的一半,亦即5〇〇微米(長)X 微米(寬)X 250微米(高),為配合0201型小尺寸被動 元件的長度(5 0 0彳政米)限制,基板上二成對鲜塾間之間隔距 離(Spacing) A1亦從400微米縮小至275微米。 然而,防銲層係一種感光型(Ph〇t〇image)材料,由 9 19294 1286830 於低感光解析度及鋅墊間開口之光罩對位精度之限制,該 銲墊之防銲層最小需有75微米之寬度,此時,若依上述°美 國專利6,521,997號所揭露之技術在焊塾之間的防鲜層上 開設覓度150微米之溝槽,則如第2B圖所示,各外露銲 •墊之防銲層開口距離該溝槽之防銲層寬度A2僅為 干 :(275-15G)/2=62.5微米’因此,當外露銲墊之防銲層開口 •與溝槽間之寬度降至62.5微米,已然超出目前基之 75微米的製造能力而無法以現有製程製作。 夕 • 復請參閱第3A圖,美國專利2〇〇5/〇253231號之技術 係揭露分別在成對設置之兩銲㈣上形成外露出麵鲜丁 塾32之相對側壁之兩防銲層開口 33〇,且於該開口 間 設置有阻隔條331,藉以形成流道33⑽,以冀絕緣樹脂填 入0 唯此技術仍受限於感光型防銲層之解析度較低之限 制,於有限的鮮墊間距小於275微米日夺,即無法形成阻隔 •條331,因而無法運用於〇2〇1型被動元件。Because the passive component size specifications (such as _3 type, 0402 type) currently used in the semiconductor industry are generally represented by two sets of numbers representing the length and width of the passive component, the length and width units are in English (generally in English).吋) is the unit, and is ranked first with a larger number. Taking the passive component of the 2 type wafer as an example, the 〇402 is a passive component of a specific specification. When the size of the component is 0.040 inches (length) x 0.020 觅 (觅), the conversion to a metric unit is equivalent to a length of 0.040 X 25.4 = 1.016 mm (approximately 1000 microns), a chip type capacitor, resistor or inductor having a width of 〇2〇X 4 〇·508 mm (approximately 500 μm) and a height of typically 500 μm. As shown in FIG. 2B, as semiconductor products are gradually moving toward light, thin, new, and small directions, the current package of thin ball grid array semiconductor packages (Thin & Fine Ball Grid Array, TFBGA) (EjiCapsulant) The thickness has been developed to 53 〇 micron, so in the future, thin packages will inevitably be able to accommodate 被动4〇2 wafer passive components with a thickness of 500 μm, and the 〇2〇1 wafer passive components will be smaller to reduce the package. The overall thickness of the piece. The length, width and height of the 0201 type passive component are half of the passive components of the 04〇2 type wafer, that is, 5 〇〇 micron (length) X micron (width) X 250 micron (height), which is suitable for the 0201 type. The length of the passive component (500 彳 米) is limited, and the spacing between the two pairs of fresh enamel on the substrate is also reduced from 400 microns to 275 microns. However, the solder resist layer is a photosensitive (Ph〇t〇image) material, which is limited by the low sensitivity resolution of the 9 19294 1286830 and the aligning accuracy of the reticle opening between the zinc pads. Having a width of 75 microns, in this case, as shown in FIG. 2B, the technique disclosed in the above-mentioned U.S. Patent No. 6,521,997 discloses a groove having a twist of 150 micrometers on the anti-fresh layer between the solder fillets. The solder mask opening distance of each exposed solder pad is only dry: (275-15G)/2=62.5 micron'. Therefore, when the solder pad of the exposed pad is opened, the trench is opened. The width of the gap is reduced to 62.5 microns, which is beyond the current 75 micron manufacturing capability and cannot be made in existing processes. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 33〇, and a barrier strip 331 is disposed between the openings to form the flow channel 33(10), and the insulating resin is filled with 0. However, the technique is still limited by the lower resolution of the photosensitive solder resist layer, and is limited. The fresh pad spacing is less than 275 micron, which means that the barrier strip 331 cannot be formed, so it cannot be applied to the 〇2〇1 passive component.
、另此技術於防銲層發生偏移時,將造成兩銲墊之潤濕 區域發生不相等之情形,如第3B圖所示,原可供銲接之 知墊面積(外路出防銲層開口面積)為A*B,防銲層若向左 偏移X微米(傳統基板製程偏移量能力為75微米),則左銲 墊之面積將為B*(A+X),右銲墊面積為B*(A 面積將有傭之差異,此種)不相^之塾 潤濕面積,將導致銲接於該銲墊之被動元件發生立碑現象 (Tombstone) 〇 19294 10 1286830 再者,前述美國專利第ό,521,997號及2005/0253231 號所揭示之技術中,面對相鄰被動元件配置影響,均無法 提供有效解決相鄰被動元件間錫膏可能經由該基板表面與 防銲層間之間隙而相互擴散、接觸等,所造成之鲜錫突伸 •現象,甚而導致相鄰被動元件發生短路之問題。 綜上所述,如何提供一種電子載板,可避免電子元件 ,接置其上時’因電子元件與電子載板中存留有間隙所導致 氣洞產生及電性橋接及銲錫突伸問題,同時避免因製程精 ^誤差問題致使形成外露銲墊之開口產生偏位,造成外 路出δ亥鋅墊之尺寸面積不同而發生立碑現象等問題,實為 業界亟需待解之問題。 【發明内容】 參於以上所述習知技術之問題,本發明之主要目的係 在提供-種電子載板,可避免因製程精度及誤差問題致使 形成外露二成對料之開口的偏位,造成外露銲塾尺寸面 積不同等問題。 ,發明之再—目的係在提供—種電子載板,避免電子 疋牛接置於该電子载板上時發生立碑現象加⑽㈣。 另—目的係在提供—種電子載板,得以有效 導;:元件與電子載板間,避免氣洞產輯 V致之乳爆以及電性橋接問題。 本t明之又—目的係在提供-種f子載板,可防止相 郴電子元件間電性導接而短路。 本么月之復目的係在提供一種電子載板,解決小型 19294 11 1286830 之表面黏著式(Surface Mounted Technology,SMT)被動 凡件底部無法形成供封裝樹脂流入溝槽的問題。 為達成上揭及其他目的,本發明揭露 其係包括:-主體;至少二成對設於該主體表面之|塾; 二:-用以覆蓋該主體表面之保護層,該保護層對應於該 :塾位置形成有開口,該開口係彼此同向且外露出該二銲 :广相同的第一及第二側壁,該銲墊第一側壁係垂 ^亥成對銲㈣設之方向’第二㈣係平行該成對鮮塾佈 向,且至少—銲塾之第—側壁間隔該開口之距離係 對二側壁間隔該開口之距離5〇微米㈣。另外 使;1: 護層開口之該二成對銲墊中,復可同時 壁間隔該開口之距離 wn , 5G^,且至少對於位在接置於 第側=之電子凡件下方之保護層開口’相距該銲墊 弟一側壁之距離大於距第二側壁之距_5g微米。 於另一較佳實施例中,哕 ψ ^ ^ ,, μ ”遵層開口係彼此同向且外 路出该一知墊之至少三相同的第一、 一 第-侧壁係垂直該成對銲墊佈7弟::壁’該 係平行該成對銲墊佈設之方向,且至少一壁 壁間隔該開口之距離至少大 _ /亥紅墊之弟-側 口之距離50微米。 於4一第三側壁間隔該開 入顯:中又:較佳實施例中,該保護層開口係彼此同向且完 王”、、員路出该二銲墊相同之第一、— 凡 苴Φ兮筮 〜 乐二、第三及第四側壁, "I亥弟一、弟四侧壁係垂直該成對銲塾佈設之方向,第 12 19294 1286830 二、第三側壁係平行該成對銲㈣設之方n 壁間隔該開口之距離至少大於 口之距離50微米。 弟二側壁間隔該開 •於再-較佳實施例中,該保護層開口係彼此同向 路出该二銲墊相同的第一側 卜 銲塾佈設之方向。 ▲ 5玄弟一側壁係垂直該成對 露出:再it:圭實施例中,該保護層開口係彼此同向Μ 出5亥一鲜墊相同的第一側壁及第四 側壁係垂直該成對鐸塾佈設之方向。 "亥弟及弟四 相同於===例中,該二成對佈設之銲塾尺寸係不 第一、第If層開Γ係彼此同向且外露出其中一銲塾之 及第四側壁,::及::側壁,且外露出另-銲墊之第- 方向,該第二=四側壁係垂直該成對鮮塾佈設之 因此施弟二侧壁鮮行該朗銲墊佈設之方向。 構係勺料本發⑽揭露之1子餘所形叙構裝姓 構係包括有··如前述 傅衣、、Ό 性連接至該電子载板 ,电子兀件,係接置並電 件,並得充佈於該電子元件下方及今電子凡 中該電子載柘于卜万及“子载板開口中。其 層係為防銲層,該電子元件係為被動元件。亥保護 口此,本發明之電子載板令 面之保護層,在$,,、 1 丨又復现於冤子载板表 口,藉心露出二配置之焊塾處形成有同向之開 防銲層)開 f Η向側壁’如此’在形成保護層( 域度及誤差考量下,由於該開 19294 13 1286830 口係同向設於該成對銲墊處,因此即便其發生偏位,而得 ^免外硌出開口之銲墊面積不同,而使後續於該銲墊上接 著私子元件日年,因濕潤面積(wetting area)之不平衡所造成 之立碑現象。 同t °亥保濩層開口係可外露出該二銲塾之至少二相 的第一及第二側壁,亦或外露出該二銲墊至少三相同的 '弟一二第二、第三侧壁,該銲墊第一側壁係垂直該成對銲 φ 布°又之方向,第二(第三)側壁係平行該成對銲墊佈設之 一 °且》亥第側壁間隔該開口之距離至少大於該第二(第 :)侧壁間隔該開口之距離5〇微米。如此’即便開口發生 位’不僅仍可維持相同的銲藝外露面積,更可供包覆電 二件之絕緣樹脂(平均練5()微米)充佈該電子元件下方 =相口中,避免氣洞產生所導致之氣爆以 喊,同時復可使絕緣樹脂至少包覆該銲墊至少一侧 ,免:生銲錫突伸⑽dere咖—現象,甚而 φ 子兀件短路之問題。 电 此外,該保護層開口復可彼此同向且 科相同之第-、第二、第三及第四側壁,其;員:第出= 弟四側壁係垂直該成對銲墊佈設之方向 _ 係平行該成對鲜塾佈設之方向,且該第-側= 離至少大於該第二、第三側壁間隔該開二Γ 微米。如此,即便該開口發生偏位,仍 之外露面積,以提供電子元件與原設計相、…干既有 同時更可供包覆電子元件之P绫± D之潤濕面積, 仵之1巴緣樹脂充佈該電子元件下方 19294 14 1286830 及該開口中,避免氣洞產生所導致之氣爆以及電性橋接問 題,復亦可使絕緣樹脂完全包覆該銲墊側邊,避免發生焊 錫突伸現象。 另外,本發明中該保護層開口係可僅外露出銲墊之第 .一側壁,該第一側壁係垂直該成對銲墊佈設之方向,如此, 在形成保護層開口時,因製程精度及誤差考量下,由於該 ’開口係同向没於該二成對銲墊處,因此即便其發生偏位, 仍得避免成對銲墊外露出開口之面積不同,而使後續於該 在干墊上接著電子元件時,因濕潤面積之不平衡造成立碑現 象。 μ再者,本發明中該保護層開口係可外露出銲墊之第一 及罘四侧壁,該第一及第四侧壁係垂直該成對銲墊佈設之 方向,且该第一側壁間隔該開口之距離至少大於該第四側 壁間隔該開口之距離約5G微米。如此,即便該開口發生偏 位,仍可維持該銲墊之既有外露面積尺寸,以提供電子元 ·_件與原設計相同之潤濕面積,同時可供包覆電子元件之絕 樹脂充佈該電子元件下方及該開口中,避免氣洞產生所 導致之氣爆以及電性橋接問題。 同時,本發明中該保護層開口之其中一者係全面外露 出其中一銲墊之第一、第二、第三及第四側壁,相對另一 開口係外鉻出另一銲墊之第一及第四側壁,且該第一側壁 間隔該開口之距離至少大於該第二、第三及第四側壁間隔 1亥開口之距離約50微米。如此,即便該開口發生偏位,仍 β、准持η亥知塾之既有外露面積尺寸,以提供電子元件與原 19294 15 1286830 没计相同之潤濕面積,同時 · 了』仏匕復私子兀件之絕緣樹脂 編電子疋件下方及該開口中’避免氣洞產生所導致之 氣爆以及電性橋接問題。 ’ 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式,熟習此技藝之人士可由本說明書所揭示之内容輕易地 貫域加以施行或應用’本說明書中的各項細節亦 種修飾與變更。 在不^本發明之精神下進行各 篇一實施例 請參閱第4Α及4Β_,係為本發明 每 施例平面示意圖。 戰孜弟貝 ,本發明之電子載板係包括有:-主體411 ;至少二成 對設於該主體411表面之銲墊42 矣而々泣4昆Μ 用以復盍该主體 2之賴43,該保護層43對應於該二銲 =開:,及431,該開口 43〇及431係彼此同向且/ 路〇亥一知塾42之二相同且寬度分別為Β之第一側壁似 為Α之第二㈣422(或第三側壁似),以 :外露面積為A*B之二成對設置之銲塾,該鮮塾第一㈣ 切係垂直該成對銲墊42佈設之方向,第二側壁422(或第 二側壁423)係平行該成對銲墊42佈設之方向,且該第— 側壁421間隔該開口 43〇,431之距離d,至少大於二 側壁422(或第三側壁423)間隔該開口 43〇,431之距離^ 19294 1286830 50 微米(μηι)。 於本實施例中’係採用業界 们對位誤差為75微米之製程加以^使^保躞層(防鮮 '中 對位誤差之能力如為75微料,係可大於 或寺於75微米’距離〇則係大於或等於為U5微米.另 =如對位誤差能力係為5〇微米時’則該距離㈣、可大於 或等於50微米,該距離〇則係大於或等於彻微米。、 即便開口 430,431發生偏位(如向左偏位乃微 米)m圖所示二成對設置之料面積 =75Γ’不僅可提供電^件相同銲墊接置面積(潤渴面 且=包覆電子元件之絕緣樹脂(平均粒徑%微幻 =心子元件下方及該開口中,避免氣洞產生所導致之 extrusion) 現象,甚而導致相鄰電子元件短路之問題。 該電子載板41係可為晶片料使用之封裝基板、電 路板或㈣轉板等,本實_巾主㈣封裝基板為例進 ㈣明。該電子載板41之本體411可為絕緣層或為其中間 堆璺有線路,之絕緣層’且於其表面佈設有複數導電線路 圖不)及#墊42,其巾部分銲墊係兩兩成對設置。該絕 緣層係例如為玻璃纖維、環氧樹脂(Ep〇xy)、聚亞醯胺 0—de)膠片、FR4 樹脂及 BT(Bismaieimide Triazine) 樹月曰等材料衣成,該線路層係例如為銅層。該電子 體411上係覆蓋有一保護層43,該保護層43係例如為防 19294 1286830 銲層⑽der mask),該防銲層之材質係選用具高度流動性 ,合物(Pc)lymer),如環氧樹脂(咖⑽㈣ 寻。亥保《又層43對應於至少二成對設置之鮮塾間形成 開口 430 及 431,JL Φ 兮 p弓 „ j, ,、中忒開口 43〇及431係彼此同向且外 路出H于墊42之二相同之第一側壁421 422 。 不 』土 復明芬閱第4D圖,當後續於該成對鲜塾上接置電子 • 7件時,該未設於電子元件下方之保護層開口 43卜亦即 位於一成對銲# 42間之保護層開口 431距離其銲塾第一 =壁似之距離,在對位誤差為75微米之條件下,復亦可 ;^等於75 U米(另在對位誤差為5〇微米之條件下可大 於5G微米),如此,即便開口佩431發生偏位(如 積米),同樣可提供電子元件相同鲜塾接置面 =二可供包覆電子元件之絕緣樹觸 所導=心:電子元件下方及該開口中,避免氣洞產生 ,少包及電性橋接問題,同時復可使絕緣樹脂至 :復该_少一側邊,以避免發生銲錫突伸_ 〜現象,甚而導致相鄰電子元件短路之問題。 ,參閱第5圖’係為本發明之電子載 面不意圖。 貝犯W卞 本查明弟一實施例之電子載板#盘命、+、》 —In addition, when the solder resist layer is offset, the wetted regions of the two solder pads may be unequal. As shown in FIG. 3B, the area of the solder pads that can be soldered (the outer solder mask layer) The opening area is A*B, and if the solder mask is shifted to the left by X microns (the traditional substrate process offset capacity is 75 microns), the area of the left pad will be B*(A+X), right pad The area of B* (A area will have a difference in commission, this kind) will not cause the wetted area, which will lead to the phenomenon of tombstoning of passive components soldered to the pad (Tombstone) 〇19294 10 1286830 In the techniques disclosed in U.S. Patent Nos. 5,521,997 and 2005/0253231, the effects of adjacent passive component configurations are not provided to effectively address the possibility of solder paste between adjacent passive components via the substrate surface and the solder resist layer. The gap between the gaps and the mutual diffusion, contact, etc., caused by the phenomenon of sharp tin protrusion and even the short circuit of adjacent passive components. In summary, how to provide an electronic carrier board can avoid the electronic components, when placed on the 'cause of the gap between the electronic components and the electronic carrier caused by the occurrence of air holes and electrical bridging and solder protruding problems, Avoiding the problem of the formation of the exposed pad by the process error, which causes the deviation of the opening of the exposed pad, which causes the difference in the size of the outer surface of the δ hai zinc pad, which is a problem that needs to be solved in the industry. SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the main object of the present invention is to provide an electronic carrier plate, which can avoid the deviation of the opening of the exposed two-pair material due to process precision and error problems. The problem is that the size of the exposed soldering iron is different. The re-invention of the invention is to provide an electronic carrier board to prevent the phenomenon of tombstoning when the electronic yak is placed on the electronic carrier (10) (4). In addition, the purpose is to provide an electronic carrier for effective guidance; between the component and the electronic carrier, avoiding the problem of bursting and electrical bridging caused by the gas cavity. The purpose of this is to provide a type of sub-carrier to prevent short-circuiting between electrical components of the electronic components. The purpose of this month is to provide an electronic carrier board that solves the problem that the surface of the surface mounted technology (SMT) passive parts of the small 19294 11 1286830 cannot form a resin resin into the trench. For the purpose of achieving the above and other objects, the present invention includes: - a body; at least two pairs of | 设 provided on the surface of the body; two: - a protective layer covering the surface of the body, the protective layer corresponding to the An opening is formed in the 塾 position, the openings are in the same direction and the second welding is exposed: the first and second sidewalls are the same, and the first sidewall of the soldering pad is perpendicular to the direction of the pair (four) (d) parallel to the pair of fresh smear, and at least - the first side of the weld bead is spaced from the opening by a distance of 5 〇 micrometers (4) from the distance between the two sidewalls. In addition, in the two pairs of pads of the protective layer opening, the distance between the walls and the opening is wn, 5G^, and at least for the protective layer located under the electronic component connected to the first side= The opening 'is spaced apart from the sidewall of the pad by more than _5g micrometers from the second sidewall. In another preferred embodiment, the 哕ψ ^ ^ , , μ ′ ” layer openings are in the same direction and the at least three identical first and first side walls are perpendicular to the pair. The pad cloth 7:: wall' is parallel to the direction in which the pair of pads are laid, and at least one wall is spaced apart from the opening by at least a distance _ / the distance between the black pad and the side port is 50 micrometers. The third sidewall is spaced apart from the opening: in the preferred embodiment, the openings of the protective layer are in the same direction of each other and are finished, and the first one of the two solder pads is the same as the first soldering pad.筮~ Le 2, the third and fourth side walls, "I Haidi, the fourth side wall of the brother is perpendicular to the direction of the pair of welding dies, the 12th 19294 1286830 second, the third side wall parallel to the pair of welding (four) The distance between the walls of the square n is at least 50 microns above the distance of the opening. The second sidewall is spaced apart. In the preferred embodiment, the protective layer openings are oriented in the same direction as the first side of the solder pads. ▲ 5 Xuandi one side wall is vertically exposed in pairs: in the example: in the embodiment, the protective layer openings are in the same direction, and the first side wall and the fourth side wall are the same in the same direction. The direction of the layout. "Hai Di and Si Si are the same as in ===, the two pairs of laid solderings are not the first, the first layer of the opening is in the same direction and the outer wall and the fourth side wall are exposed. , :: and :: the side wall, and the first direction of the other - the soldering pad is exposed, the second = four side wall is perpendicular to the pair of fresh enamel, so the direction of the slab is laid. . The structure of the structure is disclosed in (1). The structure of the surname includes the following: And the electrons are placed under the electronic component and the electrons are contained in the opening of the Bu Wan and the "sub-board". The layer is a solder mask, and the electronic component is a passive component. The protective layer of the electronic carrier board surface of the invention is reappeared on the surface of the rafter board at $, , 1 丨, and the same position of the solder joint is formed by the same place. f Η sidewalls 'so' in the formation of a protective layer (under the degree and error considerations, since the opening 19294 13 1286830 mouth is located in the same pair of pads, so even if it is biased, The area of the soldering pad of the opening is different, and the follow-up on the bonding pad is followed by the day of the private component, and the tombstoning phenomenon caused by the imbalance of the wetting area. Exposing the first and second sidewalls of the at least two phases of the solder fillet, or exposing the solder pads to at least three The same 'different one second and third side wall, the first side wall of the bonding pad is perpendicular to the paired welding φ cloth, and the second (third) side wall is parallel to the pair of bonding pads And the distance between the sidewalls of the wall is at least greater than the distance between the second (first:) sidewalls and the opening by 5 μm. Thus, even if the opening occurs, the same soldering exposed area can be maintained. The insulating resin for the two pieces of electric coating (average 5 () micron) is filled in the lower part of the electronic component = the phase mouth, to avoid the gas explosion caused by the generation of the air hole, and at the same time, the insulating resin can be coated at least At least one side of the solder pad, free of: the solder solder protrusion (10) dere coffee - phenomenon, even the short circuit of the φ sub-piece. In addition, the protective layer opening can be the same direction and the same as the first -, second, third And a fourth side wall, the member: the first out = the fourth side of the younger brother is perpendicular to the direction in which the pair of pads are laid out _ in parallel with the direction in which the pair of fresh shovel is laid, and the first side = away from at least greater than the second The third sidewall is spaced apart by two micrometers. Thus, even if the opening is misaligned The exposed area is still provided to provide the electronic component and the original design phase, ... the wetted area of the P绫±D which is both available for covering the electronic component, and the 1 bar edge resin is filled under the electronic component 19294 14 In 1286830 and the opening, the gas explosion and the electrical bridging problem caused by the generation of the air hole are avoided, and the insulating resin can completely cover the side of the soldering pad to avoid the phenomenon of solder protruding. In addition, the protection is in the present invention. The layer opening may expose only the first sidewall of the solder pad, the first sidewall is perpendicular to the direction in which the pair of pads are disposed, and thus, when forming the opening of the protective layer, due to process precision and error consideration, due to the ' The opening is not in the same direction as the pair of pads, so even if the offset occurs, the area of the exposed opening of the pair of pads is prevented from being different, so that when the electronic component is subsequently attached to the dry pad, it is wet. The imbalance of the area creates a monument. Further, in the present invention, the protective layer opening may expose the first and fourth sidewalls of the bonding pad, the first and fourth sidewalls are perpendicular to the direction in which the pair of pads are disposed, and the first sidewall The distance separating the openings is at least greater than the distance of the fourth sidewall from the opening by about 5 G microns. In this way, even if the opening is misaligned, the exposed area of the solder pad can be maintained to provide the same wetted area as the original design of the electronic component, and the resin can be filled with the resin. Under the electronic component and in the opening, air explosion and electrical bridging problems caused by air hole generation are avoided. Meanwhile, in the present invention, one of the openings of the protective layer exposes the first, second, third and fourth side walls of one of the pads, and the first one of the other pads is chromed out of the other opening. And a fourth sidewall, and the first sidewall is spaced apart from the opening by a distance greater than a distance of about 50 micrometers from the second, third, and fourth sidewalls. In this way, even if the opening is misaligned, the β, the quasi-holding has the exposed area size, so as to provide the same wetted area as the original 19294 15 1286830, and at the same time Under the insulating resin embossed electronic component of the sub-piece, and in the opening, 'avoiding gas explosion and electrical bridging caused by the generation of the cavity. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can easily implement or apply the details of the present specification by the contents disclosed in the present specification. Modifications and changes. Embodiments of each of the embodiments are described in the spirit of the present invention. Referring to Figures 4 and 4, a schematic plan view of each embodiment of the present invention is shown. The electronic carrier board of the present invention comprises: a main body 411; at least two pairs of solder pads 42 disposed on the surface of the main body 411 and weeping 4 for reclaiming the main body 2 The protective layer 43 corresponds to the second welding = open:, and 431, the openings 43 〇 and 431 are the same in the same direction and the second side of the road is the same as the first side wall of the width The second (four) 422 (or the third side wall) of the crucible is such that the exposed area is A*B, and the first (four) cutting line is perpendicular to the direction in which the pair of pads 42 are laid. The two sidewalls 422 (or the second sidewall 423) are parallel to the direction in which the pair of pads 42 are disposed, and the first sidewall 421 is spaced apart from the opening 43 〇, 431 by a distance d that is at least greater than the two sidewalls 422 (or the third sidewall 423) ) The distance between the opening 43 〇, 431 is ^ 19294 1286830 50 μm (μηι). In the present embodiment, the process of using the industry's alignment error of 75 micrometers is used to ensure that the ability of the alignment error is 75 micrometers, which can be greater than or less than 75 micrometers. The distance 〇 is greater than or equal to U5 microns. Another = if the alignment error capacity is 5 〇 microns, then the distance (four), can be greater than or equal to 50 microns, the distance 〇 is greater than or equal to the micron. Even The openings 430, 431 are offset (such as the leftward offset is micron) m shown in the two pairs of set material area = 75 Γ ' not only can provide the same solder pad connection area (tweezing surface and = coated electronic components) The insulating resin (average particle size % micro-magic = under the core element and in the opening, avoiding the extrusion caused by the generation of the cavity), and even causes the short circuit of adjacent electronic components. The electronic carrier 41 can be a wafer material. The package substrate, the circuit board or the (four) transfer board used, etc., the main package of the electronic package (4) is an example (4). The body 411 of the electronic carrier 41 may be an insulating layer or a circuit stacked in the middle thereof. Layer 'and has a plurality of conductive lines on its surface Figure No. and #垫42, the towel portion of the pad is arranged in pairs. The insulating layer is, for example, glass fiber, epoxy resin (Ep〇xy), polyamidoline 0-de) film, FR4 resin. And a material such as BT (Bismaieimide Triazine), which is, for example, a copper layer. The electronic body 411 is covered with a protective layer 43 which is, for example, a 19294 1286830 solder mask. The solder resist layer is made of a highly fluid, compound (Pc) lymer). Epoxy resin (Cai (10) (4) 寻.Haibao "Layer 43 corresponds to at least two pairs of sets of fresh enamel to form openings 430 and 431, JL Φ 兮p bow „ j, , 忒 opening 43 〇 and 431 series with each other The first side wall 421 422 is the same as the outer side of the pad 42. The second side wall 421 422 of the same type of the pad 42 is not the same as the 4D picture of the Fuming Mingfen. The protective layer opening 43 under the electronic component, that is, the protective layer opening 431 located between a pair of soldering #42 is a distance from the first = wall of the soldering wire, and under the condition of a registration error of 75 micrometers, Can be equal to 75 U meters (other than 5G micron under the condition of 5 〇 micro-division), so that even if the opening 431 is biased (such as the meter), the same electronic connection can be provided. Setting surface = two insulating tree contacts for covering electronic components = heart: under the electronic components and the opening In the mouth, avoid the generation of air holes, less package and electrical bridging problems, and at the same time can make the insulating resin to: reduce the side of the _ less side to avoid the occurrence of solder bump _ ~ phenomenon, and even cause short circuit of adjacent electronic components Referring to Figure 5, the electronic carrier of the present invention is not intended. The smack of the hacker, the identification of the electronic carrier board of an embodiment #盘命,+,》
大致相同,主要述弟一實施例 Π主要差異在於該電子載板41上之保講声C W於至少二成對設置之銲塾42間形成有開口彻及 19294 18 1286830 該開口 430及431係彼此同向且外露出該H42 二相同的第一側壁421、第二側壁422、及第三側壁奶, 该==側壁421係垂直該成對鲜塾42佈設之方向,第 :,:2、弟三側壁423係平行該成對銲墊42佈設之方 亥弟一侧壁421間隔該開口 430及431之距離D :大於該第二側壁422、第三側壁423間隔_^ 之距離d約5G微米。其中該距離㈣大於或等於以 離D係大於或等於125微米;另夕卜,如對位誤差 :力係為50微米時’則該距離“系可大於或等於%微米, 孩距離D則係大於或等於1〇〇微米。 “ 如此,即便開口 430及431發生偏位 =^如前述第—實施例中所述,仍可提供電子^;;目 〒接置面積(潤濕面積),且可供包覆電子元件之絕缘 t平、均粒# 5〇微米)充佈該電子元件下方及該開口中, =氣洞產生所導致之氣爆以及電性橋接問題,同時復可 、巴相^至少包覆該銲墊二側邊,以避免發生鮮錫突伸 (esolder extrusion)現m導致相鄰電子元件短路之問The openings are mainly the same, and the main difference is that the acoustic sound CW on the electronic carrier 41 is formed with at least two pairs of soldering holes 42 provided with openings 19294 18 1286830. The openings 430 and 431 are in the same direction. And exposing the first side wall 421, the second side wall 422, and the third side wall of the same H42, the == side wall 421 is perpendicular to the direction in which the pair of fresh shovel 42 is disposed, the first::: 2, the third side wall 423 is parallel to the pair of pads 42. The side wall 421 of the square is spaced apart from the opening 430 and 431 by a distance D: greater than the distance d between the second side wall 422 and the third side wall 423 by about 5G micrometers. Wherein the distance (4) is greater than or equal to greater than or equal to 125 microns from the D system; in addition, if the alignment error is 50 microns, the distance may be greater than or equal to % micrometer, and the distance D is Greater than or equal to 1 〇〇 micron. " Thus, even if the openings 430 and 431 are offset = ^ as described in the foregoing - the embodiment, the electrons can be provided; the contact area (wet area), and Insulation t-flat, uniform particle #5〇micron for covering electronic components is filled under the electronic component and in the opening, = gas explosion caused by gas hole and electrical bridging problem, and re-energy, phase ^ at least covering the sides of the pad to avoid the occurrence of esolder extrusion, which causes short circuit of adjacent electronic components.
題0 J 同時,當後續於該成對銲墊上接置電子元件時,哼 ^於電子尤件下方之保護層開口 43卜亦即未位於二成對 &塾42㈤之保護層開口 431距離其銲墊第一侧壁伯之距 Λ»在對位5吳差為Μ微米之條件下,復亦可大於或等於 j U米(另在對位誤差為5〇微米之條件下可大於或等於% 微米),如此,即便開口 430,431發生偏位,仍可提供電子 19 19294 1286830 元件相同銲墊接置面積(潤濕面積),且可供包覆電子元件 之絕緣樹脂(平均粒徑50微米)充佈該電子元件下方及該開 口中,避免氣洞產生所導致之氣爆以及電性橋接問題,同 日守復可使纟巴緣樹脂至少包覆該銲墊二側邊,以避免發生鮮 錫突伸(solder extrusion)現象,甚而導致相鄰電子元件短路 之問題。 座實施例 請參閱第6A圖,係為本發明之電子載板第三實施例 平面示意圖。 本叙明第二貫施例之電子載板係與前述第一實施例 致相同’主要差異在於該電子載板41上之保護層43 對應於至少二成對設置之銲墊42間形成有開口彻及 431 „亥開口 43〇及431係彼此同向且完全顯露出該二鲜塾 I2相同之第一側壁421、第二側壁422、第三側壁423及 =四侧壁424 ’其中該第—、第四侧壁421,424係垂直該 兮Ϊ鲜塾42佈設之方向’第二、第三侧壁422,423係平行 二成對銲塾42佈設之方向,且該第一側壁421㈤隔該開口 1之距離!)至少大於該第二、第三側壁似⑶ :=43。及431之距離_5。微米。其_ =或專於75微米,距離D係大於或等於 , 間隔該開口 430及431之距離係大於或 該距離d係可大^^块差月b力係為50微米時,則 等於_微米。寻於50微米,該距離°則係大於或 19294 20 1286830 —如此’即便該開口 430及431發生偏位,如第犯圖 所不之向右偏移75微米’仍可維持該銲墊Μ之既有外露 士積尺寸以提供電子儿件與原設計相同之潤濕面積,同 日守可供包覆電子元件之絕緣樹脂充佈該電子it件下方及該 J中刀避免氣/同產生所導致之氣爆以及電性橋接問題, 現^使、^、彖树全包覆該銲塾側邊,避免發生銲錫突伸 田设、、、員於该成對銲墊上接置電子元件時,該 | =子元件下方之保護層開口 431,亦即未位 護層開口 431距離其銲墊第—側壁421之距 另位在 =為75微米之條件下,復亦可大於或等於 =:广(另:對位誤差為5。微米之條件下可 =之=外t便開口 43°,4… 墊42之既有外露面積尺寸,以提供電子元件與 之潤濕面積,同時可供&胃帝 " 子元件下方及,ΡΓ: 絕緣樹脂充佈該電 子件下方及该開口中,避免氣洞產生所導致之氣爆 3橋接問題,亦可使絕緣樹脂完全包覆該銲墊側邊,避 免發生銲錫突伸現象。 于㈣逯,避 農四實差复 請參閱第7Α至7(:圖,係為本 施例平面示意圖。 电于戰板弟四貫 大致::明第四實施例之電子载板係與前述第三實施例 同,主要差異在於用以與該銲墊“ 除可佈設於該鮮塾-左右側邊外,亦可置^ 19294 21 1286830 之上方、下方、上/下方或角 而非以本圖示為限,且非^= ’係配合實際線路安排 為限,亦可對應應用於各實施例中。 出知塾四側壁 另請參閱第8A及8B圖,係A庙田士 * 所形成之構裝結構之平面及剖面=電子载板 子載板4i,該電子載板41係 ;^糸匕括·—電 之雷早韶此 〇.、 為則述各貫施例中所揭霖 二仁非以為限;電子元件44,係接置並電性 二42 ’絕緣樹脂46 ’係包覆該電子元件44,並得充; 於該電子元件44下方及該開口 43〇及431 ^充佈费 該銲墊42側表面。其中該電子载板” ^復 或印刷電路板等,該保護層土 、電路板 ㈣為被動料。 3係為叫層’該電子元件 ㈣子元件44係可透一例如錫膏之導 置於外露出該保護層開口 430及431之銲塾42上,铁= ••了回鲜作業’使該電子元件44藉錫膏銲接至該銲塾42上 _ 並形成電性耦接關係。 如此,即便製程精度及誤差影響而發生保護層開口位 置偏移,而使該保護層開口 430及431上、下、左、右偏 移乃微米時,仍不致造成外露銲墊“之尺寸同日=隨之變 更。此外,本實施例中由於該保護層開口係同時外露出該 鋅墊四側壁,將可於後續作業中使絕緣樹脂46完全包覆住 該銲墊4 2側邊,藉以避免習知將被動元件藉由錫膏而接置 於基板上時’熔融錫膏可能流經該銲墊表面與防輝層間之 19294 22 1286830 間隙’再沿基板與防銲層間之間隙而相互擴散、接觸 而發生銲錫突伸(solder extrusi〇n)現象,甚而導 元件發生短路等問題。 ^破動At the same time, when the electronic component is subsequently attached to the pair of pads, the protective layer opening 43 under the electronic component is not located at the protective layer opening 431 of the second pair & 42 (5). The first side wall of the pad is Λ» under the condition that the difference of 5 is Μ micron, the complex can also be greater than or equal to j U m (other than greater than or equal to the case where the alignment error is 5 〇 micron) % micron), so that even if the openings 430, 431 are offset, the same solder pad contact area (wetting area) of the electronic 19 19294 1286830 component can be provided, and the insulating resin (average particle size 50 μm) for covering the electronic components can be provided. Filling the underside of the electronic component and the opening to avoid the gas explosion and electrical bridging caused by the generation of the gas hole, the same day the Shouba resin can cover at least the side of the soldering pad to avoid the occurrence of fresh tin The phenomenon of solder extrusion, even causing a short circuit between adjacent electronic components. Embodiments Referring to Figure 6A, there is shown a plan view of a third embodiment of an electronic carrier board of the present invention. The electronic carrier of the second embodiment is the same as the first embodiment described above. The main difference is that the protective layer 43 on the electronic carrier 41 has an opening formed corresponding to at least two pairs of pads 42 disposed. And the first side wall 421, the second side wall 422, the third side wall 423, and the fourth side wall 424 of the second side of the bismuth I2 are in the same direction and completely reveal the same. The fourth side wall 421, 424 is perpendicular to the direction in which the fresh shovel 42 is disposed. The second and third side walls 422, 423 are parallel to the direction in which the pair of welding dies 42 are disposed, and the first side wall 421 (5) is separated from the opening 1 The distance!) is at least larger than the second and third side walls like (3):=43. and the distance of 431 is _5.micron. Its _= or is specific to 75 microns, and the distance D is greater than or equal to the opening 430 and 431. The distance is greater than or the distance d is greater than the block. When the force b is 50 microns, it is equal to _micron. Looking for 50 microns, the distance is greater than or 19294 20 1286830 - so 'even the opening 430 and 431 are offset, if the first line is not shifted to the right by 75 microns, the pad can still be maintained. There is an exposed material size to provide the same wetted area as the original design of the electronic device. On the same day, the insulating resin for covering the electronic component is filled under the electronic piece and the knife in the J is avoided. The resulting gas explosion and electrical bridging problems are now covered by the ^, eucalyptus, and eucalyptus to prevent the occurrence of solder bumps, and when the components are connected to the electronic components on the pair of pads. The protective layer opening 431 under the sub-element, that is, the unshielded layer opening 431 is at a distance of 75 micrometers from the pad side wall 421, and may be greater than or equal to =: wide (Another: the alignment error is 5. Micron can be == Outside t is open 43°, 4... The pad 42 has both exposed area dimensions to provide the wetted area of the electronic components, and is available for & Under the stomach and the sub-components, ΡΓ: The insulating resin is filled under the electronic component and in the opening to avoid the problem of gas explosion 3 bridging caused by the generation of the air hole, and the insulating resin can completely cover the side of the soldering pad. To avoid the phenomenon of solder protruding. In (4) 逯, avoid the farmer's four real difference Read the 7th to 7th (: figure, which is a schematic diagram of the embodiment of the present invention. The electric board is roughly the same as the third embodiment. The main difference is that And the solder pad "except for the left and right sides of the fresh enamel - can also be placed above, below, above / below or at the corner of ^ 19294 21 1286830 instead of the illustration, and not ^ ^ ' It can be used in conjunction with the actual circuit arrangement, and can also be applied to each of the embodiments. Please refer to Figures 8A and 8B for the four side walls. The plane and profile of the structure formed by A Temple is as follows: The board carrier board 4i, the electronic carrier board 41; ^ 糸匕 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The electrically insulating 42' insulating resin 46' covers the electronic component 44 and is filled; the side surface of the bonding pad 42 is charged under the electronic component 44 and the openings 43A and 431. Wherein the electronic carrier board or the printed circuit board, the protective layer of soil, the circuit board (4) is a passive material. The 3 series is called a layer 'the electronic component (four) sub-element 44 can be placed through a guide such as solder paste Exposed on the solder bumps 42 of the protective layer openings 430 and 431, the iron=••refraction operation 'solds the electronic component 44 to the solder bumps 42 by solder paste_ and forms an electrical coupling relationship. Even if the protection layer opening position shift occurs due to the process precision and the error, and the protective layer openings 430 and 431 are shifted up, down, left, and right by a micrometer, the exposed solder pads are not caused to have the same size. change. In addition, in this embodiment, since the opening of the protective layer simultaneously exposes the four sidewalls of the zinc pad, the insulating resin 46 can be completely covered on the side of the bonding pad 4 2 in the subsequent operation, so as to avoid the passive component. When soldered onto the substrate by solder paste, 'the molten solder paste may flow through the gap between the surface of the pad and the anti-friction layer 19294 22 1286830' and then spread and contact each other along the gap between the substrate and the solder resist layer to cause solder bumps. The problem of stretching (extander extrusi〇n), even the short-circuit of the guiding element. ^ Broken
弟五實施你I 4閱第9圖’係為本發明之電子載板 面示意圖。 戶、地例十 i如圖所示’本發明之電子載板41係包括:一主體411· 至少,成對設於該主體411表面之銲墊42,且該鲜塾Ο, 尺寸係相同;以及-用以覆蓋該主體411表面之保護層 43 ’該保護層43對應於該銲塾42位置形成有開口^及 431 ’ 5亥開口 430及431係彼此同向且外露出該二銲墊42 相同^第-側壁421,該第一側壁421係垂直該 42佈設之方向。 主The fifth implementation of your I 4 reading Figure 9 is a schematic diagram of the electronic carrier board of the present invention. The electronic carrier board 41 of the present invention includes: a main body 411 · at least, a pair of pads 42 disposed on the surface of the main body 411, and the fresh sputum has the same size; And a protective layer 43 </ RTI> covering the surface of the main body 411. The protective layer 43 is formed with openings 431 and 431 at positions corresponding to the solder dies 42. The HAI and the 431 are adjacent to each other and expose the two pads 42. The same first sidewall 421 is perpendicular to the direction in which the 42 is disposed. the Lord
該銲墊第一側壁421距離該開口 430及431之距離D '大於或等於125微米;如對位誤差能力係為%微米時, 則該距離D則係大於或等於100微米。 士此在形成保護層(防銲層)開口 430及43 1時, 因衣私精度及块差考量下,由於該開口伽及係同向 設於該二成對銲墊42處,因此即便其發生偏位,仍得避免 成對銲塾42外露出開口 43〇及431之面積不同,而使後續 於该銲墊42上接著電子元件時,因濕潤面積之不平衡造成 立碑現象。 匕卜如°亥開口向左偏位75微米時,使該銲墊第一 側壁421距離該開口 43〇之距離D變更為5〇微米(或以 23 19294 1286830 Ϊ;二可二覆 粒徑5。微幻 致之氣爆以及電性橋=:43°中’―產生所導 設於後續於該成對銲塾上接置電子元件時,該未 轨电^下方之保護層開口 431,亦即未位於二成對 ^ ^2間之保護層開口 431距離其鲜塾第一側壁切之距 7對位誤差為75微米之條件下,復亦可大於或等於 =她誤差為5。微米之條件下⑽ 如此’即便開口㈣,431發生偏位,仍得避免成對 :42外露出開口 43〇,431之面積不同,而使後續於該銲 上接者電子元件時,因濕潤面積之不平衡造成立碑現 象0 多六實施例 請參閲第10圖,係為本發明之電子載板第六實施例 平面示意圖。 • 本發明第六實施例之電子載板係與前述第一實施例 大致相同,仍係使保護層開口 430及431彼此同向,且外 露出銲塾42相同之二侧壁,惟主要差異在於該保護層開口 430及431係外露出銲塾42之第一側壁421及第四側壁 424,該第一側壁421及第四側壁424係垂直該成對銲墊 42佈設之方向,且該第一側壁421間隔該開口 43〇及々η 之距離D至少大於該第四側壁424間隔該開口 43〇及431 之距離d約50彳政米。其中該距離d係大於或等於乃微米, 距離D係大於或等於125微米;另外’如對位誤差能力係 19294 24 1286830 為50微料,職距㈣係可切 離D則係大於或等於⑽㈣。飞4方、心未,该距 = 偏位(不論向左 =寸以=):仍可维持該銲塾42之既有外露面 可I件與原設計相同之潤濕面積,同時 口中避:=ΓΤ_該電子元件下方爛 二士所¥致之氣爆以及電性橋接問題。 ’自後續於該成對料上接置電子元件時,該未 汉於電子元件下方之俘嗜层 τ /禾 r埶心 開431,亦即未位於二成對 、干藝2間之保護層開口 43 1距離1 75矜半十之#、件下,復亦可大於或等於 州“差為50微米之條件下可大於或等於50 ^),如此,即便開口 43〇,431發生偏位,仍可維持該銲 墊42之既有外露面積尺寸, 恭 、’ 之潤濕面積,同時=子元件與原設計相同 工一 μ 匕復電子疋件之絕緣樹脂充佈該電 電該開…避免氣洞產生所導致之氣爆以及 農七實施例 請參閱第11圖,係為本發 平面示意圖。 3本u之電子載板弟七實施例 一本發明第七實施例中係可同時結合前述第三及第六 貫施例中保護層開σ相對銲墊之排列設計。 如圖所示,該電子載板41上二成對銲墊42之平面尺 寸係可彼此不同,且該保護層開口 430及431係彼此同向’ 25 19294 1286830 其中該開口 430係全面外露出銲墊42之第一側壁c卜 二側壁422、第三側壁423及第四側壁424,相對該開口 431係外露出鮮墊42之第一側壁及第四側壁。1中— 侧壁4 21間隔該開口 4 3 〇及4 3丨之距離D至少^於^ 側土 422第一側壁423及第四側壁424間隔該開口咖 及431之距㈣約50微米。其中該距離d係大於或等於 75微米:距離D係大於或等於125微米;另夕卜,如對位誤 差能力係為5G微米時,則該距離d係可大於或等於、 米,該距離〇則係大於或等於100微米。 、^ 如此’即便該開口 430及431發生偏位(不論向左、向 向下偏位)’仍可維持該銲墊42之既有外露面 提供電子疋件與原設計相同之潤濕面積,同時 可 < 匕復料元件之絕緣樹脂充佈該電子元件下方及該開 免氣洞產生所導致之氣爆以及電性橋接問題。 同時’當後續☆該成對銲整上接置電子元件 ::電子元件下方之保護層開口-1,亦即未位於二成;Γ ^塾42間之保護層開口州距離其銲墊第-㈣421之距 Μ在對位誤差為75微米之條件下,復亦可大於或等於 微另在對位誤差為5G微米之條件下可大於或等於50 塾^ ) ’如此’即便開口 430,43 i發生偏位,仍可維持該銲 之潤^Λ有外Λ面積尺寸’以提供電子元件與原設計相同 子一:#貝’同時可供包覆電子元件之絕緣樹脂充佈該電 ‘橋開μ ’避免氣调產生所導致之氣爆以及 19294 26 1286830 因此,本發明之電子載板中,係使覆蓋於電 面之保護層,太1 丁執攸表 至^、二成對配置之銲墊處形成有同向之鬥 口’藉以外霞Ψ含倉一 汗 ( 。〜—銲整同向側壁,如此,在形成保護; 防銲層)開口設置時,因製程精度及誤差考量下,由於該“ 、係同向叹於該成對銲墊處,因此即便其發生偏位,而得 ,免外路出開口之銲墊面積不同,而使後續於該銲墊上接 ^ —件日守,因濕潤面積(wetting area)之不平衡所造成 之立碑現象。The distance D' of the first sidewall 421 of the pad from the openings 430 and 431 is greater than or equal to 125 micrometers; if the alignment error capability is % micrometer, the distance D is greater than or equal to 100 micrometers. Therefore, when the protective layer (solderproof layer) openings 430 and 43 1 are formed, the opening galax is disposed at the second pair of pads 42 due to the accuracy of the clothing and the block difference, so even if In the event of a misalignment, it is still necessary to avoid the difference in the area of the exposed openings 43A and 431 of the pair of pads 42, so that when the electronic components are subsequently attached to the pads 42, the phenomenon of the wet area is established. When the opening of the opening is 75 micrometers to the left, the distance D of the first side wall 421 of the bonding pad from the opening 43 is changed to 5 〇 micrometers (or 23 19294 1286830 Ϊ; The micro-magic gas burst and the electrical bridge =: 43 ° in the '--the guide is set to be connected to the pair of soldering irons on the electronic components, the protective layer opening 431 under the untracked electric That is, under the condition that the protective layer opening 431 which is not located between the two pairs of ^^2 is 7 micrometers away from the first side wall of the fresh sputum, the error may be greater than or equal to = her error is 5. Micron Under the condition (10), even if the opening (four), 431 is misaligned, it is still necessary to avoid pairing: 42 is exposed outside the opening 43〇, the area of 431 is different, and the subsequent wetted area is not included in the soldering of the electronic component. Balanced creation of the phenomenon of the monument 0 more than six embodiments, see Fig. 10, is a plan view of the sixth embodiment of the electronic carrier of the present invention. The electronic carrier of the sixth embodiment of the present invention and the foregoing first embodiment Roughly the same, the protective layer openings 430 and 431 are still in the same direction, and the soldering holes 42 are exposed. The first side wall 421 and the fourth side wall 424 of the soldering ring 42 are exposed outside the protective layer openings 430 and 431. The first side wall 421 and the fourth side wall 424 are perpendicular to the paired soldering. The distance between the first side wall 421 and the opening 43 is at least greater than the distance d between the fourth side wall 424 and the opening 43 and 431. The distance d is The system is greater than or equal to micrometers, and the distance D is greater than or equal to 125 micrometers; in addition, if the alignment error capability is 19294 24 1286830 is 50 micrometers, the service distance (four) can be cut off from D to be greater than or equal to (10) (four). , the heart is not, the distance = the deviation (regardless of the left = inch to =): can still maintain the exposed surface of the weld 42 can be the same wetted area as the original design, while avoiding the mouth: = ΓΤ _ Under the electronic component, there is a gas explosion and electrical bridging problem caused by the rotten two-story. 'From the subsequent attachment of the electronic component to the pair of materials, the trapping layer τ /her埶 below the electronic component The heart opens 431, that is, the protective layer opening 43 that is not located in the second pair and the dry art 2 is 1 75 距离Under the ##, under the piece, the complex can also be greater than or equal to the state "may be greater than or equal to 50 ^ under the condition of 50 micron difference", so that even if the opening 43〇, 431 is offset, the pad 42 can be maintained. Both the exposed area size, Kong, 'wet area, and the sub-components are the same as the original design. The insulating resin of the μ 疋 疋 疋 充 充 该 该 该 该 ... 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免For the seventh embodiment of the present invention, reference is made to the first embodiment of the present invention. The protection layer is opened to the arrangement of the pads. As shown, the planar dimensions of the two pairs of pads 42 on the electronic carrier 41 can be different from each other, and the protective layer openings 430 and 431 are in the same direction as each other '25 19294 1286830, wherein the opening 430 is fully exposed. The first sidewall c of the pad 42 includes a sidewall 422, a third sidewall 423, and a fourth sidewall 424. The first sidewall and the fourth sidewall of the fresh pad 42 are exposed outside the opening 431. 1 - the side wall 4 21 is spaced apart from the opening 4 3 〇 and 4 3 距离 the distance D is at least ^ side soil 422 the first side wall 423 and the fourth side wall 424 are spaced apart from the opening 431 and the distance 431 is about 50 microns. Wherein the distance d is greater than or equal to 75 microns: the distance D is greater than or equal to 125 microns; and, if the alignment error capability is 5G microns, the distance d can be greater than or equal to, the distance 〇 It is greater than or equal to 100 microns. ^, even if the openings 430 and 431 are offset (regardless of the leftward or downward bias), the exposed surface of the pad 42 can be maintained to provide the same wetted area as the original design of the electronic component. At the same time, the insulating resin of the 匕 匕 composite element can be filled with the air blast and the electrical bridging problem caused by the underside of the electronic component and the opening of the air-free hole. At the same time 'When the follow-up ☆ the paired soldering is connected to the electronic components:: the protective layer opening-1 below the electronic component, that is, not located in the second; Γ ^ 塾 42 protective layer open state distance from its solder pad - (4) The distance of 421 is ≤ Μ, 430, 43 i In the event of a misalignment, the weld can be maintained to have a size of the outer casing area to provide the same electronic component as the original design: #贝' at the same time, the insulating resin for covering the electronic component is filled with the electric bridge. μ 'avoiding the gas explosion caused by the generation of the atmosphere and 19294 26 1286830 Therefore, in the electronic carrier of the present invention, the protective layer covering the electric surface is welded to the second and second pairs. The pad is formed with the same direction of the mouth" by the outside of the Xia Ψ containing a sweat (. ~ - welding the same side wall, so, in the formation of protection; solder mask) opening settings, due to process accuracy and error considerations, Because the ", the same direction sighs at the pair of pads, even if it is biased , Derived from different pad area, the outer free path of an opening, so that the subsequent connection to the bonding pad ^ - keep member days, due to the phenomenon of tombstoning wetted area (wetting area) of the imbalance caused.
同日守,該保護層開口係可外露出垂直該成對銲墊佈設 之方向之莖一 /日丨丨处 σ 恭-土,以供包覆電子元件之絕緣樹脂充佈該 子元件下方及该開口中,避免氣洞產生所導致之氣爆以 電14橋接問題。另該保護層開口係可外露出該二鋅塾之 至少二相同的第—及第二侧壁,亦或外露出該二銲墊至少 三相同的笫一、结_ + 二、 弟—、弟三側壁,該銲墊第一側壁係垂直 =成,塾佈設之方向,第二(第三)側壁係平行該成對鮮 上f。又之方向,且該第一側壁間隔該開口之距離至少大於 W亥第二(第二)側壁間隔該開口之距離5〇微米。如此,即便 ^ 口偏位,不僅仍可維持相同的銲墊外露面積,更可 供包覆電子元件之絕緣樹脂(平均粒徑50微米)充佈該電子 一下方及"亥開口中,避免氣洞產生所導致之氣爆以及電 Τ接問4,同時復可使絕緣樹脂至少包覆該銲墊至少一 ^ ^以避免發生銲錫突伸(solder extrusion)現象,甚而導 致相鄰電子元件短路之問題。 此外,該保護層開口復可彼此同向且完全顯露出該二 19294 27 1286830 :墊相同之第…第二、第三及第四側壁,其中該第一、 弟四側壁係垂直該成對銲塾佈設之方向,第二、第辟 Ϊ =該成對銲塾佈設之方向,且該第—側壁間隔該開: 仙、,肖至少大於該第二、第三側壁間隔該開口之距離50 /Μ 如此,即便該開口發生偏位,仍可維持該銲塾既有 =夕士卜露面積,以提供電子元件與原設計相同之潤濕面積, 5 =更可供包覆電子元件之絕緣樹脂充佈該電子元件下方 7開π中,避免氣洞產生所導致之氣爆以及電性橋接問 通’復亦可使絕緣樹脂完全包覆該銲墊侧邊,避免發生銲 錫突伸現象。 Χ 另外,本發明中該保護層開口係可僅外露出銲墊之第 -側m側壁係垂直該成對銲墊佈設之方向,如此, 在形成保護層開口時,因製程精度及誤差考量下,由於該 開二係同向設於該二成對銲墊處,因此即便其發生偏位, 仍侍避免成對銲墊外露出開口之面積不同,而使後續於嗜 録墊上接著電子元件時,因㈣面積之不平衡造成立碑現 —再者,本發明中該保護層開口係可外露出銲墊之第一 及第四側i ’ 5亥第—及第四側壁係垂直該成對銲塾佈設之 ° X第側壁間隔該開口之距離至少大於該第四側 土門Ik «亥開口之距離約5〇微米。如此,即便該開口發生偏 位,仍可維持該銲塾之既有外露面積尺寸,以提供電子元 件與原叹4相同之潤濕面積,同時可供包覆電子元件之絕 緣樹脂充佈該電子元件下方及耗口巾,避減洞產生所 28 19294 1286830 導致之氣爆以及電性橋接問題。 =時’本發明中該保護層開口之其中一者係全面外露 出-中-銲墊之第一、第二、第三及第四侧壁,相對另一 開口係外露出另一銲塾之第一及第四側壁,且該第一側壁 間隔該開口之距離至少大 嚷外 穴於5亥弟一、弟二及弟四側壁間隔 Μ 口之距離約%微米。如此,即便該開 ,該鲜塾之既有外露面積尺寸,以提供電子元扁件與: _ Γί相同之潤濕面積’同時可供包覆電子元件之絕緣樹脂 ’ 5佈该電子元件下方及該開口中,避免氣洞產生所導致之 氣爆以及電性橋接問題。 ▲上述之實施例僅為例示性說明本發明之原理及其功 效i而非用於限制本發明。任何熟習此技藝之人士均可在 不延背本發明之精神及範脅下,對上述實施例進行修飾盘 變化。因此,本發明之權利保護範圍,應如後述之申請專 利範圍所列。 _ 【圖式簡單說明】 第1A係為習知於基板上接置表面黏著式被動元件之 平面示意圖; 第1B及1C圖係為對應該第丨八圖中之剖面線 及剖=線1CMC所形成之剖面示意圖; 第2A及2B圖係美岡直糾綠 秀囷專利弟6,521,997號所揭示之被 動元件組裝示意圖; 第3 A及3B圖係美國專利2005/025323 i號所揭示之 被動元件組裝示意圖; 19294 29 1286830 第4A及4B圖係為本發明之電子載板第一實施例之平 面示意圖; 第4C圖係為本發明第一實施例之電子載板中保護層 開口向左偏移之平面示意圖; ' 第4D圖係為本發明第一實施例之電子載板中保護層 ; 開口尺寸不同之平面示意圖; • 第5圖係為本發明之電子載板第二實施例之平面示竟 圖; • f 6A圖係為本發明之電子載板第三實施例平面.示意 昂6B圖係為本發明第三實施例之電子載板中保護層 開口向右偏移之平面示意圖; 曰 弟7A至7C圖係為本發明之電子載板第 不意圖; N 丁囬 第8A及8B圖係為應用本發明 裳結構平面及剖面示意圖;之包子載板所形成之構 圖; .第9圖係為本發明之電子載板第五實施例平面示意 六實施例平面示意 第10圖係為本發明之電子載板第 圖;以及 圖 第11圖係為本發明之電子载板第七實施例平面示意 主要元件符號說明 基板 19294 30 11 1286830 12 銲墊 13 防銲層 14 被動元件 15 錫膏 17 間隙 ' 22 銲墊 ' 23 防銲層 ^ 230 溝槽 32 銲墊 * 330 開口 331 阻隔條 3300 流道 41 電子載板 411 主體 42 鲜塾 421 第一側壁 422 第二側壁 -•423 第三側壁 • 424 第四側壁 43 保護層 430 開口 44 電子元件 45 導電材料 46 絕緣樹脂 420 導電線路 M,Al,A2,D,d,A,B,X 距離 31 19294On the same day, the opening of the protective layer may expose the stem 1/day of the pair of solder pads in the direction of the pair of pads, and the insulating resin for covering the electronic components is filled under the sub-element and In the opening, avoid the gas explosion caused by the generation of the air hole to bridge the electricity problem. In addition, the opening of the protective layer may expose at least two identical first and second sidewalls of the two zinc bismuth, or expose at least three identical bismuth, knot _ + two, brother-, brother The three side walls, the first side wall of the solder pad is perpendicular to the direction in which the crucible is laid, and the second (third) side wall is parallel to the pair of fresh f. In a further direction, the first sidewall is spaced apart from the opening by a distance greater than at least 5 μm from the second (second) sidewall of the wall. In this way, even if the interface is biased, not only can the same exposed area of the pad be maintained, but also the insulating resin (average particle size of 50 μm) covering the electronic component can be filled under the electron and under the opening. The gas explosion caused by the generation of the gas hole and the electrical contact 4 can simultaneously make the insulating resin at least cover the solder pad to avoid solder extrusion, and even cause short circuit of adjacent electronic components. The problem. In addition, the protective layer openings may be in the same direction and completely reveal the second 19294 27 1286830: the same ... second, third and fourth side walls of the pad, wherein the first and fourth side walls are perpendicular to the paired welding The direction of the 塾 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,如此 In this way, even if the opening is misaligned, the weld bead can be maintained to have the same area as the original design, and the insulation area of the electronic component is the same as that of the original design. Filling the bottom of the electronic component with 7 π to avoid the gas explosion caused by the generation of the gas hole and the electrical bridging can also make the insulating resin completely cover the side of the soldering pad to avoid the phenomenon of solder protrusion. In addition, in the present invention, the opening of the protective layer may expose only the first side m sidewall of the solder pad to be perpendicular to the direction in which the pair of pads are disposed, so that when the protective layer opening is formed, due to process precision and error considerations Since the two openings are disposed in the same pair of pads, even if the offset occurs, the area of the exposed opening of the pair of pads is prevented from being different, so that the electronic components are subsequently attached to the recording pad. In addition, in the present invention, the opening of the protective layer may expose the first and fourth sides of the bonding pad i '5 hai - and the fourth sidewall is perpendicular to the pair The distance between the X sidewalls and the opening is at least greater than the distance of the fourth side soil gate Ik «Hai opening is about 5 〇 micrometers. Thus, even if the opening is misaligned, the exposed area of the solder fillet can be maintained to provide the same wetted area of the electronic component as the original sigh 4, and the insulating resin for covering the electronic component is filled with the electron. Underneath the components and the slings, avoiding the hole explosion and the electrical bridging caused by 28 19294 1286830. In the present invention, one of the openings of the protective layer is fully exposed - the first, second, third and fourth side walls of the middle-pad are exposed to the other opening The first and fourth side walls, and the first side wall is spaced apart from the opening by at least a distance of about 10 micrometers at a distance between the outer hole and the outer wall of the fifth side. Thus, even if it is opened, the fresh enamel has both exposed area dimensions to provide an electronic element flat piece with the same wetted area as: _ Γ 同时 可供 同时 同时 同时 同时 包覆 包覆 包覆 包覆 包覆 包覆 包覆 包覆 ' 5 5 In this opening, the gas explosion caused by the generation of the air hole and the electrical bridging problem are avoided. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Any person skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the application patents described below. _ [Simple diagram of the diagram] The 1A series is a schematic plan view of the surface-attached passive component on the substrate; the 1B and 1C diagrams correspond to the section line and section 1 line CMC in Figure 8 FIG. 2A and 2B are diagrams showing the assembly of passive components disclosed in US Pat. No. 6,521,997; and Figures 3A and 3B are passive as disclosed in US Patent No. 2005/025323 i. 19294 29 1286830 4A and 4B are schematic plan views of the first embodiment of the electronic carrier of the present invention; FIG. 4C is a leftward bias of the protective layer opening in the electronic carrier of the first embodiment of the present invention; FIG. 4D is a plan view showing a protective layer in an electronic carrier according to a first embodiment of the present invention; a plan view showing a different opening size; and FIG. 5 is a plan view showing a second embodiment of the electronic carrier of the present invention. FIG. 6 is a plan view of the third embodiment of the electronic carrier of the present invention. FIG. 6B is a plan view showing the opening of the protective layer in the electronic carrier of the third embodiment of the present invention shifted to the right; The brothers 7A to 7C are The electronic carrier board of the invention is not intended; the N 8th and 8B drawings are the plane and cross-sectional view of the skirt structure of the present invention; the pattern formed by the buns carrier board; Fig. 9 is the electronic carrier board of the present invention. 5th Embodiment FIG. 10 is a plan view of an electronic carrier board according to the present invention; and FIG. 11 is a seventh embodiment of an electronic carrier board according to the present invention. 30 11 1286830 12 Pad 13 Solder Mask 14 Passive Element 15 Solder Paste 17 Gap ' 22 Pad ' 23 Solder Mask ^ 230 Groove 32 Pad * 330 Opening 331 Bar 3300 Runner 41 Electronic Carrier 411 Body 42 Fresh 421 first side wall 422 second side wall -• 423 third side wall 424 fourth side wall 43 protective layer 430 opening 44 electronic component 45 conductive material 46 insulating resin 420 conductive line M, Al, A2, D, d, A, B, X distance 31 19294
Claims (1)
Priority Applications (3)
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TW095101563A TWI286830B (en) | 2006-01-16 | 2006-01-16 | Electronic carrier board |
US11/654,273 US7573722B2 (en) | 2006-01-16 | 2007-01-16 | Electronic carrier board applicable to surface mounted technology (SMT) |
US12/535,397 US7889511B2 (en) | 2006-01-16 | 2009-08-04 | Electronic carrier board applicable to surface mount technology |
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TW095101563A TWI286830B (en) | 2006-01-16 | 2006-01-16 | Electronic carrier board |
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2006
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-
2007
- 2007-01-16 US US11/654,273 patent/US7573722B2/en active Active
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US7889511B2 (en) | 2011-02-15 |
TW200729430A (en) | 2007-08-01 |
US7573722B2 (en) | 2009-08-11 |
US20070164084A1 (en) | 2007-07-19 |
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