CN103094232A - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
- Publication number
- CN103094232A CN103094232A CN2012100342705A CN201210034270A CN103094232A CN 103094232 A CN103094232 A CN 103094232A CN 2012100342705 A CN2012100342705 A CN 2012100342705A CN 201210034270 A CN201210034270 A CN 201210034270A CN 103094232 A CN103094232 A CN 103094232A
- Authority
- CN
- China
- Prior art keywords
- chip
- projection
- packaging structure
- insulating thin
- thin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 41
- 239000011241 protective layer Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 28
- 239000000084 colloidal system Substances 0.000 claims abstract description 17
- 238000009413 insulation Methods 0.000 claims description 26
- 238000012856 packing Methods 0.000 claims description 16
- 239000004642 Polyimide Substances 0.000 claims description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 230000004907 flux Effects 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 abstract description 23
- 230000005012 migration Effects 0.000 abstract description 15
- 238000013508 migration Methods 0.000 abstract description 15
- 239000000758 substrate Substances 0.000 abstract 2
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 230000008878 coupling Effects 0.000 description 9
- 238000010168 coupling process Methods 0.000 description 9
- 238000005859 coupling reaction Methods 0.000 description 9
- 229910021645 metal ion Inorganic materials 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 238000004804 winding Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000037427 ion transport Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000032258 transport Effects 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000002322 conducting polymer Substances 0.000 description 2
- 229920001940 conductive polymer Polymers 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 230000001376 precipitating effect Effects 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The invention discloses a chip packaging structure which comprises a chip, a protective layer, a plurality of bumps, an insulating film layer, a flexible substrate and a packaging colloid. The flexible substrate is provided with a plurality of pins which are electrically connected with the plurality of bumps correspondingly, the protective layer and the plurality of bumps are formed on the chip, the insulating film layer is formed on the protective layer, and the insulating film layer between every two adjacent bumps is provided with at least one groove, so that the problem of electrical short circuit or leakage current caused by the migration phenomenon of ions separated out from the bumps can be reduced.
Description
Technical field
The present invention is about a kind of chip-packaging structure; A kind of made chip-packaging structure of the automatic bond package technology of winding that utilizes particularly.
Background technology
Along with scientific and technological progress, semiconductor element (for example chip) has become one of spare part indispensable in many electronic products.After semiconductor element completes, usually need further carry out packaging operation, being electrically connected with other outer members, and protect simultaneously the circuit of semiconductor element.Wherein, winding automatically engages (Tape Automatic Bonding, TAB) encapsulation technology and have the characteristics such as bent, frivolous, fine pitch (fine pitch) and high pin number after encapsulation, is specially adapted to the driving chip package of display.Wherein, the automatic bond package of winding is divided into again membrane of flip chip (Chip On Film, COF) encapsulation and winding carrying encapsulation (Tape Carrier Package, TCP).Yet, in response to electronic product microminiaturization, high processing rate, the demand such as multi-functional, high-effect, chip must also need increase import and export (I/O) end points density in minification, this makes the import and export end points spacing microminiaturization that more becomes, high voltage puts on the metallic conduction end points when semiconductor device operates, add high temperature and wet gas environments, make the metallic conduction end points produce metal ion transport (ion migration) phenomenon, cause the situations such as bridge joint, electrical short circuit or leakage current between the conduction end points of fine pitch.
The existing made chip-packaging structure 1 of the automatic bond package technology of winding that utilizes; as shown in Figure 1; have a chip 11, a protective layer (passivation layer) 12, a plurality of metal coupling 13 and flexible base plate 14; protective layer 12 and described a plurality of metal coupling 13 are arranged on chip 11; respectively corresponding each metal coupling 13 of a plurality of pins 141 of flexible base plate 14; and be electrically connected with each metal coupling 13, make chip 11 to be electrically connected by flexible base plate 14 and other outer members.
from the above, when reality is used, chip 11 can see through described a plurality of metal couplings 13 with flexible base plate 14 and pin 141 electrically conducts, apply under high voltage and a large amount of electric current pass through, produce a large amount of heat energy, make metal coupling 13 precipitating metal ions 131, adding moisture encourages, metal ion 131 transport phenomenas may occur, and common can dissociating along the surface of protective layer 12 of metal ion 131 migrates to adjacent other metal couplings 13 (being depicted as the migration path of metal ion 131 as Fig. 1 dotted arrow), make 13 of each metal couplings cause the problems such as electrical short circuit or leakage current because of bridge joint conducting improperly, especially in the design of fine pitch, this problem is more serious, and the electronic product of using existing chip-packaging structure 1 is also incited somebody to action the therefore situations such as generating function mistake or damage.
In view of this, a kind of chip-packaging structure is provided, and the ion that can reduce the metal coupling generation migrates to the probability of adjacent metal projection, and reduces electrical short circuit or leakage phenomenon generation, so that the quality of electronic product promotes to some extent, it is an industry problem demanding prompt solution for this reason.
Summary of the invention
A purpose of the present invention is to provide a kind of chip-packaging structure, and the ion that must reduce the projection generation on chip migrates to the probability of adjacent projections, to avoid chip-packaging structure, the problems such as electrical short circuit or leakage current occurs when reality is used.
For reaching above-mentioned purpose, the present invention discloses a kind of chip-packaging structure, comprises a chip, a protective layer, a plurality of projection, an insulating thin layer, a flexible base plate and a packing colloid.wherein, described chip has an active surface and a plurality of weld pad is arranged on described active surface, described protective layer is formed on described active surface, and described protective layer part appears each described weld pad, described a plurality of projection is formed at respectively on each described weld pad, and be electrically connected with described weld pad, described insulating thin layer is formed on described protective layer, described insulating thin layer appears described a plurality of projection, and the described insulating thin layer between the described projection of adjacent each is formed with at least one groove, described flexible base plate has a plurality of pins, described chip engages with described flexible base plate, make described a plurality of pin and the corresponding electric connection of described a plurality of projections, described packing colloid is filled in described chip and described flexible base plate formed space.
For reaching above-mentioned purpose, the present invention discloses another kind of chip-packaging structure, comprises a chip, a protective layer, a plurality of projection, a plurality of insulation projection, a flexible base plate and a packing colloid.wherein, described chip has an active surface and a plurality of weld pad is arranged on described active surface, described protective layer is formed on described active surface, described protective layer part appears each described weld pad, described a plurality of projection is formed at respectively on each described weld pad, and be electrically connected with described weld pad, described a plurality of insulation protrusion-shaped is formed on described protective layer, and has at least one described insulation projection between the described projection of adjacent each, described flexible base plate, have a plurality of pins, described chip engages with described flexible base plate, make described a plurality of pin and the corresponding electric connection of described a plurality of projections, described packing colloid is filled in described chip and described flexible base plate formed space.
In sum, be formed between each adjacent described projection by at least one groove or at least one insulation protrusion-shaped, when chip and flexible base plate electrically conduct and make projection because of voltage, overheated and moisture precipitating metal ion, can increase the metal ion transport path, and then reduce metal ion transport to adjacent projections, avoid touching mutually because of the metal ion between each projection phenomenons such as causing electrical short circuit or leakage current.
Description of drawings
Fig. 1 is the generalized section of the chip-packaging structure of prior art;
Fig. 2 A is the generalized section of the chip-packaging structure of first embodiment of the invention;
Fig. 2 B is the local schematic top plan view of chip of the chip-packaging structure of first embodiment of the invention;
Fig. 3 is the local schematic top plan view of chip of the chip-packaging structure of other embodiments of the invention;
Fig. 4 A is the generalized section of the chip-packaging structure of second embodiment of the invention;
Fig. 4 B is the local schematic top plan view of chip of the chip-packaging structure of second embodiment of the invention; And
Fig. 4 C is the generalized section of the chip-packaging structure of other embodiments of the invention.
Embodiment
The chip-packaging structure 2 of first embodiment of the invention is as shown in Fig. 2 A and Fig. 2 B, and Fig. 2 A is the generalized section of chip-packaging structure 2, and Fig. 2 B is the local schematic top plan view of the chip 21 of chip-packaging structure 2.Chip-packaging structure 2 comprises a chip 21, a plurality of projection 22, a protective layer 23, an insulating thin layer 24, a flexible base plate 25 and a packing colloid 26.
From the above, wherein, chip 21 has an active surface 211 and a plurality of weld pad 212, and described a plurality of weld pads 212 are arranged on active surface 211, and 23 of protective layers are formed on active surface 211 and the part appears each weld pad 212.Described a plurality of projection 22 is formed at respectively on each weld pad 212 and with weld pad 212 and is electrically connected, and described a plurality of projections 22 are spaced along at least two relative sides 213,214 of chip 21, and in the present embodiment, projection 22 covers on the protective layer 23 of part.Insulating thin layer 24 is formed on protective layer 23 and appears described a plurality of projection 22, and the insulating thin layer 24 that adjacent each projection is 22 has at least one groove 242.Flexible base plate 25 has a plurality of pins 251, and chip 21 engages with flexible base plate 25, makes described a plurality of pin 251 and the corresponding electric connection of described a plurality of projections 22, and 26 of packing colloids are filled in chip 21 and flexible base plate 25 formed space.
when chip 21 and flexible base plate 25 electrically conduct and make projection 22 produce that ions 221 are separated out and during transport phenomena, illustrate the migration path of ion 221 as the dotted arrow of Fig. 2 A, insulating thin layer 24 by 22 of two adjacent each projections forms at least one groove 242, make ion 221 migration paths increase, can reduce the probability that ion 221 migrates to adjacent projection 22, even in the process of migration, ion 221 can be restricted in groove 242, and avoid 22 of adjacent each projections to produce bridge joint because of ion 221 migrations, the phenomenons such as electrical short circuit or leakage current.Moreover packing colloid 26 also can increase the adhesive force of packing colloid 26 and chip 21 by being filled in groove 242.
Specifically, two relative sides of chip 21 are respectively a first side 213 and a second side 214.Please continue the 2B with reference to figure, show projection 22 and the relative position of groove 242 on chip 21, be the difference of clear difference projection 22 and groove 242, projection 22 is with the square expression of tool decorative pattern.Projection 22 is spaced along first side 213 and the second side 214 of chip 21, each projection 22 has two relative limit walls 222, the vertical first side 213 of limit wall 222 or second side 214, the limit wall 222 formed projected area of mutual projection of two adjacent spaced described a plurality of projections 22 have a plane overlapping area A1 (as shown in Fig. 2 B hatched example areas), and plane overlapping area A1 is blocked in groove 242 extensions, make plane overlapping area A1 be divided into twoth district, respectively the projection 22 of adjacency two adjacent arrangements.Can guarantee that so the ion 221 that each projection 22 is separated out can be through groove 242 (being depicted as the migration path of ion 221 as the dotted arrow of Fig. 2 B) on the path of migration.
In the present embodiment, a thickness T preferably of insulating thin layer 24 is between 5 to 10 microns, and a depth D preferably of at least one groove 242 is between 2 to 5 microns.It should be noted that, chip-packaging structure of the present invention, can be according to the transition state of the ion 221 of the spacing of 22 of quantity, the projections of projection 22 and projection 22 and adjust quantity and the size of the groove 242 of 22 of each projections, for example, as shown in Figure 3, show other aspects and the configuration mode of projection 22 and groove 242, projection 22 also illustrates with the square of tool decorative pattern equally.In this embodiment, four sides of chip 21 are provided with a plurality of projections 22, can have at least one groove 242 between each projection 22 or be formed with a plurality of grooves 242, and as long as at least one groove 242 just in time can block plane overlapping area A1, the width of each groove 242 or length all can be adjusted, for example, can be with first side 213 to second side 214 extensions of each groove 242 by chip 21.In other embodiment, groove 242 also can be oblique extension, as long as fit and to block plane overlapping area A1, the path of ion 221 migrations of projection 22 generations is bound to through groove 242, and then avoids 22 of adjacent each projections to produce the phenomenons such as bridge joint, electrical short circuit or leakage current because of ion 221 migrations.
Different being in this second embodiment of one chip encapsulation construction 3 of second embodiment of the invention and the first embodiment directly is formed in a plurality of insulation protrusion-shaped on protective layer.Please refer to Fig. 4 A and Fig. 4 B, be respectively generalized section and the local schematic top plan view of this second embodiment, chip-packaging structure 3 comprises chip 31, a plurality of projection 32, a protective layer 33, a plurality of insulation projection 34, a flexible base plate 35 and a packing colloid 36.
Wherein, chip 31 has an active surface 311 and a plurality of weld pad 312, and described a plurality of weld pads 312 are arranged on active surface 311, and 33 of protective layers are formed on active surface 311 and the part appears each weld pad 312.Described a plurality of projection 32 is formed at respectively on each weld pad 312 and with weld pad 312 and is electrically connected, and described a plurality of projections 32 are spaced along at least two relative sides 313,314 of chip 31, and in the present embodiment, projection 32 covers on the protective layer 33 of part.Described a plurality of insulation projection 34 is formed on protective layer 33; and 32 adjacent of each projections have at least one insulation projection 34; flexible base plate 35 has a plurality of pins 351; chip 31 engages with flexible base plate 35; make described a plurality of pin 351 and the corresponding electric connection of described a plurality of projections 32,36 of packing colloids are filled in chip 31 and flexible base plate 35 formed space.
identical with first embodiment of the invention, when chip 31 and flexible base plate 35 electrically conduct and make projection 32 produce that ions 321 are separated out and during transport phenomena, illustrate the migration path of ion 321 as the dotted arrow of Fig. 4 A, at least one insulation projection 34 by 32 of each projections, make ion 321 migration paths increase, can reduce the probability that ion 321 migrates to adjacent projection 32, at least one insulation projection 34 even can form a barricade rests between each projection 32 and insulation projection 34 ion 321, and then avoid 32 of adjacent each projections to produce bridge joint because of ion 321 migrations, the phenomenons such as electrical short circuit or leakage current.Moreover packing colloid 36 also can increase the adhesive force of packing colloid 36 and chip 31 by being filled between each insulation projection 34 and each projection 32.
Specifically, two relative sides of chip 31 are respectively a first side 313 and a second side 314.Please continue the 4B with reference to figure, show projection 32 and the relative position of insulation projection 34 on chip 31, be the difference of clear difference projection 32 and insulation projection 34, projection 32 is with the square expression of tool decorative pattern.Each projection 32 is spaced along first side 313 and the second side 314 of chip 31, each projection 32 has two relative limit walls 322, the vertical first side 313 of limit wall 322 or second side 314, the limit wall 322 formed projected area of mutual projection of two adjacent spaced described a plurality of projections 32 have a plane overlapping area A2 (as shown in Fig. 4 B hatched example areas), and plane overlapping area A2 is blocked in 34 extensions of insulation projection, make plane overlapping area A2 be divided into twoth district, respectively the projection 32 of adjacency two adjacent arrangements.
In the present embodiment, a height H preferably of each insulation projection 34 is between 2 to 10 microns.Similarly, identical with first embodiment of the invention, the insulation projection 34 of the present embodiment also can be carried out the adjustment on quantity and size on demand, and this is to know art technology person can spread to easily, repeats no more in this.
Please further join Fig. 4 C; in other embodiments of the invention; chip-packaging structure 3 more can comprise an insulating thin layer 37 and be formed on protective layer 33, and insulating thin layer 37 appears described a plurality of projection 32, and described a plurality of insulation projection 34 is formed on described insulating thin layer 37.
In addition, no matter be the insulating thin layer of first embodiment of the invention, the second embodiment or other embodiment and the material of insulation projection, all optional from polyimides (Polyimide, PI), photoresistance solder flux (solder resist, SR) or benzocyclobutene (benzocyclobutene, BCB).And the kind of projection can be selected from plated bumps, electroless plating projection, tie lines projection or conducting polymer projection, and its material can be selected from gold, silver, copper, indium, nickel/gold, nickel/palladium/gold, copper/nickel/gold, copper/gold, aluminium, conducting polymer composite and combination thereof etc.
In sum, the insulating thin layer of chip-packaging structure between each projection that the present invention discloses is formed with groove or the insulation projection is set, can not only increase the adhesive force of packing colloid and chip, also must increase the migration path of the ion of projection generation, by this, can reduce the probability that ion migrates to adjacent projection, to reduce chip-packaging structure, the phenomenons such as electrical short circuit or leakage current occur, and then promote the reliability of chip-packaging structure.
The above embodiments only are used for exemplifying enforcement aspect of the present invention, and explain technical characterictic of the present invention, are not to limit protection category of the present invention.Any be familiar with this operator can unlabored change or the arrangement of isotropism all belong to the scope that the present invention advocates, the scope of the present invention should be as the criterion with claim.
Claims (10)
1. chip-packaging structure comprises:
One chip has an active surface and a plurality of weld pad, and described a plurality of weld pads are arranged on described active surface;
One protective layer is formed on described active surface, and described protective layer part appears each described weld pad;
A plurality of projections are formed at respectively on each described weld pad, and are electrically connected with described weld pad;
One insulating thin layer is formed on described protective layer, and described insulating thin layer appears described a plurality of projection, and the described insulating thin layer between each adjacent described projection has at least one groove;
One flexible base plate has a plurality of pins, and described chip engages with described flexible base plate, makes described a plurality of pin and the corresponding electric connection of described a plurality of projections; And
One packing colloid is filled in described chip and described flexible base plate formed space.
2. chip-packaging structure as claimed in claim 1, it is characterized in that, described a plurality of projection is spaced along at least two relative sides of described chip, the mutual projection of one side wall of two adjacent spaced described a plurality of projections forms a plane overlapping area, and described plane overlapping area is blocked in described at least one groove extension of described insulating thin layer.
3. chip-packaging structure as claimed in claim 1, is characterized in that, a thickness of described insulating thin layer is between 5 to 10 microns, and a degree of depth of described at least one groove is between 2 to 5 microns.
4. chip-packaging structure as claimed in claim 1, is characterized in that, the material of described insulating thin layer is selected from polyimides, photoresistance solder flux or benzocyclobutene.
5. chip-packaging structure as claimed in claim 1, is characterized in that, described at least one groove is filled by described packing colloid.
6. chip-packaging structure comprises:
One chip has an active surface and a plurality of weld pad, and described a plurality of weld pads are arranged on described active surface;
One protective layer is formed on described active surface, and described protective layer part appears each described weld pad;
A plurality of projections are formed at respectively on each described weld pad, and are electrically connected with described weld pad;
A plurality of insulation projections are formed on described protective layer, and have at least one described insulation projection between each adjacent described projection;
One flexible base plate has a plurality of pins, and described chip engages with described flexible base plate, makes described a plurality of pin and the corresponding electric connection of described a plurality of projections; And
One packing colloid is filled in described chip and described flexible base plate formed space.
7. chip-packaging structure as claimed in claim 6, it is characterized in that, described a plurality of projection is spaced along at least two relative sides of described chip, the mutual projection of one side wall of two adjacent spaced described a plurality of projections forms a plane overlapping area, and described plane overlapping area is blocked in described at least one insulation projection extension.
8. chip-packaging structure as claimed in claim 6, is characterized in that, more comprises an insulating thin layer and be formed on described protective layer, and described insulating thin layer appears described a plurality of projection, and described a plurality of insulation protrusion-shaped is formed on described insulating thin layer.
9. chip-packaging structure as claimed in claim 6, is characterized in that, a height of each described insulation projection is between 2 to 10 microns.
10. chip-packaging structure as claimed in claim 8, is characterized in that, the material of described a plurality of insulation projections and described insulating thin layer is selected from polyimides, photoresistance solder flux or benzocyclobutene.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100139893 | 2011-11-02 | ||
| TW100139893A TWI462256B (en) | 2011-11-02 | 2011-11-02 | Chip package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103094232A true CN103094232A (en) | 2013-05-08 |
| CN103094232B CN103094232B (en) | 2015-12-09 |
Family
ID=48206634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210034270.5A Active CN103094232B (en) | 2011-11-02 | 2012-02-09 | Chip packaging structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103094232B (en) |
| TW (1) | TWI462256B (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517921A (en) * | 2013-09-30 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Bonded substrate and forming method thereof, and three-dimensional package structure and forming method thereof |
| CN104795363A (en) * | 2014-01-17 | 2015-07-22 | 菱生精密工业股份有限公司 | Copper-clad substrate with barrier structure and manufacturing method thereof |
| CN104867901A (en) * | 2014-02-25 | 2015-08-26 | 矽品精密工业股份有限公司 | Substrate structure and semiconductor package |
| CN105513983A (en) * | 2014-09-26 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
| CN106449579A (en) * | 2015-12-16 | 2017-02-22 | 成都芯源系统有限公司 | Semiconductor device and manufacturing method |
| CN106816388A (en) * | 2015-12-02 | 2017-06-09 | 南茂科技股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| CN107481985A (en) * | 2016-06-07 | 2017-12-15 | 南茂科技股份有限公司 | Chip packaging structure |
| CN105826213B (en) * | 2015-01-06 | 2018-12-21 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
| CN109378299A (en) * | 2016-11-27 | 2019-02-22 | 乐清市风杰电子科技有限公司 | A kind of wafer packaging structure |
| CN109786273A (en) * | 2017-11-14 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | Integrated circuit structure and forming method thereof |
| CN110544684A (en) * | 2018-05-28 | 2019-12-06 | 三星电子株式会社 | thin film package and package module including the same |
| CN110556299A (en) * | 2018-06-04 | 2019-12-10 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor structure and forming method thereof |
| CN111490026A (en) * | 2019-01-28 | 2020-08-04 | 鼎元光电科技股份有限公司 | Package structure and method for manufacturing the same |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11475804B2 (en) * | 2019-07-26 | 2022-10-18 | Au Optronics Corporation | Display panel having an auxiliary layer overlapped with a bendable region |
| TWI742519B (en) * | 2019-07-26 | 2021-10-11 | 友達光電股份有限公司 | Flexible display device and manufacturing method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW527709B (en) * | 1999-02-20 | 2003-04-11 | United Microelectronics Corp | Wafer level package |
| US20040214375A1 (en) * | 2003-04-28 | 2004-10-28 | Sharp Kabushiki Kaisha | Method of manufacturing semiconductor device, flexible substrate, and semiconductor device |
| US20060055037A1 (en) * | 2004-09-15 | 2006-03-16 | Samsung Electronics Co., Ltd. | Microelectronic device chip including hybrid Au bump, package of the same, LCD apparatus including microelectronic device chip and method of fabricating microelectronic device chip |
| US20070257347A1 (en) * | 2006-05-02 | 2007-11-08 | Hui-Ling Chang | Chip structure and fabricating process thereof |
| JP2008258439A (en) * | 2007-04-05 | 2008-10-23 | Kawasaki Microelectronics Kk | Method for manufacturing semiconductor device |
| JP2009044077A (en) * | 2007-08-10 | 2009-02-26 | Toshiba Corp | Semiconductor device, and manufacturing method of semiconductor device |
| TW201027679A (en) * | 2009-01-06 | 2010-07-16 | Raydium Semiconductor Corp | Chip packaging structure and lead frame |
-
2011
- 2011-11-02 TW TW100139893A patent/TWI462256B/en active
-
2012
- 2012-02-09 CN CN201210034270.5A patent/CN103094232B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW527709B (en) * | 1999-02-20 | 2003-04-11 | United Microelectronics Corp | Wafer level package |
| US20040214375A1 (en) * | 2003-04-28 | 2004-10-28 | Sharp Kabushiki Kaisha | Method of manufacturing semiconductor device, flexible substrate, and semiconductor device |
| CN1542934A (en) * | 2003-04-28 | 2004-11-03 | 夏普株式会社 | Method of manufacturing semiconductor device, flexible substrate, and semiconductor device |
| US20060055037A1 (en) * | 2004-09-15 | 2006-03-16 | Samsung Electronics Co., Ltd. | Microelectronic device chip including hybrid Au bump, package of the same, LCD apparatus including microelectronic device chip and method of fabricating microelectronic device chip |
| US20070257347A1 (en) * | 2006-05-02 | 2007-11-08 | Hui-Ling Chang | Chip structure and fabricating process thereof |
| JP2008258439A (en) * | 2007-04-05 | 2008-10-23 | Kawasaki Microelectronics Kk | Method for manufacturing semiconductor device |
| JP2009044077A (en) * | 2007-08-10 | 2009-02-26 | Toshiba Corp | Semiconductor device, and manufacturing method of semiconductor device |
| TW201027679A (en) * | 2009-01-06 | 2010-07-16 | Raydium Semiconductor Corp | Chip packaging structure and lead frame |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517921A (en) * | 2013-09-30 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Bonded substrate and forming method thereof, and three-dimensional package structure and forming method thereof |
| CN104517921B (en) * | 2013-09-30 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | It is bonded substrate and forming method thereof, three-dimension packaging structure and forming method thereof |
| CN104795363A (en) * | 2014-01-17 | 2015-07-22 | 菱生精密工业股份有限公司 | Copper-clad substrate with barrier structure and manufacturing method thereof |
| CN104867901A (en) * | 2014-02-25 | 2015-08-26 | 矽品精密工业股份有限公司 | Substrate structure and semiconductor package |
| CN105513983A (en) * | 2014-09-26 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
| CN105826213B (en) * | 2015-01-06 | 2018-12-21 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
| CN106816388A (en) * | 2015-12-02 | 2017-06-09 | 南茂科技股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| CN106816388B (en) * | 2015-12-02 | 2019-04-30 | 南茂科技股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| CN106449579A (en) * | 2015-12-16 | 2017-02-22 | 成都芯源系统有限公司 | Semiconductor device and manufacturing method |
| CN107481985A (en) * | 2016-06-07 | 2017-12-15 | 南茂科技股份有限公司 | Chip packaging structure |
| CN107481985B (en) * | 2016-06-07 | 2020-01-31 | 南茂科技股份有限公司 | Chip packaging structure |
| CN109378299A (en) * | 2016-11-27 | 2019-02-22 | 乐清市风杰电子科技有限公司 | A kind of wafer packaging structure |
| CN109378299B (en) * | 2016-11-27 | 2020-05-15 | 乐清市风杰电子科技有限公司 | Wafer packaging structure |
| CN109786273A (en) * | 2017-11-14 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | Integrated circuit structure and forming method thereof |
| CN110544684A (en) * | 2018-05-28 | 2019-12-06 | 三星电子株式会社 | thin film package and package module including the same |
| CN110556299A (en) * | 2018-06-04 | 2019-12-10 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor structure and forming method thereof |
| CN110556299B (en) * | 2018-06-04 | 2021-11-16 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor structure and forming method thereof |
| CN111490026A (en) * | 2019-01-28 | 2020-08-04 | 鼎元光电科技股份有限公司 | Package structure and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI462256B (en) | 2014-11-21 |
| CN103094232B (en) | 2015-12-09 |
| TW201320275A (en) | 2013-05-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103094232B (en) | Chip packaging structure | |
| US11101238B2 (en) | Surface mounting semiconductor components | |
| TW586201B (en) | Semiconductor device and the manufacturing method thereof | |
| TW201828418A (en) | Thin fan-out type multi-chip stacked package | |
| WO2014115561A1 (en) | Semiconductor device | |
| TWI752515B (en) | Anisotropically conductive film, method for producing the same, and connecting structure using the anisotropically conductive film and method for producing the same | |
| KR101974763B1 (en) | Multilayer board | |
| TW201312723A (en) | Chip packaging structure and manufacturing method for the same | |
| JP2016119306A (en) | Anisotropic conductive film and connection structure | |
| CN103811428A (en) | Methods and apparatus for flip chip substrate with guard rings outside of a die attach region | |
| JP2017175093A (en) | Electronic component, connection body, and method of designing electronic component | |
| TW202307876A (en) | Anisotropic electrically conductive film, method for producing same, and connection structural body | |
| TW201530706A (en) | Copper-clad substrate with blocking structure and manufacturing method thereof | |
| US7714425B2 (en) | Semiconductor device, method for manufacturing the same, and flexible substrate for mounting semiconductor | |
| JP2016131246A (en) | Multilayer substrate | |
| CN205723519U (en) | Semiconductor devices | |
| JP2005123463A (en) | Semiconductor device, its manufacturing method, semiconductor device module, circuit board, and electronic equipment | |
| CN104795363A (en) | Copper-clad substrate with barrier structure and manufacturing method thereof | |
| JP4324773B2 (en) | Manufacturing method of semiconductor device | |
| CN107611098A (en) | Electronic packing piece and its preparation method | |
| TW200929468A (en) | Soldering substrate, electrocial soldering structure and method for soldering same | |
| TWI459482B (en) | Multi-chip stack package structure and method of forming same | |
| TW201241981A (en) | Package substrate and fabrication method thereof | |
| JP2016134417A (en) | Semiconductor package substrate, semiconductor package and manufacturing method of the same | |
| TWI816499B (en) | Electronic package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |