CN105990302A - Method for manufacturing package structure and package substrate thereof - Google Patents
Method for manufacturing package structure and package substrate thereof Download PDFInfo
- Publication number
- CN105990302A CN105990302A CN201510039525.0A CN201510039525A CN105990302A CN 105990302 A CN105990302 A CN 105990302A CN 201510039525 A CN201510039525 A CN 201510039525A CN 105990302 A CN105990302 A CN 105990302A
- Authority
- CN
- China
- Prior art keywords
- packaging
- fluting
- base plate
- preparation
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title abstract description 8
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000004806 packaging method and process Methods 0.000 claims abstract description 44
- 239000012774 insulation material Substances 0.000 claims description 36
- 238000002360 preparation method Methods 0.000 claims description 31
- 239000011241 protective layer Substances 0.000 claims description 31
- 239000010410 layer Substances 0.000 claims description 27
- 238000005538 encapsulation Methods 0.000 claims description 6
- 238000004891 communication Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- 239000004744 fabric Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims 3
- 238000005253 cladding Methods 0.000 claims 1
- 238000013461 design Methods 0.000 abstract description 5
- 230000002349 favourable effect Effects 0.000 abstract 1
- 239000011810 insulating material Substances 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 6
- 230000032798 delamination Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000008187 granular material Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000084 colloidal system Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 235000002017 Zea mays subsp mays Nutrition 0.000 description 1
- 241000482268 Zea mays subsp. mays Species 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
A method for manufacturing a package structure and a package substrate thereof are provided, the package substrate includes: the packaging substrate comprises a substrate body, a plurality of electric contact pads arranged on the substrate body and an insulating protection layer arranged on the substrate body, wherein the insulating protection layer is provided with a plurality of slots, and each electric contact pad is exposed out of each slot, the slots comprise a plurality of openings correspondingly exposing each electric contact pad and a channel formed between at least two openings, and the design of the slots is favorable for filling insulating materials between the electronic element and the packaging substrate in the subsequent process.
Description
Technical field
The present invention relates to a kind of encapsulation technology, the preparation method of a kind of flip-chip type package structure and
Base plate for packaging used.
Background technology
Along with the prosperity of electronic industry, electronic product now has tended to compact many with function
The direction design of sample, semiconductor packaging develops different encapsulation kenels the most therewith.For
Meet high integration (Integration) and the miniaturization of semiconductor device
(Miniaturization) demand, except the semiconductor packages of tradition routing type (Wire bonding)
Outside technology, it is possible to by flip (Flip chip) mode, to promote wiring density.
Figure 1A is the cross-sectional schematic of existing flip-chip type package structure 1.As shown in Figure 1A, one
Semiconductor wafer 13 is bound to the line layer of a base plate for packaging 10 by multiple solder bumps 130
On the electric contact mat 110 of 11 and be electrically connected with the conductive trace 111 of this line layer 11, then shape
Become the insulation material 14 of packing colloid or primer in this semiconductor wafer 13 and this base plate for packaging 10 it
Between, to be coated with those solder bumps 130.
But, as shown in Figure 1A ', the insulating protective layer 12 of this base plate for packaging 10 is formed many
Individual correspondence exposes the perforate 120 of respectively this electric contact mat 110, so flowing in this insulation material 14
Time between this semiconductor wafer 13 and this base plate for packaging 10, it is easily caused in this insulation material 14 bigger
Granule (filler) cannot by and produce space (void), so that in successive process
It is susceptible to puffed rice phenomenon (Popcorn), causes product yield to reduce.
Figure 1B is the cross-sectional schematic of existing flip-chip type package structure 1 '.Such as Figure 1B and Figure 1B '
Shown in, its processing procedure is identical with the processing procedure shown in Figure 1A, but this insulating protective layer 12 is formed single
Opening 120 ', to expose respectively this electric contact mat 110 and this conductive trace 111 of part, makes each
Between this electric contact mat 110, this insulating protective layer 12 does not intercepts, so in this insulation material 14
Bigger granule can easily pass through between this semiconductor wafer 13 and this base plate for packaging 10, to avoid
The problem that this insulation material 14 occurs space.
Only, owing between copper lines layer 11 and this insulation material 14, adhesion is the best, so in
In crystalline setting area, the contact of this insulation material 14 combines more line layer 11 and contacts less insulation
Protective layer 12, thus the adhesion of this insulation material 14 is the best, causes being susceptible to delamination
(delamination) problem.
Therefore, how to overcome the variety of problems of above-mentioned prior art, become current industry urgently in fact
A difficult problem to be overcome.
Summary of the invention
In view of the disadvantages of above-mentioned prior art, the present invention provides the preparation method of a kind of encapsulating structure
And base plate for packaging, by the design of fluting, it is beneficial in successive process insulation material and inserts this electricity
Between sub-element and this base plate for packaging.
The base plate for packaging of the present invention, including: substrate body, it is provided with at least one crystalline setting area；Line
Road floor, it is formed in this substrate body, and is formed with multiple electric contact mat in this crystalline setting area；
And insulating protective layer, it is formed on this substrate body and this line layer, and this insulation protection
Layer has multiple perforate being positioned on this crystalline setting area, and this is opened to make respectively this electric connection pad expose to respectively
Hole, wherein, this insulating protective layer is also formed with a passage between at least two these perforates, makes this
Passage and those perforates connected thereof form one and are positioned at the fluting on this crystalline setting area, make this circuit
The part surface of layer exposes to this fluting.
The present invention also provides for the preparation method of a kind of encapsulating structure, including: will at least one electronic component knot
On the electric contact mat of the crystalline setting area being bonded to aforesaid base plate for packaging；And insert absolutely along this fluting
Edge material, makes this insulation material be formed between this electronic component and this base plate for packaging.
In aforesaid preparation method, it is electrical that this electronic component is electrically connected with those by multiple conducting elements
Engagement pad, and this insulation material is coated with those conducting elements.
In aforesaid preparation method, the direction of this fluting and this insulation material to insert direction identical.
In the preparation method of aforesaid encapsulating structure and base plate for packaging thereof, this insulating protective layer has multiple
This fluting of bar.Such as, the cloth of those flutings is set to be arranged side by side or the laying of those flutings
For being crisscross arranged.
In the preparation method of aforesaid encapsulating structure and base plate for packaging thereof, this fluting also has connection, and this is put
The guiding road at edge, crystalline region, makes this insulation material be formed at this electronic component via this guiding road and be somebody's turn to do
Between base plate for packaging.
In the preparation method of aforesaid encapsulating structure and base plate for packaging thereof, in the range of this crystalline setting area, should
Area shared by insulating protective layer exposes to the area on the surface of this fluting more than this line layer.
In the preparation method of aforesaid encapsulating structure and base plate for packaging thereof, the first area of this crystalline setting area with
This line layer exposes to the ratio of the second area on the surface of this fluting for less than 44%.
In the preparation method of aforesaid encapsulating structure and base plate for packaging thereof, those flutings are interconnected, and make
This insulating protective layer presents island.
In the preparation method of aforesaid encapsulating structure and base plate for packaging thereof, also include communication channel, its connection
This fluting and with this slot staggered setting.
From the foregoing, it will be observed that the preparation method of the encapsulating structure of the present invention and base plate for packaging thereof, mainly by opening
Groove replaces existing perforate or opening, is beneficial to insulation material and inserts this electronic component and this base plate for packaging
Between, and reduce the exposed area of this line layer, so compared to prior art, the present invention can
Avoid this insulation material form space and delamination occurs, thus product yield can be improved.
Accompanying drawing explanation
Figure 1A to Figure 1A ' is section view and the upper schematic diagram of existing flip-chip type package structure；
Figure 1B to Figure 1B ' is section view and the upper schematic diagram of another existing flip-chip type package structure；
Fig. 2 is the cross-sectional schematic of the preparation method of encapsulating structure of the present invention；
Fig. 2 A to Fig. 2 C is the upper schematic diagram of the different embodiments of the base plate for packaging of Fig. 2；With
And
Fig. 3 be the preparation method of the encapsulating structure of the present invention insulation material flowing virtual condition on regard
Schematic diagram.
Symbol description
1,1 ', 9 encapsulating structures
10,2 base plate for packaging
11,21 line layers
110,210 electric contact mats
111,211 conductive traces
12,22,32 insulating protective layers
120,22a perforate
120 ' openings
13 semiconductor wafers
130 solder bumps
14,4 insulation materials
20 substrate body
20a first surface
20b second surface
220,220 ' flutings
220 " communication channel
22b passage
22c guides road
3 electronic components
3a acting surface
Non-active of 3b
30 conducting elements
D crystalline setting area
Y mould flow path direction.
Detailed description of the invention
By particular specific embodiment, embodiments of the present invention, art technology are described below
Personnel can be understood other advantages and the merit of the present invention easily by content disclosed in the present specification
Effect.
It should be clear that structure depicted in this specification institute accompanying drawings, ratio, size etc., the most only use
In coordinating the content disclosed in description, for understanding and the reading of those skilled in the art, and
Non-for limiting the enforceable qualifications of the present invention, so not having technical essential meaning,
The modification of any structure, the change of proportionate relationship or the adjustment of size, do not affecting institute of the present invention
Under the effect that can produce and the purpose that can reach, all should still fall in disclosed technology
In the range of content obtains and can contain.Meanwhile, in this specification cited as " on ", " the
One ", the term of " second " and " " etc., be also only and be easy to understanding of narration, rather than
For limiting the enforceable scope of the present invention, being altered or modified of its relativeness, without essence
Under change technology contents, when being also considered as the enforceable category of the present invention.
Fig. 2 and Fig. 2 A is the schematic diagram of the preparation method of the encapsulating structure 9 of the present invention.In the present embodiment
In, this encapsulating structure 9 is crystal covering type.
As in figure 2 it is shown, an electronic component 3 is bound on a base plate for packaging 2, then formed absolutely
Edge material 4 is between this electronic component 3 and this base plate for packaging 2.Specifically, described encapsulation base
Plate 2 has substrate body 20, line layer 21 and an insulating protective layer 22.
Described substrate body 20 has relative first surface 20a and second surface 20b, and
On this first surface 20a, definition has a crystalline setting area D, as shown in Figure 2 A.
Described line layer 21 is located on the first surface 20a of this substrate body 20, and has
Multiple conductive traces 211 and the multiple electric contact mats 210 being positioned on the D of this crystalline setting area, wherein,
Those conductive traces 211 connect respectively this electric contact mat 210.
Described insulating protective layer 22 is located at first surface 20a and this line of this substrate body 20
On road floor 21, and this insulating protective layer 22 has multiple fluting 220 being positioned on the D of this crystalline setting area,
Make part surface (containing conductive trace 211 and electric contact mat 210) and the portion of this line layer 21
First surface 20a is divided to expose to those flutings 220, as shown in Figure 2 A.Specifically, this fluting
220 comprise correspondence exposes multiple perforate 22a of respectively this electric connection pad 210 and is formed at least
A passage 22b between wantonly two this perforate 22a, namely this passage 22b and connected should
A little perforate 22a form this fluting 220.
In the present embodiment, the material of this substrate body 20 can be dielectric material or other existing material,
There is no particular restriction, and this base plate for packaging 2 can have the inner wire being electrically connected with this line layer 21
Road (figure is slightly), and this insulating protective layer 22 is welding resisting layer, such as green paint.
Additionally, those flutings 220 be shaped as strip (can be rule or irregularly strip),
And it lays and presents longitudinal direction and be arranged side by side preferably for being parallel to each other；In other embodiments,
As shown in Figure 2 B, partly those flutings 220 ' also can present laterally, makes those slot
The cloth of 220,220 ' is set to be crisscross arranged；Or, as shown in Figure 2 C, also include multiple connection
Road 220 ", it connects this fluting 220 and is crisscross arranged with this fluting 220, but those communication channels
220 " position of this perforate 22a is not lined up.
Also, in the range of the D of this crystalline setting area, this area shared by insulating protective layer 22 is more than this line
Road floor 21 expose to this fluting 220 surface (i.e. this conductive trace 211 expose end face with electricity
Property engagement pad 210 expose end face) area, and this crystalline setting area D the first area (as figure
The dashed rectangle area of 2A, represents with symbol A below) expose to this fluting with this line layer 21
The ratio of the second area (representing with symbol B below) on the surface of 220 is for less than 44% (i.e.
B/A ＜ 44%), thus this insulating protective layer 22 can set on demand fluting 220 quantity with
The quantity of perforate 22a, as shown in Figure 2 B, partly this perforate 22a not with this fluting 220 phase
Logical.
Therefore, the preparation method of the present invention is that this electronic component 3 is bound to putting of this base plate for packaging 2
On the electric contact mat 210 of crystalline region D, then insert this insulation material 4 along this fluting 220, make this exhausted
Edge material 4 is formed between this electronic component 3 and this base plate for packaging 2.
In the present embodiment, this electronic component 3 is active member, passive device or a combination thereof person,
And this active member is such as wafer, and this passive device is such as resistance, electric capacity and inductance.
Specifically, this electronic component 3 has relative acting surface 3a and non-active 3b, and this effect
Face 3a combines and is electrically connected to those electric contact mats 210 by multiple conducting elements 30, its
In, those conducting elements 30 are the block (such as projection) such as containing soldering tin material.
Additionally, be depending on the scope of this crystalline setting area D is based on the size of this electronic component 3, and should
The scope of crystalline setting area D approximates the laying scope of this insulation material 4, makes the scope of this crystalline setting area D
Area more than this electronic component 3.
Also, this insulation material 4 is primer or packing colloid, and this insulation material 4 is coated with those conductions
Element 30.
It addition, this fluting 220 also has the guiding road 22c at connection D edge, this crystalline setting area, such as figure
Shown in 2A, this insulation material 4 is made to flow into this electronic component 3 and this encapsulation via this guiding road 22c
Between substrate 2, it is beneficial to this insulation material 4 and inserts.
In the preparation method of the present invention, in time carrying out the processing procedure inserting this insulation material 4, by this fluting 220
Guiding road 22c the material 4 that should insulate inserted direction, i.e. the direction of this fluting 220 and mould
Flow path direction Y (as shown in Figure 3) is identical, makes this insulation material 4 flow into according to mould flow path direction Y, and edge
This fluting 220 to flow to the other end.In an embodiment, owing to those slot 220 mutual
The design of connection, makes this insulating protective layer 32 present island in the D of this crystalline setting area, such as Fig. 3 institute
Show, so when in this insulation material 4, bigger granule touches the insulating protective layer 32 such as island,
Can walk around from this insulating protective layer 32 side and continue flowing along this fluting 220, without being subject to
To stopping, because of without producing space.
Additionally, in the D of this crystalline setting area, most conductive trace 211 is coated with this insulation
Protective layer 22, the most least a portion of conductive trace 211 does not covers this insulating protective layer 22, so in
In the D of this crystalline setting area, this area shared by insulating protective layer 22 exposes to more than this line layer 21
The area on the surface of this fluting 220, makes the contact of this insulation material 4 combine more insulating protective layer
22 and contact less line layer 21, thus the adhesion of this insulation material 4 can be increased, to avoid
There is delamination in this insulation material 4.
In sum, the preparation method of the encapsulating structure of the present invention and base plate for packaging thereof, by this fluting
Design, to avoid this insulation material to form space, and avoid this insulation material generation delamination, so
Product yield can be improved.
Above-described embodiment is only used for principle and effect thereof of the illustrative present invention, not for
Limit the present invention.Any those skilled in the art all can be in the spirit and the scope without prejudice to the present invention
Under, above-described embodiment is modified.Therefore the scope of the present invention, should be such as right
Listed by claim.
Claims (20)
1. a base plate for packaging, is characterized by, this base plate for packaging includes:
Substrate body, it is provided with at least one crystalline setting area；
Line layer, it is formed in this substrate body, and be formed in this crystalline setting area multiple electrically
Engagement pad；And
Insulating protective layer, it is formed on this substrate body and this line layer, and this insulation protection
Layer has multiple perforate being positioned on this crystalline setting area, and this is opened to make respectively this electric connection pad expose to respectively
Hole, wherein, this insulating protective layer is also formed with a passage between at least two these perforates, makes this
Passage and those perforates connected thereof form one and are positioned at the fluting on this crystalline setting area, make this circuit
The part surface of layer exposes to this fluting.
Base plate for packaging the most according to claim 1, is characterized by, this insulating protective layer has
There are multiple these flutings.
Base plate for packaging the most according to claim 2, is characterized by, the laying of those flutings
For being arranged side by side.
Base plate for packaging the most according to claim 2, is characterized by, the laying of those flutings
For being crisscross arranged.
Base plate for packaging the most according to claim 1, is characterized by, this fluting also has even
The guiding road at this edge, crystalline setting area logical.
Base plate for packaging the most according to claim 1, is characterized by, the scope of this crystalline setting area
In, the area shared by this insulating protective layer exposes to the face on the surface of this fluting more than this line layer
Long-pending.
Base plate for packaging the most according to claim 1, is characterized by, the first of this crystalline setting area
Area and this line layer expose to the ratio of the second area on the surface of this fluting for less than 44%.
Base plate for packaging the most according to claim 1, is characterized by, those flutings interconnect mutually
Logical, make this insulating protective layer present island.
Base plate for packaging the most according to claim 1, is characterized by, this base plate for packaging also wraps
Include communication channel, its connect this fluting and with this slot staggered setting.
10. a preparation method for encapsulating structure, is characterized by, this preparation method includes:
What at least one electronic component was bound to base plate for packaging according to claim 1 puts crystalline substance
On the electric contact mat in district；And
Insert insulation material along this fluting, make this insulation material be formed at this electronic component and this encapsulation base
Between plate.
The preparation method of 11. encapsulating structures according to claim 10, is characterized by, this insulation
Protective layer has multiple these flutings.
The preparation method of 12. encapsulating structures according to claim 11, is characterized by, those are opened
The cloth of groove is set to be arranged side by side.
The preparation method of 13. encapsulating structures according to claim 11, is characterized by, those are opened
The cloth of groove is set to be crisscross arranged.
The preparation method of 14. encapsulating structures according to claim 10, is characterized by, this fluting
Also there is the guiding road connecting this edge, crystalline setting area, for inserting this insulation material.
The preparation method of 15. encapsulating structures according to claim 10, is characterized by, this puts crystalline substance
In the range of district, the area shared by this insulating protective layer exposes to this fluting more than this line layer
The area on surface.
The preparation method of 16. encapsulating structures according to claim 10, is characterized by, this puts crystalline substance
The ratio of the second area that first area in district exposes to the surface of this fluting with this line layer is little
In 44%.
The preparation method of 17. encapsulating structures according to claim 10, is characterized by, those are opened
Groove is interconnected, and makes this insulating protective layer present island.
The preparation method of 18. encapsulating structures according to claim 10, is characterized by, this encapsulation
Substrate also includes connecting this fluting the communication channel with this slot staggered setting.
The preparation method of 19. encapsulating structures according to claim 10, is characterized by, this electronics
Element is to be electrically connected with those electric contact mats, and this insulation material cladding by multiple conducting elements
Those conducting elements.
The preparation method of 20. encapsulating structures according to claim 10, is characterized by, this fluting
Direction and this insulation material to insert direction identical.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104100212A TWI569339B (en) | 2015-01-06 | 2015-01-06 | Method of fabricating a package structure and a package substrate thereof |
| TW104100212 | 2015-01-06 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105990302A true CN105990302A (en) | 2016-10-05 |
| CN105990302B CN105990302B (en) | 2019-06-21 |
Family
ID=56985166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510039525.0A Active CN105990302B (en) | 2015-01-06 | 2015-01-27 | Method for manufacturing package structure and package substrate thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105990302B (en) |
| TW (1) | TWI569339B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109390311A (en) * | 2017-08-14 | 2019-02-26 | 矽品精密工业股份有限公司 | packaging structure and packaging substrate thereof |
| CN110165442A (en) * | 2018-02-12 | 2019-08-23 | 泰达电子股份有限公司 | Metal block welds the power module of column combination and its application |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI760272B (en) * | 2021-08-09 | 2022-04-01 | 矽品精密工業股份有限公司 | Electronic package and carrier structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080277802A1 (en) * | 2007-05-10 | 2008-11-13 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package and package substrate applicable thereto |
| CN102194768A (en) * | 2010-03-08 | 2011-09-21 | 三星电子株式会社 | Substrates, package substrates, semiconductor packages having the same, and methods of fabricating the semiconductor packages |
| CN103579168A (en) * | 2012-07-19 | 2014-02-12 | 矽品精密工业股份有限公司 | Substrate structure and packaging piece with same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW507341B (en) * | 2001-11-01 | 2002-10-21 | Siliconware Precision Industries Co Ltd | Substrate capable of preventing delamination of chip and semiconductor encapsulation having such a substrate |
-
2015
- 2015-01-06 TW TW104100212A patent/TWI569339B/en active
- 2015-01-27 CN CN201510039525.0A patent/CN105990302B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080277802A1 (en) * | 2007-05-10 | 2008-11-13 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package and package substrate applicable thereto |
| CN102194768A (en) * | 2010-03-08 | 2011-09-21 | 三星电子株式会社 | Substrates, package substrates, semiconductor packages having the same, and methods of fabricating the semiconductor packages |
| CN103579168A (en) * | 2012-07-19 | 2014-02-12 | 矽品精密工业股份有限公司 | Substrate structure and packaging piece with same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109390311A (en) * | 2017-08-14 | 2019-02-26 | 矽品精密工业股份有限公司 | packaging structure and packaging substrate thereof |
| CN110165442A (en) * | 2018-02-12 | 2019-08-23 | 泰达电子股份有限公司 | Metal block welds the power module of column combination and its application |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105990302B (en) | 2019-06-21 |
| TW201626469A (en) | 2016-07-16 |
| TWI569339B (en) | 2017-02-01 |
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