CN103579168A - Substrate structure and packaging piece with same - Google Patents
Substrate structure and packaging piece with same Download PDFInfo
- Publication number
- CN103579168A CN103579168A CN201210275824.0A CN201210275824A CN103579168A CN 103579168 A CN103579168 A CN 103579168A CN 201210275824 A CN201210275824 A CN 201210275824A CN 103579168 A CN103579168 A CN 103579168A
- Authority
- CN
- China
- Prior art keywords
- substrate body
- metal level
- opening
- semiconductor chip
- packaging part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims description 23
- 239000011241 protective layer Substances 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 238000001816 cooling Methods 0.000 claims description 3
- 230000032798 delamination Effects 0.000 abstract description 4
- 238000005538 encapsulation Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 5
- 239000003292 glue Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 229920002521 macromolecule Polymers 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- OMIHGPLIXGGMJB-UHFFFAOYSA-N 7-oxabicyclo[4.1.0]hepta-1,3,5-triene Chemical compound C1=CC=C2OC2=C1 OMIHGPLIXGGMJB-UHFFFAOYSA-N 0.000 description 1
- 241000531908 Aramides Species 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- -1 Poly (tetra-fluoroethylene) Polymers 0.000 description 1
- 229920006231 aramid fiber Polymers 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
A substrate structure and a package with the substrate structure are provided, the substrate structure includes a substrate body, a metal layer, an insulating protection layer and a chip placement area, the metal layer is formed on a surface of the substrate body, the insulating protection layer is formed on the surface of the substrate body and has an opening exposing the metal layer, the chip placement area is defined on the surface of the substrate body for connecting a semiconductor chip on the surface, wherein one chip placement area corresponds to one opening, the scope of the chip placement area covers the whole of the opening, or the metal layer does not exceed the scope of the chip placement area. The invention can effectively reduce the delamination phenomenon of the packaging piece so as to improve the yield.
Description
Technical field
The present invention is relevant for a kind of board structure and packaging part, espespecially a kind of board structure for chip package and packaging part.
Background technology
General flip chip comprises that covering geode grid array (FCBGA) encapsulates (as shown in Figure 1) and crystal covered chip size encapsulation (flip chip chip scale package, FCCSP) two kinds, its both differences are: cover that the base plate for packaging of geode grid array (FCBGA) encapsulation is large and thickness is high, therefore rigidity is stronger, and use in the carrying and electric connection of CPU (CPU) and Graphics Processing Unit (GPU) more, conventionally the method for making of covering geode grid array (FCBGA) encapsulation first connects semiconductor chip 11 to be placed on base plate for packaging 10, and with capillary bottom (CUF) technology of filling, be filled with protection glue material 12 in semiconductor chip 11 and 10 of base plate for packaging, with protection soldered ball 13 and make non-active of this semiconductor chip 11 111 exposed, so that this non-active 111 as connecing the use of putting heat sink (not icon).
Relatively, as shown in Fig. 2 A and Fig. 2 B, be respectively the cutaway view of packaging part and the vertical view of base plate for packaging of existing crystal covered chip size encapsulation (FCCSP), crystal covered chip size encapsulation (FCCSP) is for the less and thin base plate for packaging 20 of area, be generally used in mobile electronic product, its packaged type adopts so-called molding bottom to fill (MUF) technology, namely need not between semiconductor chip and base plate for packaging, be filled with protection glue material as aforementioned geode grid array (FCBGA) the encapsulation ground that covers, but directly with encapsulating material (Molding compound) 22, directly semiconductor chip 21 is coated on base plate for packaging 20 completely, and make this encapsulating material 22 be filled in 20 of semiconductor chip 21 and base plate for packaging.Crystal covered chip size encapsulation (FCCSP) is filled protection glue material between semiconductor chip and base plate for packaging without the another end of filling; to save man-hour and cost; can directly with the completely coated semiconductor chip 21 of encapsulating material 22, with protection semiconductor chip 21, not destroyed by external environment again; and the rigidity of this encapsulating material 22 is stronger; so can make whole flip chip be difficult for warpage, and then improve reliability issues.
In some situation, the copper layer 201 of the middle section of the base plate for packaging 20 of crystal covered chip size encapsulation (FCCSP) use need partly be revealed in outside insulating protective layer 23, for heat radiation, the electrical purposes such as conduction or ground connection.
Yet; the marginal position A place that semiconductor chip 21 in crystal covered chip size encapsulation (FCCSP) is projected to copper layer 201 has larger stress; therefore when temperature reliability test; often can there is the problem that encapsulating material 22 and copper layer 201 are peeled off in this marginal position A, and cause whole base plate for packaging 20 cannot pass through reliability test.
Therefore, how to avoid above-mentioned variety of problems of the prior art, the real problem of desiring most ardently at present solution that become.
Summary of the invention
Because the defect of above-mentioned prior art, main purpose of the present invention is to provide the packaging part of a kind of board structure and this board structure of tool, can effectively reduce the delamination of packaging part, to promote yield.
Board structure of the present invention comprises: board structure, and it comprises: substrate body; Metal level, it is formed on a surface of this substrate body; Insulating protective layer, it is formed on this surface of this substrate body, and has at least one opening that exposes this metal level; And at least one crystalline setting area, it is defined in this surface of this substrate body, for connecing on this surface, puts semiconductor chip, wherein, corresponding this opening in this crystalline setting area, the scope of this crystalline setting area contains the whole of this opening, or this metal level does not exceed the scope of this crystalline setting area.
The present invention also provides a kind of packaging part, and it comprises: substrate body; Metal level, it is formed on a surface of this substrate body; Insulating protective layer, it is formed on this surface of this substrate body, and has at least one opening that exposes this metal level; And at least one semiconductor chip, it connects and is placed on this metal level, wherein, corresponding this opening of one this semiconductor chip, one this semiconductor chip is contained the whole of this opening in this surperficial drop shadow spread of this substrate body, or this metal level does not exceed this semiconductor chip in this surperficial drop shadow spread of this substrate body.
As from the foregoing, because the present invention makes semiconductor chip be projected to substrate body surface and does not have the metal level exposing, and reduce the whole exposed area of metal level, so follow-up, on this metal level, cover after encapsulating material, (principle is that metal and encapsulating material are heterogeneous to the delamination at the heterojunction place of the existing encapsulating material of difficult generation and metal interlevel, its adherence is poor compared with the adherence between the macromolecule of homogeneity, for example: encapsulating material, adherence between the dielectric layer on insulating protective layer or substrate body surface (homogeneity class) is good), and then promote whole yield.
Accompanying drawing explanation
That shown in Figure 1 is the existing cutaway view that covers brilliant BGA packages.
Fig. 2 A and Fig. 2 B those shown are respectively the cutaway view of packaging part and the vertical view of base plate for packaging of existing crystal covered chip size encapsulation.
That shown in Figure 3 is the cutaway view of the first embodiment of board structure of the present invention and packaging part.
That shown in Figure 4 is the cutaway view of the second embodiment of board structure of the present invention and packaging part.
Primary clustering symbol description
10,20 base plate for packaging
11,21,33 semiconductor chips
111 non-active
12 protection glue materials
13,36 soldered balls
22,34 encapsulating materials
201 bronze medal layers
23,32 insulating protective layers
A marginal position
30 substrate body
30a, 30b surface
300 crystalline setting areas
31 metal levels
320 openings
35 solder ball pads.
Embodiment
By particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification below.
Notice, appended graphic the illustrated structure of this specification, ratio, size etc., equal contents in order to coordinate specification to disclose only, understanding and reading for those skilled in the art, not in order to limit the enforceable qualifications of the present invention, therefore the technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under the effect that the present invention can produce and the object that can reach, all should still drop on disclosed technology contents and obtain in the scope that can contain.Simultaneously, in this specification, quote as " on ", the term such as " central ”,“ drop shadow spread " and " ", also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under without essence change technology contents, when being also considered as the enforceable category of the present invention.
The first embodiment
That shown in Figure 3 is the cutaway view of the first embodiment of board structure of the present invention and packaging part.It first provides a kind of board structure, this board structure comprises: substrate body 30, and its material can be ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aramid fiber (Aramide) or blending epoxy glass fibre (Glass fiber); Metal level 31, it is formed at a surperficial 30a of this substrate body 30; Insulating protective layer 32 (as anti-welding green paint), its this surface 30a that is formed at this substrate body 30 is upper, and has the opening 320 that exposes this metal level 31; And crystalline setting area 300, it is defined in this surface 30a of this substrate body 30, for connecing and put semiconductor chip 33 on the 30a of this surface, wherein, one this corresponding this opening 320 in crystalline setting area 300, the scope of this crystalline setting area 300 contains the whole of this opening 320, and better this opening 320 central authorities that are positioned in this crystalline setting area 300.
The packaging part of the present embodiment connects and puts semiconductor chip 33 in 300 places, crystalline setting area of aforesaid base plate structure, make this semiconductor chip 33 be positioned at this opening 320 central authorities, wherein, corresponding this opening 320 of one this semiconductor chip 33, this semiconductor chip 33 is contained the whole of this opening 320 in the drop shadow spread of this surface of this substrate body 30 30a, and the planar dimension of this semiconductor chip 33 is greater than the size of this opening 320.
In aforesaid packaging part, also comprise encapsulating material 34, its this surface 30a that is formed at this substrate body 30 is upper, to be coated this semiconductor chip 33.
In described packaging part, this semiconductor chip 33 connects and is placed on this metal level 31 to cover crystal type, and the material of this metal level 31 is copper.
In the packaging part of the present embodiment, another surperficial 30b of this substrate body 30 also has a plurality of solder ball pads 35, and also comprises soldered ball 36, and it connects and is placed in respectively on this solder ball pad 35.
The second embodiment
That shown in Figure 4 is the cutaway view of the second embodiment of board structure of the present invention and packaging part.It first provides a kind of board structure, and this board structure comprises: substrate body 30; Metal level 31, it is formed at a surperficial 30a of this substrate body 30; Insulating protective layer 32, its this surface 30a that is formed at this substrate body 30 is upper, and has the opening 320 that exposes this metal level 31; And crystalline setting area 300, it is defined in this surface 30a of this substrate body 30, and for connecing and put semiconductor chip 33 on the 30a of this surface, wherein, this metal level 31 does not exceed the scope of this crystalline setting area 300, and better this opening 320 central authorities that are positioned in this crystalline setting area 300.
The packaging part of the present embodiment connects and puts semiconductor chip 33 in 300 places, crystalline setting area of aforesaid base plate structure, make this semiconductor chip 33 be positioned at this opening 320 central authorities, wherein, this metal level 31 does not exceed this semiconductor chip 33 in the drop shadow spread of this surface of this substrate body 30 30a.
The further feature of the present embodiment is roughly identical with last embodiment, therefore do not repeated at this.
Be noted that in board structure of the present invention and packaging part, this opening 320 also can expose the dielectric layer (not icon) on these substrate body 30 surfaces, and this metal level 31 also can comprise circuit (not icon) and cooling pad (not icon).
In sum, than prior art, because making semiconductor chip be projected to substrate body surface, the present invention do not have the metal level exposing, and reduce the whole exposed area of metal level, so follow-up, on this metal level, cover after encapsulating material, (principle is that metal and encapsulating material are heterogeneous to the delamination at the heterojunction place of the existing encapsulating material of difficult generation and metal interlevel, its adherence is poor compared with the adherence between the macromolecule of homogeneity, for example: encapsulating material, adherence between the dielectric layer on insulating protective layer or substrate body surface (homogeneity class) is good), and then promote whole yield.
Above-described embodiment is only in order to illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all can, under spirit of the present invention and category, modify to above-described embodiment.So the scope of the present invention, should be as listed in claims.
Claims (13)
1. a board structure, comprising:
Substrate body;
Metal level, it is formed on a surface of this substrate body;
Insulating protective layer, it is formed on this surface of this substrate body, and has at least one opening that exposes this metal level; And
At least one crystalline setting area, it is defined in this surface of this substrate body, for connecing on this surface, puts semiconductor chip, wherein, corresponding this opening in this crystalline setting area, the scope of this crystalline setting area contains the whole of this opening, or this metal level does not exceed the scope of this crystalline setting area.
2. board structure according to claim 1, is characterized in that, this crystalline setting area is positioned at this opening central authorities.
3. board structure according to claim 1, is characterized in that, this opening also exposes the dielectric layer on this substrate body surface.
4. board structure according to claim 1, is characterized in that, this metal level also comprises circuit and cooling pad.
5. a packaging part, comprising:
Substrate body;
Metal level, it is formed on a surface of this substrate body;
Insulating protective layer, it is formed on this surface of this substrate body, and has at least one opening that exposes this metal level; And
At least one semiconductor chip, it connects and is placed on this metal level, wherein, corresponding this opening of one this semiconductor chip, one this semiconductor chip is contained the whole of this opening in this surperficial drop shadow spread of this substrate body, or this metal level does not exceed this semiconductor chip in this surperficial drop shadow spread of this substrate body.
6. packaging part according to claim 5, is characterized in that, this packaging part also comprises encapsulating material, and it is formed on this surface of this substrate body, to be coated this semiconductor chip.
7. packaging part according to claim 5, is characterized in that, this semiconductor chip connects and is placed on this metal level to cover crystal type.
8. packaging part according to claim 5, is characterized in that, the material of this metal level is copper.
9. packaging part according to claim 5, is characterized in that, another surface of this substrate body also has a plurality of solder ball pads.
10. packaging part according to claim 9, is characterized in that, this packaging part also comprises soldered ball, and it connects and is placed in respectively on this solder ball pad.
11. packaging parts according to claim 5, is characterized in that, this semiconductor chip is positioned at this opening central authorities.
12. packaging parts according to claim 5, is characterized in that, this opening also exposes the dielectric layer on this substrate body surface.
13. packaging parts according to claim 5, is characterized in that, this metal level also comprises circuit and cooling pad.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101125980A TWI463610B (en) | 2012-07-19 | 2012-07-19 | Substrate structure and die package integrating the substrate structure |
| TW101125980 | 2012-07-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103579168A true CN103579168A (en) | 2014-02-12 |
| CN103579168B CN103579168B (en) | 2016-05-04 |
Family
ID=50050618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210275824.0A Active CN103579168B (en) | 2012-07-19 | 2012-08-03 | Substrate structure and packaging piece with same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103579168B (en) |
| TW (1) | TWI463610B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990302A (en) * | 2015-01-06 | 2016-10-05 | 矽品精密工业股份有限公司 | Method for manufacturing package structure and package substrate thereof |
| CN109390311A (en) * | 2017-08-14 | 2019-02-26 | 矽品精密工业股份有限公司 | packaging structure and packaging substrate thereof |
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| TW200933869A (en) * | 2008-01-30 | 2009-08-01 | Advanced Semiconductor Eng | Package process for embedded semiconductor device |
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| CN105990302B (en) * | 2015-01-06 | 2019-06-21 | 矽品精密工业股份有限公司 | Method for manufacturing package structure and package substrate thereof |
| CN109390311A (en) * | 2017-08-14 | 2019-02-26 | 矽品精密工业股份有限公司 | packaging structure and packaging substrate thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201405718A (en) | 2014-02-01 |
| TWI463610B (en) | 2014-12-01 |
| CN103579168B (en) | 2016-05-04 |
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