JP4052237B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a SiP (system in package) type semiconductor device having a built-in passive element and incorporating a matching circuit and a filter, and a manufacturing method thereof.

  The demand for downsizing, thinning, and weight reduction of portable electronic devices such as digital video cameras, digital mobile phones, and notebook personal computers has been increasing. While an electronic circuit device in which such a semiconductor device is mounted on a printed wiring board has been realized by 70% reduction year by year, how can the component mounting density on the mounting board (printed wiring board) be improved? Has been researched and developed as an important issue.

  For example, as a package form of a semiconductor device, a transition from a lead insertion type such as DIP (Dual Inline Package) to a surface mounting type is performed, and furthermore, bumps (projection electrodes) made of solder, gold, or the like are provided on a pad electrode of a semiconductor chip A flip-chip mounting method has been developed in which a face-down connection is made to the wiring board via bumps.

Furthermore, development is progressing to a package of a complicated form called SiP that incorporates a passive element and incorporates a matching circuit, a filter, and the like.
FIG. 10 is a cross-sectional view of an example of the above-described SiP-type semiconductor device.
A base insulating film 101 made of silicon oxide is formed on a silicon substrate 100, and a lower electrode 102 made of aluminum, a dielectric film 103 made of Ta ₂ O ₅ , a protective layer 104 made of silicon oxide, and aluminum are formed thereon. The lower electrode extraction electrode 105a and the upper electrode 105b are stacked. The lower electrode 102 and the upper electrode 105b are opposed to each other with the dielectric film 103 interposed therebetween, so that capacitance elements (C ₁ , C ₂ ) are configured.

A first insulating layer 106 made of polyimide resin is formed so as to cover the capacitance element, and an opening reaching the extraction electrode 105a of the lower electrode and the upper electrode 105b is formed.
A first wiring 107 made of copper is formed on the first insulating layer 106 so as to be integrated with the plug portion buried in the opening and connected to the lower electrode extraction electrode 105a and the upper electrode 105b. Here, illustration of the barrier metal normally formed on the inner wall surface of the opening is omitted.
A part of the first wiring 107 is formed in a spiral shape, and an inductance L is configured.

  A semiconductor chip 108 provided with active elements is bonded to the upper layer of the first insulating layer 106 and the first wiring 107 by a die attach film 109. The semiconductor chip 108 has a configuration in which a pad 108b is formed on a semiconductor body portion 108a, and a region excluding the pad 108b is covered with a silicon oxide protective layer 108c, face-up, that is, on the opposite side of the surface on which the pad 108b is formed. Mounted from the front side.

A second insulating layer 110 made of polyimide resin is formed so as to cover the first wiring 107 and the semiconductor chip 108, and an opening H ₂ reaching the pad 108 b of the semiconductor chip 108 and an opening H reaching the first wiring 107. ₃ is formed.
A second wiring 111 made of copper is formed on the second insulating layer 110 so as to be integrated with the plug 108 b and the plug portion connected to the first wiring 107 embedded in the openings (H ₁ , H ₂ ). Has been. Here, illustration of the barrier metal normally formed on the inner wall surface of the opening is omitted.

A post 112 made of copper is formed so as to be connected to the second wiring 111, and an insulating buffer layer 113 made of polyimide resin is formed on the second insulating layer 110 in the gap.
Further, bumps (projection electrodes) 114 are formed on the surface of the buffer layer 113 so as to be connected to the posts 112.

A method for manufacturing the SiP semiconductor device will be described.
First, as shown in FIG. 11A, a base insulating film 101 is formed on the surface of a silicon substrate 100, aluminum is deposited on the upper layer by sputtering, and pattern processing is performed to form a lower electrode 102. Ta ₂ O ₅ is deposited by the CVD method, patterned to form the dielectric layer 103, and further, silicon oxide is deposited to form the protective layer 104 for the dielectric layer, and the electrode is formed by RIE (reactive ion etching). An extraction window is opened, aluminum is deposited by a sputtering method, and patterning is performed to form an extraction electrode 105a and an upper electrode 105b for the lower electrode. The electrostatic capacitance elements (C ₁ , C ₂ ) are configured as described above.
Next, a photosensitive polyimide resin is supplied and applied by spin coating to form the first insulating layer 106.

Next, as shown in FIG. 11B, pattern exposure and development are performed on the first insulating film 106, and the opening H ₁ reaching the extraction electrode 105 a and the upper electrode 105 b of the lower electrode is formed in the first insulating film 106. Form.

Next, as shown in FIG. 11C, a barrier metal film (not shown) made of Ti / Cu is formed by seed sputtering, and a resist film (not shown) having a pattern that opens the opening H ₁ and the wiring formation region. ), And copper is plated by electrolytic plating using the resist film as a mask and the barrier metal film as a seed. Next, the resist film is removed, and the barrier metal film is etched away using copper as a mask. As a result, the first wiring 107 is formed integrally with the plug in the opening H ₁ . In this process, the inductance L is also patterned at the same time.

  Next, as shown in FIG. 12A, a semiconductor chip 108 previously formed in a separate process on the first insulating layer 106 and the first wiring 107 is bonded by a die attach film 109. A pad 108b is formed on the semiconductor chip 108 and is mounted face up.

Next, as shown in FIG. 12B, a photosensitive polyimide resin is supplied and applied by spin coating to form a second insulating layer 110.
Next, pattern exposure and development are performed on the second insulating film 110 to form an opening H ₂ reaching the pad 108 b of the semiconductor chip 108 and an opening H ₃ reaching the first wiring 107 in the second insulating film 110.
Next, in the same manner as the first wiring 107, the second wiring 111 is pattern-formed integrally with the plugs in the openings (H ₂ , H ₃ ).
At this time, the barrier metal film of the second wiring 111 is left without being etched for post formation in the next process.

Next, a photosensitive dry film is laminated on the second insulating layer 110 and the second wiring 111, and a post opening is formed by pattern exposure and development. Using this as a mask, a barrier metal film of the second wiring 111 is formed. A copper post 112 is formed in the opening by electrolytic plating using as a seed, and the dry film is peeled off and the barrier metal film is etched.
Further, an epoxy resin is supplied by spin coating and applied to form the buffer layer 113. After the resin is cured, the copper post 112 is cueed by grinding, and the bump 114 is formed so as to be connected to the post 112. To do.
Thus, the SiP-type semiconductor device having the configuration shown in FIG. 10 is formed.

In the above-described method for manufacturing a SiP-type semiconductor device, pattern exposure of the second insulating layer 110 for opening the opening H ₂ reaching the pad 108 b of the semiconductor chip 108 and the opening H ₃ reaching the first wiring 107 is performed by: Performed in a batch of wafers.
Therefore, the accuracy of the opening is determined by the gap from the mask, that is, the film thickness of the exposed photosensitive polyimide film. Therefore, there is a problem that an opening defect with respect to the opening H ₂ reaching the pad 108b of the semiconductor chip 108 occurs due to the inclination of the semiconductor chip in the Z direction and the variation in the thickness of the semiconductor chip.
In order to avoid this, if the exposure conditions are matched with the opening H ₂ reaching the pad 108b of the semiconductor chip 108 with a small gap, it becomes difficult to open the opening H ₃ reaching the first wiring 107 at the same time.
In particular, with the miniaturization and miniaturization of semiconductor devices, the size of wirings and electrodes has also been miniaturized. Semiconductor chip pads are also miniaturized, in order to cope with this becomes important to smaller aperture size of the aperture H ₂ reaching the pad 108b. For this reason, coexistence of the opening H ₂ reaching the pad 108 b of the semiconductor chip 108 and the opening H ₃ reaching the first wiring 107 tends to become more difficult. In order to solve this, if the opening size of the opening H ₃ reaching the first wiring 107 is set large, there is a problem that it is difficult to reduce the size of the entire SiP-type semiconductor device.

  The problem to be solved is that it is difficult to satisfactorily open the wiring and the pad of the semiconductor chip in the insulating layer formed by covering the wiring and the semiconductor chip in the semiconductor device of the SiP type. It is.

The semiconductor device of the present invention includes a substrate, a lower layer wiring formed on the substrate, an active element, a pad formed on the surface, and a semiconductor chip mounted on the substrate from the surface opposite to the pad forming surface. A conductive post formed on the lower layer wiring; an insulating resin layer formed to cover the semiconductor chip, the conductive post and the lower layer wiring; and the insulation to reach the pad of the semiconductor chip. A first opening opened in the resin layer; a second opening opened in the insulating resin layer so as to reach the conductive post; and the interior of the first opening and the second opening and the insulation. possess an upper layer wiring formed on the resin layer, the diameter of the bottom surface of the conductive post is formed larger than 10μm than the opening diameter of the second opening.

In the semiconductor device of the present invention described above, the lower layer wiring is formed on the substrate, and the semiconductor chip including the active element and having the pad formed on the surface is mounted from the surface opposite to the pad forming surface. Furthermore, a conductive post is formed on the lower layer wiring.
An insulating resin layer is formed so as to cover the semiconductor chip, the conductive post, and the lower layer wiring. The first opening is opened in the insulating resin layer so as to reach the pad of the semiconductor chip, while the conductive post reaches the conductive post. The second opening is opened, and the upper wiring is formed inside the first opening and the second opening and on the insulating resin layer.
Here, the diameter of the bottom surface of the conductive post is formed to be 10 μm or more larger than the opening diameter of the second opening.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a lower layer wiring on a substrate, a step of forming a conductive post on the lower layer wiring, and a semiconductor chip including an active element and having a pad formed on the surface. Mounting on the substrate from a surface opposite to the formation surface; covering the semiconductor chip, the conductive post and the lower layer wiring; forming an insulating resin layer; and reaching the pad of the semiconductor chip A step of opening one opening and a second opening reaching the conductive post into the insulating resin layer; and an upper layer wiring inside the first opening and the second opening and on the insulating resin layer possess and forming, in the step of forming the conductive posts, the conductive posts as the diameter of the bottom surface of said conductive posts is greater than 10μm than the opening diameter of the second opening Formation to.

In the method of manufacturing a semiconductor device according to the present invention, the lower layer wiring is formed on the substrate, and the conductive post is formed on the lower layer wiring.
Next, the semiconductor chip including the active element and having the pad formed on the surface is mounted from the surface opposite to the pad forming surface.
Next, an insulating resin layer is formed by covering the semiconductor chip, the conductive posts and the lower layer wiring, and the first opening reaching the pads of the semiconductor chip and the second opening reaching the conductive posts are opened in the insulating resin layer. Then, upper wiring is formed inside the first opening and the second opening and on the insulating resin layer.
Here, in the step of forming the conductive post, the conductive post is formed so that the diameter of the bottom surface of the conductive post is larger than the opening diameter of the second opening by 10 μm or more.

  In the semiconductor device of the present invention, since the opening for the conductive post is opened in the insulating resin layer instead of the opening for the lower layer wiring, the difference between the gap in the conductive post portion and the gap in the pad portion of the semiconductor chip. Is relaxed by the height of the conductive posts. As a result, both the opening in the conductive post portion for connection to the lower layer wiring and the opening reaching the pad of the semiconductor chip are made favorable.

  In the method of manufacturing a semiconductor device according to the present invention, the difference between the gap in the conductive post portion and the gap in the pad portion of the semiconductor chip is opened by relaxing the height of the conductive post. Both the opening at the conductive post portion and the opening reaching the pad of the semiconductor chip can be satisfactorily performed.

  Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment.
For example, a base insulating film 11 made of silicon oxide is formed on a silicon substrate 10, and a lower electrode 12 made of, for example, aluminum or copper, Ta ₂ O ₅ , BST, PZT, BaTiO ₃ , silicon nitride, polyimide resin is formed thereon. Alternatively, a dielectric film 13 made of silicon oxide or the like, and a lower electrode take-out electrode 14a and an upper electrode 14b made of aluminum or copper are laminated so that the lower electrode 12 and the upper electrode 14b face each other with the dielectric film 13 in between. The part which becomes is an electrostatic capacitance element (C _a , C _b ).

A first insulating layer 15 made of polyimide resin, epoxy resin, acrylic resin or the like is formed so as to cover the capacitive element.
The first insulating layer 15 has openings reaching the lower electrode extraction electrode 14a and the upper electrode 14b, and is integrated with a plug portion embedded in the opening and connected to the lower electrode extraction electrode 14a and the upper electrode 14b. Thus, the first wiring 16 composed of the barrier metal layer 16 a and the copper layer 16 b is formed on the first insulating layer 15.
A part of the first wiring 16 is formed in a spiral shape, and an inductance (L _a , L _b ) is configured.

In addition, a second insulating layer 17 made of the same polyimide resin as the first insulating layer 15 is formed so as to cover the first wiring 16, and an opening reaching the first wiring 16 is formed. A second wiring 18 composed of a barrier metal layer 18 a and a copper layer 18 b is formed on the second insulating layer 17 so as to be integrated with the plug portion embedded and connected to the first wiring 16.
A part of the second wiring 18 is formed in a spiral shape, and an inductance L _c is configured.

Further, a third insulating layer 19 made of the same polyimide resin as that of the first insulating layer 15 is formed so as to cover the second wiring 18, and an opening reaching the second wiring 18 is formed. A third wiring 20 including a barrier metal layer 20a and a copper layer 20b is formed on the third insulating layer 19 so as to be integrated with a plug portion that is buried and connected to the second wiring 18.
A part of the third wiring 20 is formed in a spiral shape, and an inductance (L _d , _Le ) is configured.

A semiconductor chip 21 provided with active elements is bonded to the upper layer of the third insulating layer 19 and the third wiring 20 by a die attach film 22. The semiconductor chip 21 has a structure in which a pad 21b is formed on a semiconductor body portion 21a, and a region excluding the pad 21b is covered with a silicon oxide protective layer 21c, and is face-up, that is, on the opposite side of the pad 21b formation surface. Mounted from the front side.
On the other hand, the upper layer of the third wiring 20, for example, the first conductive posts P _C of the columnar composed of a conductive material such as copper is formed.

The third wiring 20, the semiconductor chip 21 and the fourth insulating layer 23 of the first conductive post P _C covers made of the same polyimide resin as the first insulating layer 15 is formed.
The fourth insulating layer 23, the second opening H _b reaching the first opening H _a and the conductive posts P _C reaches the pad 21b of the semiconductor chip 21 is formed.
The first and second opening of the (H _a, H _b) embedded within turned plug portion integrally connecting the pads 21b and the conductive posts P _C, a barrier metal layer on the fourth insulating layer 23 A fourth wiring 24 composed of 24a and a copper layer 24b is formed.

A second conductive post 25 made of copper or the like is formed in connection with the fourth wiring 24, and a polyamide-imide resin, a polyimide resin, an epoxy resin, a phenol resin or an upper layer of the fourth insulating layer 23 in the gap is formed. An insulating buffer layer 26 made of polyparaphenylene benzobisoxazole resin or the like is formed.
Further, bumps (projection electrodes) 27 are formed on the surface of the buffer layer 26 so as to be connected to the second conductive posts 25.

In the present embodiment, for example, the first wiring 16, the second wiring 18, and the third wiring 20 formed below the conductive post (first conductive post P _C ) are referred to as a lower layer wiring. Wirings such as the fourth wiring 24 formed above the conductive posts (first conductive posts P _C ) are referred to as upper layer wirings.
In the semiconductor device of the present embodiment, the lower layer wiring (first wiring 16, second wiring 18, and third wiring 20) as described above is formed on the silicon substrate 10, and the semiconductor chip 21 is mounted face up. In addition, a conductive post (first conductive post P _C ) is formed on the lower layer wiring, and covers the semiconductor chip, the conductive post and the lower layer wiring, and an insulating resin layer (fourth insulating layer 23). In the insulating resin layer, the first opening _Ha is opened so as to reach the pad 21b of the semiconductor chip 21, while the first opening Ha is reached so as to reach the conductive post (first conductive post P _C ). Two openings _Hb are opened, and the upper wiring (fourth wiring 24) is formed inside the first opening and the second opening and on the insulating resin layer.

According to the semiconductor device of the present embodiment described above, since the opening for the conductive post is opened in the insulating resin layer instead of the opening for the lower layer wiring, the gap in the conductive post portion and the pad portion of the semiconductor chip The difference from the gap is reduced by the height of the conductive post. As a result, both the opening in the conductive post portion for connection to the lower layer wiring and the opening reaching the pad of the semiconductor chip are made favorable.
In the connection method using the conductive posts (first conductive posts P _C ) as described above, wiring with high thermal conductivity can be provided, and can be preferably applied to, for example, wiring connected to a power supply or ground.

In the semiconductor device of the present embodiment, preferably, the conductive posts (first conductive posts P _C ) and the conductive posts (first conductive posts P _C ) and the pads 21 b of the semiconductor chip 21 have substantially the same height. The height of the first conductive post P _C ) is set.
By having substantially the same height, the gap in the conductive post portion and the gap in the pad portion of the semiconductor chip become substantially equal, and the opening for both portions is made good.

The conductive post (first conductive post P _C ) is preferably cylindrical or octagonal. Thus, it is possible to prevent or reduce the voids are formed when forming a fourth insulating layer 23 to cover the first conductive posts P _C in the manufacturing process.
The aspect ratio of the conductive post (first conductive post P _C ) is preferably 1 or less. It is possible to prevent or reduce a first conductive posts P _C is or fall, voids are formed in forming the fourth insulating layer 23 in the manufacturing process.
The diameter of the bottom surface of the conductive posts (first conductive post P _C) is, 10 [mu] m than the opening diameter of the second opening H _b which is opened so as to reach the conductive posts (first conductive post P _C) It is preferable that it is formed larger. Thereby, in the opening process of the 2nd opening part _Hb , the misalignment allowance of 5 micrometers per radius can be ensured.

Further, it is preferable that a part of the wiring including the lower layer wiring and the upper layer wiring constitutes a passive element. Capacitive element (C _a, C _b) by combining passive devices such as and the inductance (L _a ~L _e), for example, LPF (Low Pass Filter), BPF (Band Pass Filter) or HPF (High Pass Filter) In addition, a so-called SiP-type semiconductor device can be configured by combining these with active elements provided on the semiconductor chip 21. For example, the number of wiring layers constituting the passive element can be provided in accordance with the number of necessary filters.
Here, as in the present embodiment, for example, a plurality of resin layers (first insulating layer 15, second insulating layer 17, third insulating layer) between the silicon substrate 10 and the insulating resin layer (fourth insulating layer 23), for example. A lower insulating resin layer formed of a layered body of layer 19) is formed, and a passive element embedded in the lower insulating resin layer is formed as a configuration in which a part of the lower wiring is embedded in the lower insulating resin layer. It can consist of a part of lower layer wiring.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. In the present embodiment, for example, all processes shown in FIGS. 2 to 9 can be performed at the wafer level.
First, as shown in FIG. 2A, silicon oxide is formed on the silicon substrate 10 by, for example, a CVD (chemical vapor deposition) method or a thermal diffusion method to form the base insulating film 11.

Next, as shown in FIG. 2B, for example, aluminum or copper is deposited by sputtering or the like, and patterned to form the lower electrode 12.
Next, for example, Ta ₂ O ₅ , BST, PZT, BaTiO ₃ , silicon nitride or silicon oxide is deposited by CVD or the like, or polyimide resin is applied by spin coating or the like to form the dielectric film 13. Then, the lower electrode outlet is opened in the obtained dielectric film 13.
Next, for example, aluminum or copper is deposited by sputtering or the like, and patterned to form a lower electrode take-out electrode 14a and an upper electrode 14b.
Capacitance elements (C _a , C _b ) in which the lower electrode 12 and the upper electrode 14 b face each other through the dielectric film 13 are configured.

Next, as shown in FIG. 2C, a photosensitive insulating material such as polyimide resin, epoxy resin, or acrylic resin is supplied by, eg, spin coating, and the first insulating layer 15 is formed to a thickness of 10 μm. Form.
In the case of a photosensitive polyimide resin, for example, the film is formed under the following conditions.
Spin coating: 50 rpm (1 second) + 50 rpm (20 seconds) + 300 rpm (5 seconds) + 1000 rpm (10 seconds)
Pre-bake: 90 ° C (120 seconds) + 100 ° C (120 seconds) + room temperature (30 seconds)

Next, pattern exposure and development are performed at an exposure amount of 150 mJ, and an opening reaching the extraction electrode 14 a and the upper electrode 14 b of the lower electrode is formed in the first insulating layer 15. The aspect ratio of the opening is set to 1.7 or less in consideration of the coverage of seed sputtering in the next process.
After the development, for example, the first insulating layer 15 is cured (cured) under the following conditions.
Post cure: 150 ° C. (20 minutes) + 150 ° C. (30 minutes) + 300 ° C. (20 minutes) + 300 ° C. (120 minutes)

Next, as shown in FIG. 3A, for example, TiCu or CrCu is formed by seed sputtering, the inner wall of the opening formed in the first insulating layer 15 is covered, and the barrier metal layer 16a is formed on the entire surface. Form and treat with O ₂ asher (300 W) for 5 minutes.

  Next, as shown in FIG. 3B, for example, in order to prevent plating other than the opening formed in the first insulating layer 15 and the formation region of the first wiring, resist coating and development processing are performed. Then, a resist film R1 having a pattern that opens the opening formed in the first insulating layer 15 and the formation region of the first wiring is formed.

  Next, as shown in FIG. 3C, for example, the film thickness on the first insulating layer 15 is obtained by 1.5 A, 90 minutes of electrolytic plating using the resist film as a mask and the barrier metal layer 16a as a seed. Is plated to have a thickness of about 5 μm to form a copper layer 16b in the opening formed in the first insulating layer 15 and the first wiring formation region.

Next, as shown in FIG. 4A, the resist film R1 is removed by, for example, ashing, and the barrier metal layer 16a is etched using the copper layer 16b as a mask, as shown in FIG. 4B. To do. In order to prevent undercut in this seed etching, the overlap portion of the opening formed in the first insulating layer 15 and the pattern of the resist film R1 is at least 5 μm.
As described above, the first wiring 16 including the barrier metal layer 16a and the copper layer 16b is formed on the first insulating layer 15 integrally with the plug portion connected to the lower electrode extraction electrode 14a and the upper electrode 14b. At this time, the inductance (L _a , L _b ), which is one of the passive elements, is simultaneously patterned as part of the first wiring 16.

Next, the formation of the wiring by the semi-additive method as described above is repeated three times, three insulating films are stacked, and wiring is formed in each layer. That is, after the steps of forming the first insulating film 15, opening the opening with respect to the first insulating film 15, and forming the first wiring 16, forming the second insulating film 17 and opening the opening with respect to the second insulating film 17 are performed. Each process of forming the opening, forming the second wiring 18, forming the third insulating film 19, opening the opening with respect to the third insulating film 19, and forming the third wiring is performed, and the state shown in FIG. To do.
When forming the second wiring 18, the inductance L _c, which is one of the passive elements, is simultaneously formed as a part of the second wiring 18.
However, in the step of forming the third wiring, when the barrier metal layer 20a film formation, the resist film pattern formation, the copper layer 20b formation by electrolytic plating, and the removal of the resist film are completed, that is, The step of removing the barrier metal layer 20a along the pattern of the third wiring is left without being performed, and the process proceeds to the next step. This is because the barrier metal layer 20a is also used in the process of forming the first conductive post in the next process.

  Next, as shown in FIG. 5B, for example, in order to prevent plating outside the formation region of the first conductive post, resist coating and development processing are performed to form the first conductive post. A resist film R2 having a pattern opening the region PP is formed.

Next, as shown in FIG. 6A, for example, copper is plated by electrolytic plating using the barrier metal layer 20a using the resist film R2 as a mask, and the opening of the resist film R2 is made of a columnar column made of copper. forming a first conductive posts P _C. Thereafter, the resist film R2 is removed.

Next, as shown in FIG. 6 (b), for example, a barrier metal layer 20a is etched a first conductive posts P _C and the copper layer 20b as a mask. Thereby, the 3rd wiring 20 which consists of barrier metal layer 20a and copper layer 20b is formed. At this time, the inductance (L _d , _Le ), which is one of the passive elements, is simultaneously patterned as part of the third wiring 20.

Next, as shown in FIG. 7A, for example, a semiconductor chip 21 having an active element previously formed in a separate process up to a thin singulation step on the third insulating layer 19 and the third wiring 20. Mount.
The semiconductor chip 21 has a structure in which a pad 21b is formed on a semiconductor body portion 21a, and a region excluding the pad 21b is covered with a silicon oxide protective layer 21c, and is face-up, that is, on the opposite side of the pad 21b formation surface. From the surface side, they are laminated via the die attach film 22 and bonded at a temperature of 60 to 70 ° C. with a load of 1.0 to 1.3 N for 0.7 to 1 second. By offsetting the alignment mark provided on the mounting surface of the semiconductor chip 21 and the electrode of the semiconductor chip 21 from the tool, it can be recognized by one camera. For example, it can be mounted with a mounting accuracy of ± 1 μm.

Next, as shown in FIG. 7B, a fourth insulating layer 23 is formed by supplying a photosensitive insulating material such as polyimide resin, epoxy resin, or acrylic resin by, for example, spin coating. For example, be formed after curing so as to be for example 50μm thickness, this may be a thickness such as to cover the semiconductor chip 21 and the first conductive post P _C.
In the case of a photosensitive polyimide resin, for example, the film is formed under the following conditions.
Viscosity of uncured photosensitive polyimide resin: 31.5 Pa · s
Spin coating: 50 rpm (1 second) + 50 rpm (30 seconds) + 300 rpm (30 seconds) + 1200 rpm (20 seconds)
Pre-bake: 60 ° C (240 seconds) + 90 ° C (240 seconds) + 110 ° C (240 seconds) + room temperature (30 seconds)

Next, pattern exposure and development with an exposure amount 150 mJ, a second opening H _b reaching the first opening H _a and the first conductive post P _C reaches the pad 21b of the semiconductor chip 21 in the fourth insulating layer 23 Form.
After the development, for example, the fourth insulating layer 23 is cured (cured) under the following conditions.
Post cure: 150 ° C. (20 minutes) + 150 ° C. (30 minutes) + 300 ° C. (20 minutes) + 300 ° C. (120 minutes)

For example, if the thickness of the third wiring 20 is about 5 μm and the thickness of the adhesive layer portion of the die attach film 22 is about 12.5 μm, the die attach film 22 is deformed with respect to the unevenness of the third wiring 20. Therefore, the position of the pad 21b of the semiconductor chip 21 is about the thickness of the semiconductor chip 21 +15 μm from the surface of the third insulating layer 19.
Therefore, in order to adjust the height of the first conductive post P _C of the surface and the surface of the pad 21b of the semiconductor chip 21 having a thickness formed on the upper layer of the third wiring 20 of about 5μm, the first conductive post P The height of _C is preferably matched with the thickness of the semiconductor chip 21 plus about 10 μm.
For example, when the thickness of the semiconductor chip 21 is about 25μm, the height of the first conductive post P _C to about 35 [mu] m, when the thickness of the semiconductor chip 21 is about 50μm, the first conductive post the height of the P _C to be about 60μm. Height variation in the wafer surface of the first conductive post P _C is about ± 2.5%. Target value for the height of the first conductive post P _C, it is needless to say that changes depending on the thickness of the wiring and a die attach film.
When the height of the surface of the first conductive post P _{C and} the surface of the pad 21b of the semiconductor chip 21 are substantially matched as described above, the gap between the pad 21b portion of the semiconductor chip 21 and the first conductive post P _C portion ( The thickness of the fourth insulating layer 23 in both portions) is substantially the same value. In this embodiment, for example, the gap in the pad 21b portion of the semiconductor chip 21 is 7 to 13 μm (average of about 10 μm), and the first conductivity The gap in the portion of the post P _C is 7 to 13 μm (average is about 10 μm), and both have the same value of about 10 μm.
At this time, the second opening H _b reaching the first opening H _a and the first conductive post P _C reaches the pad 21b of the semiconductor chip 21, which may be satisfactorily opened in diameter, for example 30μm .

In the step of forming the first conductive post P _C above, it is preferably formed as a cylindrical shape or an octagonal prism shape. Thus, it is possible to prevent or reduce the voids are formed when forming a fourth insulating layer 23 to cover the first conductive posts P _C.
Further, in the step of forming the first conductive post P _C above, that the aspect ratio of the first conductive posts P _C is formed to be 1 or less preferred. It is possible to prevent or reduce a first conductive posts P _C is or fall, voids are formed in forming the fourth insulating layer 23 in the manufacturing process.
Further, in the step of forming the first conductive post P _C, the opening diameter of the second opening H _b the diameter of the bottom surface of the first conductive posts P _C is opened so as to reach the first conductive post P _C It is preferable to form it larger than 10 μm. Thereby, in the opening process of the 2nd opening part _Hb , the misalignment allowance of 5 micrometers per radius can be ensured.

Next, as shown in FIG. 8 (a), for example, by forming a TiCu or CrCu by seed sputtering, reaches the first opening H _a and the first conductive post P _C reaches the pad 21b of the semiconductor chip 21 The inner wall of the second opening _Hb is covered to form a barrier metal layer 24a on the entire surface, and is treated with O ₂ asher (300 W) for 5 minutes.
Next, the resist coating and developing processing, opening a second opening H _b and forming region of the fourth wiring reaching the first opening H _a and the first conductive post P _C reaches the pad 21b of the semiconductor chip 21 A resist film (not shown) having a pattern to be formed is formed, using this as a mask, copper is plated at a thickness of 5 μm by electrolytic plating of 1.5 A and 90 minutes using the barrier metal layer 24a as a seed, and a semiconductor chip and a second opening H _b reaching the first opening H _a and the first conductive post P _C reaches 21 of the pad 21b forming region of the fourth wiring forming the copper layer 24b. Thereafter, the resist film is removed.

Next, for example, a photosensitive dry film is bonded or a resist film is formed, pattern exposure and development are performed to form an opening for the second conductive post, and electrolytic plating of copper using the barrier metal film 24a Thus, the second conductive post 25 having a height of 100 μm and a diameter of 150 μm is formed.
Next, the dry film or resist film is removed, and the barrier metal layer 24a is etched using the second conductive posts 25 and the copper layer 24b as a mask. Thereby, the 4th wiring 24 which consists of barrier metal layer 24a and copper layer 24b is formed.

Next, as shown in FIG. 9A, for example, a polyamide imide resin, a polyimide resin, an epoxy resin, a phenol resin, or a polyparaphenylene benzobisoxazole resin is formed by spin coating or printing, and the film thickness is 120 μm. Thus, the insulating buffer layer 26 is formed.
For example, when printing a polyamideimide resin, the viscosity of the resin is 138 Pa · s, and printing is performed at a squeegee speed of 10 mm / s.

  Next, as shown in FIG. 9B, after the resin hardening of the buffer layer 26, cueing of the second conductive post 25 is performed by grinding. The conditions at this time are, for example, a # 600 grindstone, a spindle rotation speed of 1500 rpm, and a feed rate (0.2 mm / s + 0.1 mm / s).

Next, bumps (projection electrodes) 26 are formed so as to be connected to the second conductive posts 25 by, for example, solder ball mounting, LGA, or solder bump printing.
In the case of printing solder bumps, for example, lead-free solder is printed with a diameter of 0.2 mm and reflowed at a temperature of 260 ° C. or lower to form bumps.
After that, for example, the silicon substrate 10 is half-cut and diced by thinning, thereby having secondary connection reliability and having a buffer layer that can relieve stress, and therefore can be repaired without an underfill. A wafer-level SiP semiconductor device having the configuration shown in FIG. 1 can be obtained.

According to the manufacturing method of the semiconductor device according to the above-described embodiment, the difference between the gap in the conductive post (first conductive post P _C ) portion and the gap in the pad 21 b portion of the semiconductor chip 21 is calculated as the conductive post ( Since the opening is relaxed by the height of the first conductive post P _C ), the conductive post (first conductive post) for connecting to the lower layer wiring (first wiring 16, second wiring 18, and third wiring 20) is formed. Both the opening at the portion of the conductive post P _C ) and the opening reaching the pad 21 b of the semiconductor chip 21 can be performed satisfactorily.

Furthermore, the semiconductor device according to the present embodiment can enjoy the following effects.
(1) Even if the semiconductor chip incorporated in the insulating resin layer varies in thickness, a stable opening to the pad is possible.
(2) Even when there is an inclination in the Z direction when the semiconductor chip built in the insulating resin layer is mounted, a stable opening to the pad is possible.
(3) A stable opening to the pad of the semiconductor chip built in the insulating resin layer can be achieved without limiting exposure such as contact, proximity, and stepper.
(4) The semiconductor chip pad can be reduced to 40 μm and the pitch can be reduced to 60 μm, so that the semiconductor chip can be reduced in size and reduced, and the cost can be reduced by improving the theoretical yield.

The present invention is not limited to the above description.
For example, the height of the surface of the conductive post (first conductive post) is preferably matched with the surface of the pad of the semiconductor chip, but is not necessarily limited thereto. The effect of the present invention can be obtained if the difference between the gap of the conductive post (first conductive post) portion and the gap of the pad portion of the semiconductor chip can be reduced.
In addition, although three-layer wiring (first wiring, second wiring, and third wiring) is formed as the lower-layer wiring, the present invention is not limited to this, and at least one lower-layer wiring may be provided.
The resin used for the buffer layer and the first to fourth insulating layers is not limited to the above, and other resins can also be used.
In addition, various modifications can be made without departing from the scope of the present invention.

  The semiconductor device of the present invention can be applied to a semiconductor device in a system in package form.

  The semiconductor device manufacturing method of the present invention can be applied to a system-in-package semiconductor device manufacturing method.

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2A to 2C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 3A to 3C are cross-sectional views illustrating the manufacturing process of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 4A and FIG. 4B are cross-sectional views showing manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 5A and FIG. 5B are cross-sectional views showing manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 6A and FIG. 6B are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 7A and FIG. 7B are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the embodiment of the present invention. FIG. 8A and FIG. 8B are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 9A and FIG. 9B are cross-sectional views showing manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 10 is a cross-sectional view of a conventional semiconductor device. 11A to 11C are cross-sectional views illustrating manufacturing steps of a conventional method for manufacturing a semiconductor device. 12 (a) and 12 (b) are cross-sectional views showing manufacturing steps of a method for manufacturing a semiconductor device according to a conventional example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 11 ... Base insulating film, 12 ... Lower electrode, 13 ... Dielectric film, 14a ... Lower electrode taking-out electrode, 14b ... Upper electrode, 15 ... 1st insulating layer, 16 ... 1st wiring, 16a, 18a , 20a, 24a ... barrier metal layer, 16b, 18b, 20b, 24b ... copper layer, 17 ... second insulating layer, 18 ... second wiring, 19 ... third insulating layer, 20 ... third wiring, 21 ... semiconductor chip 21a ... Semiconductor body part, 21b ... Pad, 21c ... Protective layer, 22 ... Die attach film, 23 ... Fourth insulating layer, 24 ... Fourth wiring, 25 ... Second conductive post, 26 ... Buffer layer, 27 ... Bump, P _C ... first conductive post, C _a , C _b ... capacitance element, L _a , L _b , L _c , L _d , L _e ... inductance, H _a ... first opening, H _b ... Second opening, 100 ... silicon substrate, 101 ... base Edge film, 102 ... lower electrode, 103 ... dielectric film, 104 ... protective layer, 105a ... lower electrode take-out electrode, 105b ... upper electrode, 106 ... first insulating layer, 107 ... first wiring, 108 ... semiconductor chip, 108a ... Semiconductor body part 108b ... Pad 108c ... Protective layer 109 ... Die attach film 110 ... Second insulating layer 111 ... Second wiring 112 ... Post 113 113 Buffer layer 114 ... Bump C ₁ , C ₂ ... capacitance device, L ... inductance, H ₁ to H ₃ ... opening.

Claims (11)

A substrate,
Lower layer wiring formed on the substrate;
A semiconductor chip including an active element, having a pad formed on the surface, and mounted on the substrate from a surface opposite to the pad forming surface;
A conductive post formed on the lower layer wiring;
An insulating resin layer formed to cover the semiconductor chip, the conductive post and the lower layer wiring;
A first opening opened in the insulating resin layer so as to reach the pad of the semiconductor chip;
A second opening opened in the insulating resin layer to reach the conductive post;
Possess an upper layer wiring formed therein and the insulating resin layer of said first opening and said second opening,
The diameter of the bottom face of the conductive post is a semiconductor device formed to be 10 μm or more larger than the opening diameter of the second opening . The semiconductor device according to claim 1, wherein a height of the conductive post is set so that a surface of the conductive post and a surface of the pad have substantially the same height. The semiconductor device according to claim 1, wherein the conductive post has a cylindrical shape or an octagonal prism shape. The semiconductor device according to claim 1, wherein an aspect ratio of the conductive post is 1 or less. The semiconductor device according to claim 1, wherein a part of the wiring including the lower layer wiring and the upper layer wiring forms a passive element. The semiconductor device according to claim 1, wherein a lower insulating resin layer is formed between the substrate and the insulating resin layer, and a part of the lower wiring is embedded in the lower insulating resin layer. The semiconductor device according to claim 6 , wherein the lower insulating resin layer includes a laminate of a plurality of resin layers. Forming a lower layer wiring on the substrate;
Forming a conductive post on the lower layer wiring; and
Mounting a semiconductor chip including an active element and having a pad formed on the surface thereof from the surface opposite to the pad forming surface;
Forming an insulating resin layer by covering the semiconductor chip, the conductive post and the lower layer wiring;
Opening a first opening reaching the pad of the semiconductor chip and a second opening reaching the conductive post in the insulating resin layer;
Have a forming an upper wiring on the first internal opening and the second opening and the insulating resin layer,
A method of manufacturing a semiconductor device , wherein in the step of forming the conductive post, the conductive post is formed so that a diameter of a bottom surface of the conductive post is larger than an opening diameter of the second opening by 10 μm or more . In the step of forming the conductive posts, as with the conductive posts of the surface and the surface of the pad is substantially the same height, according to claim 8 which is formed by setting the height of the conductive posts A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 8 , wherein in the step of forming the conductive post, the conductive post is formed in a cylindrical shape or an octagonal prism shape. The method for manufacturing a semiconductor device according to claim 8 , wherein in the step of forming the conductive post, the conductive post is formed so that an aspect ratio is 1 or less.

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