JP2007103716A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2007103716A
JP2007103716A JP2005292419A JP2005292419A JP2007103716A JP 2007103716 A JP2007103716 A JP 2007103716A JP 2005292419 A JP2005292419 A JP 2005292419A JP 2005292419 A JP2005292419 A JP 2005292419A JP 2007103716 A JP2007103716 A JP 2007103716A
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semiconductor
insulating layer
layer
semiconductor device
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Osamu Yamagata
修 山形
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Sony Corp
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
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    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of realizing microfabrication of re-wiring connected to a semiconductor chip in the semiconductor device of a SiP mode in which the semiconductor chip is buried in an insulated film, and to provide a manufacturing method thereof. <P>SOLUTION: The semiconductor device is packaged so as to include a semiconductor provided with an electronic circuit. In this device, semiconductor chips (1a, 1b) having semiconductor bodies (10a, 10b) each having an electronic circuit formed thereon, and having pad electrodes (11a, 11b) formed on the semiconductor bodies are mounted on a substrate 20 from the rear surface side of the forming surface of the projection electrodes. The semiconductor chip is buried to form a first insulation layer 22. First wirings (seed layer 23, copper layer 25) are formed on an upper layer of a first insulated layer so as to be connected to the pad electrode piercing the first insulated layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置及びその製造方法に関し、特に、ウェハレベルでパッケージ化されたシステムインパッケージ（ＳｉＰ）と呼ばれる形態の半導体装置及びその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in a form called a system in package (SiP) packaged at a wafer level and a manufacturing method thereof.

デジタルビデオカメラ、デジタル携帯電話、あるいはノートパソコンなど、携帯用電子機器の小型化、薄型化、軽量化に対する要求は強くなる一方であり、これに応えるために近年のＶＬＳＩなどの半導体装置においては３年で７割の縮小化を実現してきた一方で、このような半導体装置をプリント配線基板上に実装した電子回路装置としても、実装基板（プリント配線基板）上の部品の実装密度をいかに向上させるかが重要な課題として研究及び開発がなされてきた。   The demand for downsizing, thinning, and weight reduction of portable electronic devices such as digital video cameras, digital mobile phones, and notebook personal computers has been increasing. While 70% reduction has been achieved year by year, how to improve the mounting density of components on the mounting board (printed wiring board) even in an electronic circuit device in which such a semiconductor device is mounted on the printed wiring board Research and development has been made as an important issue.

例えば、半導体装置のパッケージ形態としては、ＤＩＰ（Dual Inline Package）などのリード挿入型から表面実装型へと移行し、さらには半導体チップのパッド電極にはんだや金などからなるバンプ（突起電極）を設け、フェースダウンでバンプを介して配線基板に接続するフリップチップ実装法が開発された。   For example, the package form of a semiconductor device has shifted from a lead insertion type such as DIP (Dual Inline Package) to a surface mount type, and furthermore, bumps (projection electrodes) made of solder, gold, etc. are applied to pad electrodes of a semiconductor chip. A flip-chip mounting method has been developed in which a face-down connection is made to the wiring board through bumps.

さらに、半導体基板（チップ）上に形成される配線（再配線とも称する）を絶縁する絶縁層の層間に、能動素子を含む電子回路などが形成された半導体チップや、静電容量素子及びコイルなどの受動素子が埋め込まれ、ウェハレベルでパッケージ化されたシステムインパッケージ（ＳｉＰ）と呼ばれる複雑な形態のパッケージへと開発が進んでいる。
上記のＳｉＰの構成や製造方法は、例えば特許文献１〜３に開示されている。 Further, a semiconductor chip in which an electronic circuit including an active element is formed between layers of an insulating layer that insulates wiring (also referred to as rewiring) formed on a semiconductor substrate (chip), a capacitive element, a coil, and the like Development of a package having a complicated form called a system-in-package (SiP) packaged at the wafer level and embedded with the passive elements is progressing.
The configuration and manufacturing method of the above SiP are disclosed in, for example, Patent Documents 1 to 3.

上記の能動素子を有する半導体チップが絶縁層中に埋め込まれているタイプのウェハレベルＳｉＰの製造方法としては、例えば、基板上に半導体チップを搭載し、スピンコートもしくは印刷などで感光性の樹脂で半導体チップを埋め込んで絶縁層を形成し、得られた絶縁層を露光及び現像によりパターニングして半導体チップのパッド電極を開口し、メッキ処理などで開口部内に導電層を埋め込んで再配線層を形成する。   As a method for manufacturing a wafer level SiP of a type in which a semiconductor chip having the active element is embedded in an insulating layer, for example, a semiconductor chip is mounted on a substrate, and a photosensitive resin is used by spin coating or printing. An insulating layer is formed by embedding a semiconductor chip, the resulting insulating layer is patterned by exposure and development to open pad electrodes of the semiconductor chip, and a conductive layer is embedded in the opening by plating or the like to form a rewiring layer To do.

上記のＳｉＰの製造方法では、半導体チップを埋め込んでいる樹脂からなる絶縁層を形成する工程において、５０μｍ以上の厚さで絶縁層の形成を行うには高粘度の樹脂が必要でスピンコートの１回の塗布での膜厚は最大１００μｍが限界であり、例えば数１００μｍの半導体チップの板厚に合わせて絶縁層を厚く形成する場合には、１回塗布するごとに仮乾燥を行い、１度目の層が２度目の塗布工程で溶解するのを防止して膜厚を確保する必要がある。   In the above SiP manufacturing method, in the step of forming an insulating layer made of a resin in which a semiconductor chip is embedded, a high-viscosity resin is required to form an insulating layer with a thickness of 50 μm or more. The maximum film thickness is 100 μm for each application. For example, when the insulating layer is formed thick in accordance with the thickness of a semiconductor chip of several hundreds μm, temporary drying is performed for each application. It is necessary to prevent the layer from being dissolved in the second coating step and to secure the film thickness.

上記のようにして厚い半導体チップを樹脂の絶縁層で埋め込んだ工程の後、半導体チップのパッド電極を開口するようにパターニングするための露光工程において、露光量は露光すべき樹脂絶縁膜の膜厚に応じて大きくしなければならない。この結果、露光量を大きくすることに起因してパターン潰れが発生してしまい、安定したパターニングを行うことが困難となる。   After the process of embedding a thick semiconductor chip with a resin insulating layer as described above, in the exposure process for patterning to open the pad electrode of the semiconductor chip, the exposure amount is the film thickness of the resin insulating film to be exposed It must be enlarged according to. As a result, pattern collapse occurs due to an increase in exposure amount, and it becomes difficult to perform stable patterning.

上記の理由により、安定したパターニングを行うためには樹脂層の膜厚は制限され、これを実現するために埋め込む半導体チップの板厚を５０μｍ程度にまで薄型化する必要がある。   For the above reasons, the thickness of the resin layer is limited in order to perform stable patterning, and in order to realize this, it is necessary to reduce the thickness of the embedded semiconductor chip to about 50 μm.

上記の構成において、樹脂絶縁膜中に半導体チップを埋め込んだ領域と埋め込んでいない領域とでは樹脂絶縁膜表面の段差は、樹脂絶縁膜が７０μｍ程度の膜厚の場合、１５〜２０μｍ程度となる。このため、後工程で形成する再配線の段切れを防止するにはメッキ用レジストの膜厚は１０〜２０ミクロン塗布する必要があり、従ってレジストの解像度は３０μｍが限界となってしまう。
従って、更なる微細な再配線形成のため、再配線形成時のメッキ用レジストの薄膜化を実現することが必要となっている。
特開２００５−１７５４０２号公報 特開２００５−１７５３２０号公報 特開２００５−１７５３１９号公報 In the above configuration, the step on the surface of the resin insulating film between the region where the semiconductor chip is embedded in the resin insulating film and the region where the semiconductor chip is not embedded is about 15 to 20 μm when the resin insulating film has a thickness of about 70 μm. For this reason, in order to prevent rewiring from being disconnected in a subsequent process, it is necessary to apply a plating resist with a thickness of 10 to 20 microns. Therefore, the resist resolution is limited to 30 μm.
Therefore, in order to form a finer rewiring, it is necessary to reduce the thickness of the plating resist when forming the rewiring.
JP 2005-175402 A JP 2005-175320 A JP 2005-175319 A

本発明の目的は、半導体チップが絶縁膜中に埋め込まれているＳｉＰ形態の半導体装置において、半導体チップに接続されている再配線の微細化が実現できる半導体装置及びその製造方法を提供することである。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a semiconductor chip is embedded in an insulating film and in which a rewiring connected to the semiconductor chip can be miniaturized and a method for manufacturing the same. is there.

上記の課題を解決するため、本発明の半導体装置は、電子回路が設けられた半導体を含んでパッケージ化された半導体装置であって、基板と、前記電子回路が形成された半導体本体と、前記半導体本体上に形成されたパッド電極とを有し、前記パッド電極の形成面の裏面側から前記基板にマウントされた半導体チップと、前記半導体チップを埋め込んで形成され、表面が平坦化された第１絶縁層と、前記第１絶縁層を貫通して前記パッド電極に接続し、前記第１絶縁層の上層に形成された第１配線とを有する。   In order to solve the above problems, a semiconductor device of the present invention is a packaged semiconductor device including a semiconductor provided with an electronic circuit, and includes a substrate, a semiconductor body on which the electronic circuit is formed, A semiconductor chip mounted on the substrate from the back side of the pad electrode forming surface, and a semiconductor chip embedded in the semiconductor chip, and the surface is planarized. A first insulating layer; and a first wiring that penetrates the first insulating layer and is connected to the pad electrode and is formed in an upper layer of the first insulating layer.

上記の本発明の半導体装置は、電子回路が設けられた半導体を含んでパッケージ化された半導体装置であって、電子回路が形成された半導体本体と半導体本体上に形成されたパッド電極とを有する半導体チップが、パッド電極の形成面の裏面側から基板にマウントされており、半導体チップを埋め込んで表面が平坦化された第１絶縁層が形成されており、第１絶縁層を貫通してパッド電極に接続するように第１絶縁層の上層に第１配線が形成されている。   The semiconductor device according to the present invention is a semiconductor device packaged including a semiconductor provided with an electronic circuit, and includes a semiconductor body in which the electronic circuit is formed and a pad electrode formed on the semiconductor body. A semiconductor chip is mounted on a substrate from the back side of the pad electrode forming surface, a first insulating layer having a flattened surface is formed by embedding the semiconductor chip, and a pad is formed through the first insulating layer. First wiring is formed in the upper layer of the first insulating layer so as to be connected to the electrode.

また、上記の課題を解決するため、本発明の半導体装置の製造方法は、電子回路が設けられた半導体を含んでパッケージ化された半導体装置の製造方法であって、基板に、前記電子回路が形成された半導体本体と、前記半導体本体上に形成されたパッド電極とを有する半導体チップを、前記パッド電極の形成面の裏面側からマウントする工程と、前記半導体チップを埋め込んで第１絶縁層を形成する工程と、前記第１絶縁層の表面を平坦化する工程と、前記パッド電極に達する開口部を前記第１絶縁層に形成する工程と、前記開口部を埋め込んで前記第１絶縁層の上層に第１配線を形成する工程とを有する。   In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device packaged including a semiconductor provided with an electronic circuit, and the electronic circuit is mounted on a substrate. Mounting a semiconductor chip having a formed semiconductor body and a pad electrode formed on the semiconductor body from the back side of the pad electrode forming surface; and embedding the semiconductor chip to form a first insulating layer. A step of flattening the surface of the first insulating layer, a step of forming an opening reaching the pad electrode in the first insulating layer, and filling the opening to fill the opening of the first insulating layer. Forming a first wiring on the upper layer.

上記の本発明の半導体装置の製造方法は、基板に、電子回路が形成された半導体本体と、半導体本体上に形成されたパッド電極とを有する半導体チップを、パッド電極の形成面の裏面側からマウントする。
次に、半導体チップを埋め込んで第１絶縁層を形成し、次に、第１絶縁層の表面を平坦化する。
次に、パッド電極に達する開口部を第１絶縁層に形成し、開口部を埋め込んで第１絶縁層の上層に第１配線を形成する。 In the method of manufacturing a semiconductor device according to the present invention, a semiconductor chip having a semiconductor body on which an electronic circuit is formed and a pad electrode formed on the semiconductor body is formed on a substrate from the back side of the surface on which the pad electrode is formed. Mount.
Next, a semiconductor chip is embedded to form a first insulating layer, and then the surface of the first insulating layer is planarized.
Next, an opening reaching the pad electrode is formed in the first insulating layer, and the first wiring is formed in the upper layer of the first insulating layer by filling the opening.

本発明の半導体装置は、半導体チップを絶縁膜中に埋め込んでなるＳｉＰ形態の半導体装置において、半導体チップを埋め込む絶縁層が平坦化されているので、その上層に形成される再配線形成時のメッキ用レジストの薄膜化を可能にし、これによって半導体チップに接続される再配線の微細化が実現できる。   In the semiconductor device of the present invention, in an SiP-type semiconductor device in which a semiconductor chip is embedded in an insulating film, the insulating layer in which the semiconductor chip is embedded is flattened, so that plating at the time of rewiring formation formed on the upper layer is performed. This makes it possible to reduce the thickness of the resist for use in the semiconductor device, thereby realizing miniaturization of the rewiring connected to the semiconductor chip.

本発明の半導体装置の製造方法は、半導体チップを絶縁膜中に埋め込んでなるＳｉＰ形態の半導体装置の製造方法において、半導体チップを埋め込む絶縁層を平坦化する工程を有しており、その上層に形成する再配線形成時のメッキ用レジストの薄膜化を可能にし、これによって半導体チップに接続される再配線の微細化が実現できる。   The method of manufacturing a semiconductor device according to the present invention includes a step of planarizing an insulating layer in which a semiconductor chip is embedded, in a method of manufacturing a semiconductor device in the form of SiP in which a semiconductor chip is embedded in an insulating film. It is possible to reduce the thickness of the resist for plating at the time of forming the rewiring to be formed, thereby realizing miniaturization of the rewiring connected to the semiconductor chip.

以下に、本発明の半導体装置及びその製造方法の実施の形態について、図面を参照して説明する。   Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

図１は、本実施形態に係る半導体装置の模式断面図である。
例えば、シリコンからなる半導体基板２０上に、酸化シリコンなどの絶縁膜２１が形成されており、その上層に、例えばトランジスタなどの能動素子を含む電子回路が形成されたシリコンからなる、例えば２個の半導体チップ（１ａ，１ｂ）がダイアタッチフィルム１３によりマウントされている。 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the present embodiment.
For example, an insulating film 21 such as silicon oxide is formed on a semiconductor substrate 20 made of silicon, and an upper layer of the insulating film 21 is made of silicon on which an electronic circuit including an active element such as a transistor is formed. Semiconductor chips (1a, 1b) are mounted by a die attach film 13.

半導体チップ（１ａ，１ｂ）は、それぞれ、例えば、電子回路が形成された半導体本体（１０ａ，１０ｂ）の表面にパッド電極（１１ａ，１１ｂ）が形成されており、パッド電極（１１ａ，１１ｂ）を開口するように保護絶縁膜（１２ａ，１２ｂ）が形成されている構成である。
例えば、上記の２個の半導体チップ（１ａ，１ｂ）の半導体本体（１０ａ，１０ｂ）の板厚は、それぞれ５０μｍ程度となっている。 In the semiconductor chip (1a, 1b), for example, pad electrodes (11a, 11b) are formed on the surface of a semiconductor body (10a, 10b) on which an electronic circuit is formed, and the pad electrodes (11a, 11b) are formed. In this configuration, protective insulating films (12a, 12b) are formed so as to open.
For example, the thickness of the semiconductor body (10a, 10b) of the two semiconductor chips (1a, 1b) is about 50 μm.

上記の半導体チップ（１ａ，１ｂ）を被覆して、感光性樹脂からなる第１絶縁層２２が形成されており、第１絶縁層２２は、例えば上面から研削あるいは切削されることなどにより、表面が平坦化されている。   A first insulating layer 22 made of a photosensitive resin is formed so as to cover the semiconductor chip (1a, 1b), and the first insulating layer 22 is ground by cutting or cutting from the upper surface, for example. Is flattened.

第１絶縁層２２には、半導体チップ（１ａ，１ｂ）のパッド電極（１１ａ，１１ｂ）を露出する開口部が形成されている。
上記の第１絶縁層２２の開口部内及び第１絶縁層２２の上層に、パッド電極（１１ａ，１１ｂ）に接続して、シード層２３及び銅層２５からなる第１配線が形成されている。 The first insulating layer 22 is formed with openings that expose the pad electrodes (11a, 11b) of the semiconductor chip (1a, 1b).
A first wiring composed of a seed layer 23 and a copper layer 25 is formed in the opening of the first insulating layer 22 and in the upper layer of the first insulating layer 22 so as to be connected to the pad electrodes (11a, 11b).

第１配線を被覆して、第１絶縁層２２の上層に第２絶縁層２６が形成されており、第２絶縁層２６には第１配線に達する開口部が形成されている。
第２樹脂層２６の開口部内及び第２絶縁層２６上に、第１配線に接続して、シード層２７及び銅層２８からなる第２配線が形成されている。 A second insulating layer 26 is formed on the first insulating layer 22 so as to cover the first wiring, and an opening reaching the first wiring is formed in the second insulating layer 26.
A second wiring made of a seed layer 27 and a copper layer 28 is formed in the opening of the second resin layer 26 and on the second insulating layer 26 so as to be connected to the first wiring.

第１絶縁層２２と第２絶縁層２６が積層した絶縁層上において、第２配線に接続して導電性ポスト２９が形成されている。
また、導電性ポスト２９の外周部において、第１絶縁層２２と第２絶縁層２６が積層した絶縁層上に形成され、半導体装置が実装基板に実装されたときに発生する応力を緩和する絶縁性のバッファ層３０が形成されている。
さらにバッファ層３０の表面から突出するように導電性ポスト２９に接続してバンプ（突起電極）３１が形成されている。 On the insulating layer in which the first insulating layer 22 and the second insulating layer 26 are stacked, a conductive post 29 is formed in connection with the second wiring.
In addition, in the outer peripheral portion of the conductive post 29, the insulating layer is formed on the insulating layer in which the first insulating layer 22 and the second insulating layer 26 are stacked, and relieves stress generated when the semiconductor device is mounted on the mounting substrate. A buffer layer 30 is formed.
Further, bumps (projection electrodes) 31 are formed so as to be connected to the conductive posts 29 so as to protrude from the surface of the buffer layer 30.

上記のようにして、第１配線の上層に第２樹脂層２６及びバッファ層３０が積層して上層絶縁層が形成されており、半導体チップ（１ａ，１ｂ）のパッド電極（１１ａ，１１ｂ）に接続している第１配線に接続し、上層絶縁層中に埋め込まれて第２配線及び導電性ポスト２９などの上層配線が形成されている。   As described above, the second resin layer 26 and the buffer layer 30 are laminated on the upper layer of the first wiring to form the upper insulating layer, and are formed on the pad electrodes (11a, 11b) of the semiconductor chip (1a, 1b). The upper wiring such as the second wiring and the conductive post 29 is formed so as to be connected to the connected first wiring and embedded in the upper insulating layer.

上記の本実施形態の半導体装置は、半導体チップを絶縁膜中に埋め込んでなるＳｉＰ形態の半導体装置において、半導体チップを埋め込む第１絶縁層を研削あるいは切削などにより平坦化した構成となっており、その上層に形成される再配線形成時のメッキ用レジストの薄膜化を可能にし、これによって半導体チップに接続される再配線の微細化が実現できる。   The semiconductor device of the present embodiment has a configuration in which the first insulating layer in which the semiconductor chip is embedded is planarized by grinding or cutting in the SiP type semiconductor device in which the semiconductor chip is embedded in the insulating film, It is possible to reduce the thickness of the plating resist when forming the rewiring formed on the upper layer, thereby realizing miniaturization of the rewiring connected to the semiconductor chip.

上記の第１、第２配線あるいはさらに積層させた配線の一部は、静電容量素子やインダクタンスなどの受動素子を構成していることができる。例えばこれらの受動素子を組み合わせることで、例えばＬＰＦ（Low Pass Filter）、ＢＰＦ（Band Pass Filter）あるいはＨＰＦ（High Pass Filter）などを構成することができ、また、これらと電子回路に設けられた能動素子との組み合わせで、いわゆるＳｉＰ形態の半導体装置を構成することができる。   Part of the first and second wirings or further stacked wirings may constitute a passive element such as a capacitance element or an inductance. For example, by combining these passive elements, for example, an LPF (Low Pass Filter), a BPF (Band Pass Filter), or an HPF (High Pass Filter) can be configured. A combination of the element and the so-called SiP semiconductor device can be formed.

次に、上記の本実施形態に係る半導体装置の製造方法について説明する。
まず、図２（ａ）に示すように、例えば、φ２００ｍｍ、０．７２５ｍｍ厚の半導体ウェハ１０ｗにトランジスタなどの能動素子を含む電子回路を形成し、電子回路に接続するパッド電極１１と、パッド電極１１を開口し、電子回路を被覆するように保護絶縁膜１２を形成する。 Next, a method for manufacturing the semiconductor device according to the above-described embodiment will be described.
First, as shown in FIG. 2A, for example, an electronic circuit including active elements such as transistors is formed on a semiconductor wafer 10w having a diameter of 200 mm and a thickness of 0.725 mm, and a pad electrode 11 connected to the electronic circuit, and a pad electrode 11 is opened, and a protective insulating film 12 is formed so as to cover the electronic circuit.

次に、図２（ｂ）に示すように、例えば、半導体ウェハ１０ｗの裏面を＃２０００のホイールで研削して薄型化し、例えば５０μｍ程度の板厚とする。   Next, as shown in FIG. 2B, for example, the back surface of the semiconductor wafer 10w is ground with a # 2000 wheel to reduce the thickness, for example, to a thickness of about 50 μm.

次に、図２（ｃ）に示すように、例えば、半導体ウェハ１０ｗの裏面にダイアタッチフィルム１３をラミネートして張り合わせる。ラミネート条件は、例えばスピード１ｍ／分、圧力１０Ｎ／ｃｍ、温度６５℃とする。   Next, as shown in FIG. 2C, for example, the die attach film 13 is laminated and bonded to the back surface of the semiconductor wafer 10w. Lamination conditions are, for example, a speed of 1 m / min, a pressure of 10 N / cm, and a temperature of 65 ° C.

次に、図２（ｄ）に示すように、半導体ウェハ１０ｗをダイシングして所定形状の半導体チップ１とする。ダイシングの条件は、例えば、スピンドル回転数４０００ｒｐｍ、送りスピード１０ｍｍ／秒とする。
以上のようにして、本実施形態の半導体装置に内蔵する、半導体本体１０の表面にパッド電極１１が形成されており、パッド電極１１を開口するように保護絶縁膜１２が形成されている構成の半導体チップ１を形成する。得られる半導体チップの板厚は、上記のように数１０μｍ程度となっている。 Next, as shown in FIG. 2D, the semiconductor wafer 10w is diced into semiconductor chips 1 having a predetermined shape. The dicing conditions are, for example, a spindle rotation speed of 4000 rpm and a feed speed of 10 mm / second.
As described above, the pad electrode 11 is formed on the surface of the semiconductor body 10 incorporated in the semiconductor device of the present embodiment, and the protective insulating film 12 is formed so as to open the pad electrode 11. A semiconductor chip 1 is formed. The thickness of the obtained semiconductor chip is about several tens of μm as described above.

次に、図３（ａ）に示すように、表面に酸化シリコンなどの絶縁膜２１が形成されたウェハ状態の基板２０上に、基板２０に予め形成されているアライメントマークを認識して、上記のようにして形成した２個の半導体チップ（１ａ，１ｂ）をフェイスアップでダイアタッチフィルム１３の熱圧着によりマウントする。熱圧着条件は、例えば、荷重１．６Ｎ、温度１６０℃、時間２秒とする。   Next, as shown in FIG. 3A, an alignment mark formed in advance on the substrate 20 is recognized on the wafer-like substrate 20 on the surface of which the insulating film 21 such as silicon oxide is formed. The two semiconductor chips (1a, 1b) formed as described above are mounted face-up by thermocompression bonding of the die attach film 13. The thermocompression bonding conditions are, for example, a load of 1.6 N, a temperature of 160 ° C., and a time of 2 seconds.

上記の２個の半導体チップ（１ａ，１ｂ）は、それぞれ、半導体本体（１０ａ，１０ｂ）の表面にパッド電極（１１ａ，１１ｂ）が形成されており、パッド電極（１１ａ，１１ｂ）を開口するように保護絶縁膜（１２ａ，１２ｂ）が形成された構成である。
半導体チップ（１ａ，１ｂ）の半導体本体（１０ａ，１０ｂ）の板厚は、例えば５０μｍとする。 In the two semiconductor chips (1a, 1b), pad electrodes (11a, 11b) are formed on the surfaces of the semiconductor bodies (10a, 10b), respectively, so that the pad electrodes (11a, 11b) are opened. The protective insulating film (12a, 12b) is formed on the surface.
The plate thickness of the semiconductor body (10a, 10b) of the semiconductor chip (1a, 1b) is, for example, 50 μm.

次に、図３（ｂ）に示すように、例えば、ポリイミド系、フェノール系、エポキシ系の感光性樹脂の粘度を上げて、スピンコート法などで１０μｍ程度の膜厚で半導体チップ（１ａ，１ｂ）が全面が被覆されるように塗布して、第１絶縁膜２２を形成する。この状態で、半導体チップの有無に起因して生じる最も薄い層が半導体チップの厚さより１５μｍ以上厚い状態となる。
例えば、感光性ポリイミドをスピンコート法で形成する場合、（１０００ｒｐｍ，３０秒）＋（２０００ｒｐｍ，４０秒）＋（１０００ｒｐｍ，１０秒）＋（１５００ｒｐｍ，１０秒）の塗布条件で行い、プリベークとして（９０℃，１２０秒）＋（１００℃，１２０秒）の熱処理を行う。 Next, as shown in FIG. 3B, for example, the viscosity of a polyimide-based, phenol-based, or epoxy-based photosensitive resin is increased, and the semiconductor chip (1a, 1b) is formed to a thickness of about 10 μm by spin coating or the like. The first insulating film 22 is formed by coating so that the entire surface is covered. In this state, the thinnest layer generated due to the presence or absence of the semiconductor chip is in a state of being 15 μm or more thicker than the thickness of the semiconductor chip.
For example, when a photosensitive polyimide is formed by a spin coating method, it is performed under a coating condition of (1000 rpm, 30 seconds) + (2000 rpm, 40 seconds) + (1000 rpm, 10 seconds) + (1500 rpm, 10 seconds) as pre-baking ( 90 ° C., 120 seconds) + (100 ° C., 120 seconds).

次に、図３（ｃ）に示すように、例えば、プリベーク後この状態で、半導体チップの有無に起因する段差を平坦化するために第１絶縁層２２の上面から１５μｍ程度研削あるいは切削して、第１絶縁膜２２を平坦化する。
研削する場合の条件は、例えば、＃６００のホイールでスピンドル回転数３５００ｒｐｍとして行う。 Next, as shown in FIG. 3C, for example, in this state after pre-baking, the surface of the first insulating layer 22 is ground or cut by about 15 μm in order to flatten the step caused by the presence or absence of the semiconductor chip. Then, the first insulating film 22 is planarized.
The conditions for grinding are, for example, set at a spindle rotation speed of 3500 rpm with a # 600 wheel.

次に、図４（ａ）に示すように、例えば、露光及び現像を行って、第１絶縁層２２に、半導体チップ（１ａ，１ｂ）のパッド電極（１１ａ，１１ｂ）を開口する開口部を開口する。この露光は、例えば露光量１２５ｍＪ／ｃｍ２で行う。
上記の第１絶縁層２２のパターニングの後、第１絶縁層２２の硬化処理を行う。 Next, as shown in FIG. 4A, for example, exposure and development are performed to form openings in the first insulating layer 22 for opening the pad electrodes (11a, 11b) of the semiconductor chips (1a, 1b). Open. This exposure is performed, for example, with an exposure dose of 125 mJ / cm 2 .
After the patterning of the first insulating layer 22, the first insulating layer 22 is cured.

次に、図４（ｂ）に示すように、例えば、スパッタリング法により、第１絶縁層２２に形成された開口部の内壁面を被覆して、例えばＴｉを６００ｎｍ、続いてＣｕを６００ｎｍの膜厚でそれぞれ堆積させ、次工程における電解メッキ処理のシード層２３を形成する。   Next, as shown in FIG. 4B, the inner wall surface of the opening formed in the first insulating layer 22 is covered by, for example, a sputtering method to form, for example, a Ti film of 600 nm and then a Cu film of 600 nm. Each of the layers is deposited with a thickness to form a seed layer 23 for electrolytic plating in the next step.

次に、図４（ｃ）に示すように、例えば、フォトリソグラフィー工程により、第１絶縁層２２に形成された開口部及び第１配線形成領域を開口するパターンのレジスト膜２４を形成する。
上記のレジスト膜２４の膜厚は、第１絶縁膜２２の平坦化処理の効果により、１０μｍ以下で形成することが可能となり、解像度は例えばＬ／Ｓ＝１０／１０μｍ程度である。 Next, as shown in FIG. 4C, a resist film 24 having a pattern that opens the opening formed in the first insulating layer 22 and the first wiring formation region is formed by, for example, a photolithography process.
The film thickness of the resist film 24 can be formed to be 10 μm or less due to the effect of the planarization process of the first insulating film 22, and the resolution is, for example, about L / S = 10/10 μm.

次に、図５（ａ）に示すように、例えば、シード層２３を一方の電極とする電解メッキ処理により、レジスト膜２４の形成領域を除く領域に銅を成膜し、所定の配線回路パターンの銅層２５を形成する。銅のメッキは、例えば１．５ＡＳＤ（１．５Ａ／ｄｍ２）の条件とする。 Next, as shown in FIG. 5A, for example, copper is formed in a region excluding the formation region of the resist film 24 by an electrolytic plating process using the seed layer 23 as one electrode, and a predetermined wiring circuit pattern is formed. The copper layer 25 is formed. Copper plating is performed under conditions of 1.5 ASD (1.5 A / dm 2 ), for example.

次に、図５（ｂ）に示すように、例えば、溶剤処理などによりレジスト膜２４を剥離する。さらに、図５（ｃ）に示すように、銅層２５をマスクとしてウェットエッチングなどを行い、各銅層２５間におけるシード層２３を除去する。
これにより、シード層２３及び銅層２５からなる第１配線が形成される。 Next, as shown in FIG. 5B, the resist film 24 is removed by, for example, a solvent treatment. Further, as shown in FIG. 5C, wet etching or the like is performed using the copper layer 25 as a mask, and the seed layer 23 between the copper layers 25 is removed.
Thereby, the first wiring composed of the seed layer 23 and the copper layer 25 is formed.

次に、上記と同様の工程を繰り返して、図６（ａ）に示すように、第２絶縁層２６と、シード層２７及び銅層２８からなる第２配線を積層させる。
第２絶縁層２６の形成は、例えば、スピンコート法、ＣＶＤ法あるいは印刷法などで行い、感光性ポリイミドをスピンコート法により形成する場合、例えば、（７０００ｒｐｍ，２５秒）＋（１０００ｒｐｍ，１２５秒）＋（１０００ｒｐｍ，１０秒）＋（１５００ｒｐｍ，１０秒）の塗布条件で行い、プリベークとしては、（６０℃，２４０秒）＋（９０℃，２４０秒）＋（１１０℃，１２０秒）の熱処理を行って、７８μｍの膜厚の第２絶縁層とする。
上記のように形成した第２絶縁層２６を露光量３００ｍＪ／ｃｍ２の露光条件でパターン露光及び現像を行う。さらにスパッタリング法などで１６０ｎｍのＴｉと６００ｎｍのＣｕを積層してシード層２７を形成し、不図示のレジスト膜を形成して、シード層２７を一方の電極とする電解メッキ処理により所定の配線回路パターンの銅層２８を形成する。電解メッキ処理の電流密度は１．５ＡＳＤ（１．５Ａ／ｄｍ２）で４００ｍＡ／５０分とする。
上記のレジスト膜の膜厚は、第１絶縁膜の平坦化処理の効果により、１０μｍ以下で形成することが可能となり、解像度は例えばＬ／Ｓ＝１０／１０μｍ程度である。
さらに、溶剤処理などによりレジスト膜を剥離する。シード層２７は、次工程で導電性ポストを形成する電解メッキ処理工程においても用いるので、エッチングせずにおく。 Next, the same process as described above is repeated, and as shown in FIG. 6A, the second insulating layer 26 and the second wiring made of the seed layer 27 and the copper layer 28 are laminated.
The second insulating layer 26 is formed by, for example, a spin coating method, a CVD method, or a printing method. When the photosensitive polyimide is formed by a spin coating method, for example, (7000 rpm, 25 seconds) + (1000 rpm, 125 seconds) ) + (1000 rpm, 10 seconds) + (1500 rpm, 10 seconds), and pre-baking is (60 ° C., 240 seconds) + (90 ° C., 240 seconds) + (110 ° C., 120 seconds) heat treatment To obtain a second insulating layer having a thickness of 78 μm.
The second insulating layer 26 formed as described above is subjected to pattern exposure and development under exposure conditions of an exposure amount of 300 mJ / cm 2 . Further, a seed layer 27 is formed by laminating 160 nm Ti and 600 nm Cu by sputtering or the like, a resist film (not shown) is formed, and a predetermined wiring circuit is formed by electrolytic plating using the seed layer 27 as one electrode. A patterned copper layer 28 is formed. The current density of the electrolytic plating process is 1.5 ASD (1.5 A / dm 2 ) and 400 mA / 50 minutes.
The film thickness of the resist film can be formed at 10 μm or less due to the effect of the planarization treatment of the first insulating film, and the resolution is, for example, about L / S = 10/10 μm.
Further, the resist film is removed by solvent treatment or the like. Since the seed layer 27 is also used in an electroplating process in which a conductive post is formed in the next process, it is not etched.

次に、図６（ｂ）に示すように、例えば、フォトリソグラフィー工程により導電性ポストの形成領域を開口するパターンでレジスト膜をパターン形成し、さらにシード層２７を一方の電極とする電解メッキ処理により、第２配線に接続するように、銅からなる導電性ポスト２９を形成する。銅からなる導電性ポストの径は２５０μｍ、高さは８０μｍとする。
この後、レジスト膜を除去し、さらに導電性ポスト２９及び銅層２８をマスクとしてウェットエッチングなどを行い、各銅層２８間におけるシード層２７を除去する。 Next, as shown in FIG. 6B, for example, a resist film is formed in a pattern that opens the formation region of the conductive post by a photolithography process, and the electroplating process using the seed layer 27 as one electrode. Thus, a conductive post 29 made of copper is formed so as to be connected to the second wiring. The diameter of the conductive post made of copper is 250 μm and the height is 80 μm.
Thereafter, the resist film is removed, and further, wet etching or the like is performed using the conductive posts 29 and the copper layer 28 as a mask, and the seed layer 27 between the copper layers 28 is removed.

以上のようにして、また、以上のような工程を繰り返すことにより、第１絶縁層及び第２絶縁層さらにはそれ以上の樹脂層が積層した絶縁層が形成でき、また、絶縁層中に埋め込まれて、第１配線及び第２配線さらにはそれ以上の配線を積層することができる。   As described above, by repeating the above-described steps, an insulating layer in which the first insulating layer, the second insulating layer, and further the resin layer are laminated can be formed and embedded in the insulating layer. Thus, the first wiring, the second wiring, and further wiring can be stacked.

次に、図７（ａ）に示すように、例えば、印刷法あるいはモールド法により、導電性ポスト２９の外周部において第２絶縁層２６の上層に、エポキシ系、ポリイミド系、シリコーン系などの樹脂からなり、半導体装置が実装基板に実装されたときに発生する応力を緩和する絶縁性のバッファ層３０を形成する。
ポリイミド系樹脂の場合には、印刷法によりＮＶ値２７．５のペーストを使用し、スキージで印刷を行うことで形成する。硬化は（１００℃，１０分）＋（１５０℃，１０分）＋（２００℃，１０分）＋（２５０℃，６０分）の熱処理で行う。 Next, as shown in FIG. 7A, an epoxy-based, polyimide-based, or silicone-based resin is formed on the second insulating layer 26 on the outer periphery of the conductive post 29 by, for example, a printing method or a molding method. The insulating buffer layer 30 is formed to relieve stress generated when the semiconductor device is mounted on the mounting substrate.
In the case of a polyimide resin, it is formed by using a paste having an NV value of 27.5 by printing and printing with a squeegee. Curing is performed by a heat treatment of (100 ° C., 10 minutes) + (150 ° C., 10 minutes) + (200 ° C., 10 minutes) + (250 ° C., 60 minutes).

次に、図７（ｂ）に示すように、例えば、バッファ層３０を上面から研削し、導電性ポスト２９の頂部を露出させる。条件は、例えば＃６００のホイールを用いて３５００ｒｐｍ，０．５ｍｍ／秒とする。   Next, as shown in FIG. 7B, for example, the buffer layer 30 is ground from the upper surface to expose the tops of the conductive posts 29. The conditions are, for example, 3500 rpm and 0.5 mm / second using a # 600 wheel.

次に、図８（ａ）に示すように、例えば、露出した導電性ポスト上にはんだボールまたははんだペーストにてバンプ（突起電極）３１を形成する。   Next, as shown in FIG. 8A, for example, bumps (projection electrodes) 31 are formed on the exposed conductive posts with solder balls or solder paste.

次に、図８（ｂ）に示すように、基板２０の裏面側から研削して薄型化した後、ダイシングラインにおいてダイシングを行うことで、図１に示すような構成の半導体装置を製造することができる。   Next, as shown in FIG. 8B, after thinning by grinding from the back side of the substrate 20, the semiconductor device having the structure shown in FIG. 1 is manufactured by dicing in a dicing line. Can do.

上記の半導体装置において、内蔵する半導体チップを薄型化した場合、基板をも薄く加工すると半導体装置全体の総厚を７２５μｍまで薄くすることができる。これ以上の薄型化をおこなう場合は、搭載した半導体チップをさらに研削する。   In the above semiconductor device, when the built-in semiconductor chip is thinned, the total thickness of the entire semiconductor device can be reduced to 725 μm by thinning the substrate. When the thickness is further reduced, the mounted semiconductor chip is further ground.

本実施形態に係る半導体装置の製造方法によれば、半導体チップを絶縁膜中に埋め込んで形成するＳｉＰ形態の半導体装置の製造方法において、半導体チップを埋め込む絶縁層を平坦化する工程を有しており、その上層に形成する再配線形成時のメッキ用レジストの薄膜化を可能にし、これによって半導体チップに接続される再配線の微細化が実現できる。   According to the method for manufacturing a semiconductor device according to the present embodiment, in the method for manufacturing a semiconductor device of the SiP type in which the semiconductor chip is formed by embedding the semiconductor chip in the insulating film, the step of planarizing the insulating layer in which the semiconductor chip is embedded is provided. Therefore, it is possible to reduce the thickness of the resist for plating at the time of forming the rewiring formed on the upper layer, thereby realizing miniaturization of the rewiring connected to the semiconductor chip.

本実施形態の半導体装置及びその製造方法によれば、以下の利点を享受できる。
（１）半導体チップに接続して再配線を形成する工程のレジスト膜の解像度がＬ／Ｓ＝１０／１０μｍにまで微細化できる。
（２）半導体チップ搭載領域と非搭載領域との間における配線の傾斜がなくなり、内蔵素子を半導体チップ近傍に配置することも可能となり、半導体装置全体の面積の小型化が図れる。 According to the semiconductor device and the manufacturing method thereof of the present embodiment, the following advantages can be obtained.
(1) The resolution of the resist film in the process of forming a rewiring by connecting to a semiconductor chip can be miniaturized to L / S = 10/10 μm.
(2) The inclination of the wiring between the semiconductor chip mounting region and the non-mounting region is eliminated, and the built-in element can be arranged in the vicinity of the semiconductor chip, so that the area of the entire semiconductor device can be reduced.

本発明は上記の説明に限定されない。
例えば、基板にも電子回路が形成されていてもよい。この場合には絶縁層に埋め込まれる配線が基板に接続するように形成される。
その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。 The present invention is not limited to the above description.
For example, an electronic circuit may be formed on the substrate. In this case, the wiring embedded in the insulating layer is formed so as to be connected to the substrate.
In addition, various modifications can be made without departing from the scope of the present invention.

本発明の半導体装置は、システムインパッケージ形態の半導体装置に適用できる。
また、本発明の半導体装置の製造方法は、システムインパッケージ形態の半導体装置を製造する方法に適用できる。 The semiconductor device of the present invention can be applied to a semiconductor device in a system in package form.
The semiconductor device manufacturing method of the present invention can be applied to a method of manufacturing a system-in-package semiconductor device.

図１は、本発明の施形態に係る半導体装置の模式断面図である。FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 図２（ａ）〜（ｄ）は、本発明の施形態に係る半導体装置の製造方法の製造工程を示す断面図である。2A to 2D are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 図３（ａ）〜（ｃ）は、本発明の実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。3A to 3C are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. 図４（ａ）〜（ｃ）は、本発明の実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。4A to 4C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 図５（ａ）〜（ｃ）は、本発明の実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。5A to 5C are cross-sectional views illustrating the manufacturing process of the method for manufacturing a semiconductor device according to the embodiment of the present invention. 図６（ａ）及び図６（ｂ）は、本発明の実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。FIG. 6A and FIG. 6B are cross-sectional views showing manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. 図７（ａ）及び図７（ｂ）は、本発明の実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。FIG. 7A and FIG. 7B are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. 図８（ａ）及び図８（ｂ）は、本発明の実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。FIG. 8A and FIG. 8B are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

符号の説明Explanation of symbols

１，１ａ，１ｂ…半導体チップ、１０，１０ａ，１０ｂ…半導体本体、１０ｗ…半導体ウェハ、１１，１１ａ，１１ｂ…パッド電極、１２，１２ａ，１２ｂ…保護絶縁膜、１３ダイアタッチフィルム、２０…基板、２１…絶縁膜、２２…第１絶縁層、２３…シード層、２４…レジスト膜、２５…銅層、２６…第２絶縁層、２７…シード層、２８…銅層、２９…導電性ポスト、３０…バッファ層、３１…バンプ   DESCRIPTION OF SYMBOLS 1,1a, 1b ... Semiconductor chip, 10, 10a, 10b ... Semiconductor main body, 10w ... Semiconductor wafer, 11, 11a, 11b ... Pad electrode, 12, 12a, 12b ... Protective insulating film, 13 die attach film, 20 ... Substrate , 21 ... insulating film, 22 ... first insulating layer, 23 ... seed layer, 24 ... resist film, 25 ... copper layer, 26 ... second insulating layer, 27 ... seed layer, 28 ... copper layer, 29 ... conductive post 30 ... Buffer layer, 31 ... Bump

Claims (7)

電子回路が設けられた半導体を含んでパッケージ化された半導体装置であって、
基板と、
前記電子回路が形成された半導体本体と、前記半導体本体上に形成されたパッド電極とを有し、前記パッド電極の形成面の裏面側から前記基板にマウントされた半導体チップと、
前記半導体チップを埋め込んで形成され、表面が平坦化された第１絶縁層と、
前記第１絶縁層を貫通して前記パッド電極に接続し、前記第１絶縁層の上層に形成された第１配線と
を有する半導体装置。 A semiconductor device packaged including a semiconductor provided with an electronic circuit,
A substrate,
A semiconductor body having a semiconductor body on which the electronic circuit is formed; a pad electrode formed on the semiconductor body; and a semiconductor chip mounted on the substrate from the back side of the pad electrode forming surface;
A first insulating layer formed by embedding the semiconductor chip and having a planarized surface;
A semiconductor device comprising: a first wiring penetrating through the first insulating layer and connected to the pad electrode, and formed in an upper layer of the first insulating layer. 前記第１絶縁層の上層に、前記第１配線に接続する上層配線と、前記上層配線を埋め込む上層絶縁層が形成されている
請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein an upper-layer wiring connected to the first wiring and an upper-layer insulating layer that embeds the upper-layer wiring are formed in an upper layer of the first insulating layer. 前記半導体チップとして複数の半導体チップが前記第１絶縁層中に埋め込まれている
請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein a plurality of semiconductor chips are embedded in the first insulating layer as the semiconductor chips. 電子回路が設けられた半導体を含んでパッケージ化された半導体装置の製造方法であって、
基板に、前記電子回路が形成された半導体本体と、前記半導体本体上に形成されたパッド電極とを有する半導体チップを、前記パッド電極の形成面の裏面側からマウントする工程と、
前記半導体チップを埋め込んで第１絶縁層を形成する工程と、
前記第１絶縁層の表面を平坦化する工程と、
前記パッド電極に達する開口部を前記第１絶縁層に形成する工程と、
前記開口部を埋め込んで前記第１絶縁層の上層に第１配線を形成する工程と
を有する半導体装置の製造方法。 A method of manufacturing a semiconductor device packaged including a semiconductor provided with an electronic circuit,
Mounting a semiconductor chip having a semiconductor body on which the electronic circuit is formed and a pad electrode formed on the semiconductor body from the back side of the pad electrode forming surface;
Forming a first insulating layer by embedding the semiconductor chip;
Planarizing the surface of the first insulating layer;
Forming an opening reaching the pad electrode in the first insulating layer;
And a step of filling the opening and forming a first wiring in an upper layer of the first insulating layer. 前記第１絶縁膜を平坦化する工程は、前記第１絶縁膜を上面から研削あるいは切削する工程を含む
請求項４に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 4, wherein the step of planarizing the first insulating film includes a step of grinding or cutting the first insulating film from an upper surface. 前記第１配線を形成する工程の後に、前記第１絶縁層の上層に前記第１配線に接続する上層配線と前記上層配線を埋め込む上層絶縁層とを形成する工程をさらに有する
請求項４に記載の半導体装置の製造方法。 5. The method according to claim 4, further comprising a step of forming, after the step of forming the first wiring, an upper layer wiring connected to the first wiring and an upper layer insulating layer for embedding the upper layer wiring in an upper layer of the first insulating layer. Semiconductor device manufacturing method. 前記半導体チップをマウントする工程において複数の半導体チップをマウントし、前記第１絶縁層を形成する工程において前記複数の半導体チップを埋め込む
請求項４に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 4, wherein a plurality of semiconductor chips are mounted in the step of mounting the semiconductor chips, and the plurality of semiconductor chips are embedded in the step of forming the first insulating layer.
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