JP5245209B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5245209B2
JP5245209B2 JP2006119610A JP2006119610A JP5245209B2 JP 5245209 B2 JP5245209 B2 JP 5245209B2 JP 2006119610 A JP2006119610 A JP 2006119610A JP 2006119610 A JP2006119610 A JP 2006119610A JP 5245209 B2 JP5245209 B2 JP 5245209B2
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semiconductor chip
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修 山形
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Sony Corp
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Description

本発明は半導体装置及びその製造方法に関し、特に能動素子や受動素子を内蔵し、整合回路やフィルタなどを取り込んだＳｉＰ（システムインパッケージ）形態の半導体装置とその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a SiP (system in package) type semiconductor device incorporating an active element and a passive element and incorporating a matching circuit and a filter, and a manufacturing method thereof.

デジタルビデオカメラ、デジタル携帯電話、あるいはノートパソコンなど、携帯用電子機器の小型化、薄型化、軽量化に対する要求は強くなる一方であり、これに応えるために近年のＶＬＳＩなどの半導体装置においては３年で７割の縮小化を実現してきた一方で、このような半導体装置をプリント配線基板上に実装した電子回路装置としても、実装基板（プリント配線基板）上の部品実装密度をいかに向上させるかが重要な課題として研究及び開発がなされてきた。   The demand for downsizing, thinning, and weight reduction of portable electronic devices such as digital video cameras, digital mobile phones, and notebook personal computers is increasing. While an electronic circuit device in which such a semiconductor device is mounted on a printed wiring board has been realized by 70% reduction year by year, how can the component mounting density on the mounting substrate (printed wiring substrate) be improved? Has been studied and developed as an important issue.

例えば、半導体装置のパッケージ形態としては、ＤＩＰ（Dual Inline Package ）などのリード挿入型から表面実装型へと移行し、さらには半導体チップのパッド電極にはんだや金などからなるバンプ（突起電極）を設け、フェースダウンでバンプを介して配線基板に接続するフリップチップ実装法が開発された。   For example, as a package form of a semiconductor device, a transition from a lead insertion type such as DIP (Dual Inline Package) to a surface mounting type is performed, and furthermore, bumps (projection electrodes) made of solder, gold, or the like are provided on a pad electrode of a semiconductor chip. A flip-chip mounting method has been developed in which a face-down connection is made to the wiring board via bumps.

さらに、インダクタンスやキャパシタなどの受動素子を内蔵し、整合回路やフィルタなどを取り込んだＳｉＰと呼ばれる複雑な形態のパッケージへと開発が進んでいる。   Furthermore, development is progressing into a package of a complicated form called SiP that incorporates passive elements such as inductances and capacitors and incorporates a matching circuit and a filter.

例えば、デジタルチップとデジタルチップ、デジタルチップとアナログチップ、アナログチップとアナログチップなど、能動素子を含むチップを２個以上含んで一体化する場合、有機基板の両側にアナログ、デジタルチップをそれぞれ実装する構成が知られている。
しかし、この構造では基板のスルーホールと片側に外部電極の形成が必要で全体の厚さが厚くなり薄型化は行えない。 For example, when integrating two or more chips including active elements such as a digital chip and a digital chip, a digital chip and an analog chip, and an analog chip and an analog chip, the analog and digital chips are respectively mounted on both sides of the organic substrate. The configuration is known.
However, in this structure, it is necessary to form external electrodes on one side and the through hole of the substrate, so that the entire thickness becomes thick and the thickness cannot be reduced.

そこで、上記のようなＳｉＰ形態の半導体装置として、上記のような能動素子を含むチップを２個以上含んで一体化した半導体装置が開発されており、例えば２つの半導体チップを同一平面に平置きした構造が取られる。
しかしながら、この構造ではサイズが大きくなり小型化の要求を満足しない。 Therefore, as an SiP type semiconductor device as described above, a semiconductor device in which two or more chips including active elements as described above are integrated has been developed. For example, two semiconductor chips are placed on the same plane. The structure is taken.
However, this structure increases the size and does not satisfy the demand for miniaturization.

そこで、２つの半導体チップをスタックして配置した構造の半導体装置が開発され、例えば、特許文献１に上記のＳｉＰ形態の半導体装置の構成が開示されている。   In view of this, a semiconductor device having a structure in which two semiconductor chips are stacked and developed has been developed. For example, Patent Document 1 discloses the configuration of the above-described SiP-type semiconductor device.

図１５は上記のような２つの半導体チップをスタックしてパッケージ化したＳｉＰ形態の半導体装置である。
シリコン基板１００上に、例えば、酸化シリコンからなる下地絶縁膜１０１が形成され、能動素子が形成された第１半導体チップ１０２がマウントされている。第１半導体チップ１０２は、半導体本体部分１０２ａの回路面にパッド１０２ｂが形成され、パッド１０２ｂを除く領域は酸化シリコンなどの保護層１０２ｃで覆われた構成であり、ダイアタッチフィルム１０２ｄにより、パッド１０２ｂの形成面が基板１００と反対側を向くようにしてマウントされている。 FIG. 15 shows an SiP semiconductor device in which two semiconductor chips as described above are stacked and packaged.
On the silicon substrate 100, for example, a base insulating film 101 made of silicon oxide is formed, and a first semiconductor chip 102 on which an active element is formed is mounted. The first semiconductor chip 102 has a configuration in which a pad 102b is formed on the circuit surface of the semiconductor body portion 102a, and an area excluding the pad 102b is covered with a protective layer 102c such as silicon oxide, and the pad 102b is covered with a die attach film 102d. Is mounted so that the formation surface of the substrate faces the side opposite to the substrate 100.

例えば、第１半導体チップ１０２を被覆してポリイミド樹脂などからなる第１絶縁層１０３が形成され、第１半導体チップ１０２のパッド１０２ｂに達する開口部１０３ａが形成されており、開口部１０３ａ内に埋め込まれて、第１半導体チップ１０２のパッド１０２ｂに接続するプラグ部分と一体になって、第１絶縁層１０２上にＴｉＣｕなどのシード層１０４及び銅層１０５からなる第１配線が形成されている。   For example, a first insulating layer 103 made of polyimide resin or the like is formed so as to cover the first semiconductor chip 102, and an opening 103a reaching the pad 102b of the first semiconductor chip 102 is formed and embedded in the opening 103a. Thus, a first wiring made of a seed layer 104 such as TiCu and a copper layer 105 is formed on the first insulating layer 102 so as to be integrated with the plug portion connected to the pad 102 b of the first semiconductor chip 102.

また、例えば、第１配線を被覆してポリイミド樹脂などからなる第２絶縁層１０６が形成され、第１配線に達する開口部１０６ａが形成されており、開口部１０６ａ内に埋め込まれて、第１配線に接続するプラグ部分と一体になって、第２絶縁層１０６上にＴｉＣｕなどのシード層１０７及び銅層１０８からなる第２配線が形成され、さらに第２配線上に導電性ポスト１０９が形成されている。   In addition, for example, a second insulating layer 106 made of polyimide resin or the like is formed so as to cover the first wiring, and an opening 106a reaching the first wiring is formed, embedded in the opening 106a, A second wiring made of a seed layer 107 such as TiCu and a copper layer 108 is formed on the second insulating layer 106 integrally with a plug portion connected to the wiring, and a conductive post 109 is formed on the second wiring. Has been.

また、第１半導体チップ１０２の上方であって、第２絶縁層１０６の上層に、能動素子が形成された第２半導体チップ１１０がマウントされている。第２半導体チップ１１０は、半導体本体部分１１０ａの回路面にパッド１１０ｂが形成され、パッド１１０ｂを除く領域は酸化シリコンなどの保護層１１０ｃで覆われた構成であり、ダイアタッチフィルム１１０ｄにより、パッド１１０ｂの形成面が基板１００と反対側を向くようにしてマウントされている。   A second semiconductor chip 110 on which an active element is formed is mounted above the first semiconductor chip 102 and above the second insulating layer 106. The second semiconductor chip 110 has a configuration in which a pad 110b is formed on the circuit surface of the semiconductor body 110a, and a region excluding the pad 110b is covered with a protective layer 110c such as silicon oxide. The pad 110b is formed by a die attach film 110d. Is mounted so that the formation surface of the substrate faces the side opposite to the substrate 100.

また、例えば、導電性ポスト１０９、第２配線及び第２半導体チップ１１０を被覆して、ポリイミド樹脂などからなる第３絶縁層１１１が形成され、導電性ポスト１０９及び第２半導体チップ１１０のパッド１１０ｂに達する開口部１１１ａが形成されており、開口部１１１ａ内に埋め込まれて、導電性ポスト１０９及び第２半導体チップ１１０のパッド１１０ｂに接続するプラグ部分と一体になって、第３絶縁層１１１上にＴｉＣｕなどのシード層１１２及び銅層１１３からなる第３配線が形成されている。   Further, for example, a third insulating layer 111 made of polyimide resin is formed so as to cover the conductive post 109, the second wiring, and the second semiconductor chip 110, and the pad 110 b of the conductive post 109 and the second semiconductor chip 110 is formed. Is formed in the opening 111a, and is embedded in the opening 111a so as to be integrated with the plug portion connected to the conductive post 109 and the pad 110b of the second semiconductor chip 110, and on the third insulating layer 111. A third wiring made of a seed layer 112 such as TiCu and a copper layer 113 is formed.

また、第３配線に接続して、銅などからなる導電性ポスト１１４が形成されており、導電性ポスト１１４の間隙における第３絶縁層１１１の上層に、ポリアミドイミド樹脂などからなる絶縁性のバッファ層１１５が形成され、バッファ層１１５の表面において導電性ポスト１１４に接続するようにバンプ（突起電極）１１６が形成されている。   In addition, a conductive post 114 made of copper or the like is formed in connection with the third wiring, and an insulating buffer made of polyamideimide resin or the like is formed above the third insulating layer 111 in the gap between the conductive posts 114. A layer 115 is formed, and bumps (projection electrodes) 116 are formed on the surface of the buffer layer 115 so as to be connected to the conductive posts 114.

上記の従来例に係る半導体装置において、チップ上とそれ以外部分での段差がチップ１つのみの場合に比べ２倍以上になる。従って、半導体チップ上に再配線層を形成してＳｉＰ形態の半導体装置とする場合、再配線層形成の形成工程におけるレジスト膜などのカバレージが悪くなってしまい、段切れを起こして再配線の形成が困難となる場合があり、また、実装基板に実装したときの実装基板との間に生じる応力緩和に寄与する導電性ポストの高さがパッケージ位置で異なってしまうことに起因して応力緩和機能が不十分となるおそれがある。
特開２００３−１２４２３６号公報 In the semiconductor device according to the above-described conventional example, the step difference between the chip and the other part is more than twice as compared with the case of only one chip. Therefore, when a rewiring layer is formed on a semiconductor chip to form a SiP-type semiconductor device, the coverage of the resist film or the like in the rewiring layer formation forming process is deteriorated, causing disconnection and forming a rewiring. Stress relief function due to differences in the height of the conductive posts that contribute to stress relaxation that occurs between the mounting board and the mounting board when mounted on the mounting board. May become insufficient.
JP 2003-124236 A

解決しようとする問題点は、ＳｉＰ形態の半導体装置において２個以上の半導体チップをスタック型に一体化する場合に、段切れを抑制し、実装基板に実装したときの実装基板との間に生じる応力を緩和する機能を確保することが困難である点である。   A problem to be solved is that when two or more semiconductor chips are integrated into a stack type in a SiP-type semiconductor device, the disconnection is suppressed and the mounting substrate is mounted on the mounting substrate. It is difficult to ensure a function to relieve stress.

本発明の半導体装置は、半導体を含んでパッケージ化された半導体装置であって、チップ埋め込み用凹部が形成された基板と、能動素子が形成され、前記チップ埋め込み用凹部の底面上にマウントされた第１半導体チップと、能動素子が形成され、前記第１半導体チップの上方に積層してマウントされた第２半導体チップとを有する。   The semiconductor device of the present invention is a semiconductor device packaged including a semiconductor, wherein a substrate on which a chip-embedded recess is formed and an active element are formed and mounted on the bottom surface of the chip-embedded recess. A first semiconductor chip; and a second semiconductor chip on which an active element is formed and stacked and mounted above the first semiconductor chip.

上記の本発明の半導体装置は、半導体を含んでパッケージ化された半導体装置であって、基板に形成されたチップ埋め込み用凹部の底面上に、能動素子が形成された第１半導体チップがマウントされており、また、能動素子が形成された第２半導体チップが第１半導体チップの上方に積層してマウントされている。   The semiconductor device according to the present invention is a semiconductor device packaged including a semiconductor, and a first semiconductor chip having an active element formed thereon is mounted on a bottom surface of a chip embedding recess formed on a substrate. In addition, a second semiconductor chip on which active elements are formed is stacked and mounted above the first semiconductor chip.

本発明の半導体装置の製造方法は、半導体を含んでパッケージ化された半導体装置の製造方法であって、基板にチップ埋め込み用凹部を形成する工程と、前記チップ埋め込み用凹部の底面上に、能動素子が形成された第１半導体チップをマウントする工程と、前記第１半導体チップの上方に積層して、能動素子が形成された第２半導体チップをマウントする工程とを有する。   A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device packaged including a semiconductor, and includes a step of forming a recess for embedding a chip in a substrate, and an active process on a bottom surface of the recess for embedding a chip. A step of mounting the first semiconductor chip on which the element is formed, and a step of mounting the second semiconductor chip on which the active element is formed by being stacked above the first semiconductor chip.

上記の本発明の半導体装置の製造方法は、半導体を含んでパッケージ化して半導体装置を製造する方法であって、基板にチップ埋め込み用凹部を形成し、チップ埋め込み用凹部の底面上に、能動素子が形成された第１半導体チップをマウントし、さらに、第１半導体チップの上方に積層して、能動素子が形成された第２半導体チップをマウントする。   The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device by packaging a semiconductor including a semiconductor, wherein a chip embedding recess is formed on a substrate, and an active element is formed on the bottom surface of the chip embedding recess. The first semiconductor chip formed with is mounted, and further stacked on the first semiconductor chip, and the second semiconductor chip formed with the active element is mounted.

本発明の半導体装置は、ＳｉＰ形態の半導体装置において、基板に形成されたチップ埋め込み用凹部の底面上に第１半導体チップがマウントされ、さらにその上方に積層して第２半導体チップがマウントされているので、絶縁層に生じる段差に対して第１半導体チップの分影響が軽減され、２個以上の半導体チップをスタック型に一体化しても段切れを抑制することができ、また、実装基板に実装したときの実装基板との間に生じる応力緩和に寄与する導電性ポストの高さのばらつきを低減して応力緩和機能を確保することができる。   In the semiconductor device of the present invention, in the SiP type semiconductor device, the first semiconductor chip is mounted on the bottom surface of the chip embedding concave portion formed on the substrate, and the second semiconductor chip is mounted further stacked thereon. As a result, the influence of the first semiconductor chip on the step generated in the insulating layer is reduced, and even if two or more semiconductor chips are integrated into a stack type, step disconnection can be suppressed. It is possible to secure the stress relaxation function by reducing the variation in the height of the conductive posts contributing to the stress relaxation generated between the mounting substrate and the mounting substrate.

本発明の半導体装置の製造方法は、ＳｉＰ形態の半導体装置において、基板に形成されたチップ埋め込み用凹部の底面上に第１半導体チップをマウントし、さらにその上方に積層して第２半導体チップをマウントするので、絶縁層に生じる段差に対して第１半導体チップの分影響が軽減され、２個以上の半導体チップをスタック型に一体化しても段切れを抑制して、また、実装基板に実装したときの実装基板との間に生じる応力緩和に寄与する導電性ポストの高さのばらつきを低減して応力緩和機能を確保して、半導体装置を製造することができる。   According to a method of manufacturing a semiconductor device of the present invention, in a SiP type semiconductor device, a first semiconductor chip is mounted on a bottom surface of a chip embedding recess formed on a substrate, and further stacked thereon to form a second semiconductor chip. Since it is mounted, the influence of the first semiconductor chip on the step generated in the insulating layer is reduced, and even if two or more semiconductor chips are integrated into a stack type, the step breakage is suppressed, and the step is mounted on the mounting substrate. The semiconductor device can be manufactured by ensuring the stress relaxation function by reducing the variation in the height of the conductive posts contributing to the stress relaxation generated between the mounting substrate and the mounting substrate.

以下に、本発明に係る半導体装置及びその製造方法の実施の形態について、図面を参照して説明する。   Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

第１実施形態
図１は本実施形態に係るＳｉＰ形態の半導体装置の断面図である。
例えば、シリコン基板１０にチップ埋め込み用凹部１０ａが形成されている。チップ埋め込み用凹部１０ａの深さは、埋め込む半導体チップの板厚とダイアタッチフィルムの膜厚を合わせた厚みに合わせることが好ましく、例えば数１０μｍ程度とする。また、チップ埋め込み用凹部１０ａの広さは、半導体チップを埋め込んだときの半導体チップの側面と凹部の内壁面の間隔が３０μｍ程度となるように、半導体チップの広さより若干広く形成されていることが好ましい。
また、チップ埋め込み用凹部１０ａ内壁を含んでシリコン基板上に酸化シリコンからなり、膜厚が３００ｎｍ程度の下地絶縁膜１２が形成されている。 First Embodiment FIG. 1 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment.
For example, a chip embedding recess 10 a is formed in the silicon substrate 10. The depth of the recess 10a for embedding the chip is preferably matched to the thickness of the thickness of the semiconductor chip to be embedded and the thickness of the die attach film, for example, about several tens of μm. Further, the width of the chip embedding recess 10a is slightly larger than the width of the semiconductor chip so that the distance between the side surface of the semiconductor chip and the inner wall surface of the recess when the semiconductor chip is embedded is about 30 μm. Is preferred.
A base insulating film 12 made of silicon oxide and having a thickness of about 300 nm is formed on the silicon substrate including the inner wall of the chip embedding recess 10a.

チップ埋め込み用凹部１０ａの底面上に、例えば、能動素子が形成された回路面を有する第１半導体チップ１４がマウントされている。第１半導体チップ１４の板厚は、例えば２５〜５０μｍ程度である。第１半導体チップ１４は、半導体本体部分１４ａの回路面にパッド１４ｂが形成され、パッド１４ｂを除く領域は酸化シリコンなどの保護層１４ｃで覆われた構成であり、例えば１０μｍ程度の膜厚のダイアタッチフィルム１４ｄにより、フェースアップで、即ち、パッド１４ｂの形成面が上面を向くようにしてマウントされている。
また、例えば、チップ埋め込み用凹部１０ａの縁部近傍にＴｉＣｕ層がパターン形成されており、これは上記の第１半導体チップ１４をマウントするためのアライメントマーク１３である。 For example, a first semiconductor chip 14 having a circuit surface on which an active element is formed is mounted on the bottom surface of the chip embedding recess 10a. The plate thickness of the first semiconductor chip 14 is, for example, about 25 to 50 μm. The first semiconductor chip 14 has a structure in which a pad 14b is formed on the circuit surface of the semiconductor body portion 14a, and a region excluding the pad 14b is covered with a protective layer 14c such as silicon oxide. For example, the first semiconductor chip 14 has a thickness of about 10 μm. The touch film 14d is mounted face-up, that is, with the formation surface of the pad 14b facing the upper surface.
Further, for example, a TiCu layer is formed in the vicinity of the edge of the chip embedding recess 10a, which is the alignment mark 13 for mounting the first semiconductor chip 14 described above.

例えば、チップ埋め込み用凹部１０ａ内を埋め込み、第１半導体チップ１４を被覆して、ポリイミド樹脂、エポキシ樹脂あるいはアクリル樹脂などからなる第１樹脂層１５が形成されている。
第１樹脂層１５には、第１半導体チップ１４のパッド１４ｂに達する開口部１５ａが形成されている。
上記の開口部１５ａ内に埋め込まれて、第１半導体チップ１４のパッド１４ｂに接続するプラグ部分と一体になって、第１樹脂層１５上にＴｉＣｕなどのシード層１６及び銅層１８からなる第１配線が形成されている。 For example, the first resin layer 15 made of polyimide resin, epoxy resin, acrylic resin, or the like is formed so as to be embedded in the chip embedding recess 10a and to cover the first semiconductor chip 14.
In the first resin layer 15, an opening 15 a reaching the pad 14 b of the first semiconductor chip 14 is formed.
A first layer made of a seed layer 16 such as TiCu and a copper layer 18 is formed on the first resin layer 15 so as to be integrated with the plug portion embedded in the opening 15 a and connected to the pad 14 b of the first semiconductor chip 14. One wiring is formed.

また、例えば、第１半導体チップ１４の上方であって、第１樹脂層１５の上層あるいはその上層に形成された第１配線の上層に、能動素子が形成された回路面を有する第２半導体チップ２１がマウントされている。第２半導体チップ２１の板厚は、例えば２５〜５０μｍ程度である。第２半導体チップ２１は、半導体本体部分２１ａの回路面にパッド２１ｂが形成され、パッド２１ｂを除く領域は酸化シリコンなどの保護層２１ｃで覆われている構成であり、ダイアタッチフィルム２１ｄにより、フェースアップで、即ち、パッド２１ｂの形成面が上面を向くようにしてマウントされている。   Further, for example, a second semiconductor chip having a circuit surface on which an active element is formed above the first semiconductor chip 14 and above the first resin layer 15 or above the first wiring formed in the upper layer. 21 is mounted. The plate thickness of the second semiconductor chip 21 is, for example, about 25 to 50 μm. The second semiconductor chip 21 has a structure in which a pad 21b is formed on the circuit surface of the semiconductor body 21a, and a region excluding the pad 21b is covered with a protective layer 21c such as silicon oxide. That is, it is mounted so that the formation surface of the pad 21b faces the upper surface.

また、例えば、第１配線上には導電性ポスト２０が形成されている。導電性ポスト２０の高さは、例えば第２半導体チップ２１の表面の高さと同程度となっていることが好ましい。   Further, for example, a conductive post 20 is formed on the first wiring. The height of the conductive post 20 is preferably approximately the same as the height of the surface of the second semiconductor chip 21, for example.

また、例えば、導電性ポスト２０、第２半導体チップ２１、第１配線及び第１樹脂層を被覆して、ポリイミド樹脂、エポキシ樹脂あるいはアクリル樹脂などからなる第２樹脂層２２が形成されている。
第２樹脂層２２には、導電性ポスト２０の上面及び第２半導体チップ２１のパッド２１ｂに達する開口部２２ａが形成されている。
上記の開口部２２ａ内に埋め込まれて、導電性ポスト２０の上面及び第２半導体チップ２１のパッド２１ｂに接続するプラグ部分と一体になって、第２樹脂層２２上にＴｉＣｕなどのシード層２３及び銅層２５からなる第２配線が形成されている。 Further, for example, the second resin layer 22 made of polyimide resin, epoxy resin, acrylic resin, or the like is formed by covering the conductive posts 20, the second semiconductor chip 21, the first wiring, and the first resin layer.
In the second resin layer 22, an opening 22 a reaching the upper surface of the conductive post 20 and the pad 21 b of the second semiconductor chip 21 is formed.
A seed layer 23 made of TiCu or the like is formed on the second resin layer 22 by being embedded in the opening 22a and integrated with a plug portion connected to the upper surface of the conductive post 20 and the pad 21b of the second semiconductor chip 21. And the 2nd wiring which consists of a copper layer 25 is formed.

また、第２配線に接続して、銅などからなる導電性ポスト２７が形成されている。
導電性ポスト２７の間隙における第２樹脂層２２の上層に、ポリアミドイミド樹脂、ポリイミド樹脂、エポキシ樹脂、フェノール樹脂あるいはポリパラフェニレンベンゾビスオキサゾール樹脂などからなる絶縁性のバッファ層２８が形成されている。
さらに、バッファ層２８の表面において導電性ポスト２７に接続するようにバンプ（突起電極）２９が形成されている。 In addition, a conductive post 27 made of copper or the like is formed in connection with the second wiring.
An insulating buffer layer 28 made of polyamideimide resin, polyimide resin, epoxy resin, phenol resin, polyparaphenylenebenzobisoxazole resin, or the like is formed on the second resin layer 22 in the gap between the conductive posts 27. .
Further, bumps (projection electrodes) 29 are formed on the surface of the buffer layer 28 so as to be connected to the conductive posts 27.

上記の本実施形態の半導体装置において、第１半導体チップ１４は、例えばデジタルチップであり、一方、第２半導体チップ２１は、例えばアナログチップである。
基板１０に第１樹脂層１５及び第２樹脂層２２などが積層して絶縁層が形成されており、上記の第１半導体チップ１４及び第２半導体チップ２１が絶縁層中に埋め込まれている。 In the semiconductor device of the present embodiment, the first semiconductor chip 14 is, for example, a digital chip, while the second semiconductor chip 21 is, for example, an analog chip.
An insulating layer is formed by laminating a first resin layer 15 and a second resin layer 22 on the substrate 10, and the first semiconductor chip 14 and the second semiconductor chip 21 are embedded in the insulating layer.

上記の本実施形態の半導体装置は、ＳｉＰ形態の半導体装置において、基板上に２個の半導体チップが積層して一体化したスタック型であるが、基板に形成されたチップ埋め込み用凹部の底面上に第１半導体チップ１４がマウントされ、さらにその上方に積層して第２半導体チップ２１がマウントされているので、絶縁層に生じる段差に対して第１半導体チップ１４の分影響が軽減され、２個以上の半導体チップをスタック型に一体化しても段切れを抑制することができ、また、実装基板に実装したときの実装基板との間に生じる応力緩和に寄与する導電性ポストの高さのばらつきを低減して応力緩和機能を確保することができる。   The semiconductor device according to the present embodiment is a stack type in which two semiconductor chips are stacked and integrated on a substrate in the SiP type semiconductor device, but on the bottom surface of the chip embedding recess formed on the substrate. Since the first semiconductor chip 14 is mounted on the first semiconductor chip 14 and the second semiconductor chip 21 is further stacked on the first semiconductor chip 14, the influence of the first semiconductor chip 14 on the step generated in the insulating layer is reduced. Even if two or more semiconductor chips are integrated into a stack type, the step breakage can be suppressed, and the height of the conductive posts contributing to the relief of stress generated between the mounting chips and the mounting board can be reduced. Variations can be reduced to ensure a stress relaxation function.

第１半導体チップ１４及び第２半導体チップ２１が、上記と上下が逆の組み合わせ、あるいは、両者共にデジタルチップあるいはアナログチップであっても、上記と同様の効果が得られる。   Even when the first semiconductor chip 14 and the second semiconductor chip 21 are a combination of the above and upside down, or both are digital chips or analog chips, the same effects as described above can be obtained.

次に、上記の本実施形態の半導体装置の製造方法について図２〜１２を参照して説明する。本実施形態においては、例えば図２〜１２に示す全ての工程についてウェハレベルで行うことができる。
まず、図２（ａ）に示すように、例えば、７２５μｍの厚さのシリコン基板１０上に、スピン塗布などによりレジスト膜１１を形成し、フォトリソグラフィー工程により露光及び現像などを行って、チップ埋め込み用凹部形成領域を開口する。 Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. In the present embodiment, for example, all processes shown in FIGS. 2 to 12 can be performed at the wafer level.
First, as shown in FIG. 2A, for example, a resist film 11 is formed on a silicon substrate 10 having a thickness of 725 μm by spin coating or the like, and exposure and development are performed by a photolithography process to embed a chip. Open the recess forming region.

次に、図２（ｂ）に示すように、例えば、レジスト膜１１をマスクとしてドライまたはウェットエッチングを行い、シリコン基板１０にチップ埋め込み用凹部１０ａを形成する。チップ埋め込み用凹部１０ａの深さは、埋め込む半導体チップの板厚とダイアタッチフィルムの膜厚を合わせた厚みに合わせることが好ましく、例えば数１０μｍ程度とする。また、チップ埋め込み用凹部１０ａの広さは、半導体チップのサイズより片側３０μｍ大きく形成する。これは後工程で樹脂を埋め込みときのボイドの発生を抑制するためである。   Next, as shown in FIG. 2B, for example, dry or wet etching is performed using the resist film 11 as a mask to form a chip embedding recess 10 a in the silicon substrate 10. The depth of the recess 10a for embedding the chip is preferably matched to the thickness of the thickness of the semiconductor chip to be embedded and the thickness of the die attach film, for example, about several tens of μm. The width of the chip embedding recess 10a is formed to be 30 μm larger on one side than the size of the semiconductor chip. This is to suppress the generation of voids when the resin is embedded in a later process.

次に、図２（ｃ）に示すように、例えば、レジスト膜１１を除去した後、図２（ｄ）に示すように、例えば熱酸化法、ＣＶＤ（化学気相成長）法あるいはスパッタリング法などにより、３００ｎｍの膜厚の酸化シリコンからなる下地絶縁膜１２を形成する。   Next, as shown in FIG. 2C, for example, after the resist film 11 is removed, as shown in FIG. 2D, for example, a thermal oxidation method, a CVD (chemical vapor deposition) method, a sputtering method, or the like. Thus, the base insulating film 12 made of silicon oxide having a thickness of 300 nm is formed.

次に、図３（ａ）に示すように、例えば、チップ埋め込み用凹部１０ａ内を被覆して全面に、スパッタリング法によりＴｉＣｕ層１３ａを形成する。膜厚は、例えばＴｉを３００ｎｍ、Ｃｕを３００ｎｍとする。   Next, as shown in FIG. 3A, for example, a TiCu layer 13a is formed on the entire surface by covering the inside of the chip embedding recess 10a by sputtering. The film thickness is, for example, 300 nm for Ti and 300 nm for Cu.

次に、図３（ｂ）に示すように、例えば、スピン塗布などによりレジスト膜１３ｂを形成し、フォトリソグラフィー工程により露光及び現像などを行い、アライメントマークのパターンにパターニングする。例えば、半導体チップの１辺または２辺において形成され、チップ埋め込み用凹部１０ａの縁部近傍、例えば半導体チップのマウント位置のエッジから５０μｍ離れた場所におけるＬ字形状のパターンとする。   Next, as shown in FIG. 3B, for example, a resist film 13b is formed by spin coating or the like, and exposure and development are performed by a photolithography process to pattern an alignment mark pattern. For example, an L-shaped pattern is formed on one or two sides of the semiconductor chip and in the vicinity of the edge of the chip embedding recess 10a, for example, 50 μm away from the edge of the mounting position of the semiconductor chip.

次に、図３（ｃ）に示すように、例えば、レジスト膜１３ｂをマスクとしてＴｉＣｕ層１３ａをＲＩＥなどのドライエッチングによりパターン加工し、ＴｉＣｕからなるアライメントマーク１３とする。   Next, as shown in FIG. 3C, for example, the TiCu layer 13a is patterned by dry etching such as RIE using the resist film 13b as a mask to form an alignment mark 13 made of TiCu.

次に、図４（ａ）に示すように、レジスト膜１３ｂを除去した後、図４（ｂ）に示すように、例えば、チップ埋め込み用凹部１０ａの底面上において、予め別工程で形成された、半導体本体部分１４ａの能動素子が形成された回路面にパッド１４ｂが形成され、パッド１４ｂを除く領域は酸化シリコンなどの保護層１４ｃで覆われた構成の第１半導体チップ１４を、ダイアタッチフィルム１４ｄにより、フェースアップで、即ち、パッド１４ｂの形成面が上面を向くようにしてマウントする。   Next, as shown in FIG. 4A, after the resist film 13b is removed, as shown in FIG. 4B, for example, it was previously formed in a separate step on the bottom surface of the chip embedding recess 10a. The first semiconductor chip 14 having a structure in which the pad 14b is formed on the circuit surface on which the active element of the semiconductor body portion 14a is formed and the region excluding the pad 14b is covered with the protective layer 14c such as silicon oxide is attached to the die attach film. 14d is mounted face up, that is, with the formation surface of the pad 14b facing the upper surface.

第１半導体チップ１４の製造方法においては、例えば、研削法などにより２５〜５０μｍまで薄型化し、接着剤であるダイアタッチフィルム１４ｄを裏面にラミネートし、フルカットダイシングすることで個片薄型化を行う。
また、例えば、チップ埋め込み用凹部１０ａが半導体チップのサイズより片側３０μｍずつ大きくなるように形成されており、上記のように半導体チップを搭載したときの半導体チップの側面と凹部の内壁面の間隔Ｗが３０μｍ程度となる。 In the manufacturing method of the first semiconductor chip 14, for example, the thickness is reduced to 25 to 50 μm by a grinding method or the like, the die attach film 14 d as an adhesive is laminated on the back surface, and the individual pieces are thinned by full-cut dicing. .
Further, for example, the chip embedding recess 10a is formed so as to be larger by 30 μm on one side than the size of the semiconductor chip, and the distance W between the side surface of the semiconductor chip and the inner wall surface of the recess when the semiconductor chip is mounted as described above. Is about 30 μm.

上記の第１半導体チップの搭載においては、アライメントマーク１３と第１半導体チップ１４のパッド１４ｂを同時に認識して高精度に搭載を行う。
搭載条件は、チップサイズが１．５ｍｍ□の場合、温度１６０℃、荷重１．６Ｎ、時間２秒とする。チップサイズにより搭載の荷重を調整する。
搭載後、ダイアタッチフィルム１４ｄの硬化のため、１７０℃、１時間以上で硬化処理を行う。 In mounting the first semiconductor chip, the alignment mark 13 and the pad 14b of the first semiconductor chip 14 are simultaneously recognized and mounted with high accuracy.
The mounting conditions are a temperature of 160 ° C., a load of 1.6 N, and a time of 2 seconds when the chip size is 1.5 mm □. The mounting load is adjusted according to the chip size.
After mounting, a curing process is performed at 170 ° C. for 1 hour or longer in order to cure the die attach film 14d.

次に、図４（ｃ）に示すように、例えば、スピンコート法あるいは印刷法などにより、ポリイミド樹脂、シリコーン変性ポリイミド樹脂、エポキシ樹脂、ＢＣＢ樹脂、ＰＢＯ樹脂などの絶縁材料を供給し、チップ埋め込み用凹部内１０ａを埋め込んで第１半導体チップ１４を被覆する第１樹脂層１５を形成する。第１樹脂層１５は硬化後に５０μｍ程度の膜厚となるようにする。   Next, as shown in FIG. 4C, an insulating material such as a polyimide resin, a silicone-modified polyimide resin, an epoxy resin, a BCB resin, or a PBO resin is supplied by, for example, a spin coating method or a printing method to embed the chip. A first resin layer 15 that covers the first semiconductor chip 14 is formed by filling the recess 10 a for use. The first resin layer 15 has a thickness of about 50 μm after curing.

次に、図５（ａ）に示すように、例えば、露光量３００ｍＪ／ｃｍ2でパターン露光及び現像し、第１半導体チップ１４のパッド１４ｂに達する開口部１５ａを第１樹脂層１５に形成する。開口部１５ａのサイズは、例えば直径５０μｍ程度である。
現像後、３００℃（６０分）のポストキュア処理を行って第１樹脂層１５を硬化させる。 Next, as shown in FIG. 5A, for example, pattern exposure and development are performed at an exposure amount of 300 mJ / cm 2 , and an opening 15 a reaching the pad 14 b of the first semiconductor chip 14 is formed in the first resin layer 15. . The size of the opening 15a is, for example, about 50 μm in diameter.
After the development, post-curing treatment at 300 ° C. (60 minutes) is performed to cure the first resin layer 15.

次に、図５（ｂ）に示すように、例えば、デスカム処理を行い、スパッタリングの前処理エッチングを行い、さらにスパッタリングにより第１樹脂層１５の開口部１５ａ内を被覆して全面にＴｉＣｕ膜を成膜してシード層１６とする。例えば、膜厚はＴｉが１６０ｎｍ、Ｃｕが６００ｎｍとする。   Next, as shown in FIG. 5B, for example, a descum treatment is performed, a pretreatment etching of sputtering is performed, and the inside of the opening 15a of the first resin layer 15 is further coated by sputtering to form a TiCu film on the entire surface. A seed layer 16 is formed by film formation. For example, the film thickness is 160 nm for Ti and 600 nm for Cu.

次に、図５（ｃ）に示すように、例えば、第１樹脂層１５に形成した開口部１５ａと第１配線の形成領域以外にメッキされるのを防止するために、レジスト塗布及び現像処理を行い、第１樹脂層１５の開口部１５ａと第１配線の形成領域を開口するパターンのレジスト膜１７を成膜する。   Next, as shown in FIG. 5C, for example, in order to prevent plating in areas other than the opening 15a formed in the first resin layer 15 and the formation area of the first wiring, resist coating and development processing are performed. Then, a resist film 17 having a pattern opening the opening 15a of the first resin layer 15 and the formation region of the first wiring is formed.

次に、図６（ａ）に示すように、例えば、レジスト膜１７をマスクとし、シード層１６を一方の電極とする電解メッキにより銅をメッキして、第１樹脂層１５に形成した開口部１５ａと第１配線の形成領域に銅層１８を形成する。   Next, as shown in FIG. 6A, for example, an opening formed in the first resin layer 15 by plating copper by electrolytic plating using the resist film 17 as a mask and the seed layer 16 as one electrode. A copper layer 18 is formed in the formation region of 15a and the first wiring.

次に、図６（ｂ）に示すように、例えば、アッシング処理などによりレジスト膜１７を除去する。   Next, as shown in FIG. 6B, the resist film 17 is removed by, for example, an ashing process.

次に、図６（ｃ）に示すように、例えば、レジスト塗布及び現像処理を行い、導電性ポストの形成領域を開口するパターンのレジスト膜１９を成膜する。   Next, as shown in FIG. 6C, for example, resist coating and development are performed to form a resist film 19 having a pattern that opens a conductive post formation region.

次に、図７（ａ）に示すように、例えば、シード層１６を一方の電極とした銅の電解メッキにより、導電性ポスト用の開口部内に導電性ポスト２０を形成する。導電性ポスト２０は、例えば５０μｍ程度の高さとする。   Next, as shown in FIG. 7A, the conductive posts 20 are formed in the openings for the conductive posts by, for example, electrolytic plating of copper using the seed layer 16 as one electrode. The conductive post 20 has a height of about 50 μm, for example.

次に、図７（ｂ）に示すように、例えば、レジスト膜１９を除去し、図７（ｃ）に示すように、導電性ポスト２０及び銅層１８をマスクとしてシード層１６をエッチング加工する。これにより、シード層１６及び銅層１８からなる第１配線が形成され、さらに第１配線上に導電性ポストが形成された構成とする。   Next, as shown in FIG. 7B, for example, the resist film 19 is removed, and as shown in FIG. 7C, the seed layer 16 is etched using the conductive posts 20 and the copper layer 18 as a mask. . Thereby, the first wiring composed of the seed layer 16 and the copper layer 18 is formed, and the conductive post is further formed on the first wiring.

次に、図８（ａ）に示すように、例えば、予め別工程で形成された、半導体本体部分２１ａの能動素子が形成された回路面にパッド２１ｂが形成され、パッド２１ｂを除く領域は酸化シリコンなどの保護層２１ｃで覆われた構成の第２半導体チップ２１を、第１半導体チップ１４の上方であって、第１樹脂層１５及び第１配線の上層に、ダイアタッチフィルム２１ｄにより、フェースアップで、即ち、パッド２１ｂの形成面を上面にしてマウントする。
このとき、第１配線を形成するときなどにおいて予め形成したアライメントマークと第２半導体チップのパッドを同時に認識して高精度に搭載を行う。 Next, as shown in FIG. 8A, for example, a pad 21b is formed on the circuit surface on which the active element of the semiconductor body portion 21a is formed in a separate process in advance, and the region excluding the pad 21b is oxidized. The second semiconductor chip 21 having a configuration covered with a protective layer 21c such as silicon is disposed above the first semiconductor chip 14 and above the first resin layer 15 and the first wiring by a die attach film 21d. In other words, the mounting is performed with the formation surface of the pad 21b as the upper surface.
At this time, when forming the first wiring or the like, the alignment mark formed in advance and the pad of the second semiconductor chip are simultaneously recognized and mounted with high accuracy.

第２半導体チップ２１の製造方法においては、例えば、研削法などにより２５〜５０μｍまで薄型化し、接着剤であるダイアタッチフィルム２１ｄを裏面にラミネートし、フルカットダイシングすることで個片薄型化を行う。
搭載条件は、チップサイズが１．５ｍｍ□の場合、温度１６０℃、荷重１．６Ｎ、時間２秒とする。チップサイズにより搭載の荷重を調整する。
搭載後、ダイアタッチフィルム２１ｄの硬化のため、１７０℃、１時間以上で硬化処理を行う。 In the manufacturing method of the second semiconductor chip 21, for example, the thickness is reduced to 25 to 50 μm by a grinding method or the like, the die attach film 21 d as an adhesive is laminated on the back surface, and the individual pieces are thinned by full-cut dicing. .
The mounting conditions are a temperature of 160 ° C., a load of 1.6 N, and a time of 2 seconds when the chip size is 1.5 mm □. The mounting load is adjusted according to the chip size.
After mounting, a curing process is performed at 170 ° C. for 1 hour or more for curing the die attach film 21d.

次に、図８（ｂ）に示すように、例えば、スピンコート法あるいは印刷法などにより、ＢＣＢ樹脂、ポリイミド樹脂、エポキシ樹脂、ＰＢＯ樹脂などの感光性絶縁材料を供給し、第２樹脂層２２を形成する。例えば、硬化後に５０μｍの膜厚となるように形成する。   Next, as shown in FIG. 8B, a photosensitive insulating material such as BCB resin, polyimide resin, epoxy resin, PBO resin or the like is supplied by, for example, a spin coating method or a printing method, and the second resin layer 22 is supplied. Form. For example, it is formed to have a film thickness of 50 μm after curing.

次に、図８（ｃ）に示すように、例えば、露光量３００ｍＪ／ｃｍ2でパターン露光及び現像し、導電性ポスト２０の上面及び第２半導体チップ２１のパッド２１ｂに達する開口部２２ａを第２樹脂層２２に形成する。
現像後、３００℃（６０分）のポストキュア処理を行って第２樹脂層２２を硬化させる。 Next, as shown in FIG. 8C, for example, pattern exposure and development are performed at an exposure amount of 300 mJ / cm 2 , and the opening 22a reaching the top surface of the conductive post 20 and the pad 21b of the second semiconductor chip 21 is formed. Two resin layers 22 are formed.
After development, post-curing treatment at 300 ° C. (60 minutes) is performed to cure the second resin layer 22.

次に、図９（ａ）に示すように、例えば、デスカム処理を行い、スパッタリングの前処理エッチングを行い、さらにスパッタリングにより第２樹脂層２２の開口部２２ａ内を被覆して全面にＴｉＣｕ膜を成膜してシード層２３とする。例えば、膜厚はＴｉが１６０ｎｍ、Ｃｕが６００ｎｍとする。   Next, as shown in FIG. 9A, for example, a descum treatment is performed, a pretreatment etching of sputtering is performed, and the inside of the opening 22a of the second resin layer 22 is further coated by sputtering to form a TiCu film on the entire surface. A seed layer 23 is formed by film formation. For example, the film thickness is 160 nm for Ti and 600 nm for Cu.

次に、図９（ｂ）に示すように、例えば、第２樹脂層２２に形成した開口部２２ａと第２配線の形成領域以外にメッキされるのを防止するために、レジスト塗布及び現像処理を行い、第２樹脂層２２の開口部２２ａと第２配線の形成領域を開口するパターンのレジスト膜２４を成膜する。   Next, as shown in FIG. 9B, for example, in order to prevent plating other than the opening 22a formed in the second resin layer 22 and the formation area of the second wiring, resist coating and development processing are performed. Then, a resist film 24 having a pattern that opens the opening 22a of the second resin layer 22 and the formation region of the second wiring is formed.

次に、図９（ｃ）に示すように、例えば、レジスト膜２４をマスクとし、シード層２３を一方の電極とする電解メッキにより銅をメッキして、第２樹脂層２２に形成した開口部２２ａと第２配線の形成領域に銅層２５を形成する。   Next, as shown in FIG. 9C, for example, an opening formed in the second resin layer 22 by plating copper by electrolytic plating using the resist film 24 as a mask and the seed layer 23 as one electrode. A copper layer 25 is formed in the formation region of 22a and the second wiring.

次に、図１０（ａ）に示すように、例えば、アッシング処理などによりレジスト膜２４を除去する。   Next, as shown in FIG. 10A, the resist film 24 is removed by, for example, an ashing process.

次に、図１０（ｂ）に示すように、例えば、レジスト膜２６を成膜あるいは感光性ドライフィルムを貼り合わせ、パターン露光及び現像して導電性ポスト用の開口部を形成する。   Next, as shown in FIG. 10B, for example, a resist film 26 is formed or a photosensitive dry film is bonded, and pattern exposure and development are performed to form openings for conductive posts.

次に、図１０（ｃ）に示すように、例えば、シード層２３を一方の電極とした銅の電解メッキにより、導電性ポスト用の開口部内に導電性ポスト２７を形成する。導電性ポスト２７は、例えば直径１８０〜３００μｍ、高さ８０〜１８０μｍとする。   Next, as shown in FIG. 10C, the conductive posts 27 are formed in the openings for the conductive posts by, for example, electrolytic plating of copper using the seed layer 23 as one electrode. The conductive post 27 has a diameter of 180 to 300 μm and a height of 80 to 180 μm, for example.

次に、図１１（ａ）に示すように、例えば、レジスト膜２６あるいはドライフィルムを除去し、図１１（ｂ）に示すように、導電性ポスト２７及び銅層２５をマスクとしてシード層２３をエッチング加工する。これにより、シード層２３及び銅層２５からなる第２配線が形成される。   Next, as shown in FIG. 11A, for example, the resist film 26 or the dry film is removed, and as shown in FIG. 11B, the seed layer 23 is formed using the conductive posts 27 and the copper layer 25 as a mask. Etching process. Thereby, the second wiring composed of the seed layer 23 and the copper layer 25 is formed.

次に、図１１（ｃ）に示すように、例えば、エポキシ系樹脂、ポリイミド系樹脂、シリコーン系樹脂、ポリアミドイミド樹脂、ポリイミド樹脂、フェノール樹脂あるいはポリパラフェニレンベンゾビスオキサゾール樹脂などの樹脂を、スピンコート、印刷またはモールドなどにより成膜し、導電性ポスト２７を完全に覆うような膜厚で絶縁性のバッファ層２８を形成する。   Next, as shown in FIG. 11C, for example, a resin such as an epoxy resin, a polyimide resin, a silicone resin, a polyamideimide resin, a polyimide resin, a phenol resin, or a polyparaphenylene benzobisoxazole resin is spun. A film is formed by coating, printing, molding, or the like, and the insulating buffer layer 28 is formed with a film thickness that completely covers the conductive post 27.

次に、図１２（ａ）に示すように、例えば、バッファ層２８の樹脂硬化後に、研削により導電性ポスト２７の頭出しを行う。このときの条件は、例えば＃６００のホイールを用い、３５００ｒｐｍ、０．５ｍｍ／秒とする。   Next, as shown in FIG. 12A, for example, after the resin hardening of the buffer layer 28, the cue of the conductive post 27 is performed by grinding. The conditions at this time are set to 3500 rpm and 0.5 mm / second using, for example, a # 600 wheel.

次に、図１２（ｂ）に示すように、例えば、導電性ポスト２７に接続するように、例えばハンダボールの搭載、あるいはハンダペーストの印刷などにより、バンプ（突起電極）２９を形成する。   Next, as shown in FIG. 12B, bumps (projection electrodes) 29 are formed by, for example, mounting solder balls or printing solder paste so as to connect to the conductive posts 27, for example.

次に、図１２（ｃ）に示すように、例えば、シリコン基板１０の裏面側からＢＧＲにより所望の薄さまで薄型化し、さらにブレードＢによりシリコン基板１０をダイシングして薄型個片化する。   Next, as shown in FIG. 12C, for example, the silicon substrate 10 is thinned to a desired thickness by BGR from the back side of the silicon substrate 10, and the silicon substrate 10 is diced by the blade B to be thinly divided into individual pieces.

上記の本実施形態に係る半導体装置の製造方法によれば、ＳｉＰ形態の半導体装置において、基板に形成されたチップ埋め込み用凹部の底面上に第１半導体チップをマウントし、さらにその上方に積層して第２半導体チップをマウントするので、絶縁層に生じる段差に対して第１半導体チップの分影響が軽減され、２個以上の半導体チップをスタック型に一体化しても段切れを抑制して、また、実装基板に実装したときの実装基板との間に生じる応力緩和に寄与する導電性ポストの高さのばらつきを低減して応力緩和機能を確保して、半導体装置を製造することができる。   According to the method of manufacturing a semiconductor device according to the present embodiment, in the SiP-type semiconductor device, the first semiconductor chip is mounted on the bottom surface of the chip embedding recess formed on the substrate, and further laminated thereon. Since the second semiconductor chip is mounted, the influence of the first semiconductor chip is reduced with respect to the step generated in the insulating layer, and even if two or more semiconductor chips are integrated into a stack type, the disconnection is suppressed, In addition, it is possible to manufacture a semiconductor device by ensuring the stress relaxation function by reducing the variation in the height of the conductive posts that contribute to stress relaxation generated between the mounting substrate and the mounting substrate.

上記の本実施形態に係る半導体装置に内蔵される半導体チップとしては、デジタル、デジタルチップの組み合わせ、アナログ、アナログチップの組み合わせ、デジタル、アナログチップの組み合わせにおいて相互干渉にないスタック型薄型構造が可能である。
また、１層目と２層目のチップサイズは、再配線構造のため大小関係の制約を受けない。いずれのチップもワイヤーボンディングでの接続がないので、ワイヤのループ高さの分絶縁膜の厚さを厚くする必要がなく、薄型化のスタック構造が実現する。
高熱放散性が必要な半導体チップを１層目に配置し、シリコン基板の高熱放散性を利用させることで低熱抵抗型のＳｉＰを構成することが可能である。 As a semiconductor chip built in the semiconductor device according to the above-described embodiment, a stack type thin structure that is free from mutual interference in a combination of digital and digital chips, a combination of analog and analog chips, and a combination of digital and analog chips is possible. is there.
Further, the chip size of the first layer and the second layer is not restricted by the size relationship because of the rewiring structure. Since none of the chips is connected by wire bonding, it is not necessary to increase the thickness of the insulating film by the wire loop height, and a thin stack structure is realized.
A low thermal resistance type SiP can be configured by arranging a semiconductor chip that requires high heat dissipation in the first layer and utilizing the high heat dissipation of the silicon substrate.

（変形例）
上記の実施形態においては、シリコン基板と第１半導体チップの間にノイズ遮蔽層は形成されていないが、チップ埋め込み用凹部１０ａ内において、シリコン基板１０と第１半導体チップ１４の間にノイズ遮蔽層となる誘電体層あるいは導電層が形成された構成とすることができる。
例えば、チップ埋め込み用凹部１０ａ内における底面上の所定の領域に、誘電体層あるいは導電層をパターン形成し、導電層の場合にはグラウンドなど一定電位に固定されるように電気的に接続して製造することができる。例えば、アライメントマークを形成するために成膜されたＴｉＣｕ層を、チップ埋め込み用凹部の底面上において、３０μｍ□のメッシュのパターンにエッチング加工し、これをグラウンド電位に固定することなどによりノイズ遮蔽層とすることができる。
このように、ノイズ遮蔽層となる誘電体層あるいはグランドパターンとなる導電層が設けられていると、チップ間のノイズをさらに抑制できる。 (Modification)
In the above embodiment, the noise shielding layer is not formed between the silicon substrate and the first semiconductor chip. However, the noise shielding layer is interposed between the silicon substrate 10 and the first semiconductor chip 14 in the chip embedding recess 10a. A dielectric layer or a conductive layer to be formed can be formed.
For example, a dielectric layer or a conductive layer is patterned in a predetermined region on the bottom surface in the chip embedding recess 10a, and in the case of the conductive layer, it is electrically connected so as to be fixed at a constant potential such as ground. Can be manufactured. For example, the TiCu layer formed to form the alignment mark is etched into a 30 μm square mesh pattern on the bottom surface of the chip embedding recess, and this is fixed to the ground potential. It can be.
Thus, when a dielectric layer serving as a noise shielding layer or a conductive layer serving as a ground pattern is provided, noise between chips can be further suppressed.

第２実施形態
図１３は本実施形態に係るＳｉＰ形態の半導体装置の断面図である。
実質的に第１実施形態の半導体装置と同様の構成であるが、シリコン基板１０に形成されたチップ埋め込み用凹部１０ａの底面が露出する程度にまで、シリコン基板１０の裏面側から研削された構成である。
第１実施形態の半導体装置よりもさらに薄型化を実現できる。
また、図１４は本実施形態に係るＳｉＰ形態の半導体装置の変形例の断面図である。
図１３の半導体装置よりもさらにシリコン基板１０裏面からの研削が進められ、第１半導体チップ１４の途中まで研削された構成である。
第１半導体チップ１４は回路面が上方を向いてマウントされているので、シリコン基板１０側から研削されても問題はなく、図１３の半導体装置よりもさらに薄型化を実現できる。 Second Embodiment FIG. 13 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment.
The structure is substantially the same as that of the semiconductor device of the first embodiment, but is ground from the back side of the silicon substrate 10 to such an extent that the bottom surface of the chip embedding recess 10a formed in the silicon substrate 10 is exposed. It is.
Thinning can be realized further than the semiconductor device of the first embodiment.
FIG. 14 is a cross-sectional view of a modification of the SiP-type semiconductor device according to this embodiment.
In this configuration, grinding from the rear surface of the silicon substrate 10 is further advanced than in the semiconductor device of FIG.
Since the first semiconductor chip 14 is mounted with the circuit surface facing upward, there is no problem even if the first semiconductor chip 14 is ground from the silicon substrate 10 side, and the thickness can be further reduced as compared with the semiconductor device of FIG.

本発明は上記の説明に限定されない。
例えば、第１及び第２配線などに、インダクタンスやキャパシタなどの受動素子が形成されていてもよい。
実施形態においては、絶縁層中の配線として２層の配線（第１配線及び第２配線）が形成されているが、これに限らない。樹脂の絶縁層の層数も上記のような層数などに限定されない。
シリコン基板自体にも能動素子などを含む電子回路が形成されていてもよい。
その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。 The present invention is not limited to the above description.
For example, passive elements such as inductances and capacitors may be formed on the first and second wirings.
In the embodiment, two layers of wiring (first wiring and second wiring) are formed as the wiring in the insulating layer, but the present invention is not limited to this. The number of resin insulation layers is not limited to the number of layers as described above.
An electronic circuit including active elements may be formed on the silicon substrate itself.
In addition, various modifications can be made without departing from the scope of the present invention.

本発明の半導体装置は、システムインパッケージ形態の半導体装置に適用できる。   The semiconductor device of the present invention can be applied to a semiconductor device in a system in package form.

本発明の半導体装置の製造方法は、システムインパッケージ形態の半導体装置の製造方法に適用できる。   The semiconductor device manufacturing method of the present invention can be applied to a system-in-package semiconductor device manufacturing method.

図１は本発明の第１実施形態に係る半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device according to the first embodiment of the present invention. 図２（ａ）〜（ｄ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。2A to 2D are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図３（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。3A to 3C are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図４（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。4A to 4C are cross-sectional views illustrating the manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図５（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。5A to 5C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図６（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。6A to 6C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図７（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。FIGS. 7A to 7C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図８（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。8A to 8C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図９（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。9A to 9C are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図１０（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。10A to 10C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図１１（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。11A to 11C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図１２（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。12A to 12C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図１３は本発明の第２実施形態に係る半導体装置の断面図である。FIG. 13 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention. 図１４は本発明の第２実施形態に係る半導体装置の変形例の断面図である。FIG. 14 is a cross-sectional view of a modification of the semiconductor device according to the second embodiment of the present invention. 図１５は従来例に係る半導体装置の断面図である。FIG. 15 is a cross-sectional view of a conventional semiconductor device.

符号の説明Explanation of symbols

１０…シリコン基板、１１…レジスト膜、１２…下地絶縁膜、１３…アライメントマーク、１３ａ…ＴｉＣｕ層、１３ｂ…レジスト膜、１４…第１半導体チップ、１４ａ…半導体本体部分、１４ｂ…パッド、１４ｃ…保護層、１４ｄ…ダイアタッチフィルム、１５…第１樹脂層、１５ａ…開口部、１６…シード層、１７…レジスト膜、１８…銅層、１９…レジスト膜、２０…導電性ポスト、２１…第２半導体チップ、２１ａ…半導体本体部分、２１ｂ…パッド、２１ｃ…保護層、２１ｄ…ダイアタッチフィルム、２２…第２樹脂層、２２ａ…開口部、２３…シード層、２４…レジスト膜、２５…銅層、２６…レジスト膜、２７…導電性ポスト、２８…バッファ層、２９…バンプ、Ｂ…ブレード
DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 11 ... Resist film, 12 ... Base insulating film, 13 ... Alignment mark, 13a ... TiCu layer, 13b ... Resist film, 14 ... 1st semiconductor chip, 14a ... Semiconductor main-body part, 14b ... Pad, 14c ... Protective layer, 14d ... die attach film, 15 ... first resin layer, 15a ... opening, 16 ... seed layer, 17 ... resist film, 18 ... copper layer, 19 ... resist film, 20 ... conductive post, 21 ... first 2 semiconductor chip, 21a ... semiconductor body portion, 21b ... pad, 21c ... protective layer, 21d ... die attach film, 22 ... second resin layer, 22a ... opening, 23 ... seed layer, 24 ... resist film, 25 ... copper Layer, 26 ... resist film, 27 ... conductive post, 28 ... buffer layer, 29 ... bump, B ... blade

Claims (6)

半導体を含んでパッケージ化されており、
チップ埋め込み用凹部が形成されたシリコン基板と、
能動素子が形成され、前記チップ埋め込み用凹部の底面上にマウントされた第１半導体チップと、
能動素子が形成され、前記第１半導体チップの上方に積層してマウントされた第２半導体チップと、
前記チップ埋め込み用凹部内を埋め込んで前記第１半導体チップの上層であって前記第２半導体チップの下層に形成された第１樹脂層と、前記第２半導体チップの上層に前記第２半導体チップを被覆して形成された第２樹脂層とを含む絶縁層と、
前記絶縁層中に埋め込まれて前記第１半導体チップ及び前記第２半導体チップに接続して形成された配線層と
を有し、
前記配線層が前記第１樹脂層と前記第２樹脂層の間において前記第２樹脂層に被覆された導電性ポストを含む
半導体装置。 Packaged with semiconductors,
A silicon substrate having a chip embedding recess formed therein;
A first semiconductor chip on which an active element is formed and mounted on the bottom surface of the chip embedding recess;
A second semiconductor chip on which an active element is formed and stacked and mounted above the first semiconductor chip ;
A first resin layer formed in an upper layer of the first semiconductor chip and in a lower layer of the second semiconductor chip by filling the recess for embedding the chip, and the second semiconductor chip on an upper layer of the second semiconductor chip. An insulating layer including a second resin layer formed by coating;
A wiring layer embedded in the insulating layer and connected to the first semiconductor chip and the second semiconductor chip;
Have
A semiconductor device, wherein the wiring layer includes a conductive post covered with the second resin layer between the first resin layer and the second resin layer . 前記チップ埋め込み用凹部内において前記シリコン基板と前記第１半導体チップの間に誘電体層が形成されている
請求項１に記載の半導体装置。 The semiconductor device according to claim 1 , wherein a dielectric layer is formed between the silicon substrate and the first semiconductor chip in the recess for embedding the chip. 前記チップ埋め込み用凹部内において前記シリコン基板と前記第１半導体チップの間に導電層が形成されている
請求項１に記載の半導体装置。 The semiconductor device according to claim 1 , wherein a conductive layer is formed between the silicon substrate and the first semiconductor chip in the recess for embedding the chip. 半導体を含んでパッケージ化された半導体装置を製造するために、
シリコン基板にチップ埋め込み用凹部を形成する工程と、
前記チップ埋め込み用凹部の底面上に、能動素子が形成された第１半導体チップをマウントする工程と、
前記第１半導体チップの上方に積層して、能動素子が形成された第２半導体チップをマウントする工程と、
前記チップ埋め込み用凹部内を埋め込んで前記第１半導体チップの上層であって前記第２半導体チップの下層に第１樹脂層を形成する工程と、前記第２半導体チップの上層に前記第２半導体チップを被覆して第２樹脂層を形成する工程とを含む絶縁層を形成する工程と、
前記絶縁層中に埋め込まれて前記第１半導体チップ及び前記第２半導体チップに接続して配線層を形成する工程を有し、
前記配線層を形成する工程が前記第１樹脂層と前記第２樹脂層の間に導電性ポストを形成する工程を含み、前記第２樹脂層を形成する工程において前記導電性ポストを被覆して形成する
半導体装置の製造方法。 In order to manufacture a semiconductor device packaged including a semiconductor,
Forming a recess for chip embedding in a silicon substrate;
Mounting a first semiconductor chip on which an active element is formed on the bottom surface of the chip embedding recess;
Mounting a second semiconductor chip on which an active element is formed by stacking above the first semiconductor chip ;
Forming a first resin layer in an upper layer of the first semiconductor chip and in a lower layer of the second semiconductor chip by filling the recess for chip embedding; and the second semiconductor chip in an upper layer of the second semiconductor chip. Forming an insulating layer including a step of forming a second resin layer by covering
Forming a wiring layer embedded in the insulating layer and connected to the first semiconductor chip and the second semiconductor chip;
The step of forming the wiring layer includes a step of forming a conductive post between the first resin layer and the second resin layer, and the conductive post is covered in the step of forming the second resin layer. A method for manufacturing a semiconductor device to be formed . 前記第１半導体チップをマウントする工程の前に前記チップ埋め込み用凹部内において誘電体層を形成する工程をさらに有し、
前記第１半導体チップをマウントする工程において前記誘電体層上にマウントする
請求項４に記載の半導体装置の製造方法。 A step of forming a dielectric layer in the recess for embedding the chip before the step of mounting the first semiconductor chip;
The method for manufacturing a semiconductor device according to claim 4 , wherein the first semiconductor chip is mounted on the dielectric layer in the step of mounting. 前記第１半導体チップをマウントする工程の前に前記チップ埋め込み用凹部内において導電層を形成する工程をさらに有し、
前記第１半導体チップをマウントする工程において前記導電層上にマウントする
請求項４に記載の半導体装置の製造方法。 A step of forming a conductive layer in the recess for embedding the chip before the step of mounting the first semiconductor chip;
The method for manufacturing a semiconductor device according to claim 4 , wherein the first semiconductor chip is mounted on the conductive layer in the step of mounting the first semiconductor chip.
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