JP4343777B2 - Electronic component built-in wafer - Google Patents

Electronic component built-in wafer Download PDF

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JP4343777B2
JP4343777B2 JP2004178089A JP2004178089A JP4343777B2 JP 4343777 B2 JP4343777 B2 JP 4343777B2 JP 2004178089 A JP2004178089 A JP 2004178089A JP 2004178089 A JP2004178089 A JP 2004178089A JP 4343777 B2 JP4343777 B2 JP 4343777B2
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electronic component
wafer
component built
layer
wafer substrate
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JP2006005053A5 (en
JP2006005053A (en
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政隆 山口
悟 倉持
敦 高野
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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  • Engineering & Computer Science (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component built-in wafer which can manufacture an electronic component built-in module usable in a plurality of stacks. <P>SOLUTION: The electronic component built-in wafer comprises a wafer board 21 which is zoned for forming a plurality of faces by the dicing area 12 of a predetermined width, an electronic component built-in recess 22 every face formation, an electronic component 31 contained in each recess, and a plurality of wires 25 arranged on a wafer board through an insulating layer 24 so as to be connected with a terminal 32 of the electronic component every face formation. These wires have a bump pad 26 or a wire bonding pad, and a both-side conducting pad 27 at a pointed end thereof. The both-side conducting pad 27 is located in the dicing area and has a fine opening 27a at a substantial center, and the wafer board is exposed to this fine opening 27a. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

本発明は、多面付けでＬＳＩチップ等の電子部品を内蔵した電子部品内蔵ウエハに関する。   The present invention relates to an electronic component built-in wafer in which electronic components such as LSI chips are built in a multifaceted manner.

従来の多層配線基板は、例えば、サブトラクティブ法等で作製した低密度配線を有する両面基板をコア基板とし、このコア基板の両面にビルドアップ法により高密度配線を形成して作製されたものである。また、最近では、ＬＳＩチップ等を多層配線基板上に直接実装するベアチップ実装法が提案されている。ベアチップ実装法では、予め多層配線基板上に形成された配線の接続パッド部に、ボンディング・ワイヤ、ハンダや金属球等からなるバンプ、異方性導電膜、導電性接着剤、光収縮性樹脂等の接続手段を用いて半導体チップが実装される。また、作製する半導体装置にキャパシターやインダクター等のＬＣＲ回路部品が必要な場合は、半導体チップと同様に、多層配線基板に外付けで実装されている。   A conventional multilayer wiring board is produced by, for example, using a double-sided board having low-density wiring produced by a subtractive method or the like as a core board, and forming high-density wiring on both sides of the core board by a build-up method. is there. Recently, a bare chip mounting method in which an LSI chip or the like is directly mounted on a multilayer wiring board has been proposed. In the bare chip mounting method, bonding wires, bumps made of solder, metal balls, etc., anisotropic conductive films, conductive adhesives, light-shrinkable resins, etc., are formed on wiring connection pads formed on a multilayer wiring board in advance. A semiconductor chip is mounted using the connecting means. Further, when an LCR circuit component such as a capacitor or an inductor is required for the semiconductor device to be manufactured, it is externally mounted on a multilayer wiring board as in the semiconductor chip.

しかし、多層配線基板上に形成された配線の接続パッド部は、半導体チップ等の電子部品の実装部位とは別の部位に設けられるため、多層配線基板の面方向の広がりが必要であった。このため、多層配線基板の小型化には限界があり、実装される電子部品の数が増えるにしたがって、小型化は更に困難となる傾向にあった。
これに対応するために、半導体チップを実装した薄い基板と、上下導通ビアを備えた穴明き枠基板を、それぞれ複数個作製しておき、多層配線基板の作製時に、この実装基板と枠基板とを１つのモジュールとして一括で積層する方法が開示されている（特許文献１）。この方法では、複数のモジュールを積層しても、多層配線基板の面方向の広がりは必要がないため、多層配線基板の小型化が可能であった。
特開２００２−２７１０１５号公報 However, since the connection pad portion of the wiring formed on the multilayer wiring board is provided in a part different from the mounting part of the electronic component such as a semiconductor chip, it is necessary to expand the surface direction of the multilayer wiring board. For this reason, there is a limit to the miniaturization of the multilayer wiring board, and the miniaturization tends to become more difficult as the number of electronic components to be mounted increases.
In order to cope with this, a plurality of thin substrates on which semiconductor chips are mounted and a perforated frame substrate having vertical conduction vias are prepared, and when mounting a multilayer wiring substrate, the mounting substrate and the frame substrate are prepared. Has been disclosed as a single module (Patent Document 1). In this method, even if a plurality of modules are stacked, it is not necessary to expand the surface direction of the multilayer wiring board, and therefore the multilayer wiring board can be reduced in size.
JP 2002-271015 A

しかしながら、上述のような実装基板と枠基板とからなるモジュールでは、個々の電子部品を基板の所定の位置に実装するための位置合せを正確に行なう必要があり、工程管理が煩雑であるとともに、実装位置のズレを生じた場合、多層配線基板の信頼性が低下するという問題がある
この問題を解消するために、電子部品を載置するための凹部を基板の所定位置に形成することにより、電子部品の実装を容易、確実なものとすることが考えられる。この場合、多面付けのウエハ基板に上記のような電子部品を内蔵させ、その後、所望の多層配線をウエハ基板上に形成した後、ダイシングすることにより個々の電子部品内蔵モジュールが得られる。このような電子部品内蔵モジュールを複数重ねて使用する場合、重ねられた各電子部品内蔵モジュール間の接続、すなわち、電子部品モジュールにおける表裏導通が必要となる。しかし、内蔵されている電子部品の内部構造は非常に密であり、表裏導通のための貫通孔を形成するようなスペースの余裕はなく、また、電子部品の周囲にワイヤボンディング用のパッドが設けられている場合もあるが、ワイヤボンディング用のパッドは、一般に面積が小さく、表裏導通のための貫通孔を形成することは困難であった。 However, in the module composed of the mounting board and the frame board as described above, it is necessary to accurately perform alignment for mounting each electronic component at a predetermined position on the board, and the process management is complicated. When the mounting position shift occurs, there is a problem that the reliability of the multilayer wiring board is lowered.To solve this problem, by forming a recess for placing electronic components at a predetermined position on the board, It is conceivable that electronic parts can be easily and reliably mounted. In this case, individual electronic component built-in modules can be obtained by incorporating the electronic components as described above into a multi-sided wafer substrate, and then forming a desired multilayer wiring on the wafer substrate and then dicing. When a plurality of such electronic component built-in modules are used in a stacked manner, connection between the stacked electronic component built-in modules, that is, conduction between the front and back of the electronic component module is required. However, the internal structure of the built-in electronic components is very dense, so there is not enough room to form through holes for front and back conduction, and pads for wire bonding are provided around the electronic components. In some cases, the wire bonding pad generally has a small area, and it is difficult to form a through-hole for front and back conduction.

さらに、所望の電子部品を組み込みながら多層配線基板を作製することも考えられるが、配線の端子上にバンプを介して電子部品を載置するための精密な位置合せが必要であり、また、電気絶縁層、導通ビア、配線層等を形成する工程が繰り返され、このため工程が複雑で長いものとなり、製造歩留まりの低下を来たし易いという問題があった。
本発明は、上記のような実情に鑑みてなされたものであり、複数積み重ねての使用が可能な電子部品内蔵モジュールを製造することができる電子部品内蔵ウエハを提供することを目的とする。 Furthermore, it is conceivable to fabricate a multilayer wiring board while incorporating desired electronic components, but precise alignment is required for placing the electronic components on the wiring terminals via bumps. The process of forming an insulating layer, a conductive via, a wiring layer, and the like is repeated, which causes a problem that the process becomes complicated and long, and the manufacturing yield tends to be lowered.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an electronic component built-in wafer capable of manufacturing an electronic component built-in module that can be used in a stacked state.

このような目的を達成するために、本発明の電子部品内蔵ウエハは、所定の幅のダイシングエリアにより多面付けに区画され、各面付け毎に電子部品内蔵用の凹部を備えるウエハ基板と、該凹部の内部を含むウエハ基板の全面に配設された絶縁層と、前記凹部に前記絶縁層を介して内蔵された電子部品と、各面付け毎に該電子部品を端子部を除いて被覆する絶縁樹脂層と、各面付け毎に前記電子部品の端子部と接続するように前記絶縁層と前記絶縁樹脂層を介して前記ウエハ基板上に配設された複数の配線とを備え、該配線はバンプパッドまたはワイヤボンディングパッドを有し、かつ、先端部に表裏導通用パッドを有し、前記バンプパッドまたは前記ワイヤボンディングパッドは前記ダイシングエリアよりも内側の領域に位置し、前記表裏導通用パッドは前記ダイシングエリア内に位置するとともに略中央に微細開口部を有し、該微細開口部には前記ウエハ基板を貫通する貫通孔が位置し、該貫通孔には導電材料が充填されて表裏導通が取られているような構成とした。 In order to achieve such an object, an electronic component built-in wafer according to the present invention is divided into multiple faces by a dicing area having a predetermined width, and a wafer substrate having a recessed portion for incorporating an electronic component for each imposition, An insulating layer disposed on the entire surface of the wafer substrate including the inside of the recess, an electronic component built in the recess through the insulating layer, and covering the electronic component except for the terminal portion for each imposition comprising an insulating resin layer, and said insulating layer and said plurality of through the insulating resin layer disposed on the wafer substrate wiring so as to connect the terminal portions of the electronic component in each surface with, wiring has a bump pads or wire bond pads, and has a front and back conductive pad on the tip portion, the bump pads or the wire bonding pad is located in the inner area than the dicing area, the front and back Spoken pad has a fine opening substantially in the center as well as positioned in the dicing area in the fine openings located through hole extending through the wafer substrate, the through hole is filled conductive material It was set as the structure where front and back conduction was taken .

本発明の他の態様として、前記絶縁層は二酸化珪素膜であり、前記配線はアルミニウムであるような構成とした。
本発明の他の態様として、前記バンプパッドまたは前記ワイヤボンディングパッドと、前記表裏導通用パッドのみを露出し、かつ、前記配線層を被覆した絶縁被覆層を前記ウエハ基板上に備えるような構成とした。
本発明の他の態様として、前記ウエハ基板は、ＸＹ方向の熱膨張係数が２〜２０ｐｐｍの範囲内であるような構成とした。
本発明の他の態様として、前記電子部品は、ＬＳＩチップ、ＩＣチップ、ＬＣＲ回路部品、センサ部品のいずれかであるような構成とした。
本発明の他の態様として、前記配線は、絶縁樹脂層を介して対向する上下電極からなるキャパシタを有するような構成とした。 As another aspect of the present invention, the insulating layer is a silicon dioxide film, and the wiring is aluminum.
As another aspect of the present invention, the bump pad or the wire bonding pad, and a configuration in which only the front and back conductive pads are exposed and an insulating coating layer covering the wiring layer is provided on the wafer substrate, did.
As another aspect of the present invention, the wafer substrate is configured such that the thermal expansion coefficient in the XY direction is in the range of 2 to 20 ppm.
As another aspect of the present invention, the electronic component is configured as any one of an LSI chip, an IC chip, an LCR circuit component, and a sensor component.
As another aspect of the present invention, the wiring is configured to have a capacitor composed of upper and lower electrodes opposed via an insulating resin layer.

このような本発明の電子部品内蔵ウエハは、ダイシングエリア内に表裏導通用パッドを備えており、この表裏導通用パッドの微細開口部にはウエハ基板が露出しているので、この微細開口部からウエハ基板に貫通孔を形成し、内部に導電材料を充填することにより、容易に表裏導通をとることができ、これにより、ダイシング後の電子部品内蔵モジュールを積層して、多層構造のマルチチップモジュールの製造も可能である。   The electronic component built-in wafer according to the present invention includes front and back conductive pads in the dicing area, and the wafer substrate is exposed in the fine opening of the front and back conductive pad. By forming through-holes in the wafer substrate and filling the inside with a conductive material, it is possible to easily connect the front and the back. By this, modules with built-in electronic components after dicing are stacked, and a multi-chip module with a multilayer structure Is also possible.

以下、本発明の実施の形態について図面を参照して説明する。
図１は、本発明の電子部品内蔵ウエハの一実施形態を示す平面図であり、図１（Ａ）は電子部品内蔵ウエハ全体を示す平面図、図１（Ｂ）は図１（Ａ）の円１０１で囲まれた部位の拡大平面図、図１（Ｃ）は図１（Ｂ）の円１０２で囲まれた部位の拡大平面図である。また、図２は図１（Ｂ）に示される電子部品内蔵ウエハのＡ−Ａ線矢視縦断面図であり、図３は、図２に示される断面図の円１０３で囲まれた部位近傍の平面図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a plan view showing an embodiment of a wafer with built-in electronic components according to the present invention, FIG. 1 (A) is a plan view showing the whole wafer with built-in electronic components, and FIG. 1 (B) is a plan view of FIG. FIG. 1C is an enlarged plan view of a part surrounded by a circle 102 in FIG. 1B. 2 is a vertical cross-sectional view taken along line AA of the electronic component built-in wafer shown in FIG. 1B, and FIG. 3 is the vicinity of a portion surrounded by a circle 103 in the cross-sectional view shown in FIG. FIG.

図１〜図３において、本発明の電子部品内蔵ウエハ１は、単位エリア１１が多面付けで設定されたウエハ基板２１を備え、各単位エリア１１は、所定の幅のダイシングエリア１２により区画されており、各面付け（単位エリア１１）毎に電子部品内蔵用の凹部２２を備えている。また、ウエハ基板２１は、凹部２２内部を含む全面に絶縁層２３を備えている。図１（Ｂ）では、ダイシングエリア１２に斜線を付し、ダイシングラインを鎖線で示し、凹部２２を一点鎖線で示している。ダイシングエリア１１の幅Ｗは、例えば、０．０５〜０．２ｍｍの範囲で設定することができ、このダイシングエリア１２と凹部２２との距離Ｌは、例えば、５０〜５００μｍの範囲で設定することができる。   1 to 3, an electronic component built-in wafer 1 according to the present invention includes a wafer substrate 21 in which unit areas 11 are set in a multi-sided manner, and each unit area 11 is partitioned by a dicing area 12 having a predetermined width. In addition, each imposition (unit area 11) is provided with a recess 22 for incorporating an electronic component. The wafer substrate 21 includes an insulating layer 23 on the entire surface including the inside of the recess 22. In FIG. 1B, the dicing area 12 is hatched, the dicing line is indicated by a chain line, and the recess 22 is indicated by a one-dot chain line. The width W of the dicing area 11 can be set in a range of 0.05 to 0.2 mm, for example, and the distance L between the dicing area 12 and the recess 22 is set in a range of 50 to 500 μm, for example. Can do.

上記の凹部２２には電子部品３１が内蔵されており、また、各面付け（単位エリア１１）毎に、絶縁層２３と電子部品３１上に絶縁樹脂層２４が所定のパターンで形成されている。そして、各面付け（単位エリア１１）毎に、電子部品３１の複数の端子部３２と接続するように複数の配線２５が絶縁層２３および絶縁樹脂層２４上に配設されている。これらの配線２５は、バンプパッド２６を介して先端部に表裏導通用パッド２７を有し、この表裏導通用パッド２７は、ダイシングエリア１２内に位置している。各表裏導通用パッド２７は、略中央に微細開口部２７ａを有し、この微細開口部２７ａには絶縁層２３が存在せず、ウエハ基板２１が露出している。図３では、絶縁樹脂層２４に斜線を付して示し、凹部２２（電子部品３１）の境界を一点鎖線で示している。
尚、図示例では、バンプパッド２６は、ダイシングエリア１２と電子部品３１（凹部２２）との間の部位に位置しているが、バンプパッド２６の全部または一部が、絶縁樹脂層２４を介して電子部品３１上に位置するものでもよい。 An electronic component 31 is built in the recess 22, and an insulating resin layer 24 is formed in a predetermined pattern on the insulating layer 23 and the electronic component 31 for each imposition (unit area 11). . A plurality of wirings 25 are arranged on the insulating layer 23 and the insulating resin layer 24 so as to be connected to the plurality of terminal portions 32 of the electronic component 31 for each imposition (unit area 11). These wirings 25 have front and back conductive pads 27 at the tip portions via bump pads 26, and the front and back conductive pads 27 are located in the dicing area 12. Each of the front and back conductive pads 27 has a fine opening 27a substantially in the center. The insulating layer 23 does not exist in the fine opening 27a, and the wafer substrate 21 is exposed. In FIG. 3, the insulating resin layer 24 is indicated by hatching, and the boundary of the recess 22 (electronic component 31) is indicated by a one-dot chain line.
In the illustrated example, the bump pad 26 is located at a portion between the dicing area 12 and the electronic component 31 (recessed portion 22). It may be located on the electronic component 31.

上記の表裏導通用パッド２７は、例えば、一辺の長さが５〜１５０μｍの範囲であるような方形、直径が５〜１５０μｍの範囲にあるような円形等とすることができ、形状に制限はない。また、表裏導通用パッド２７が有する微細開口部２７ａは、その形状に制限はなく、また、開口幅は５〜１００μｍ程度とすることができる。
また、バンプパッド２６は、例えば、一辺の長さが１０〜２００μｍの範囲であるような方形、直径が１０〜３００μｍの範囲にあるような円形等とすることができ、形状には制限はない。尚、本発明では、バンプパッド２６の代わりに、ワイヤボンディングパッドを備えるものであってもよい。この場合、ワイヤボンディングパッドは、例えば、一辺の長さが１０〜２００μｍの範囲であるような方形、直径が１０〜３００μｍの範囲にあるような円形等とすることができる。 The front and back conductive pads 27 can be, for example, a square having a side length in the range of 5 to 150 μm, a circle having a diameter in the range of 5 to 150 μm, and the shape is not limited. Absent. Further, the shape of the fine opening 27a of the front and back conductive pad 27 is not limited, and the opening width can be about 5 to 100 μm.
The bump pad 26 can be, for example, a square having a side length of 10 to 200 μm, a circle having a diameter of 10 to 300 μm, etc., and the shape is not limited. . In the present invention, a wire bonding pad may be provided instead of the bump pad 26. In this case, the wire bonding pad can be, for example, a square having a side length of 10 to 200 μm, a circle having a diameter of 10 to 300 μm, or the like.

本発明では、電子部品内蔵ウエハは、図４に示されるように、バンプパッド２６を露出する開口部２８ａと、表裏導通用パッド２７を露出する開口部２８ｂを有し、かつ、配線２５を被覆した絶縁被覆層２８を備えるものであってもよい。
また、本発明では、電子部品内蔵ウエハがキャパシタを有するものであってもよい。図５に示される例では、１層目の配線２５と、絶縁樹脂層２９を介して形成された２層目の配線３０を有している。１層目の配線２５は、電子部品３１の端子部３２に接続され、キャパシタの一方の電極を構成する配線２５ａと、上述のように、バンプパッド２６と表裏導通用パッド２７とを備えた配線２５ｂからなっている。また、２層目の配線３０は、キャパシタの他方の電極を構成し、ビア３０ａを介して１層目の配線２５ｂに接続している。これにより、上下電極２５ａ、３０と、絶縁樹脂層２９とからなるキャパシタ４１が形成されている。 In the present invention, as shown in FIG. 4, the electronic component built-in wafer has an opening 28 a that exposes the bump pad 26 and an opening 28 b that exposes the front and back conductive pad 27, and covers the wiring 25. The insulating coating layer 28 may be provided.
In the present invention, the electronic component built-in wafer may have a capacitor. In the example shown in FIG. 5, a first-layer wiring 25 and a second-layer wiring 30 formed through an insulating resin layer 29 are provided. The first-layer wiring 25 is connected to the terminal portion 32 of the electronic component 31 and includes the wiring 25a constituting one electrode of the capacitor, and the bump pad 26 and the front and back conduction pads 27 as described above. 25b. The second-layer wiring 30 constitutes the other electrode of the capacitor and is connected to the first-layer wiring 25b through the via 30a. Thereby, a capacitor 41 composed of the upper and lower electrodes 25a and 30 and the insulating resin layer 29 is formed.

ウエハ基板２１は、ＸＹ方向（基板表面に平行な平面）の熱膨張係数が２〜２０ｐｐｍ、好ましくは２．５〜１７ｐｐｍの範囲内であることが望ましく、例えば、シリコン、セラミック、ガラス、ガラス−エポキシ複合材料等の材質を使用することができる。ウエハ基板２１の厚みは、例えば、５０〜３００μｍの範囲で設定することができ、凹部２２の深さは４０〜４００μｍ、一辺の長さは０．１〜１０ｍｍの範囲で設定することができる。尚、凹部２２の形状は、内蔵する電子部品３１に対応して適宜設定することができ、図示の形状に限定されるものではない。
凹部２２に内蔵された電子部品３１としては、ＬＳＩチップ、ＩＣチップ、ＬＣＲ回路部品、センサ部品のいずれか１種または２種以上とすることができる。 The wafer substrate 21 desirably has a thermal expansion coefficient in the XY direction (a plane parallel to the substrate surface) of 2 to 20 ppm, preferably 2.5 to 17 ppm. For example, silicon, ceramic, glass, glass- A material such as an epoxy composite material can be used. The thickness of the wafer substrate 21 can be set, for example, in the range of 50 to 300 μm, the depth of the recess 22 can be set in the range of 40 to 400 μm, and the length of one side can be set in the range of 0.1 to 10 mm. Note that the shape of the recess 22 can be set as appropriate in accordance with the electronic component 31 incorporated therein, and is not limited to the illustrated shape.
The electronic component 31 incorporated in the recess 22 may be one or more of LSI chip, IC chip, LCR circuit component, and sensor component.

電子部品内蔵ウエハ１を構成する絶縁層２３は、二酸化珪素膜、窒化珪素膜等とすることができ、例えば、ウエハ基板２１の材質がシリコンである場合、ウエハ基板２１を熱酸化することにより絶縁層２３を形成してもよい。
電子部品内蔵ウエハ１を構成する絶縁樹脂層２４、絶縁被覆層２８、絶縁樹脂層２９の材質は、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の有機材料、あるいは、これらの有機材料とガラス繊維等を組み合わせたもの等とすることができる。また、絶縁樹脂層２４、絶縁被覆層２８、絶縁樹脂層２９の厚みは、例えば、３〜２０μｍの範囲で設定することができる。
また、配線２４，３０、ビア３０ａの材質は、銅、銀、金、クロム、アルミニウム等の導電材料とすることができ、ウエハ基板２１がシリコンからなる場合、配線をアルミニウムとすることにより、後述するウエハ基板２１への貫通孔形成を、配線をマスクとしたドライエッチングにより容易に行うことができ好適である。 The insulating layer 23 constituting the electronic component built-in wafer 1 can be a silicon dioxide film, a silicon nitride film, or the like. For example, when the material of the wafer substrate 21 is silicon, the wafer substrate 21 is insulated by thermal oxidation. The layer 23 may be formed.
The materials of the insulating resin layer 24, the insulating coating layer 28, and the insulating resin layer 29 that constitute the electronic component built-in wafer 1 are organic materials such as epoxy resin, benzocyclobutene resin, cardo resin, and polyimide resin, or these organic materials. And a combination of glass fiber and the like. Moreover, the thickness of the insulating resin layer 24, the insulating coating layer 28, and the insulating resin layer 29 can be set in the range of 3 to 20 μm, for example.
The material of the wirings 24 and 30 and the via 30a can be a conductive material such as copper, silver, gold, chromium, and aluminum. When the wafer substrate 21 is made of silicon, the wiring is made of aluminum, which will be described later. It is preferable that the through-hole formation in the wafer substrate 21 to be performed can be easily performed by dry etching using the wiring as a mask.

上述のような本発明の電子部品内蔵ウエハ１は、ダイシングエリア１２内に表裏導通用パッド２７を備え、この表裏導通用パッド２７の微細開口部２７ａにはウエハ基板２１が露出しているので、例えば、図６（Ａ）に示すように、微細開口部２７ａからウエハ基板２１に貫通孔５１を形成し、この貫通孔５１内部に導電材料５２を充填（図６（Ｂ））することにより、容易に表裏導通をとることができる。このように表裏導通をとった電子部品内蔵ウエハをダイシングすることにより、電子部品内蔵モジュール６１を得ることができる。そして、この電子部品内蔵モジュール６１において、はんだボール６２をバンプパッド２６に形成（図６（Ｃ））し、その後、他の電子部品内蔵モジュール６１と積層することにより、多層構造のマルチチップモジュール（図６（Ｄ））を製造することが容易である。尚、図示例では、電子部品内蔵モジュール６１を２段積層しているが、３段以上に積層することも可能である。また、表裏導通をとった電子部品内蔵ウエハの状態で積層を行い、その後、ダイシングすることにより、多層構造のマルチチップモジュールを作製してもよい。 The electronic component built-in wafer 1 of the present invention as described above includes the front and back conductive pads 27 in the dicing area 12, and the wafer substrate 21 is exposed in the fine opening 27 a of the front and back conductive pads 27. For example, as shown in FIG. 6A, by forming a through hole 51 in the wafer substrate 21 from the fine opening 27a and filling the through hole 51 with a conductive material 52 (FIG. 6B), Front-back conduction can be easily achieved. Thus, the electronic component built-in module 61 can be obtained by dicing the electronic component built-in wafer having the front-back conduction. In this electronic component built-in module 61, solder balls 62 are formed on the bump pads 26 (FIG. 6C), and then laminated with other electronic component built-in modules 61, so that a multi-chip module having a multilayer structure ( FIG. 6D is easy to manufacture. In the example shown in the figure, the electronic component built-in modules 61 are stacked in two stages, but can be stacked in three or more stages. Alternatively, a multi-chip module having a multilayer structure may be manufactured by laminating in the state of the electronic component built-in wafer in which front and back conduction is performed and then dicing.

上述の電子部品内蔵ウエハの実施形態は例示であり、例えば、多面付けの数、位置、各面付け（単位エリア１１）に内蔵される電子部品の端子数等は任意に設定することができる。   The above-described embodiment of the electronic component built-in wafer is an exemplification, and for example, the number and position of multiple impositions, the number of terminals of electronic components incorporated in each imposition (unit area 11), and the like can be arbitrarily set.

次に、本発明の電子部品内蔵ウエハの製造例について説明する。
図７は、本発明の電子部品内蔵ウエハの製造例の一例を、図１〜図３に示される電子部品内蔵ウエハ１を例として説明する工程図である。
本発明の電子部品内蔵ウエハの製造方法では、まず、ウエハ基板２１を所定の幅のダイシングエリア１２により多面付けで区画して各単位エリア１１を設定し、ウエハ基板２１の一方の面２１ａに、電子部品内蔵用の凹部２２を各面付け（単位エリア１１）毎に形成する（図７（Ａ））。凹部２２は、例えば、ウエハ基板２１の面２１ａ上にマスクパターンを形成し、この面２１ａに露出しているウエハ基板２１に対して、プラズマを利用したドライエッチング法であるＩＣＰ−ＲＩＥ（Inductively Coupled Plasma − Reactive Ion Etching：誘導結合プラズマ−反応性イオンエッチング）法により凹部２２を形成することができる。また、サンドブラスト法により凹部２２を形成することもできる。この凹部２２の深さ、開口形状、開口寸法は、内蔵する電子部品に応じて適宜設定することができる。 Next, an example of manufacturing the electronic component built-in wafer of the present invention will be described.
FIG. 7 is a process diagram illustrating an example of the production of the electronic component built-in wafer according to the present invention, taking the electronic component built-in wafer 1 shown in FIGS. 1 to 3 as an example.
In the method of manufacturing an electronic component built-in wafer according to the present invention, first, the wafer substrate 21 is divided into multiple faces by a dicing area 12 having a predetermined width to set each unit area 11, and on one surface 21a of the wafer substrate 21, A recess 22 for incorporating an electronic component is formed for each imposition (unit area 11) (FIG. 7A). For example, the concave portion 22 forms a mask pattern on the surface 21 a of the wafer substrate 21, and the ICP-RIE (Inductively Coupled), which is a dry etching method using plasma, is applied to the wafer substrate 21 exposed on the surface 21 a. The concave portion 22 can be formed by a plasma-reactive ion etching (inductively coupled plasma-reactive ion etching) method. Moreover, the recessed part 22 can also be formed by the sandblasting method. The depth, the opening shape, and the opening dimension of the recess 22 can be set as appropriate according to the built-in electronic component.

次に、上記の凹部２２の内部を含むウエハ基板２１に絶縁層２３を形成する（図７（Ｂ））。この絶縁層２３は、ダイシングエリア１２内に位置する所定箇所に微細開口部２３ａを備えたものとする。絶縁層２３は、プラズマＣＶＤ法等の真空成膜法を用いて二酸化珪素膜、窒化珪素等の絶縁膜として形成することができる。また、塗布方法により珪素酸化物の懸濁液、あるいはベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の絶縁性樹脂をコア材面に塗布し熱硬化させて形成することができる。さらに、例えば、ウエハ基板２１の材質がシリコンである場合、熱酸化によりウエハ基板２１の表面に二酸化珪素膜を形成して絶縁層２３とすることができる。また、上記の微細開口部２３ａは、後工程において表裏導通用パッド２７の微細開口部２７ａが形成される位置に設けるものである。この微細開口部２３ａは、絶縁層２３の形成時に、該当箇所のウエハ基板２１をマスキングしておくことにより形成することができる。また、絶縁層２３の形成後に、該当箇所のみを露出するマスクパターンを形成し、リフトオフ法により微細開口部２３ａを形成してもよい。   Next, an insulating layer 23 is formed on the wafer substrate 21 including the inside of the recess 22 (FIG. 7B). The insulating layer 23 is assumed to have a fine opening 23 a at a predetermined position located in the dicing area 12. The insulating layer 23 can be formed as an insulating film such as a silicon dioxide film or silicon nitride by using a vacuum film forming method such as a plasma CVD method. Further, a silicon oxide suspension or an insulating resin such as a benzocyclobutene resin, a cardo resin, or a polyimide resin may be applied to the core material surface by a coating method and thermally cured. Further, for example, when the material of the wafer substrate 21 is silicon, a silicon dioxide film can be formed on the surface of the wafer substrate 21 by thermal oxidation to form the insulating layer 23. The fine opening 23a is provided at a position where the fine opening 27a of the front and back conductive pad 27 is formed in a later step. The fine opening 23a can be formed by masking the wafer substrate 21 at a corresponding position when the insulating layer 23 is formed. Further, after the insulating layer 23 is formed, a mask pattern that exposes only the corresponding portion may be formed, and the fine opening 23a may be formed by a lift-off method.

次に、上記の凹部２２に電子部品３１を配設する（図７（Ｃ））。この電子部品３１の配設は、完成された電子部品を接着剤により固着する方法、凹部２２内に電子部品を嵌合する方法のいずれであってもよい。
次に、電子部品３１が配設されたウエハ基板２１の面２１ａ側に感光性の絶縁樹脂材料を用いて絶縁樹脂層２４となる感光性絶縁樹脂層を形成し、この感光性絶縁樹脂層を所定のマスクを介して露光し、現像することにより、端子接続ビア用の孔部２４ａを備えた絶縁樹脂層２４をダイシングエリア１２の内側領域に形成する。そして、洗浄後、ダイシングエリア１２と端子接続ビア用の孔部２４ａの内部と絶縁樹脂層２４上に真空成膜法により下地導電層を形成し、この下地導電層上にレジスト層を形成し、所望のパターン露光、現像を行うことによりレジストパターンを形成する。その後、このレジストパターンをマスクとし、下地導電層を給電層として、上記の孔部２４ａを含む露出部に電解めっきにより導電材料を析出させて、バンプパッド２６、表裏導通用パッド２７を含む配線２５を形成し、その後、レジストパターンと不要な下地導電層を除去する（図７（Ｄ））。表裏導通用パッド２７は、絶縁層２３の微細開口部２３ａ形成部位に位置し、表裏導通用パッド２７の微細開口部２７ａは、絶縁層２３の微細開口部２３ａと同位置にあり、ウエハ基板２１が露出したものとなる。 Next, the electronic component 31 is disposed in the recess 22 (FIG. 7C). The electronic component 31 may be disposed by either a method of fixing the completed electronic component with an adhesive or a method of fitting the electronic component in the recess 22.
Next, a photosensitive insulating resin layer to be the insulating resin layer 24 is formed on the surface 21a side of the wafer substrate 21 on which the electronic component 31 is disposed by using a photosensitive insulating resin material. By exposing and developing through a predetermined mask, the insulating resin layer 24 having the terminal connection via hole 24a is formed in the inner region of the dicing area 12. Then, after cleaning, a base conductive layer is formed by vacuum film formation on the inside of the dicing area 12 and the terminal connection via hole 24a and on the insulating resin layer 24, and a resist layer is formed on the base conductive layer, A resist pattern is formed by performing desired pattern exposure and development. Thereafter, using this resist pattern as a mask, using the underlying conductive layer as a power supply layer, a conductive material is deposited on the exposed portion including the hole 24a by electrolytic plating, and the wiring 25 including the bump pad 26 and the front / back conductive pad 27 is formed. After that, the resist pattern and an unnecessary underlying conductive layer are removed (FIG. 7D). The front / back conduction pad 27 is located at the site where the fine opening 23a of the insulating layer 23 is formed, and the fine opening 27a of the front / back conduction pad 27 is located at the same position as the fine opening 23a of the insulating layer 23. Will be exposed.

上述の電子部品内蔵ウエハの製造方法は例示であり、これに限定されるものではない。例えば、バンプパッド２６、表裏導通用パッド２７を含む配線２５の形成を以下のように行なってもよい。まず、上記と同様に、端子接続ビア用の孔部２４ａを備えた絶縁樹脂層２４をダイシングエリア１２の内側領域に形成する。次に、ダイシングエリア１２と端子接続ビア用の孔部２４ａの内部と絶縁樹脂層２４上に真空成膜法により導電層を形成し、この導電層上にレジスト層を形成し、所望のパターン露光、現像を行うことによりレジストパターンを形成する。その後、このレジストパターンをマスクとし、導電層をパターニングし、その後、レジストパターンを除去することにより、バンプパッド２６、表裏導通用パッド２７を含む配線２５を形成する。   The above-described method for manufacturing an electronic component built-in wafer is an example, and the present invention is not limited to this. For example, the wiring 25 including the bump pad 26 and the front / back conduction pad 27 may be formed as follows. First, in the same manner as described above, the insulating resin layer 24 having the terminal connection via hole 24 a is formed in the inner region of the dicing area 12. Next, a conductive layer is formed by vacuum film formation on the inside of the dicing area 12 and the hole 24a for terminal connection vias and on the insulating resin layer 24, a resist layer is formed on the conductive layer, and desired pattern exposure is performed. The resist pattern is formed by developing. Thereafter, using the resist pattern as a mask, the conductive layer is patterned, and then the resist pattern is removed, thereby forming the wiring 25 including the bump pad 26 and the front and back conductive pads 27.

次に、具体的実施例を挙げて本発明を更に詳細に説明する。
ウエハ基板として、厚み６２５μｍのシリコンウエハを準備し、このウエハ基板の一方の面に感光性ドライフィルムレジスト（東京応化工業（株）製ＢＦ４０５）をラミネートし、凹部形成用のフォトマスクを介して露光、現像することによりマスクパターンを形成した。上記のシリコンウエハのＸＹ方向（シリコンウエハの表面に平行な平面）の熱膨張係数は、４ｐｐｍであった。また、マスクパターンは、一辺５ｍｍである正方形の開口が６ｍｍピッチで形成された多面付けであった。
尚、この多面付けでは、幅が１ｍｍである格子形状（格子ピッチは６ｍｍ、格子形状は正方形）のダイシングエリアを設定した。 Next, the present invention will be described in more detail with specific examples.
A silicon wafer having a thickness of 625 μm was prepared as a wafer substrate, a photosensitive dry film resist (BF405 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was laminated on one surface of the wafer substrate, and exposed through a photomask for forming a recess. The mask pattern was formed by developing. The thermal expansion coefficient of the above silicon wafer in the XY direction (a plane parallel to the surface of the silicon wafer) was 4 ppm. The mask pattern was multi-faceted with square openings having a side of 5 mm formed at a pitch of 6 mm.
In this multi-faceted layout, a dicing area having a grid shape with a width of 1 mm (lattice pitch is 6 mm, grid shape is square) was set.

次に、このマスクパターンをマスクとしてサンドブラストによりウエハ基板に凹部を形成した。この凹部は、開口が一辺５ｍｍの正方形であり、深さが２００μｍであった。
次に、凹部が形成されたウエハ基板に熱酸化処理（１０５０℃、１２０分間）を施し、凹部の内壁面を含むウエハ基板表面に二酸化珪素膜からなる絶縁層を形成した。その後、凹部を有するウエハ基板面に感光性ドライフィルムレジスト（東京応化工業（株）製ＢＦ４０５）をラミネートし、微細開口部形成用のフォトマスクを介して露光、現像することによりマスクパターンを形成した。マスクパターンは、各面付け毎に、ダイシングエリアの各辺に直径１００μｍの円形開口を２２０μｍピッチで２５個（４辺合計１００個）備えるものであった。次に、このマスクパターンをマスクとしてサンドブラスト法により絶縁層に複数の微細開口部を形成し、マスクパターンをアセトンを用いて除去した。この微細開口部は、ダイシングエリア内に２００μｍ入り込んだ部位に位置するものであった。 Next, a concave portion was formed on the wafer substrate by sand blasting using this mask pattern as a mask. The recess was a square having an opening of 5 mm on a side and a depth of 200 μm.
Next, a thermal oxidation treatment (1050 ° C., 120 minutes) was performed on the wafer substrate on which the concave portion was formed, and an insulating layer made of a silicon dioxide film was formed on the wafer substrate surface including the inner wall surface of the concave portion. Thereafter, a photosensitive dry film resist (BF405 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was laminated on the wafer substrate surface having the recesses, and a mask pattern was formed by exposing and developing through a photomask for forming fine openings. . The mask pattern was provided with 25 circular openings having a diameter of 100 μm on each side of the dicing area for each imposition, with a pitch of 220 μm (total of 100 on four sides). Next, using this mask pattern as a mask, a plurality of fine openings were formed in the insulating layer by sandblasting, and the mask pattern was removed using acetone. The fine opening was located at a site that entered 200 μm into the dicing area.

次いで、上記の凹部にＬＳＩチップ（４．８ｍｍ×４．８ｍｍ、厚み２５０μｍ、端子数１００個）を接着剤（エイブルスティック（株）製エイブルボンド３２３０）を用いて配設した。
次に、ＬＳＩチップが内蔵されたウエハ基板面に、ＬＳＩチップを被覆するように、ベンゾシクロブテン樹脂組成物（ダウ・ケミカル社製サイクロテン４０２４）をスピンコーターにより塗布、乾燥して、ＬＳＩチップ上の厚みが１０μｍとなるように感光性絶縁樹脂層を形成した。
次に、ビア形成用のマスクを介して上記の感光性絶縁樹脂層を露光し、現像を行った。これにより、各面付けのダイシングエリア内側に、絶縁樹脂層を形成するとともに、ＬＳＩチップの端子部が露出するように端子接続ビア用の孔部（内径３０μｍ）を絶縁樹脂層の所定位置に形成した。尚、ダイシングエリアには絶縁樹脂層は形成せず、上述の二酸化珪素膜からなる絶縁層のみは存在するものとした。 Next, an LSI chip (4.8 mm × 4.8 mm, thickness 250 μm, number of terminals 100) was disposed in the recess using an adhesive (Able Bond 3230 manufactured by Able Stick Co., Ltd.).
Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) is applied by a spin coater so as to cover the LSI chip on the surface of the wafer substrate in which the LSI chip is built, and dried. A photosensitive insulating resin layer was formed so that the upper thickness was 10 μm.
Next, the photosensitive insulating resin layer was exposed through a mask for forming vias and developed. As a result, an insulating resin layer is formed inside each imposition dicing area, and a terminal connection via hole (inner diameter of 30 μm) is formed at a predetermined position of the insulating resin layer so that the terminal portion of the LSI chip is exposed. did. Note that the insulating resin layer was not formed in the dicing area, and only the insulating layer made of the silicon dioxide film was present.

次いで、洗浄後、端子接続ビア用の孔部の内部、絶縁樹脂層上、および二酸化珪素膜からなる絶縁層上に、スパッタリング法によりアルミニウムからなる導電層を形成し、この導電層上に液状レジスト（東京応化工業（株）製ＬＡ９００）を塗布した。次いで、フォトマスクを介し露光、現像して、バンプパッドと表裏導通用パッドを含む配線と、ビアとを形成するためのレジストパターンを形成した。このレジストパターンをマスクとしてアルミニウム導電層をエッチングによりパターニングし、その後、レジストパターンを除去した。これにより、ＬＳＩチップの端子に接続する端子ビアを絶縁樹脂層に形成し、各端子ビアからバンプパッド（直径１００μｍ）を経由して表裏導通用パッド（一辺が５０μｍの正方形）に至る複数の配線を形成した。この配線は、端子ビアからバンプパッドまでが絶縁樹脂層上に位置し、表裏導通用パッドは絶縁樹脂層よりも外側（ダイシングエリア内）の絶縁層（二酸化珪素膜）上に位置し、かつ、表裏導通用パッドは直径３０μｍの微細開口部を有し、この微細開口部は上記の絶縁層に形成した微細開口部と一致するものであった。これにより、表裏導通用パッドの微細開口部にウエハ基板が露出した電子部品内蔵ウエハを得た。   Next, after cleaning, a conductive layer made of aluminum is formed by sputtering on the inside of the hole for the terminal connection via, on the insulating resin layer, and on the insulating layer made of the silicon dioxide film, and a liquid resist is formed on the conductive layer. (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied. Next, exposure and development were performed through a photomask to form a resist pattern for forming wiring including bump pads and front and back conductive pads and vias. The aluminum conductive layer was patterned by etching using this resist pattern as a mask, and then the resist pattern was removed. As a result, terminal vias connected to the terminals of the LSI chip are formed in the insulating resin layer, and a plurality of wirings extending from each terminal via to the front and back conductive pads (square with a side of 50 μm) via the bump pads (diameter 100 μm). Formed. This wiring is located on the insulating resin layer from the terminal via to the bump pad, the front and back conductive pads are located on the insulating layer (silicon dioxide film) outside the insulating resin layer (in the dicing area), and The front and back conductive pads had a fine opening with a diameter of 30 μm, and this fine opening coincided with the fine opening formed in the insulating layer. As a result, an electronic component built-in wafer was obtained in which the wafer substrate was exposed in the fine opening of the front and back conductive pads.

次に、上記の配線を被覆するように、ベンゾシクロブテン樹脂組成物（ダウ・ケミカル社製サイクロテン４０２４）をスピンコーターにより塗布、乾燥して、厚み１０μｍの感光性絶縁樹脂層を形成した。次に、マスクを介して上記の感光性絶縁樹脂層を露光し、現像を行った。これにより、バンプパッドと表裏導通用パッドが露出する開口部を備えた絶縁被覆層を形成した。
上述のように作製した電子部品内蔵ウエハにおいて、絶縁被覆層、アルミニウムからなる配線、および絶縁層（二酸化珪素膜）をマスクとして、表裏導通用パッドの微細開口部に露出しているウエハ基板を、ＩＣＰ−ＲＩＥ装置によりドライエッチングして、貫通孔を形成した。このドライエッチングは、ＣＦ6をエッチングガスとして使用した。 Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) was applied with a spin coater and dried so as to cover the above wiring, thereby forming a photosensitive insulating resin layer having a thickness of 10 μm. Next, the photosensitive insulating resin layer was exposed through a mask and developed. As a result, an insulating coating layer having an opening through which the bump pad and the front and back conductive pads were exposed was formed.
In the electronic component built-in wafer produced as described above, using the insulating coating layer, the wiring made of aluminum, and the insulating layer (silicon dioxide film) as a mask, the wafer substrate exposed in the fine opening of the front and back conductive pads, A through hole was formed by dry etching using an ICP-RIE apparatus. In this dry etching, CF 6 was used as an etching gas.

次に、上記の貫通孔内部に、銅粒子を含有する導電性ペーストをスクリーン印刷法により充填し、硬化処理（１７０℃、２０分間）を施した。その後、表面に硬化突出した導電性ペーストを研磨した。次に、電子部品内蔵ウエハの裏面（ＬＳＩチップが内蔵されていない面）側にスパッタリング法によりＴｉ／Ｃｕからなる下地導電層を形成し、この下地導電層上に液状レジスト（東京応化工業（株）製ＬＡ９００）を塗布した。次いで、フォトマスクを介し露光、現像して、バンプパッドを形成するためのレジストパターンを形成した。このレジストパターンをマスクとして下地導電層上に電解銅めっきにより導電層を形成し、その後、レジストパターンを除去し、露出している下地導電層をソフトエッチングにより除去した。これにより、所望のバンプパッドを電子部品内蔵ウエハの裏面であって、表面にすでに形成されているバンプパッドに対応する位置に形成し、表裏の導通をとった電子部品内蔵ウエハを形成した。   Next, the through-hole was filled with a conductive paste containing copper particles by a screen printing method and subjected to a curing process (170 ° C., 20 minutes). Thereafter, the conductive paste protruding on the surface was polished. Next, a base conductive layer made of Ti / Cu is formed on the back surface (the surface on which the LSI chip is not embedded) of the electronic component built-in wafer by sputtering, and a liquid resist (Tokyo Ohka Kogyo Co., Ltd.) is formed on the base conductive layer. ) LA900). Next, exposure and development were performed through a photomask to form a resist pattern for forming a bump pad. Using this resist pattern as a mask, a conductive layer was formed on the underlying conductive layer by electrolytic copper plating. Thereafter, the resist pattern was removed, and the exposed underlying conductive layer was removed by soft etching. As a result, a desired bump pad was formed on the back surface of the electronic component built-in wafer at a position corresponding to the bump pad already formed on the front surface, thereby forming an electronic component built-in wafer in which the front and back surfaces were electrically connected.

次に、表裏の導通がとられていない電子部品内蔵ウエハのバンプパッドにはんだボールを形成し、この電子部品内蔵ウエハと、上記の表裏の導通をとった電子部品内蔵ウエハとを、はんだボールを介して固着積層した。
次いで、積層状態の多面付けの電子部品内蔵ウエハを、ダイシングエリアの中央部にてダイシングして、一辺が６ｍｍの正方形の電子部品内蔵モジュールを得た。 Next, a solder ball is formed on the bump pad of the electronic component built-in wafer that is not electrically conductive on the front and back sides, and the electronic component built-in wafer and the electronic component built-in wafer that is electrically conductive on the front and back are attached to the solder ball. The laminate was fixed through.
Next, the laminated multi-sided electronic component built-in wafer was diced at the center of the dicing area to obtain a square electronic component built-in module having a side of 6 mm.

小型で高信頼性が要求される半導体装置や各種電子機器への用途にも適用できる。   The present invention can also be applied to small semiconductor devices and various electronic devices that require high reliability.

本発明の電子部品内蔵ウエハの一実施形態を示す平面図であり、図１（Ａ）は電子部品内蔵ウエハ全体を示す平面図、図１（Ｂ）は図１（Ａ）の部分拡大平面図、図１（Ｃ）は図１（Ｂ）の部分拡大平面図である。1 is a plan view showing an embodiment of an electronic component built-in wafer according to the present invention, FIG. 1A is a plan view showing the entire electronic component built-in wafer, and FIG. 1B is a partially enlarged plan view of FIG. FIG. 1C is a partially enlarged plan view of FIG. 図１（Ｂ）に示される電子部品内蔵ウエハのＡ−Ａ線矢視縦断面図である。It is an AA arrow longitudinal cross-sectional view of the electronic component built-in wafer shown by FIG. 1 (B). 図２に示される断面図の円で囲まれた部位近傍の拡大平面図である。FIG. 3 is an enlarged plan view of the vicinity of a portion surrounded by a circle in the cross-sectional view shown in FIG. 本発明の電子部品内蔵ウエハの他の実施形態を示す図２相当の縦断面図である。FIG. 5 is a longitudinal sectional view corresponding to FIG. 2 showing another embodiment of the electronic component built-in wafer of the present invention. 本発明の電子部品内蔵ウエハの他の実施形態を示す図２相当の縦断面図である。FIG. 5 is a longitudinal sectional view corresponding to FIG. 2 showing another embodiment of the electronic component built-in wafer of the present invention. 本発明の電子部品内蔵ウエハを用いた多層構造のマルチチップモジュールの製造例を説明するための図である。It is a figure for demonstrating the manufacture example of the multichip module of a multilayer structure using the electronic component built-in wafer of this invention. 本発明の電子部品内蔵ウエハの製造例の一例を説明する工程図である。It is process drawing explaining an example of the manufacture example of the electronic component built-in wafer of this invention.

符号の説明Explanation of symbols

１…電子部品内蔵ウエハ
１１…単位エリア
１２…ダイシングエリア
２１…ウエハ基板
２２…凹部
２３…絶縁層
２４，２９…絶縁樹脂層
２５，３０…配線
２６…バンプパッド２６
２７…表裏導通用パッド
２７ａ…微細開口部
２８…絶縁被膜層
３１…電子部品
４１…キャパシタ DESCRIPTION OF SYMBOLS 1 ... Electronic component built-in wafer 11 ... Unit area 12 ... Dicing area 21 ... Wafer substrate 22 ... Recessed part 23 ... Insulating layer 24, 29 ... Insulating resin layer 25, 30 ... Wiring 26 ... Bump pad 26
27 ... Front and back conductive pads 27a ... Fine opening 28 ... Insulating coating layer 31 ... Electronic component 41 ... Capacitor

Claims (6)

所定の幅のダイシングエリアにより多面付けに区画され、各面付け毎に電子部品内蔵用の凹部を備えるウエハ基板と、該凹部の内部を含むウエハ基板の全面に配設された絶縁層と、前記凹部に前記絶縁層を介して内蔵された電子部品と、各面付け毎に該電子部品を端子部を除いて被覆する絶縁樹脂層と、各面付け毎に前記電子部品の端子部と接続するように前記絶縁層と前記絶縁樹脂層を介して前記ウエハ基板上に配設された複数の配線とを備え、該配線はバンプパッドまたはワイヤボンディングパッドを有し、かつ、先端部に表裏導通用パッドを有し、前記バンプパッドまたは前記ワイヤボンディングパッドは前記ダイシングエリアよりも内側の領域に位置し、前記表裏導通用パッドは前記ダイシングエリア内に位置するとともに略中央に微細開口部を有し、該微細開口部には前記ウエハ基板を貫通する貫通孔が位置し、該貫通孔には導電材料が充填されて表裏導通が取られていることを特徴とする電子部品内蔵ウエハ。 A wafer substrate that is divided into multiple imprints by a dicing area of a predetermined width, and includes a recess for incorporating an electronic component for each imposition, an insulating layer disposed on the entire surface of the wafer substrate including the inside of the recess, An electronic component embedded in the recess through the insulating layer, an insulating resin layer that covers the electronic component except for the terminal portion for each imposition, and a terminal portion of the electronic component for each imposition wherein the insulating layer through the insulating resin layer and a plurality of wirings disposed on the wafer substrate, wiring has a bump pad or wire bond pads, as, and, for the front and back conductive to tip a pad, the bump pads or the wire bonding pad is located in the inner area than the dicing area, the front and rear conductive pads in a substantially central with located in the dicing area Has a narrow opening, the electronic component to the fine opening and the through hole is positioned through said wafer substrate, characterized in that the through hole sides conducting conductive material is filled is taken Built-in wafer. 前記絶縁層は二酸化珪素膜であり、前記配線はアルミニウムであることを特徴とする請求項１に記載の電子部品内蔵ウエハ。   2. The electronic component built-in wafer according to claim 1, wherein the insulating layer is a silicon dioxide film, and the wiring is aluminum. 前記バンプパッドまたは前記ワイヤボンディングパッドと、前記表裏導通用パッドのみを露出し、かつ、前記配線層を被覆した絶縁被覆層を前記ウエハ基板上に備えることを特徴とする請求項１または請求項２に記載の電子部品内蔵ウエハ。   3. An insulating coating layer that exposes only the bump pads or the wire bonding pads and the front and back conductive pads and covers the wiring layer is provided on the wafer substrate. The electronic component built-in wafer according to 1. 前記ウエハ基板は、ＸＹ方向の熱膨張係数が２〜２０ｐｐｍの範囲内であることを特徴とする請求項１乃至請求項３のいずれかに記載の電子部品内蔵ウエハ。   4. The electronic component built-in wafer according to claim 1, wherein the wafer substrate has a thermal expansion coefficient in the XY direction in a range of 2 to 20 ppm. 前記電子部品は、ＬＳＩチップ、ＩＣチップ、ＬＣＲ回路部品、センサ部品のいずれかであることを特徴とする請求項１乃至請求項４のいずれかに記載の電子部品内蔵ウエハ。   5. The electronic component built-in wafer according to claim 1, wherein the electronic component is one of an LSI chip, an IC chip, an LCR circuit component, and a sensor component. 前記配線は、絶縁樹脂層を介して対向する上下電極からなるキャパシタを有することを特徴とする請求項１乃至請求項５のいずれかに記載の電子部品内蔵ウエハ。   6. The electronic component built-in wafer according to claim 1, wherein the wiring includes a capacitor composed of upper and lower electrodes opposed via an insulating resin layer.
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