JP2005064446A - Method of manufacturing laminating module - Google Patents
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Abstract
Description
本発明は、多層配線基板製造に使用する積層用モジュール、特にLSIチップ等の電子部品を内蔵した積層用モジュールの製造方法に関する。 The present invention relates to a stacking module used for manufacturing a multilayer wiring board, and more particularly to a manufacturing method of a stacking module incorporating electronic components such as LSI chips.
従来の多層配線基板は、例えば、サブトラクティブ法等で作製した低密度配線を有する両面基板をコア基板とし、このコア基板の両面にビルドアップ法により高密度配線を形成して作製されたものである。また、最近では、LSIチップ等を多層配線基板上に直接実装するベアチップ実装法が提案されている。ベアチップ実装法では、予め多層配線基板上に形成された配線の接続パッド部に、ボンディング・ワイヤ、ハンダや金属球等からなるバンプ、異方性導電膜、導電性接着剤、光収縮性樹脂等の接続手段を用いて半導体チップが実装される。そして、作製する半導体装置にキャパシターやインダクター等のLCR回路部品が必要な場合は、半導体チップと同様に、多層配線基板に外付けで実装されている A conventional multilayer wiring board is produced by, for example, using a double-sided board having low-density wiring produced by a subtractive method or the like as a core board, and forming high-density wiring on both sides of the core board by a build-up method. is there. Recently, a bare chip mounting method in which an LSI chip or the like is directly mounted on a multilayer wiring board has been proposed. In the bare chip mounting method, bonding pads, wiring bumps made of solder, metal balls, etc., anisotropic conductive films, conductive adhesives, light-shrinkable resins, etc. are formed in advance on wiring connection pads formed on a multilayer wiring board. A semiconductor chip is mounted using the connecting means. If the semiconductor device to be manufactured requires an LCR circuit component such as a capacitor or an inductor, it is externally mounted on the multilayer wiring board in the same manner as the semiconductor chip.
しかし、多層配線基板上に形成された配線の接続パッド部は、半導体チップ等の電子部品の実装部位とは別の部位に設けられるため、多層配線基板の面方向の広がりが必要であった。したがって、多層配線基板の小型化には限界があり、実装される電子部品の数が増えることにより、小型化は更に困難となる傾向にあった。
これに対応するために、半導体チップを実装した薄い基板と、上下導通ビアを備えた穴明きの枠基板を、それぞれ複数個作製しておき、多層配線基板の作製時に、この実装基板と枠基板とを1つのモジュールとして一括で積層する方法が開示されている(特許文献1)。この方法によれば、複数のモジュールを積層しても、多層配線基板の面方向の広がりは必要がないため、多層配線基板の小型化が可能であった。
In order to cope with this, a plurality of thin substrates on which semiconductor chips are mounted and a perforated frame substrate with vertical conduction vias are respectively prepared. A method of laminating a substrate as a single module is disclosed (Patent Document 1). According to this method, even if a plurality of modules are stacked, it is not necessary to expand the multilayer wiring board in the surface direction, so that the multilayer wiring board can be reduced in size.
しかしながら、上述のような実装基板と枠基板とからなるモジュールでは、個々の半導体チップを基板の所定の部位に実装するための位置合わせを正確に行う必要があり、工程管理が煩雑であるとともに、実装位置のズレが生じた場合、多層配線基板の信頼性が低下するという問題があった。
本発明は、上記のような実情に鑑みてなされたものであり、電子部品を内蔵した信頼性の高い積層用モジュールの製造方法を提供することを目的とする。
However, in the module composed of the mounting substrate and the frame substrate as described above, it is necessary to accurately perform alignment for mounting each semiconductor chip on a predetermined portion of the substrate, and the process management is complicated. When the mounting position is shifted, there is a problem that the reliability of the multilayer wiring board is lowered.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a highly reliable stacking module incorporating an electronic component.
このような目的を達成するために、本発明は、コア基板と、該コア基板に内蔵された電子部品と、導電材料により前記コア基板の表裏の導通をとるためのスルーホールと、前記コア基板上に電気絶縁層を介して配設された配線層と、を備えた積層用モジュールの製造方法において、電子部品を内蔵するための凹部を一方の面に有し、導電材料によりスルーホールを介した表裏の導通がとられたコア基板を作製する工程と、該コア基板の前記凹部内に電子部品を配設する工程と、前記電子部品が配設された前記コア基板上に電気絶縁層を介し該電気絶縁層に形成されたビア部で必要な導通がとられた配線層を形成する工程と、を有するような構成とした。 In order to achieve such an object, the present invention provides a core substrate, an electronic component built in the core substrate, a through hole for conducting conduction between the front and back surfaces of the core substrate with a conductive material, and the core substrate. And a wiring layer disposed on an electrical insulating layer on the one side having a recess for containing an electronic component, and through the through hole with a conductive material. A step of producing a core substrate having electrical conduction between the front and back sides, a step of disposing an electronic component in the recess of the core substrate, and an electrical insulating layer on the core substrate on which the electronic component is disposed. And a step of forming a wiring layer in which necessary conduction is obtained in the via portion formed in the electrical insulating layer.
本発明の他の態様として、配設された電子部品がコア基板表面から突出しないように、電子部品の厚み、大きさに合わせて前記凹部を形成するような構成とした。
本発明の他の態様として、コア基板用のコア材の一方の面にICP−RIEまたはサンドブラストにより孔部を穿設し、前記コア材の他方の面を研磨して前記孔部を露出させて前記スルーホールを形成するような構成、あるいは、コア基板用のコア材を研磨して所定の厚みとし、その後、一方の面、あるいは、両面から、ICP−RIEまたはサンドブラストによりスルーホールを形成するような構成とした。
As another aspect of the present invention, the concave portion is formed in accordance with the thickness and size of the electronic component so that the arranged electronic component does not protrude from the core substrate surface.
As another aspect of the present invention, a hole is formed in one surface of the core material for the core substrate by ICP-RIE or sandblast, and the other surface of the core material is polished to expose the hole. The structure for forming the through hole, or the core material for the core substrate is polished to a predetermined thickness, and then the through hole is formed by ICP-RIE or sandblasting from one side or both sides. The configuration was
本発明の他の態様として、前記コア基板の厚みを50〜300μmの範囲内で設定し、前記スルーホールの開口径を5〜300μmの範囲内で設定するような構成とした。
本発明の他の態様として、前記電子部品を前記凹部内に配設した後、コア基板の反対面を研磨して、コア基板の厚みを50〜300μmの範囲内の所定の厚みにするような構成とした。
As another aspect of the present invention, the thickness of the core substrate is set within a range of 50 to 300 μm, and the opening diameter of the through hole is set within a range of 5 to 300 μm.
As another aspect of the present invention, after disposing the electronic component in the recess, the opposite surface of the core substrate is polished so that the thickness of the core substrate becomes a predetermined thickness in the range of 50 to 300 μm. The configuration.
本発明によれば、導電材料によりスルーホールを介した表裏の導通がとられたコア基板の凹部内に電子部品を配設するだけで複数の電子部品の位置合わせが完了し、個々の電子部品の精密な位置合わせが不要であり、このように複数の電子部品が所望の位置に配設されているコア基板上に電気絶縁層を介しビア部で必要な導通がとられた配線層を形成するので、配線の端子部上にバンプを介して個々の電子部品を搭載する従来の方法に比べて、電子部品の位置合わせが極めて容易であるとともに、配線層と各電子部品との接続信頼性が格段に向上する。 According to the present invention, alignment of a plurality of electronic components is completed simply by disposing the electronic components in the recesses of the core substrate in which conduction between the front and back sides is made through the through holes with the conductive material. In this way, a wiring layer that has the necessary electrical conduction at the via portion is formed on the core substrate on which a plurality of electronic components are arranged at a desired position via an electrical insulating layer. Therefore, compared with the conventional method in which individual electronic components are mounted on the terminal portions of the wiring via bumps, the positioning of the electronic components is extremely easy, and the connection reliability between the wiring layer and each electronic component is very high. Is significantly improved.
以下、本発明の実施の形態について図面を参照して説明する。
図1は、本発明の一実施形態を説明するための工程図である。本発明では、まず、コア基板12を準備する(図1(A))。コア基板12は、コア材12′に凹部13とスルーホール14が形成されたものであり、各スルーホール14には導電材料15が充填され、この導電材料15によりスルーホール14を介した表面12aと裏面12bの導通がなされている。このようなコア基板12の厚みは、50〜300μmの範囲内で設定することが好ましい。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a process diagram for explaining an embodiment of the present invention. In the present invention, first, the
コア基板12に用いるコア材12′は、XY方向(コア基板12の表面12a(あるいは裏面12b)に平行な平面)の熱膨張係数が2〜20ppm、好ましくは2.5〜17ppmの範囲内であることが望ましい。このようなコア材12′は、例えば、シリコン、セラミック、ガラス、ガラス−エポキシ複合材料等を用いることができる。尚、本発明では、熱膨張係数はTMA(サーマルメカニカルアナリシス)により測定するものである。
凹部13は、配設する電子部品の厚み、大きさに合わせて形成することができる。例えば、配設された電子部品の表面とコア基板12の表面12aが同一面をなすような深さで凹部13を形成する。凹部13の形成方法には特に制限はないが、例えば、コア材12′の一方の面に、形成する凹部13に対応する開口部を有するマスクパターンを形成し、このマスクパターンをマスクとして、プラズマを利用したドライエッチング法であるICP−RIE(Inductive Coupled Plasma - Reactive Ion Etching)またはサンドブラストによりコア材12′を所定の深さまで掘り下げることにより、凹部13を形成することができる。
The core material 12 'used for the
The
スルーホール14は内径が略同一であるストレート形状、一端の開口径が他端の開口径よりも大きいテーパー形状、中央部の内径が両端の開口径と異なる形状等、いずれであってもよい。図示例では、コア基板12の表面12a側のスルーホール14の開口径が、反対側(コア基板12の裏面12b側)の開口径よりも大きいテーパー形状となっている。このようなスルーホール14の開口径は、5〜300μmの範囲内で設定することが好ましい。
The through
スルーホール14に充填された導電材料15としては、例えば、銅粒子、銀粒子等の導電性粒子を含有した公知の導電性ペーストを用いることができる。この場合、スルーホール14の内壁面、コア材12′の表面に、必要に応じて二酸化珪素、窒化珪素等の電気絶縁膜を形成してもよい。また、例えば、スルーホール14の内壁に絶縁層と導電薄膜を積層して形成することにより表面12aと裏面12bの導通をとってもよい。この場合、絶縁層は二酸化珪素、窒化珪素等の電気絶縁膜とすることができ、導電薄膜は銅、クロム、チタン、窒化チタン、ニッケル等の下地導電薄膜と、下地導電薄膜上に積層された銅、銀、金、ニッケル等の導電材料からなる薄膜とすることができる。尚、このような構成で表面12aと裏面12bの導通をとった場合、スルーホール14内には、導電性ペースト、絶縁性ペースト等の任意の充填材料を充填することができる。
As the
次に、コア基板12の凹部13に電子部品16を配設する(図1(B))。電子部品16は、ダイボンディングペースト等の接着剤を用いて凹部13内に固着してもよい。電子部品16としては、LSIチップ、ICチップ、LCR電子部品、センサ部品のいずれか1種または2種以上とすることができ、また、複数個の電子部品16を内蔵してもよく、特に制限はない。
次いで、電子部品16を内蔵したコア基板12の表面12a上に、ビア部18を有する電気絶縁層17を介して配線層19を形成して、積層用モジュール11を作製する(図1(C))。
Next, the
Next, a
ビア部18を有する電気絶縁層17と配線層19の形成は、例えば、以下のように行うことができる。まず、電子部品16を内蔵したコア基板12の表面12aを覆うように感光性の電気絶縁層17を形成する。この電気絶縁層17を所定のマスクを介して露光し、現像することにより、コア基板12のスルーホール14に充填された導電材料15と、電子部品16の端子部16aが露出するように小径の穴部を電気絶縁層17の所定位置に形成する。そして、洗浄後、穴部内および電気絶縁層17上に真空成膜法により導電層を形成し、この導電層上にレジスト層を形成し、所望のパターン露光、現像を行うことによりレジストパターンを形成する。その後、このレジストパターンをマスクとして、上記の穴部を含む露出部に電解めっきにより導電材料を析出させてビア部18と配線層19を形成し、レジストパターンと導電層を除去する。
また、ビア部18を有する電気絶縁層17と配線層19の形成は、以下のように行うこともできる。すなわち、電子部品16を内蔵したコア基板12の表面12aを覆うように電気絶縁層17を形成する。次に、炭酸ガスレーザー、UV−YAGレーザー等を用いて小径の穴部を電気絶縁層17の所定位置に形成する。この穴部は、コア基板12のスルーホール14に充填された導電材料15と、電子部品16の端子部16aが露出するように形成する。そして、洗浄後、穴部内および電気絶縁層17に無電解めっきにより導電層を形成し、この導電層上にドライフィルムレジストをラミネートして所望のパターン露光、現像を行うことによりレジストパターンを形成する。その後、このレジストパターンをマスクとして、上記の穴部を含む露出部に電解めっきにより導電材料を析出させてビア部18と配線層19を形成し、レジストパターンと導電層を除去する。
ビア部18と配線層19を形成する導電材料としては、銅、銀、金、アルミニウム等を使用することができる。
For example, the
The formation of the electrical insulating
As the conductive material for forming the via
ここで、コア基板12におけるスルーホール14の形成方法について説明する。
スルーホール14の形成方法としては、例えば、以下の方法が挙げられる。ます、コア基板用のコア材12′の一方の面にマスクパターンを形成し、このマスクパターンを形成した面から、プラズマを利用したドライエッチング法であるICP−RIE(Inductive Coupled Plasma - Reactive Ion Etching)またはサンドブラストによりコア材12′に微細孔を穿設する。次に、コア材12′からマスクパターンを除去し、コア材12′の他方の面を研磨して、上記の微細孔を露出させることによりスルーホール14を形成することができる。
Here, a method of forming the through
Examples of a method for forming the through
また、スルーホールの他の形成方法として、以下の方法が挙げられる。まず、コア基板用のコア材12′の両面を研磨して所定の厚みとし、その後、コア材12′の一方の面にマスクパターンを形成する。次に、このマスクパターンをマスクとして、ICP−RIEまたはサンドブラストによりコア材12′に微細な貫通孔を形成してスルーホール14を形成する。尚、コア材12′の両面を研磨して所定の厚みとした後、コア材12′の両面にマスクパターンを形成し、コア材12′の両面から微細孔を穿設してスルーホール14を形成してもよい。
Moreover, the following method is mentioned as another formation method of a through hole. First, both surfaces of the core material 12 'for the core substrate are polished to a predetermined thickness, and then a mask pattern is formed on one surface of the core material 12'. Next, using this mask pattern as a mask, a fine through hole is formed in the
上述の本発明の積層用モジュールの製造方法は例示であり、これに限定されるものではなく、例えば、電子部品16を凹部13内に配設した後、コア基板12の反対面を研磨することにより、コア基板の厚みの最終的な調整を行ってもよい。また、内蔵する電子部品の数には制限はなく、内蔵される電子部品は同一種、あるいは、異種のものであってもよい。
The above-described method for manufacturing the stacking module of the present invention is an example, and is not limited thereto. For example, after the
次に、具体的実施例を挙げて本発明を更に詳細に説明する。
[実施例1]
コア材として、厚み625μmのシリコンウエハを準備し、このコア材の一方の面に感光性ドライフィルムレジスト(旭化成(株)製APR)をラミネートし、スルーホール形成用のフォトマスクを介して露光、現像することによりマスクパターンを形成した。上記のシリコンウエハのXY方向(シリコンウエハの表面に平行な平面)の熱膨張係数は、2.5ppmであった。また、マスクパターンは、直径が100μmである円形開口が300μmピッチで20000個形成されたものであった。次に、このマスクパターンをマスクとしてICP−RIEによりドライエッチングを行い、コア材に20000個の微細孔を穿設し、その後、アセトンを用いてマスクパターンをコア材から除去した。形成した微細孔は、開口径が150μm、深さが300μmの円筒形状の内壁面を有するものであった。
Next, the present invention will be described in more detail with specific examples.
[Example 1]
A silicon wafer having a thickness of 625 μm is prepared as a core material, a photosensitive dry film resist (APR manufactured by Asahi Kasei Co., Ltd.) is laminated on one surface of the core material, and exposure is performed through a photomask for forming a through hole. A mask pattern was formed by development. The thermal expansion coefficient of the above silicon wafer in the XY direction (a plane parallel to the surface of the silicon wafer) was 2.5 ppm. Further, the mask pattern was formed by 20000 circular openings having a diameter of 100 μm at a pitch of 300 μm. Next, using this mask pattern as a mask, dry etching was performed by ICP-RIE to make 20000 fine holes in the core material, and then the mask pattern was removed from the core material using acetone. The formed micropores had a cylindrical inner wall surface with an opening diameter of 150 μm and a depth of 300 μm.
次に、コア材の微細孔を形成した面側に、再度、感光性ドライフィルムレジスト(旭化成(株)製APR)をラミネートし、凹部形成用のフォトマスクを介して露光、現像することによりマスクパターンを形成した。このマスクパターンは、微細孔非形成部位に10mm×10mmの長方形開口が12mmピッチで49個形成されたものであった。次に、このマスクパターンをマスクとしてサンドブラストによりコア材に凹部を形成し、その後、アセトンを用いてマスクパターンをコア材から除去した。このように形成した凹部は、開口寸法が10mm×10mm、深さが50μmの長方体形状であった。 Next, a photosensitive dry film resist (APR manufactured by Asahi Kasei Co., Ltd.) is laminated again on the side of the core material where the micropores are formed, and the mask is formed by exposing and developing through a photomask for forming recesses. A pattern was formed. This mask pattern was such that 49 rectangular openings of 10 mm × 10 mm were formed at 12 mm pitch in the non-micro-hole formation site. Next, a concave portion was formed in the core material by sand blasting using this mask pattern as a mask, and then the mask pattern was removed from the core material using acetone. The concave portion thus formed was a rectangular shape having an opening size of 10 mm × 10 mm and a depth of 50 μm.
次いで、上記の微細孔および凹部を形成していないコア材の面を研削装置により研磨してコア材の厚みを300μmとすることにより、この研磨面に微細孔を露出させてスルーホールを形成した。
次いで、コア材に熱酸化処理(1050℃、20分間)を施して、コア材の表面(スルーホール内壁面、凹部内壁面を含む)に二酸化珪素からなる絶縁膜を形成した。次いで、銅粒子を含有する導電性ペーストを、コア材の凹部を形成していない面側からスクリーン印刷によりスルーホール内に充填し、硬化処理(170℃、20分間)を施した。その後、コア材面から硬化突出した導電性ペーストを研磨して、スルーホール内に充填された導電性ペーストの表面とコア材の表面とが同一面となるようにしてコア基板を得た。
Next, the surface of the core material in which the fine holes and the recesses are not formed is polished by a grinding device so that the thickness of the core material is 300 μm, thereby exposing the fine holes on the polished surface to form a through hole. .
Next, the core material was subjected to thermal oxidation treatment (1050 ° C., 20 minutes) to form an insulating film made of silicon dioxide on the surface of the core material (including the inner wall surface of the through hole and the inner wall surface of the recess). Subsequently, the conductive paste containing copper particles was filled into the through hole by screen printing from the surface side where the concave portion of the core material was not formed, and subjected to curing treatment (170 ° C., 20 minutes). Thereafter, the conductive paste that hardened and protruded from the core material surface was polished to obtain a core substrate so that the surface of the conductive paste filled in the through hole and the surface of the core material were flush with each other.
次に、コア基板の複数の凹部にLSIチップ(10mm×10mm、厚み50μm)を、端子部が上面となるように、接着剤(エイブルスティック(株)製エイブルボンド3230)を用いて配設した。このLSIチップの配設では、従来の配線端子上へのLSIチップ搭載に要求されるような精密な位置合わせ管理は不要であった。
次に、上記のようにLSIチップを配設したコア基板上にベンゾシクロブテン樹脂組成物(ダウ・ケミカル社製サイクロテン4024)をスピンコーターにより塗布、乾燥して厚み10μmの電気絶縁層を形成した。
Next, LSI chips (10 mm × 10 mm, thickness 50 μm) were disposed in the plurality of recesses of the core substrate using an adhesive (Able Bond 3230 manufactured by Able Stick Co., Ltd.) so that the terminal portion was on the upper surface. . In the arrangement of the LSI chip, the precise alignment management required for mounting the LSI chip on the conventional wiring terminal is unnecessary.
Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) is applied to the core substrate on which the LSI chip is disposed as described above by a spin coater and dried to form an electrical insulating layer having a thickness of 10 μm. did.
次に、炭酸ガスレーザーを用いて、スルーホールに充填した導電性ペーストとLSIチップの端子部が露出するように小径の穴部(内径25μm)を電気絶縁層の所定位置に形成した。そして、洗浄後、穴部内および電気絶縁層上にスパッタリング法によりクロムと銅からなる導電層を形成し、この導電層上に液状レジスト(東京応化工業(株)製LA900)を塗布した。次いで、配線層形成用のフォトマスクを介し露光、現像して配線形成用のレジストパターンを形成した。このレジストパターンをマスクとして電解銅めっき(厚み4μm)を行い、その後、レジストパターンと導電層を除去した。これにより、スルーホールに充填した導電性ペーストやLSIチップの端子部の所定部位とビア部によって接続された配線層を、電気絶縁層を介してコア基板上に形成し、積層用モジュール(実施例1)を得た。
このように作製した積層用モジュールでは、コア基板に内蔵された49個のLSIチップの全てが、配線層と良好な接続状態であることが確認された。
Next, a carbon dioxide laser was used to form a small-diameter hole (inner diameter 25 μm) at a predetermined position of the electrical insulating layer so that the conductive paste filled in the through hole and the terminal portion of the LSI chip were exposed. After cleaning, a conductive layer made of chromium and copper was formed by sputtering in the hole and on the electrical insulating layer, and a liquid resist (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the conductive layer. Next, a resist pattern for wiring formation was formed by exposure and development through a photomask for wiring layer formation. Electrolytic copper plating (thickness: 4 μm) was performed using this resist pattern as a mask, and then the resist pattern and the conductive layer were removed. As a result, a conductive paste filled in the through hole and a wiring layer connected by a predetermined portion of the terminal portion of the LSI chip and the via portion are formed on the core substrate via the electric insulating layer, and the module for stacking (Example) 1) was obtained.
In the laminated module thus fabricated, it was confirmed that all 49 LSI chips built in the core substrate were in good connection with the wiring layer.
小型で高信頼性が要求される半導体装置や各種電子機器への用途にも適用できる。 It can also be applied to small semiconductor devices and various electronic devices that require high reliability.
11…積層用モジュール
12……コア基板
12′…コア材
13…凹部
14…スルーホール
15…導電材料
16…電子部品内蔵層
17…絶縁樹脂層
18…ビア部
19…配線層
DESCRIPTION OF SYMBOLS 11 ... Module for lamination | stacking 12 ... Core board | substrate 12 '...
Claims (6)
電子部品を内蔵するための凹部を一方の面に有し、導電材料によりスルーホールを介した表裏の導通がとられたコア基板を作製する工程と、
該コア基板の前記凹部内に電子部品を配設する工程と、
前記電子部品が配設された前記コア基板上に電気絶縁層を介し該電気絶縁層に形成されたビア部で必要な導通がとられた配線層を形成する工程と、を有することを特徴とする積層用モジュールの製造方法。 A core substrate, an electronic component embedded in the core substrate, a through hole for conducting conduction between the front and back surfaces of the core substrate by a conductive material, and a wiring layer disposed on the core substrate via an electrical insulating layer In a manufacturing method of a module for lamination comprising
A step of producing a core substrate having a recess for incorporating an electronic component on one side and conducting conduction between the front and back through a through hole with a conductive material;
Disposing an electronic component in the recess of the core substrate;
Forming a wiring layer having a necessary electrical connection at a via portion formed in the electrical insulating layer via the electrical insulating layer on the core substrate on which the electronic component is disposed. A method for manufacturing a stacking module.
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