JP4268560B2 - Electronic component built-in module and manufacturing method thereof - Google Patents

Electronic component built-in module and manufacturing method thereof Download PDF

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JP4268560B2
JP4268560B2 JP2004130849A JP2004130849A JP4268560B2 JP 4268560 B2 JP4268560 B2 JP 4268560B2 JP 2004130849 A JP2004130849 A JP 2004130849A JP 2004130849 A JP2004130849 A JP 2004130849A JP 4268560 B2 JP4268560 B2 JP 4268560B2
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electronic component
module
component built
built
insulating resin
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JP2005317585A (en
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悟 倉持
義孝 福岡
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Dai Nippon Printing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a module with built-in electronic components with high reliability, capable of activity as a simple body, and also as a layered body, and to provide its manufacturing method for easily and simply manufacturing such a module with built-in electronic components. <P>SOLUTION: The module with built-in electronic components is provided with a board, comprising a recess for built-in electronic components on one face of the board, electronic parts built in the recess of the board, an insulating resin layer for covering at least a part of side edge of the board while covering the face having the recess of the board, two or more up-and-down conductive vias penetrating the insulating resin layer for covering the side edge of the board, terminal vias allocated in the insulating resin layer for connecting to the terminal area of the electronic components, and a wiring layer for connecting the terminal vias with the desired conduction vias above and below. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

本発明は、ＬＳＩチップ等の電子部品を内蔵した電子部品内蔵モジュールと、このような電子部品内蔵モジュールを製造するための製造方法に関する。   The present invention relates to an electronic component built-in module incorporating an electronic component such as an LSI chip, and a manufacturing method for producing such an electronic component built-in module.

従来の多層配線基板は、例えば、サブトラクティブ法等で作製した低密度配線を有する両面基板をコア基板とし、このコア基板の両面にビルドアップ法により高密度配線を形成して作製されたものである。また、最近では、ＬＳＩチップ等を多層配線基板上に直接実装するベアチップ実装法が提案されている。ベアチップ実装法では、予め多層配線基板上に形成された配線の接続パッド部に、ボンディング・ワイヤ、ハンダや金属球等からなるバンプ、異方性導電膜、導電性接着剤、光収縮性樹脂等の接続手段を用いて半導体チップが実装される。また、作製する半導体装置にキャパシターやインダクター等のＬＣＲ回路部品が必要な場合は、半導体チップと同様に、多層配線基板に外付けで実装されている。   A conventional multilayer wiring board is produced by, for example, using a double-sided board having low-density wiring produced by a subtractive method or the like as a core board, and forming high-density wiring on both sides of the core board by a build-up method. is there. Recently, a bare chip mounting method in which an LSI chip or the like is directly mounted on a multilayer wiring board has been proposed. In the bare chip mounting method, bonding wires, bumps made of solder, metal balls, etc., anisotropic conductive films, conductive adhesives, light-shrinkable resins, etc., are formed on wiring connection pads formed on a multilayer wiring board in advance. A semiconductor chip is mounted using the connecting means. Further, when an LCR circuit component such as a capacitor or an inductor is required for the semiconductor device to be manufactured, it is externally mounted on a multilayer wiring board as in the semiconductor chip.

しかし、多層配線基板上に形成された配線の接続パッド部は、半導体チップ等の電子部品の実装部位とは別の部位に設けられるため、多層配線基板の面方向の広がりが必要であった。このため、多層配線基板の小型化には限界があり、実装される電子部品の数が増えるにしたがって、小型化は更に困難となる傾向にあった。
これに対応するために、半導体チップを実装した薄い基板と、上下導通ビアを備えた穴明き枠基板を、それぞれ複数個作製しておき、多層配線基板の作製時に、この実装基板と枠基板とを１つのモジュールとして一括で積層する方法が開示されている（特許文献１）。この方法では、複数のモジュールを積層しても、多層配線基板の面方向の広がりは必要がないため、多層配線基板の小型化が可能であった。
特開２００２−２７１０１５号公報 However, since the connection pad portion of the wiring formed on the multilayer wiring board is provided in a part different from the mounting part of the electronic component such as a semiconductor chip, it is necessary to expand the surface direction of the multilayer wiring board. For this reason, there is a limit to the miniaturization of the multilayer wiring board, and the miniaturization tends to become more difficult as the number of electronic components to be mounted increases.
In order to cope with this, a plurality of thin substrates on which semiconductor chips are mounted and a perforated frame substrate having vertical conduction vias are prepared, and when mounting a multilayer wiring substrate, the mounting substrate and the frame substrate are prepared. Has been disclosed as a single module (Patent Document 1). In this method, even if a plurality of modules are stacked, it is not necessary to expand the surface direction of the multilayer wiring board, and therefore the multilayer wiring board can be reduced in size.
JP 2002-271015 A

しかしながら、上述のような実装基板と枠基板とからなるモジュールでは、個々の電子部品を基板の所定の位置に実装するための位置合せを正確に行なう必要があり、工程管理が煩雑であるとともに、実装位置のズレを生じた場合、多層配線基板の信頼性が低下するという問題がある
また、所望の電子部品を組み込みながら多層配線基板を作製することも考えられるが、配線の端子上にバンプを介して電子部品を載置するための精密な位置合せが必要であり、また、電気絶縁層、導通ビア、配線層等を形成する工程が繰り返され、このため工程が複雑で長いものとなり、製造歩留まりの低下を来たし易いという問題がある。 However, in the module composed of the mounting board and the frame board as described above, it is necessary to accurately perform alignment for mounting each electronic component at a predetermined position on the board, and the process management is complicated. If the mounting position is misaligned, the reliability of the multilayer wiring board is reduced. In addition, it is conceivable to fabricate the multilayer wiring board while incorporating the desired electronic components, but bumps are formed on the wiring terminals. Precise positioning for mounting electronic components is necessary, and the process of forming an electrical insulating layer, conductive via, wiring layer, etc. is repeated, which makes the process complicated and long There is a problem that the yield tends to decrease.

本発明は、上記のような実情に鑑みてなされたものであり、単体での使用、積層体としての使用いずれも可能であり信頼性が高い電子部品内蔵モジュールと、このような電子部品内蔵モジュールを簡便に製造するための製造方法を提供することを目的とする。   The present invention has been made in view of the above circumstances, and can be used as a single unit or as a laminate, and has a highly reliable electronic component built-in module, and such an electronic component built-in module. It aims at providing the manufacturing method for manufacturing simply.

このような目的を達成するために、本発明の電子部品内蔵モジュールは、一方の面に電子部品内蔵用の凹部を備える基板と、該基板の前記凹部に内蔵された電子部品と、前記基板の前記凹部を有する面を被覆するとともに、前記基板の側端面の少なくとも一部を被覆する絶縁樹脂層と、前記基板の側端面を被覆する前記絶縁樹脂層を貫通する複数の上下導通ビアと、前記電子部品の端子部と接続するように前記絶縁樹脂層に配設された端子ビアと、該端子ビアと所望の前記上下導通ビアとを接続するように前記絶縁樹脂層上に配設された配線層とを備え、前記基板は基板の側端面を被覆する前記絶縁樹脂層が存在するための空間を介して端部基板を有するような構成とした。 In order to achieve such an object, an electronic component built-in module according to the present invention includes a substrate having a concave portion for incorporating an electronic component on one surface, an electronic component embedded in the concave portion of the substrate, The insulating resin layer covering the surface having the recess and covering at least a part of the side end surface of the substrate; a plurality of vertical conduction vias penetrating the insulating resin layer covering the side end surface of the substrate; Terminal vias arranged in the insulating resin layer so as to be connected to terminal portions of the electronic component, and wiring arranged on the insulating resin layer so as to connect the terminal vias and the desired vertical conduction vias and a layer, the substrate was so that a structure having a end substrate through a space for the insulating resin layer covering the side end surface of the substrate is present.

本発明の他の態様として、前記上下導通ビアの数は、前記電子部品の端子数以上であるような構成とした。
本発明の他の態様として、１個の電子部品を内蔵し、前記上下導通ビアは前記電子部品の周囲に配設され、また、前記上下導通ビアを露出し、かつ、前記配線層を被覆した絶縁被覆層を前記絶縁樹脂層上に備えるような構成とした。 As another aspect of the present invention, the number of the vertical conduction vias is equal to or more than the number of terminals of the electronic component.
As another aspect of the present invention, one electronic component is incorporated, the vertical conductive via is disposed around the electronic component, the vertical conductive via is exposed, and the wiring layer is covered. An insulating coating layer is provided on the insulating resin layer.

また、本発明の電子部品内蔵モジュールは、同じ位置に上下導通ビアを備える上述の電子部品内蔵モジュールが電子部品内蔵面を同じ向きにして前記上下導通ビアを接続するように複数個積層されたものであり、各電子部品内蔵モジュールは所望の電子部品を内蔵するものであり、各電子部品内蔵モジュールが有する上下導通ビアの数は、１個の電子部品内蔵モジュールに内蔵される電子部品の端子数より多く、積層された電子部品内蔵モジュールに内蔵される全電子部品の総端子数以下であるような構成とした。   Also, the electronic component built-in module according to the present invention includes a plurality of the above-described electronic component built-in modules provided with vertical conduction vias at the same position and stacked such that the vertical conduction vias are connected with the electronic component built-in surface in the same direction. Each electronic component built-in module incorporates a desired electronic component, and the number of vertical conduction vias of each electronic component built-in module is the number of terminals of the electronic component built in one electronic component built-in module. More than the total number of terminals of all the electronic components built in the stacked electronic component built-in module.

本発明の他の態様として、最外層に位置する前記電気部品内蔵モジュールの前記配線層が配設されている面に、前記上下導通ビアを露出し、かつ、前記配線層を被覆した絶縁被覆層を備えるような構成とした。
本発明の他の態様として、前記配線層が配設されている面と反対の面に露出している前記上下導通ビアに、はんだボールが配設されているような構成とした。
本発明の他の態様として、前記基板は、ＸＹ方向の熱膨張係数が２〜２０ｐｐｍの範囲内であるような構成とした。
本発明の他の態様として、前記電子部品は、ＬＳＩチップ、ＩＣチップ、ＬＣＲ回路部品、センサ部品のいずれかであるような構成とした。 As another aspect of the present invention, an insulating coating layer that exposes the upper and lower conductive vias and covers the wiring layer on a surface of the module with a built-in electrical component located in the outermost layer. It was set as the structure provided with.
As another aspect of the present invention, a solder ball is disposed in the vertical conduction via exposed on the surface opposite to the surface on which the wiring layer is disposed.
As another aspect of the present invention, the substrate is configured such that the thermal expansion coefficient in the XY direction is in the range of 2 to 20 ppm.
As another aspect of the present invention, the electronic component is configured as any one of an LSI chip, an IC chip, an LCR circuit component, and a sensor component.

本発明の電子部品内蔵モジュールの製造方法は、ベース基板の一方の面に電子部品内蔵用の凹部を形成し、該凹部に電子部品を配設する工程と、前記ベース基板に溝部を形成する工程と、前記電子部品を被覆し、かつ、前記溝部を充填するように前記ベース基板の一方の面に絶縁樹脂層を形成する工程と、前記溝部内に位置する上下導通ビア用孔部と前記電子部品の端子が露出する端子ビア用孔部とを、それぞれ前記絶縁樹脂層に形成する工程と、前記上下導通ビア用孔部と前記端子ビア用孔部とを導電材料で充填して上下導通ビアと端子ビアを形成するとともに、該端子ビアと所望の前記上下導通ビアとを接続するための配線層を形成する工程と、前記ベース基板の他方の面を研磨して前記溝部内に位置する前記絶縁樹脂層と前記上下導通ビアを露出させる工程と、を有するような構成とした。   The method of manufacturing an electronic component built-in module according to the present invention includes a step of forming a recess for incorporating an electronic component on one surface of a base substrate, disposing the electronic component in the recess, and a step of forming a groove in the base substrate. A step of forming an insulating resin layer on one surface of the base substrate so as to cover the electronic component and fill the groove, and a hole for a vertical conductive via located in the groove and the electronic Forming a terminal via hole in which the terminal of the component is exposed in the insulating resin layer; filling the vertical conductive via hole and the terminal via hole with a conductive material; Forming a wiring layer for connecting the terminal via and the desired vertical conduction via, and polishing the other surface of the base substrate to position the groove in the groove portion. Insulating resin layer and vertical conduction Exposing a A, it was such as to have configure.

本発明の他の態様として、前記ベース基板への前記凹部の形成、前記溝部の形成は、ＩＣＰ−ＲＩＥ法またはサンドブラスト法により行うような構成とした。
本発明の他の態様として、レーザー加工法による前記絶縁樹脂層の加工により、あるいは、前記絶縁樹脂層を感光性絶縁樹脂層としフォトリソグラフィー法で加工することにより、前記上下導通ビア用孔部と前記端子ビア用孔部を同時に形成するような構成とした。
本発明の他の態様として、多面付けで電子部品内蔵モジュールを形成した後、ダイシングにより個々の電子部品内蔵モジュールを得る工程を有するような構成とした。 As another aspect of the present invention, the recess and the groove are formed on the base substrate by an ICP-RIE method or a sand blast method.
As another aspect of the present invention, by processing the insulating resin layer by a laser processing method, or by processing the insulating resin layer as a photosensitive insulating resin layer by a photolithography method, The terminal via hole is formed at the same time.
As another aspect of the present invention, the electronic component built-in module is formed by multi-face mounting, and then the individual electronic component built-in module is obtained by dicing.

本発明の他の態様として、前記上下導通ビアを露出し、かつ、前記配線層を被覆するように前記絶縁樹脂層上に絶縁被覆層を形成する工程を有するような構成とした。
本発明の他の態様として、同じ位置に上下導通ビアを備える電子部品内蔵モジュールを多面付けで形成した後、多面付け状態の電子部品内蔵モジュールを前記上下導通ビアが接続されるように複数積層して固着し、次いで、ダイシングにより個々の電子部品内蔵モジュールを得る工程を有するような構成とした。
本発明の他の態様として、最外層に位置する電子部品内蔵モジュールの前記配線層が配設されている面に、前記上下導通ビアを露出し、かつ、前記配線層を被覆するように絶縁被覆層を形成する工程を有するような構成とした。
本発明の他の態様として、多面付けを構成する各電子部品内蔵モジュールが有する上下導通ビアの数を、内蔵される電子部品の総端子数より多く、積層される複数個の電子部品内蔵モジュールに内蔵される全電子部品の総端子数以下とするような構成とした。 As another aspect of the present invention, the vertical conductive via is exposed and an insulating coating layer is formed on the insulating resin layer so as to cover the wiring layer.
As another aspect of the present invention, after forming the electronic component built-in module having the vertical conduction vias at the same position by multi-sided attachment, a plurality of the multi-sided electronic component built-in modules are stacked so that the vertical conduction vias are connected. Then, it is configured to have a step of obtaining individual electronic component built-in modules by dicing.
As another aspect of the present invention, the upper and lower conductive vias are exposed on the surface of the electronic component built-in module located in the outermost layer where the wiring layer is disposed, and the insulating coating is provided so as to cover the wiring layer It was set as the structure which has the process of forming a layer.
As another aspect of the present invention, the number of vertically conductive vias included in each electronic component built-in module constituting multi-sided layout is larger than the total number of terminals of the built-in electronic components, and a plurality of electronic component built-in modules stacked are stacked. The total number of terminals of all the built-in electronic components is set to be equal to or less.

このような本発明の電子部品内蔵モジュールは、基板の凹部内に電子部品が内蔵されているので、小型化、薄型化が可能であるとともに、上下導通ビアが絶縁樹脂層中に形成されているため、例えば、基板がシリコンであるときに、上下導通ビアの周囲に酸化シリコン等の絶縁材料が存在する場合に比べて特性インピーダンスの整合の点で有利であり、また、内蔵される電子部品の端子数より上下導通ビアの数を多く設定した場合、所望の上下導通ビアを電子部品と接続し複数の電子部品内蔵モジュールを、上下導通ビアが接続するように積層するのみで、多層構造のマルチモチップジュールが可能であり、個々の電子部品の精密な位置合せが不要である。
本発明の電子部品内蔵モジュールの製造方法では、凹部に電子部品が配設された基板上に絶縁樹脂層を配し、上下導通ビアや端子ビアを介して必要な導通がとられた配線層を形成するので、配線層の端子上にバンプを介して電子部品を載置する従来の方法に比べて、電子部品の位置合せが容易であるとともに、配線層と電子部品との接続信頼性が格段に向上する。 Such an electronic component built-in module according to the present invention has an electronic component built in the concave portion of the substrate. Therefore, the electronic component built-in module can be reduced in size and thickness, and a vertical conductive via is formed in the insulating resin layer. Therefore, for example, when the substrate is silicon, it is advantageous in terms of matching of characteristic impedance as compared with the case where an insulating material such as silicon oxide exists around the vertical conduction via, and the built-in electronic component When the number of vertical conduction vias is set to be larger than the number of terminals, a multi-layered multi-module can be obtained simply by connecting a desired vertical conduction via to an electronic component and stacking a plurality of electronic component built-in modules so that the vertical conduction via is connected. Chip joules are possible and precise alignment of individual electronic components is not required.
In the method for manufacturing an electronic component built-in module according to the present invention, an insulating resin layer is disposed on a substrate in which an electronic component is disposed in a recess, and a wiring layer in which necessary conduction is obtained via a vertical conduction via or a terminal via is provided. As a result, the positioning of the electronic components is easier and the connection reliability between the wiring layers and the electronic components is significantly higher than the conventional method of placing the electronic components on the wiring layer terminals via bumps. To improve.

以下、本発明の実施の形態について図面を参照して説明する。
電子部品内蔵モジュール
図１は、本発明の電子部品内蔵モジュールの一実施形態を示す平面図であり、図２は図１に示される電子部品内蔵モジュールのＡ−Ａ線（二点鎖線）矢視縦断面図である。図１および図２において、本発明の電子部品内蔵モジュール１１は、基板１２と、この基板１２の一方の面に設けられた電子部品内蔵用の凹部１３と、この凹部１３に内蔵された電子部品２１と、基板１２の凹部１３を有する面を被覆するとともに、基板１２の側端面１２ａを被覆する絶縁樹脂層１６とを備えている。絶縁樹脂層１６のうち、基板１２の側端面１２ａを被覆する絶縁樹脂層１６には、これを貫通する複数の上下導通ビア１７が配設され、また、基板１２上の絶縁樹脂層１６は、電子部品２１の端子部２２と接続した端子ビア１８が配設されている。そして、端子ビア１８と所望の上下導通ビア１７とを接続するように配線層１９が絶縁樹脂層１６上に配設され、さらに、上下導通ビア１７を露出する開口部２０ａを有し、かつ、配線層１９を被覆した絶縁被覆層２０を絶縁樹脂層１６上に備えている。尚、図１は、構成を理解し易くするために、絶縁被覆層２０を取り除いた状態で示されている。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Electronic component built-in module 1 is a plan view showing one embodiment of an electronic component built-in module of the present invention, FIG. 2 (chain double-dashed line) A-A line of the electronic component built-in module shown in FIG. 1 arrow It is a longitudinal cross-sectional view. 1 and 2, an electronic component built-in module 11 according to the present invention includes a substrate 12, a recessed portion 13 for incorporating an electronic component provided on one surface of the substrate 12, and an electronic component incorporated in the recessed portion 13. 21 and an insulating resin layer 16 that covers the surface of the substrate 12 having the recess 13 and covers the side end surface 12 a of the substrate 12. Among the insulating resin layers 16, the insulating resin layer 16 covering the side end surface 12a of the substrate 12 is provided with a plurality of vertical conductive vias 17 penetrating therethrough, and the insulating resin layer 16 on the substrate 12 is A terminal via 18 connected to the terminal portion 22 of the electronic component 21 is disposed. A wiring layer 19 is disposed on the insulating resin layer 16 so as to connect the terminal via 18 and a desired vertical conduction via 17, and further has an opening 20 a that exposes the vertical conduction via 17. An insulating coating layer 20 that covers the wiring layer 19 is provided on the insulating resin layer 16. Note that FIG. 1 is shown with the insulating coating layer 20 removed for easy understanding of the configuration.

図３は、上述の本発明の電子部品内蔵モジュール１１を構成する基板１２の平面図であり、電子部品内蔵モジュール１１の外郭を二点鎖線で示している。基板１２は方形状の板状体であり、一方の面に方形状の電子部品内蔵用の凹部１３を備えている。そして、基板１２の全ての側端面１２ａが絶縁樹脂層１６で被覆されている。このような基板１２は、ＸＹ方向（基板１２の表面（凹部１３が形成されている面）に平行な平面）の熱膨張係数が２〜２０ｐｐｍ、好ましくは２．５〜１７ｐｐｍの範囲内であることが望ましく、例えば、シリコン、セラミック、ガラス、ガラス−エポキシ複合材料等の材質を使用することができる。基板１２の厚みは、例えば、３０〜３００μｍの範囲で設定することができ、凹部１３の深さは２０〜２５０μｍ、一辺の長さは０．５〜２０ｍｍの範囲で設定することができる。尚、凹部１３の形状は、内蔵する電子部品２１に対応して適宜設定することができ、図示の形状に限定されるものではない。   FIG. 3 is a plan view of the substrate 12 constituting the electronic component built-in module 11 of the present invention described above, and the outline of the electronic component built-in module 11 is indicated by a two-dot chain line. The substrate 12 is a rectangular plate-like body, and includes a concave portion 13 for incorporating a rectangular electronic component on one surface. All side end surfaces 12 a of the substrate 12 are covered with the insulating resin layer 16. Such a substrate 12 has a coefficient of thermal expansion of 2 to 20 ppm, preferably 2.5 to 17 ppm in the XY direction (a plane parallel to the surface of the substrate 12 (surface on which the recess 13 is formed)). For example, a material such as silicon, ceramic, glass, glass-epoxy composite material, or the like can be used. The thickness of the substrate 12 can be set, for example, in the range of 30 to 300 μm, the depth of the recess 13 can be set in the range of 20 to 250 μm, and the length of one side can be set in the range of 0.5 to 20 mm. In addition, the shape of the recessed part 13 can be suitably set corresponding to the electronic component 21 to be incorporated, and is not limited to the illustrated shape.

凹部１３に内蔵された電子部品２１としては、ＬＳＩチップ、ＩＣチップ、ＬＣＲ回路部品、センサ部品のいずれか１種または２種以上とすることができる。
電子部品内蔵モジュール１１を構成する絶縁樹脂層１６、絶縁被覆層２０の材質は、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の有機材料、あるいは、これらの有機材料とガラス繊維等を組み合わせたもの等とすることができる。基板１２上の絶縁樹脂層１６の厚みは、例えば、３〜２０μｍの範囲で設定することができ、配線層１９を被覆する絶縁被覆層２０の厚みは、３〜２０μｍの範囲で設定することができる。また、上下導通ビア１７の材質、端子ビア１８の材質、配線層１９の材質は、銅、銀、金、クロム、アルミニウム等の導電材料とすることができる。上下導通ビア１７、端子ビア１８の太さは、例えば、１０〜１００μｍの範囲で設定することができる。 The electronic component 21 built in the recess 13 may be one or more of LSI chip, IC chip, LCR circuit component, and sensor component.
The insulating resin layer 16 and the insulating coating layer 20 constituting the electronic component built-in module 11 are made of an organic material such as an epoxy resin, a benzocyclobutene resin, a cardo resin, or a polyimide resin, or these organic materials and glass fiber. It can be combined. The thickness of the insulating resin layer 16 on the substrate 12 can be set in the range of 3 to 20 μm, for example, and the thickness of the insulating coating layer 20 covering the wiring layer 19 can be set in the range of 3 to 20 μm. it can. The material of the vertical conduction via 17, the material of the terminal via 18, and the material of the wiring layer 19 can be conductive materials such as copper, silver, gold, chromium, and aluminum. The thickness of the vertical conduction via 17 and the terminal via 18 can be set in the range of 10 to 100 μm, for example.

上述の電子部品内蔵モジュール１１では、電子部品２１を囲むように１６個の上下導通ビア１７が配設されており、また、電子部品２１は４個の端子２２を有し、各端子に接続するように４個の端子ビア１８が配設されている。そして、４個の端子ビア１８は所望の上下導通ビア１７に配線層１９にて接続されている。このような電子部品内蔵モジュール１１の外形寸法は、例えば、一辺を０．５〜３０ｍｍの範囲で設定することができる。
上述のような本発明の電子部品内蔵モジュールは、基板１２の凹部１３内に電子部品２１が内蔵されているので、小型化、薄型化が可能である。また、上下導通ビア１７が絶縁樹脂層１６中に形成されているため、例えば、基板１２の材質がシリコンであるときに、上下導通ビア１７の周囲に酸化シリコン等の誘電率が大きい絶縁材料が存在する場合に比べて特性インピーダンスの整合の点で有利である。 In the electronic component built-in module 11 described above, 16 vertical conduction vias 17 are disposed so as to surround the electronic component 21, and the electronic component 21 has four terminals 22 and is connected to each terminal. Thus, four terminal vias 18 are arranged. The four terminal vias 18 are connected to a desired vertical conduction via 17 by a wiring layer 19. The external dimensions of such an electronic component built-in module 11 can be set, for example, within a range of 0.5 to 30 mm on one side.
Since the electronic component built-in module of the present invention as described above has the electronic component 21 built in the recess 13 of the substrate 12, it can be reduced in size and thickness. In addition, since the vertical conduction via 17 is formed in the insulating resin layer 16, for example, when the material of the substrate 12 is silicon, an insulating material having a large dielectric constant such as silicon oxide is formed around the vertical conduction via 17. It is advantageous in terms of matching of characteristic impedance compared to the case where it exists.

尚、本発明の電子部品内蔵モジュールの上下導通ビア１７の数と、電子部品２１の端子２１の数（端子ビア１８の数）には、特に制限はなく、後述の積層構造をとる場合には、上下導通ビア１７の数が、電子部品２１の端子２２の数（端子ビア１８の数）以上であることが好ましい。
また、上述の電子部品内蔵モジュール１１では、基板１２は方形状の板状体であり、その側端面１２ａが全て絶縁樹脂層１６で被覆されているが、これに限定されるものではない。例えば、基板１２の側端面１２ａを被覆する絶縁樹脂層１６が存在するための空間を介して端部基板を有し、この端部基板が電子部品内蔵モジュール１１の端部に位置するものであってもよい。図４〜図６は、このような基板１２の例を示すものであり、図４では、凹部１３を有する基板１２の周囲に帯状の空間１４が交差するように存在し、その周囲に２種の形状の端部基板１５ａ，１５ｂが配設されている。また、図５に示される例では、凹部１３を有する基板１２の四方向に長方形状の空間１４が存在し、その外側に端部基板１５が配設されている。さらに、図６に示される例では、凹部１３を有する基板１２の四方向に円形の空間１４が複数存在し、その外側に端部基板１５が配設されている。 There are no particular restrictions on the number of vertical conduction vias 17 and the number of terminals 21 (number of terminal vias 18) of the electronic component 21 of the electronic component built-in module of the present invention. The number of the vertical conduction vias 17 is preferably equal to or greater than the number of terminals 22 (the number of terminal vias 18) of the electronic component 21.
Further, in the electronic component built-in module 11 described above, the substrate 12 is a rectangular plate-like body, and the side end face 12a is entirely covered with the insulating resin layer 16, but the invention is not limited to this. For example, an end substrate is provided through a space for the insulating resin layer 16 covering the side end surface 12a of the substrate 12 to be located, and this end substrate is located at the end of the electronic component built-in module 11. May be. FIGS. 4 to 6 show examples of such a substrate 12. In FIG. 4, there are two belt-like spaces 14 around the substrate 12 having the recesses 13 so as to intersect therewith. The end substrates 15a and 15b having the shape are arranged. In the example shown in FIG. 5, there are rectangular spaces 14 in the four directions of the substrate 12 having the recesses 13, and the end substrate 15 is disposed outside thereof. Further, in the example shown in FIG. 6, a plurality of circular spaces 14 exist in the four directions of the substrate 12 having the recesses 13, and the end substrate 15 is disposed outside thereof.

図７は、図１に示される電子部品内蔵モジュール１１を構成する基板が、図４〜図６に示されるような形状の場合の、図２相当の縦断面図である。図７に示されるように、空間１４内には絶縁樹脂層１６と上下導通ビア１７が存在し、端部基板１５は電子部品内蔵モジュール１１の端部に位置している。
上述の空間１４の幅は、基板１２の側端面１２ａを被覆する絶縁樹脂層１６が存在し、その中に上下導通ビア１７が配設され得る大きさであり、例えば、上下導通ビア１７の周囲に少なくとも５μｍの厚みの絶縁樹脂層１６が存在可能な大きさに設定することができる。尚、上記の空間１４は、基板１２の周囲、あるいは四方向に存在する他に、図８に示されように、対向する二方向に存在するものであってもよい。 FIG. 7 is a longitudinal sectional view corresponding to FIG. 2 when the substrate constituting the electronic component built-in module 11 shown in FIG. 1 has a shape as shown in FIGS. As shown in FIG. 7, the insulating resin layer 16 and the vertical conduction via 17 exist in the space 14, and the end substrate 15 is located at the end of the electronic component built-in module 11.
The width of the space 14 described above is such a size that the insulating resin layer 16 covering the side end face 12a of the substrate 12 is present and the vertical conduction via 17 can be disposed therein. The size of the insulating resin layer 16 having a thickness of at least 5 μm can be set. In addition, the space 14 may exist in two opposite directions as shown in FIG. 8 in addition to the circumference of the substrate 12 or in the four directions.

また、本発明の電子部品内蔵モジュール１１は、図９に示されるように、配線層１９が配設されている面と反対の面に露出している上下導通ビア１７に、はんだボール２５が配設されたものであってもよい。また、絶縁被覆層２０を備えないものであってもよい。   In the electronic component built-in module 11 of the present invention, as shown in FIG. 9, solder balls 25 are arranged on the vertical conductive vias 17 exposed on the surface opposite to the surface on which the wiring layer 19 is disposed. It may be provided. Further, the insulating coating layer 20 may not be provided.

図１０は、本発明の電子部品内蔵モジュールの他の実施形態を示す図２相当の縦断面図である。図１０において、本発明の電子部品内蔵モジュール３１は、平面方向に複数の電子部品を内蔵したものであり、複数（図示例では２個）の基板３２と、各基板３２の一方の面に設けられた電子部品内蔵用の凹部３３と、この凹部３３に内蔵された電子部品４１と、基板３２の凹部３３を有する面を被覆するとともに、基板３２の側端面３２ａを被覆する絶縁樹脂層３６とを備えている。また、絶縁樹脂層３６のうち、基板３２の側端面３２ａを被覆する絶縁樹脂層３６（基板３２と端部基板３５との間の空間３４に存在する絶縁樹脂層３６）には、これを貫通する複数の上下導通ビア３７が配設され、また、基板３２上の絶縁樹脂層３６には、電子部品４１の端子部４２と接続した端子ビア３８が配設されている。そして、端子ビア３８と所望の上下導通ビア３７とを接続するように配線層３９が絶縁樹脂層３６上に配設され、さらに、上下導通ビア３７を露出する開口部４０ａを有し、かつ、配線層１９を被覆した絶縁被覆層４０を絶縁樹脂層３６上に備えている。   FIG. 10 is a longitudinal sectional view corresponding to FIG. 2 showing another embodiment of the electronic component built-in module of the present invention. In FIG. 10, an electronic component built-in module 31 according to the present invention has a plurality of electronic components built in the plane direction, and is provided on a plurality of (two in the illustrated example) substrates 32 and one surface of each substrate 32. The recessed portion 33 for incorporating the electronic component, the electronic component 41 incorporated in the recessed portion 33, the insulating resin layer 36 covering the surface of the substrate 32 having the recessed portion 33 and covering the side end surface 32 a of the substrate 32, It has. Further, among the insulating resin layers 36, the insulating resin layer 36 (the insulating resin layer 36 existing in the space 34 between the substrate 32 and the end substrate 35) that covers the side end surface 32a of the substrate 32 passes through this. A plurality of vertical conduction vias 37 are disposed, and a terminal via 38 connected to the terminal portion 42 of the electronic component 41 is disposed in the insulating resin layer 36 on the substrate 32. A wiring layer 39 is disposed on the insulating resin layer 36 so as to connect the terminal via 38 and the desired vertical conduction via 37, and further has an opening 40a exposing the vertical conduction via 37, and An insulating coating layer 40 covering the wiring layer 19 is provided on the insulating resin layer 36.

このような電子部品内蔵モジュール３１は、上述の電子部品内蔵モジュール１１を２個併設したものであり、併設する個数は２個に限定されない。また、電子部品内蔵モジュール３１を構成する基板３２、絶縁樹脂層３６、上下導通ビア３７、端子ビア３８、配線層３９、絶縁被覆層４０は、それぞれ上述の電子部品内蔵モジュール１１を構成する基板１２、絶縁樹脂層１６、上下導通ビア１７、端子ビア１８、配線層１９、絶縁被覆層２０と同様とすることができ、ここでの説明は省略する。   Such an electronic component built-in module 31 includes two electronic component built-in modules 11 described above, and the number of the electronic component built-in modules 31 is not limited to two. Further, the substrate 32, the insulating resin layer 36, the vertical conduction via 37, the terminal via 38, the wiring layer 39, and the insulating coating layer 40 constituting the electronic component built-in module 31 are respectively formed on the substrate 12 constituting the electronic component built-in module 11 described above. The insulating resin layer 16, the vertical conductive via 17, the terminal via 18, the wiring layer 19, and the insulating coating layer 20 can be the same, and the description thereof is omitted here.

また、電子部品４１としては、ＬＳＩチップ、ＩＣチップ、ＬＣＲ回路部品、センサ部品のいずれかとすることができ、各凹部３３に内蔵される電子部品４１が同じものであってもよく、また、異なるものであってもよい。
このような電子部品内蔵モジュール３１においても、配線層３９が配設されている面と反対の面に露出している上下導通ビア３７に、はんだボールを配設することができる。また、絶縁被覆層４０を備えないものであってもよい。 Further, the electronic component 41 can be any of an LSI chip, an IC chip, an LCR circuit component, and a sensor component, and the electronic component 41 built in each recess 33 may be the same or different. It may be a thing.
In such an electronic component built-in module 31 as well, solder balls can be disposed on the vertical conduction vias 37 exposed on the surface opposite to the surface on which the wiring layer 39 is disposed. Further, the insulating coating layer 40 may not be provided.

図１１は、本発明の電子部品内蔵モジュールの他の実施形態を示す図２相当の縦断面図である。図１１において、本発明の電子部品内蔵モジュール５１は、複数の電子部品内蔵モジュール５１Ａ，５１Ｂ，５１Ｃ，５１Ｄが積層されたものである。各電子部品内蔵モジュール５１Ａ，５１Ｂ，５１Ｃ，５１Ｄは、基板５２と、基板５２の一方の面に設けられた電子部品内蔵用の凹部５３と、この凹部５３に内蔵された電子部品６１と、基板５２の凹部５３を有する面を被覆するとともに、基板５２の側端面５２ａを被覆する絶縁樹脂層５６とを備えている。また、絶縁樹脂層５６のうち、基板５２の側端面５２ａを被覆する絶縁樹脂層５６（基板５２と端部基板５５との間の空間５４に存在する絶縁樹脂層５６）には、これを貫通する複数の上下導通ビア５７が配設され、また、基板５２上の絶縁樹脂層５６には、電子部品６１の端子部６２と接続した端子ビア５８が配設されている。そして、端子ビア５８と所望の上下導通ビア５７とを接続するように配線層５９が絶縁樹脂層５６上に配設されている。   FIG. 11 is a longitudinal sectional view corresponding to FIG. 2 showing another embodiment of the electronic component built-in module of the present invention. In FIG. 11, an electronic component built-in module 51 of the present invention is formed by stacking a plurality of electronic component built-in modules 51A, 51B, 51C, and 51D. Each of the electronic component built-in modules 51A, 51B, 51C, 51D includes a substrate 52, a concave portion 53 for incorporating an electronic component provided on one surface of the substrate 52, an electronic component 61 built in the concave portion 53, and a substrate. The insulating resin layer 56 that covers the side end surface 52 a of the substrate 52 is provided. In addition, among the insulating resin layers 56, the insulating resin layer 56 (the insulating resin layer 56 existing in the space 54 between the substrate 52 and the end substrate 55) covering the side end surface 52a of the substrate 52 passes therethrough. A plurality of vertical conductive vias 57 are disposed, and a terminal via 58 connected to the terminal portion 62 of the electronic component 61 is disposed in the insulating resin layer 56 on the substrate 52. A wiring layer 59 is disposed on the insulating resin layer 56 so as to connect the terminal via 58 and a desired vertical conduction via 57.

この電子部品内蔵モジュール５１では、複数の電子部品内蔵モジュール５１Ａ，５１Ｂ，５１Ｃ，５１Ｄが同じ位置に上下導通ビア５７を備えており、各電子部品内蔵モジュールは所望の上下導通ビア５７を配線層５９、端子ビア５８を介して電子部品６１と接続されている。そして、各電子部品内蔵モジュール５１Ａ，５１Ｂ，５１Ｃ，５１Ｄを同じ向きにして、上下導通ビア５７を接続するようにして積層した多層構造のマルチチップモジュールである。尚、電子部品内蔵モジュール５１では、最外層に位置する電子部品内蔵モジュール５１Ａの配線層５９が配設されている面に、上下導通ビア５７を露出し、かつ、配線層５９を被覆する絶縁被覆層を設けてもよい。このような絶縁被覆層は、上述の絶縁被覆層２０と同様とすることができる。   In this electronic component built-in module 51, the plurality of electronic component built-in modules 51A, 51B, 51C, 51D are provided with vertical conduction vias 57 at the same position, and each electronic component built-in module has a desired vertical conduction via 57 formed on the wiring layer 59. The electronic component 61 is connected via the terminal via 58. Each of the electronic component built-in modules 51A, 51B, 51C, 51D is a multi-chip module having a multilayer structure in which the upper and lower conductive vias 57 are connected in the same direction. In the electronic component built-in module 51, an insulating coating that exposes the vertical conduction via 57 and covers the wiring layer 59 on the surface on which the wiring layer 59 of the electronic component built-in module 51A located in the outermost layer is disposed. A layer may be provided. Such an insulating coating layer can be the same as the insulating coating layer 20 described above.

図１２は、各電子部品内蔵モジュール５１Ａ，５１Ｂ，５１Ｃ，５１Ｄの平面図である。各電子部品内蔵モジュール５１Ａ，５１Ｂ，５１Ｃ，５１Ｄでは、電子部品６１を囲むように１６個の上下導通ビア５７が配設されており、また、電子部品６１は４個の端子６２を有し、各端子に接続するように４個の端子ビア５８が配設されている。そして、４個の端子ビア５８は所望の上下導通ビア５７に配線層５９にて接続されている。図示例では、積層方向に接続されている同じ位置の上下導通ビア５７は、４個の電子部品６１のいずれかの端子に配線層５９と端子ビア６２を介して接続されており、他の位置で積層方向に接続されている上下導通ビア５７と、電気的に独立している。この場合、各電子部品内蔵モジュール５１Ａ，５１Ｂ，５１Ｃ，５１Ｄが有する上下導通ビア５７の数（１６個）は、電子部品内蔵モジュール５１に内蔵されている４個の電子部品６１の総端子数（４×４個）と等しいものとなっている。尚、電子部品内蔵モジュール５１に内蔵されている４個の電子部品６１のうち、複数の電子部品６１において、配線を共通とする端子が存在する場合がある。この場合には、積層方向に接続されている同じ位置の上下導通ビア５７が、複数の電子部品６１の端子に接続されることとなる。したがって、１６個の上下導通ビア５７の中に配線に供しないものが存在することになる。
上述の電子部品内蔵モジュールの実施形態は例示であり、例えば、上下導通ビアの数、端子ビアの数、電子部品の端子数等、積層数等は任意に設定することができる。 FIG. 12 is a plan view of each electronic component built-in module 51A, 51B, 51C, 51D. In each electronic component built-in module 51A, 51B, 51C, 51D, 16 vertical conduction vias 57 are disposed so as to surround the electronic component 61, and the electronic component 61 has four terminals 62, Four terminal vias 58 are arranged so as to connect to each terminal. The four terminal vias 58 are connected to a desired vertical conduction via 57 by a wiring layer 59. In the illustrated example, the vertical conductive via 57 at the same position connected in the stacking direction is connected to one of the terminals of the four electronic components 61 via the wiring layer 59 and the terminal via 62, and the other position. Are electrically independent of the vertical conduction vias 57 connected in the stacking direction. In this case, the number (16) of the vertical conduction vias 57 included in each electronic component built-in module 51A, 51B, 51C, 51D is the total number of terminals of the four electronic components 61 built in the electronic component built-in module 51 ( 4 × 4). Of the four electronic components 61 built in the electronic component built-in module 51, a plurality of electronic components 61 may have terminals that share wiring. In this case, the vertical conduction vias 57 at the same position connected in the stacking direction are connected to the terminals of the plurality of electronic components 61. Therefore, some of the 16 vertical conductive vias 57 are not used for wiring.
The above-described embodiment of the electronic component built-in module is merely an example, and the number of stacked layers such as the number of vertical conduction vias, the number of terminal vias, and the number of terminals of the electronic component can be arbitrarily set.

電子部品内蔵モジュールの製造方法
次に、本発明の電子部品内蔵モジュールの製造方法を図面を参照しながら説明する。
図１３および図１４は、本発明の電子部品内蔵モジュールの製造方法の一実施形態を、図２に示される電子部品内蔵モジュールを例として説明する工程図である。
本発明の電子部品内蔵モジュールの製造方法では、まず、ベース基板１の一方の面１ａに、電子部品内蔵用の凹部１３を形成する（図１３（Ａ））。図示例では、凹部１３を多面付けでベース基板１に形成している。 Next, a method for manufacturing an electronic component built-in module according to the present invention will be described with reference to the drawings.
FIG. 13 and FIG. 14 are process diagrams illustrating an embodiment of a method for manufacturing an electronic component built-in module according to the present invention, taking the electronic component built-in module shown in FIG. 2 as an example.
In the method for manufacturing an electronic component built-in module according to the present invention, first, a concave portion 13 for incorporating an electronic component is formed on one surface 1a of the base substrate 1 (FIG. 13A). In the illustrated example, the recess 13 is formed on the base substrate 1 with multiple faces.

ベース基板１は、ＸＹ方向（ベース基板１の面１ａに平行な平面）の熱膨張係数が２〜２０ｐｐｍ、好ましくは２．５〜１７ｐｐｍの範囲内である材質、例えば、シリコン、セラミック、ガラス、ガラス−エポキシ複合材料等の材質からなるものであってよい。このベース基板１の厚みは、内蔵する電子部品の厚み、作製する電子部品内蔵モジュールの厚み等を考慮して設定することができ、例えば、３０〜３００μｍの範囲で設定することができる。
凹部１３は、例えば、以下の方法により形成することができる。すなわち、ベース基板１の面１ａ上にマスクパターンを形成し、この面１ａに露出しているベース基板１に対して、プラズマを利用したドライエッチング法であるＩＣＰ−ＲＩＥ（Inductively Coupled Plasma - Reactive Ion Etching：誘導結合プラズマ−反応性イオンエッチング）法、またはサンドブラスト法により凹部を形成することができる。この凹部１３の深さ、開口形状、開口寸法は、内蔵する電子部品に応じて適宜設定することができる。 The base substrate 1 is made of a material having a thermal expansion coefficient in the XY direction (a plane parallel to the surface 1a of the base substrate 1) of 2 to 20 ppm, preferably 2.5 to 17 ppm, such as silicon, ceramic, glass, It may be made of a material such as a glass-epoxy composite material. The thickness of the base substrate 1 can be set in consideration of the thickness of a built-in electronic component, the thickness of a built-in electronic component built-in module, and the like, and can be set in the range of 30 to 300 μm, for example.
The recess 13 can be formed by the following method, for example. That is, a mask pattern is formed on the surface 1a of the base substrate 1, and an ICP-RIE (Inductively Coupled Plasma-Reactive Ion) which is a dry etching method using plasma is applied to the base substrate 1 exposed on the surface 1a. The recess can be formed by an etching (inductively coupled plasma-reactive ion etching) method or a sandblast method. The depth, opening shape, and opening size of the recess 13 can be set as appropriate according to the electronic component incorporated.

次に、上記の凹部１３に電子部品２１を配設する（図１３（Ｂ））。この電子部品２１の配設は、完成された電子部品を接着剤により固着する方法、凹部１３内に電子部品を嵌合する方法のいずれであってもよい。
次に、電子部品２１が配設されたベース基板１の面１ａに溝部２を形成する（図１３（Ｃ））。この溝部２は、後工程にて絶縁樹脂層が充填され、さらに、上下導通ビアが形成される部位であり、深さは作製する電子部品内蔵モジュールの厚みを考慮して設定することができ、また、開口形状は、形成する上下導通ビアの配設位置、個数等を考慮して設定することができる。この溝部２の形成は、例えば、上述の凹部１３の形成方法と同様の方法により形成することができる。 Next, the electronic component 21 is disposed in the recess 13 (FIG. 13B). The electronic component 21 may be arranged by either a method of fixing the completed electronic component with an adhesive or a method of fitting the electronic component in the recess 13.
Next, the groove portion 2 is formed in the surface 1a of the base substrate 1 on which the electronic component 21 is disposed (FIG. 13C). This groove part 2 is a part where an insulating resin layer is filled in a later process and further a vertical conduction via is formed, and the depth can be set in consideration of the thickness of the electronic component built-in module to be manufactured, Moreover, the opening shape can be set in consideration of the arrangement position, the number, and the like of the vertical conduction vias to be formed. The groove 2 can be formed by, for example, a method similar to the method of forming the recess 13 described above.

次いで、電子部品２１を被覆し、溝部２を充填するように、ベース基板１の面１ａに絶縁樹脂層１６を形成し（図１３（Ｄ））、溝部２内に位置する上下導通ビア用孔部７と、電子部品２１の端子２２が露出する端子ビア用孔部８とを、それぞれ絶縁樹脂層１６に形成する（図１３（Ｅ））。その後、上下導通ビア用孔部７と端子ビア用孔部８に導電材料を充填して上下導通ビア１７と端子ビア１８を形成するとともに、端子ビア１８と所望の上下導通ビア１７とを接続するための配線層１９を形成する。次いで、上下導通ビア１７を露出させるための開口部２０ａを有し、かつ、配線層１９を被覆するように絶縁被覆層２０を絶縁樹脂層１６上に形成する（図１４（Ａ））。   Next, an insulating resin layer 16 is formed on the surface 1a of the base substrate 1 so as to cover the electronic component 21 and fill the groove 2 (FIG. 13D), and the holes for the vertical conduction vias located in the groove 2 are formed. The part 7 and the terminal via hole 8 through which the terminal 22 of the electronic component 21 is exposed are respectively formed in the insulating resin layer 16 (FIG. 13E). Thereafter, the vertical conductive via hole 7 and the terminal via hole 8 are filled with a conductive material to form the vertical conductive via 17 and the terminal via 18, and the terminal via 18 and the desired vertical conductive via 17 are connected. A wiring layer 19 is formed. Next, the insulating coating layer 20 is formed on the insulating resin layer 16 so as to cover the wiring layer 19 and to have the opening 20a for exposing the vertical conductive via 17 (FIG. 14A).

絶縁樹脂層１６の形成は、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の電気絶縁性樹脂材料を含有する塗布液、あるいはこれらの電気絶縁性樹脂材料とガラス繊維とを組み合わせたものを含有する塗布液を公知の塗布方法で塗布し、その後、加熱、紫外線照射、電子線照射等の所定の硬化処理を施すことにより行うことができる。   The insulating resin layer 16 is formed by applying a coating solution containing an electrically insulating resin material such as an epoxy resin, a benzocyclobutene resin, a cardo resin, a polyimide resin, or a combination of these electrically insulating resin materials and glass fibers. Can be performed by applying a predetermined curing treatment such as heating, ultraviolet irradiation, electron beam irradiation, and the like.

上記の上下導通ビア用孔部７と端子ビア用孔部８の形成と、上下導通ビア１７、端子ビア１８、配線層１９の形成は、例えば、以下のように行うことができる。まず、感光性の絶縁樹脂材料を用いて絶縁樹脂層１６となる感光性絶縁樹脂層を形成し、この感光性絶縁樹脂層を所定のマスクを介して露光し、現像することにより、上下導通ビア用孔部７と端子ビア用孔部８を備えた絶縁樹脂層１６を形成する。そして、洗浄後、上下導通ビア用孔部７と端子ビア用孔部８の内部、および絶縁樹脂層１６上に真空成膜法により導電層を形成し、この導電層上にレジスト層を形成し、所望のパターン露光、現像を行うことによりレジストパターンを形成する。その後、このレジストパターンをマスクとして、上記の穴部を含む露出部に電解めっきにより導電材料を析出させて上下導通ビア１７、端子ビア１８、配線層１９を形成し、レジストパターンと導電層を除去する。   The formation of the vertical conduction via hole 7 and the terminal via hole 8 and the formation of the vertical conduction via 17, the terminal via 18, and the wiring layer 19 can be performed as follows, for example. First, a photosensitive insulating resin layer to be the insulating resin layer 16 is formed using a photosensitive insulating resin material, and the photosensitive insulating resin layer is exposed through a predetermined mask and developed, whereby a vertical conductive via is formed. An insulating resin layer 16 including the hole 7 and the terminal via hole 8 is formed. After cleaning, a conductive layer is formed by vacuum film formation inside the vertical conductive via hole 7 and the terminal via hole 8 and on the insulating resin layer 16, and a resist layer is formed on the conductive layer. Then, a resist pattern is formed by performing desired pattern exposure and development. Thereafter, using this resist pattern as a mask, a conductive material is deposited by electrolytic plating on the exposed part including the hole part to form the vertical conductive via 17, the terminal via 18, and the wiring layer 19, and the resist pattern and the conductive layer are removed. To do.

また、絶縁被覆層２０の形成は、まず、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の感光性の絶縁樹脂材料を用いて感光性絶縁樹脂層を形成する。次いで、この感光性絶縁樹脂層を所定のマスクを介して露光し、現像することにより、上下導通ビア１７を露出させるための開口部２０ａを備えた絶縁被覆層２０を形成する。   The insulating coating layer 20 is formed by first forming a photosensitive insulating resin layer using a photosensitive insulating resin material such as an epoxy resin, a benzocyclobutene resin, a cardo resin, or a polyimide resin. Next, the photosensitive insulating resin layer is exposed through a predetermined mask and developed to form an insulating coating layer 20 having an opening 20a for exposing the vertical conductive via 17.

また、上下導通ビア用孔部７と端子ビア用孔部８の形成と、上下導通ビア１７、端子ビア１８、配線層１９の形成は、以下のように行うこともできる。すなわち、炭酸ガスレーザー、ＵＶ−ＹＡＧレーザー等を用いて絶縁樹脂層１６に上下導通ビア用孔部７と端子ビア用孔部８を形成する。そして、洗浄後、上下導通ビア用孔部７と端子ビア用孔部８の内部、および絶縁樹脂層１６に無電解めっきにより導電層を形成し、この導電層上にドライフィルムレジストをラミネートして所望のパターン露光、現像を行うことによりレジストパターンを形成する。その後、このレジストパターンをマスクとして、上記の上下導通ビア用孔部７と端子ビア用孔部８の内部を含む露出部に電解めっきにより導電材料を析出させて上下導通ビア１７、端子ビア１８、配線層１９を形成し、レジストパターンと導電層を除去する。   The formation of the vertical conduction via hole 7 and the terminal via hole 8 and the formation of the vertical conduction via 17, the terminal via 18, and the wiring layer 19 can also be performed as follows. That is, the vertical conductive via hole 7 and the terminal via hole 8 are formed in the insulating resin layer 16 using a carbon dioxide gas laser, a UV-YAG laser, or the like. After cleaning, a conductive layer is formed by electroless plating inside the vertical conductive via hole 7 and the terminal via hole 8 and the insulating resin layer 16, and a dry film resist is laminated on the conductive layer. A resist pattern is formed by performing desired pattern exposure and development. After that, using this resist pattern as a mask, a conductive material is deposited by electrolytic plating on the exposed portion including the inside of the above-described vertical conductive via hole 7 and terminal via hole 8, so that the vertical conductive via 17, terminal via 18, A wiring layer 19 is formed, and the resist pattern and the conductive layer are removed.

上記の導電材料としては、例えば、銅、銀、金、クロム、アルミニウム等を挙げることができる。
次に、ベース基板１の他方の面１ｂを研磨して、上記の溝部２内に位置する絶縁樹脂層１６と上下導通ビア１７を露出させる（図１４（Ｂ））。ベース基板１の研磨は、例えば、ダイヤモンドグラインダーのような研磨装置により行なうことができる。尚、絶縁被覆層２０の形成は、ベース基板１の研磨後に行なってもよい。 Examples of the conductive material include copper, silver, gold, chromium, and aluminum.
Next, the other surface 1b of the base substrate 1 is polished to expose the insulating resin layer 16 and the vertical conduction via 17 located in the groove 2 (FIG. 14B). The base substrate 1 can be polished by a polishing apparatus such as a diamond grinder, for example. The insulating coating layer 20 may be formed after the base substrate 1 is polished.

この工程まで行なうことにより、多面付けの電子部品内蔵モジュールを得ることができ、図１４（Ｂ）の矢印ａでダイシングすることにより、図２に示されるような電子部品内蔵モジュール１１を得ることができる。この場合のダイシングは、絶縁樹脂層１６において行なわれる。また、ダイシングする位置を適宜設定することにより、図１０に示されるような平面方向に複数の電子部品２１を内蔵した電子部品内蔵モジュール３１を得ることができる。この場合、必要に応じて内蔵する電子部品２１の種類を選定することができる。   By performing this process, a multi-sided electronic component built-in module can be obtained. By dicing at the arrow a in FIG. 14B, an electronic component built-in module 11 as shown in FIG. 2 can be obtained. it can. Dicing in this case is performed in the insulating resin layer 16. Further, by appropriately setting the dicing position, an electronic component built-in module 31 in which a plurality of electronic components 21 are built in the planar direction as shown in FIG. 10 can be obtained. In this case, the type of the electronic component 21 to be incorporated can be selected as necessary.

また、図１１に示されるような積層構造の電子部品内蔵モジュールを作製する場合には、上述の製造方法と同様の工程にて、多面付けの電子部品内蔵モジュールを複数作製する。この場合、各電子部品内蔵モジュールは、同じ位置に上下導通ビア１７を備え、同じ位置にある（積層された状態で上下関係となる）電子部品２１は同種、異種いずれであってもよい。但し、配線層１９を介した端子ビア１８と所望の上下導通ビア１７との接続は、積層後の配線設計を基に、各電子部品内蔵モジュール毎に設計する。その後、複数の電子部品内蔵モジュールを、同じ位置に存在する上下導通ビアを厚み方向で接続するように積層し（図１４（Ｃ））、所望の箇所でダイシングすることにより、図１１に示されるような積層構造の電子部品内蔵モジュールを得ることができる。尚、図１４（Ｃ）に示す積層構造の電子部品内蔵モジュールの製造では、絶縁被覆層２０を設けずに作製した多面付けの電子部品内蔵モジュールを使用している。勿論、積層後に、最外層に位置する電子部品内蔵モジュールの配線層１９が配設されている面に、絶縁被覆素２０を設けてもよい。   Further, when the electronic component built-in module having a laminated structure as shown in FIG. 11 is produced, a plurality of multi-sided electronic component built-in modules are produced by the same process as the manufacturing method described above. In this case, each electronic component built-in module includes the vertical conduction vias 17 at the same position, and the electronic components 21 at the same position (which are in a vertical relationship in a stacked state) may be of the same type or different types. However, the connection between the terminal via 18 and the desired vertical conduction via 17 via the wiring layer 19 is designed for each electronic component built-in module based on the wiring design after lamination. Thereafter, a plurality of modules with built-in electronic components are stacked so that the upper and lower conductive vias existing at the same position are connected in the thickness direction (FIG. 14C), and dicing is performed at a desired location, as shown in FIG. An electronic component built-in module having such a laminated structure can be obtained. In the manufacture of the electronic component built-in module having a laminated structure shown in FIG. 14C, a multi-sided electronic component built-in module manufactured without providing the insulating coating layer 20 is used. Of course, the insulating covering element 20 may be provided on the surface on which the wiring layer 19 of the electronic component built-in module located in the outermost layer is disposed after lamination.

上記の各電子部品内蔵モジュールの積層では、金バンプを設け、ＮＣＰ（ノンコンダクティブ ペースト）やＡＣＦ（アンチアイソロトピック コンダクティブ フィルム）を用いた上下接続、金バンプ同士の超音波接続等を用いることにより、厚み方向における上下導通ビア１７の接続を行なうことができる。   In the stacking of each electronic component built-in module described above, gold bumps are provided, and vertical connection using NCP (non-conductive paste) or ACF (anti-isotopic conductive film), ultrasonic connection between gold bumps, etc. are used. The upper and lower conductive vias 17 in the thickness direction can be connected.

上述の電子部品内蔵モジュールの製造方法では、隣り合う電子部品内蔵モジュールを構成する上下導通ビア１７が１個の溝部２に形成されており、製造される電子部品内蔵モジュールは、図２に示されるような構造であるが、例えば、図７に示されるような構造の電子部品内蔵モジュールは、以下のような工程で製造することができる。すなわち、まず、上述の図１３（Ａ）、図１３（Ｂ）と同様にして、ベース基板１に凹部１３を形成し、電子部品２１を配設する。次いで、電子部品２１が配設されたベース基板１の面１ａに溝部２′を形成する（図１５（Ａ））。この溝部２′は、後工程にて絶縁樹脂層が充填され、さらに、上下導通ビアが形成される部位であり、図４〜図６、図８に示される空間１４を構成するものとなる。したがって、溝部２′の開口形状は、空間１４の形状に応じて設定される。この溝部２′は、上述の溝部２の形成方法と同様の方法により形成することができる。   In the above-described method for manufacturing an electronic component built-in module, the vertical conduction via 17 constituting the adjacent electronic component built-in module is formed in one groove portion 2, and the electronic component built-in module to be manufactured is shown in FIG. For example, an electronic component built-in module having a structure as shown in FIG. 7 can be manufactured by the following process. That is, first, similarly to the above-described FIG. 13A and FIG. 13B, the recess 13 is formed in the base substrate 1 and the electronic component 21 is disposed. Next, a groove 2 ′ is formed on the surface 1 a of the base substrate 1 on which the electronic component 21 is disposed (FIG. 15A). The groove 2 'is a portion where an insulating resin layer is filled in a later process and further a vertical conduction via is formed, and constitutes the space 14 shown in FIGS. 4 to 6 and FIG. Therefore, the opening shape of the groove 2 ′ is set according to the shape of the space 14. This groove 2 'can be formed by a method similar to the method of forming the groove 2 described above.

次に、電子部品２１を被覆し、溝部２′を充填するように、ベース基板１の面１ａに絶縁樹脂層１６を形成し、溝部２′内に位置する上下導通ビア用孔部７と、電子部品２１の端子２２が露出する端子ビア用孔部８を絶縁樹脂層１６に形成する（図１５（Ｂ））。ここでは、１個の溝部には、該当する電子部品内蔵モジュール用の上下導通ビア用孔部７のみが形成され、隣り合う電子部品内蔵モジュール用の上下導通ビア用孔部７は形成されない。次いで、上下導通ビア用孔部７と端子ビア用孔部８に導電材料を充填して上下導通ビア１７と端子ビア１８を形成するとともに、端子ビア１８と所望の上下導通ビア１７とを接続するための配線層１９を形成する。次いで、上下導通ビア１７を露出させるための開口部２０ａを有し、かつ、配線層１９を被覆するように絶縁被覆層２０を絶縁樹脂層１６上に形成し、ベース基板１の他方の面を研磨する（図１５（Ｃ））。尚、絶縁被覆層２０の形成は、ベース基板１の研磨後に行なってもよい。   Next, an insulating resin layer 16 is formed on the surface 1a of the base substrate 1 so as to cover the electronic component 21 and fill the groove 2 ', and the vertical conduction via hole 7 located in the groove 2'; A terminal via hole 8 through which the terminal 22 of the electronic component 21 is exposed is formed in the insulating resin layer 16 (FIG. 15B). Here, only the vertical conduction via hole 7 for the corresponding electronic component built-in module is formed in one groove, and the vertical conduction via hole 7 for the adjacent electronic component built-in module is not formed. Next, the vertical conductive via hole 7 and the terminal via hole 8 are filled with a conductive material to form the vertical conductive via 17 and the terminal via 18, and the terminal via 18 and the desired vertical conductive via 17 are connected to each other. A wiring layer 19 is formed. Next, the insulating coating layer 20 is formed on the insulating resin layer 16 so as to cover the wiring layer 19 and has an opening 20a for exposing the vertical conductive vias 17, and the other surface of the base substrate 1 is formed. Polishing is performed (FIG. 15C). The insulating coating layer 20 may be formed after the base substrate 1 is polished.

絶縁樹脂層１６、絶縁被覆層２０の形成、上下導通ビア用孔部７や端子ビア用孔部８の形成、上下導通ビア１７、端子ビア１８、配線層１９の形成は、上述と同様の形成方法により行なうことができる。
この工程まで行なうことにより、多面付けの電子部品内蔵モジュールを得ることができ、図１５（Ｃ）の矢印ａでダイシングすることにより、図７に示されるような電子部品内蔵モジュール１１を得ることができる。この場合のダイシングは、絶縁樹脂層１６と端部基板１５の積層部において行なわれる。また、図１０に示されるような平面方向に複数の電子部品２１を内蔵した電子部品内蔵モジュール３１、図１１に示されるような積層構造の電子部品内蔵モジュール５１も、上述の態様と同様にして作製することができる。
上述の本発明の電子部品内蔵モジュールの製造方法は例示であり、これに限定されるものではない。 The formation of the insulating resin layer 16 and the insulating coating layer 20, the formation of the vertical conduction via hole 7 and the terminal via hole 8, the formation of the vertical conduction via 17, the terminal via 18, and the wiring layer 19 are the same as described above. It can be done by the method.
By performing up to this step, a multi-sided electronic component built-in module can be obtained, and by dicing at the arrow a in FIG. 15C, an electronic component built-in module 11 as shown in FIG. 7 can be obtained. it can. In this case, dicing is performed in the laminated portion of the insulating resin layer 16 and the end substrate 15. Further, an electronic component built-in module 31 in which a plurality of electronic components 21 are built in a planar direction as shown in FIG. 10 and a laminated electronic component built-in module 51 as shown in FIG. Can be produced.
The above-described method for manufacturing the electronic component built-in module of the present invention is an example, and the present invention is not limited to this.

次に、具体的実施例を挙げて本発明を更に詳細に説明する。
［実施例１］
ベース基板として、厚み６２５μｍのシリコンウエハを準備し、このベース基板の一方の面に感光性ドライフィルムレジスト（東京応化工業（株）製ＢＦ４０５）をラミネートし、凹部形成用のフォトマスクを介して露光、現像することによりマスクパターンを形成した。上記のシリコンウエハのＸＹ方向（シリコンウエハの表面に平行な平面）の熱膨張係数は、４ｐｐｍであった。また、マスクパターンは、一辺５ｍｍである正方形の開口が１２ｍｍピッチで形成された多面付けであった。 Next, the present invention will be described in more detail with specific examples.
[Example 1]
A silicon wafer having a thickness of 625 μm is prepared as a base substrate, a photosensitive dry film resist (BF405 manufactured by Tokyo Ohka Kogyo Co., Ltd.) is laminated on one surface of the base substrate, and exposed through a photomask for forming a recess. The mask pattern was formed by developing. The thermal expansion coefficient of the above silicon wafer in the XY direction (a plane parallel to the surface of the silicon wafer) was 4 ppm. The mask pattern was multi-faceted with square openings having a side of 5 mm formed at a pitch of 12 mm.

次に、このマスクパターンをマスクとしてサンドブラストによりベース基板に凹部を形成した。この凹部は、開口が一辺６ｍｍの正方形であり、深さが６０μｍのものであった。
次いで、上記の凹部にＬＳＩチップ（５ｍｍ×５ｍｍ、厚み５０μｍ、端子数２０個）を接着剤（エイブルスティック（株）製エイブルボンド３２３０）を用いて配設した。
次に、ＬＳＩチップが内蔵されたベース基板面に感光性ドライフィルムレジスト（東京応化工業（株）製ＢＦ４０５）をラミネートし、溝部形成用のフォトマスクを介して露光、現像することによりマスクパターンを形成した。マスクパターンは、幅３ｍｍのストライプ状の開口が上記凹部の各辺に平行となるように１２ｍｍピッチで格子状に形成され、各格子の中心部にＬＳＩチップが位置するようにした。その後、このマスクパターンをマスクとしてサンドブラストによりベース基板に溝部を形成した。この溝部は、開口幅が３ｍｍのストライプ状であり、深さが６０μｍのものであった。 Next, a concave portion was formed on the base substrate by sand blasting using this mask pattern as a mask. The recess had a square shape with an opening of 6 mm on a side and a depth of 60 μm.
Next, an LSI chip (5 mm × 5 mm, thickness 50 μm, number of terminals 20) was arranged in the recess using an adhesive (Able Bond 3230 manufactured by Able Stick Co., Ltd.).
Next, a photosensitive dry film resist (BF405 manufactured by Tokyo Ohka Kogyo Co., Ltd.) is laminated on the surface of the base substrate in which the LSI chip is built, and the mask pattern is formed by exposing and developing through a photomask for forming a groove. Formed. The mask pattern was formed in a lattice pattern with a pitch of 12 mm so that stripe-shaped openings with a width of 3 mm were parallel to each side of the recess, and the LSI chip was positioned at the center of each lattice. Thereafter, grooves were formed on the base substrate by sand blasting using this mask pattern as a mask. The groove portion had a stripe shape with an opening width of 3 mm and a depth of 60 μm.

次に、上記のＬＳＩチップを被覆し、溝部を充填するように、ベンゾシクロブテン樹脂組成物（ダウ・ケミカル社製サイクロテン４０２４）をスピンコーターにより塗布、乾燥して、ＬＳＩチップ上の厚みが１０μｍとなるように感光性絶縁樹脂層を形成した。
次に、ビア形成用のマスクを介して上記の感光性絶縁樹脂層を露光し、現像を行った。これにより、絶縁樹脂層を形成するとともに、上記の溝部を充填している絶縁樹脂層に上下導通ビア用孔部（内径５０μｍ）を複数形成し、また、ＬＳＩチップの端子部が露出するように端子ビア用孔部（内径２０μｍ）を絶縁樹脂層の所定位置に形成した。上記の上下導通ビア用孔部は、各ＬＳＩチップの周囲に２００個（ＬＳＩチップの１辺に対して５０個）形成され、１本のストライプ状の凹部には、隣接するＬＳＩチップ用の上下導通ビア用孔部が間隔１００μｍで並行して配列されたものとなった。 Next, the LSI chip is coated, and a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) is applied by a spin coater so as to fill the groove portion, and then dried. A photosensitive insulating resin layer was formed to have a thickness of 10 μm.
Next, the photosensitive insulating resin layer was exposed through a mask for forming vias and developed. As a result, an insulating resin layer is formed, and a plurality of vertical conductive via holes (inner diameter 50 μm) are formed in the insulating resin layer filling the groove, and the terminal portion of the LSI chip is exposed. Terminal via holes (inner diameter 20 μm) were formed at predetermined positions of the insulating resin layer. The upper and lower conductive via holes are formed 200 around each LSI chip (50 per side of the LSI chip), and one stripe-shaped recess has upper and lower holes for adjacent LSI chips. The conductive via holes were arranged in parallel at intervals of 100 μm.

次いで、洗浄後、上下導通ビア用孔部、端子ビア用孔部の内部、および絶縁樹脂層上にスパッタリング法によりチタンと銅からなる導電層を形成し、この導電層上に液状レジスト（東京応化工業（株）製ＬＡ９００）を塗布した。次いで、ビア・配線層形成用のフォトマスクを介し露光、現像して、ビア・配線形成用のレジストパターンを形成した。このレジストパターンをマスクとして電解銅めっき（厚み６０μｍ）を行い、上下導通ビア用孔部、端子ビア用孔部の内部を銅で充填するとともに、絶縁樹脂層上に露出している導電層上に銅薄膜を形成した。その後、レジストパターンと導電層を除去した。これにより、溝部内の絶縁樹脂層中に上下導通ビアを形成し、また、ＬＳＩチップの端子に接続する端子ビアを絶縁樹脂層に形成し、各端子ビアを所望の上下導通ビアに接続する配線層を絶縁樹脂層上に形成した。   Next, after cleaning, a conductive layer made of titanium and copper is formed by sputtering on the inside of the hole for the vertical conduction via, the hole for the terminal via, and the insulating resin layer, and a liquid resist (Tokyo Ohka Kogyo) is formed on this conductive layer. Industrial application LA900) was applied. Next, exposure and development were performed through a photomask for forming a via / wiring layer to form a resist pattern for forming a via / wiring layer. Using this resist pattern as a mask, electrolytic copper plating (thickness 60 μm) is performed to fill the inside of the hole for the vertical conduction via and the hole for the terminal via with copper, and on the exposed conductive layer on the insulating resin layer A copper thin film was formed. Thereafter, the resist pattern and the conductive layer were removed. As a result, a vertical conductive via is formed in the insulating resin layer in the groove, a terminal via connected to the LSI chip terminal is formed in the insulating resin layer, and each terminal via is connected to a desired vertical conductive via. A layer was formed on the insulating resin layer.

次に、上記の配線層を被覆するように、ベンゾシクロブテン樹脂組成物（ダウ・ケミカル社製サイクロテン４０２４）をスピンコーターにより塗布、乾燥して、厚み７μｍの感光性絶縁樹脂層を形成した。次に、上下導通ビアの開口部形成用のマスクを介して上記の感光性絶縁樹脂層を露光し、現像を行った。これにより、上下導通ビアが露出する開口部（内径５０μｍ）を２００個備え、配線層を被覆する絶縁被覆層を形成した。
次に、絶縁被覆層形成面に粘着テープを貼り、ダイヤモンドグラインダーによりベース基板を厚み６０μｍとなるまで研磨して、溝部内に位置する絶縁樹脂層で囲まれた上下導通ビアを露出させた。これにより、多面付けの電子部品内蔵モジュールを得た。
次いで、隣接するＬＳＩチップ用の上下導通ビアが並行して配列された中央の部位（図１４（Ｂ）に矢印ａで示される部位）にて、絶縁樹脂層をダイシングして、一辺が１２ｍｍの正方形の本発明の電子部品内蔵モジュールを得た。 Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) was applied by a spin coater so as to cover the wiring layer and dried to form a photosensitive insulating resin layer having a thickness of 7 μm. . Next, the photosensitive insulating resin layer was exposed and developed through a mask for forming openings of vertical conduction vias. As a result, 200 openings (inner diameter: 50 μm) from which the vertical conductive vias were exposed were formed, and an insulating coating layer covering the wiring layer was formed.
Next, an adhesive tape was applied to the insulating coating layer forming surface, and the base substrate was polished with a diamond grinder to a thickness of 60 μm to expose the vertical conduction via surrounded by the insulating resin layer located in the groove. As a result, a multi-sided electronic component built-in module was obtained.
Next, the insulating resin layer is diced at a central part (a part indicated by an arrow a in FIG. 14B) in which the vertical conduction vias for adjacent LSI chips are arranged in parallel, and each side is 12 mm. A square electronic component built-in module of the present invention was obtained.

［実施例２］
まず、実施例１と同様にして、端子ビアと接続する上下導通ビアが異なる４種の多面付けの電子部品内蔵モジュールを作製した。
次に、同じ位置の上下導通ビアを接続するようにダイマウンターを用いて４種の多面付けの電子部品内蔵モジュールを固着積層した。
次いで、積層状態の多面付けの電子部品内蔵モジュールを、実施例１と同じ位置でダイシングして、一辺が１０ｍｍの正方形の本発明の電子部品内蔵モジュールを得た。 [Example 2]
First, in the same manner as in Example 1, four types of multi-sided electronic component built-in modules having different vertical conduction vias connected to terminal vias were produced.
Next, four types of multi-sided electronic component built-in modules were fixed and laminated using a die mounter so as to connect the vertical conduction vias at the same position.
Next, the multi-sided electronic component built-in module in a laminated state was diced at the same position as in Example 1 to obtain a square electronic component built-in module of the present invention having a side of 10 mm.

小型で高信頼性が要求される半導体装置や各種電子機器への用途にも適用できる。   The present invention can also be applied to small semiconductor devices and various electronic devices that require high reliability.

本発明の電子部品内蔵モジュールの一実施形態を示す平面図である。It is a top view which shows one Embodiment of the electronic component built-in module of this invention. 図１に示される電子部品内蔵モジュールのＡ−Ａ線（二点鎖線）矢視縦断面図である。It is an AA line (two-dot chain line) arrow longitudinal cross-sectional view of the electronic component built-in module shown by FIG. 図１に示される電子部品内蔵モジュールを構成する基板の平面図である。It is a top view of the board | substrate which comprises the electronic component built-in module shown by FIG. 本発明の電子部品内蔵モジュールを構成する基板の他の例を示す平面図である。It is a top view which shows the other example of the board | substrate which comprises the electronic component built-in module of this invention. 本発明の電子部品内蔵モジュールを構成する基板の他の例を示す平面図である。It is a top view which shows the other example of the board | substrate which comprises the electronic component built-in module of this invention. 本発明の電子部品内蔵モジュールを構成する基板の他の例を示す平面図である。It is a top view which shows the other example of the board | substrate which comprises the electronic component built-in module of this invention. 本発明の電子部品内蔵モジュールの他の実施形態を示す図２相当の縦断面図である。It is a longitudinal cross-sectional view equivalent to FIG. 2 which shows other embodiment of the electronic component built-in module of this invention. 本発明の電子部品内蔵モジュールを構成する基板の他の例を示す平面図である。It is a top view which shows the other example of the board | substrate which comprises the electronic component built-in module of this invention. 本発明の電子部品内蔵モジュールの他の実施形態を示す縦断面図である。It is a longitudinal cross-sectional view which shows other embodiment of the electronic component built-in module of this invention. 本発明の電子部品内蔵モジュールの他の実施形態を示す縦断面図である。It is a longitudinal cross-sectional view which shows other embodiment of the electronic component built-in module of this invention. 本発明の電子部品内蔵モジュールの他の実施形態を示す縦断面図である。It is a longitudinal cross-sectional view which shows other embodiment of the electronic component built-in module of this invention. 図１２に示される本発明の電子部品内蔵モジュールを構成する各電子部品内蔵モジュールの平面図である。It is a top view of each electronic component built-in module which comprises the electronic component built-in module of this invention shown by FIG. 本発明の電子部品内蔵モジュールの製造方法の一実施形態を示す工程図である。It is process drawing which shows one Embodiment of the manufacturing method of the electronic component built-in module of this invention. 本発明の電子部品内蔵モジュールの製造方法の一実施形態を示す工程図である。It is process drawing which shows one Embodiment of the manufacturing method of the electronic component built-in module of this invention. 本発明の電子部品内蔵モジュールの製造方法の他の実施形態を示す工程図である。It is process drawing which shows other embodiment of the manufacturing method of the electronic component built-in module of this invention.

符号の説明Explanation of symbols

１…ベース基板
２…溝部
１１，３１，５１…電子部品内蔵モジュール
１２，３２，５２…基板
１３，３３，５３…凹部
１４，３４，５４…空間
１５，３５，５５…端部基板
１６，３６，５６…絶縁樹脂層
１７，３７，５７…上下導通ビア
１８，３８，５８…端子ビア
１９，３９，５９…配線層
２０，４０…絶縁被覆層
２１，４１，６１…電子部品 DESCRIPTION OF SYMBOLS 1 ... Base board 2 ... Groove part 11, 31, 51 ... Electronic component built-in module 12, 32, 52 ... Board | substrate 13, 33, 53 ... Recessed part 14, 34, 54 ... Space 15, 35, 55 ... End board | substrate 16, 36 , 56 ... Insulating resin layer 17, 37, 57 ... Vertical conducting vias 18, 38, 58 ... Terminal vias 19, 39, 59 ... Wiring layers 20, 40 ... Insulating coating layers 21, 41, 61 ... Electronic components

Claims (16)

一方の面に電子部品内蔵用の凹部を備える基板と、該基板の前記凹部に内蔵された電子部品と、前記基板の前記凹部を有する面を被覆するとともに、前記基板の側端面の少なくとも一部を被覆する絶縁樹脂層と、前記基板の側端面を被覆する前記絶縁樹脂層を貫通する複数の上下導通ビアと、前記電子部品の端子部と接続するように前記絶縁樹脂層に配設された端子ビアと、該端子ビアと所望の前記上下導通ビアとを接続するように前記絶縁樹脂層上に配設された配線層とを備え、前記基板は基板の側端面を被覆する前記絶縁樹脂層が存在するための空間を介して端部基板を有することを特徴とする電子部品内蔵モジュール。 A substrate having a recess for incorporating an electronic component on one surface, an electronic component embedded in the recess of the substrate, and a surface of the substrate having the recess, and at least a part of a side end surface of the substrate An insulating resin layer that covers the substrate, a plurality of vertical conductive vias that penetrate the insulating resin layer that covers the side end surfaces of the substrate, and a terminal portion of the electronic component that is disposed on the insulating resin layer. A wiring layer disposed on the insulating resin layer so as to connect the terminal via and the desired vertical conductive via, and the substrate covers the side end face of the substrate. electronic component built-in module according to claim Rukoto but which have a end substrate through a space for existing. 前記上下導通ビアの数は、前記電子部品の端子数以上であることを特徴とする請求項１に記載の電子部品内蔵モジュール。 The electronic component built-in module according to claim 1 , wherein the number of the vertical conduction vias is equal to or greater than the number of terminals of the electronic component. １個の電子部品を内蔵し、前記上下導通ビアは前記電子部品の周囲に配設され、また、前記上下導通ビアを露出し、かつ、前記配線層を被覆した絶縁被覆層を前記絶縁樹脂層上に備えることを特徴とする請求項１または請求項２に記載の電子部品内蔵モジュール。 One electronic component is incorporated, the vertical conduction via is disposed around the electronic component, and the insulating coating layer that exposes the vertical conduction via and covers the wiring layer is provided as the insulating resin layer. The electronic component built-in module according to claim 1 , wherein the electronic component built-in module is provided above. 同じ位置に上下導通ビアを備える請求項１乃至請求項３のいずれかに記載の電子部品内蔵モジュールが電子部品内蔵面を同じ向きにして前記上下導通ビアを接続するように複数個積層されたものであり、各電子部品内蔵モジュールは所望の電子部品を内蔵するものであり、各電子部品内蔵モジュールが有する上下導通ビアの数は、１個の電子部品内蔵モジュールに内蔵される電子部品の端子数より多く、積層された電子部品内蔵モジュールに内蔵される全電子部品の総端子数以下であることを特徴とする電子部品内蔵モジュール。   4. A plurality of electronic component built-in modules according to claim 1, each having a vertical conductive via at the same position, wherein a plurality of layers are stacked so as to connect the vertical conductive vias with the electronic component built-in surface in the same direction. Each electronic component built-in module incorporates a desired electronic component, and the number of vertical conduction vias of each electronic component built-in module is the number of terminals of the electronic component built in one electronic component built-in module. The electronic component built-in module, characterized in that the number is less than the total number of terminals of all the electronic components incorporated in the stacked electronic component built-in module. 最外層に位置する前記電気部品内蔵モジュールの前記配線層が配設されている面に、前記上下導通ビアを露出し、かつ、前記配線層を被覆した絶縁被覆層を備えることを特徴とする請求項４に記載の電子部品内蔵モジュール。 The surface on which the wiring layer of the electrical component built-in module located in the outermost layer is arranged, wherein said upper and lower conductive vias exposed, and characterized in that it comprises an insulating coating layer covering the wiring layer Item 5. The electronic component built-in module according to Item 4 . 前記配線層が配設されている面と反対の面に露出している前記上下導通ビアに、はんだボールが配設されていることを特徴とする請求項１乃至請求項５のいずれかに記載の電子部品内蔵モジュール。 The vertically conducting vias exposed on the opposite surface to the surface on which the wiring layer is arranged, according to any one of claims 1 to 5, characterized in that the solder balls are disposed Module with built-in electronic components. 前記基板は、ＸＹ方向の熱膨張係数が２〜２０ｐｐｍの範囲内であることを特徴とする請求項１乃至請求項６のいずれかに記載の電子部品内蔵モジュール。 The substrate, the electronic component built-in module according to any one of claims 1 to 6 thermal expansion coefficient of the XY direction is being in the range of 2～20Ppm. 前記電子部品は、ＬＳＩチップ、ＩＣチップ、ＬＣＲ回路部品、センサ部品のいずれかであることを特徴とする請求項１乃至請求項７のいずれかに記載の電子部品内蔵モジュール。 The electronic component is, LSI chips, IC chips, LCR circuit component, the electronic component built-in module according to any one of claims 1 to 7, characterized in that either the sensor component. ベース基板の一方の面に電子部品内蔵用の凹部を形成し、該凹部に電子部品を配設する工程と、
前記ベース基板に溝部を形成する工程と、
前記電子部品を被覆し、かつ、前記溝部を充填するように前記ベース基板の一方の面に絶縁樹脂層を形成する工程と、
前記溝部内に位置する上下導通ビア用孔部と前記電子部品の端子が露出する端子ビア用孔部とを、それぞれ前記絶縁樹脂層に形成する工程と、
前記上下導通ビア用孔部と前記端子ビア用孔部とを導電材料で充填して上下導通ビアと端子ビアを形成するとともに、該端子ビアと所望の前記上下導通ビアとを接続するための配線層を形成する工程と、
前記ベース基板の他方の面を研磨して前記溝部内に位置する前記絶縁樹脂層と前記上下導通ビアを露出させる工程と、を有することを特徴とする電子部品内蔵モジュールの製造方法。 Forming a recess for incorporating an electronic component on one surface of the base substrate, and disposing the electronic component in the recess;
Forming a groove in the base substrate;
Forming an insulating resin layer on one surface of the base substrate so as to cover the electronic component and fill the groove;
Forming a hole for a vertical conductive via located in the groove and a hole for a terminal via from which a terminal of the electronic component is exposed in the insulating resin layer, and
The upper and lower conductive via holes and the terminal via hole are filled with a conductive material to form vertical conductive vias and terminal vias, and wiring for connecting the terminal vias to the desired vertical conductive vias Forming a layer;
And a step of polishing the other surface of the base substrate to expose the insulating resin layer located in the groove and the vertical conduction via. 前記ベース基板への前記凹部の形成、前記溝部の形成は、ＩＣＰ−ＲＩＥ法またはサンドブラスト法により行うことを特徴とする請求項９に記載の電子部品内蔵モジュールの製造方法。 The method for manufacturing an electronic component built-in module according to claim 9 , wherein the formation of the concave portion and the formation of the groove portion on the base substrate are performed by an ICP-RIE method or a sandblast method. レーザー加工法による前記絶縁樹脂層の加工により、あるいは、前記絶縁樹脂層を感光性絶縁樹脂層としフォトリソグラフィー法で加工することにより、前記上下導通ビア用孔部と前記端子ビア用孔部を同時に形成することを特徴とする請求項９または請求項１０に記載の電子部品内蔵モジュールの製造方法。 By processing the insulating resin layer by a laser processing method or by processing the insulating resin layer as a photosensitive insulating resin layer by a photolithography method, the vertical conductive via hole and the terminal via hole are simultaneously formed. The method of manufacturing an electronic component built-in module according to claim 9 or 10 , wherein the electronic component built-in module is formed. 多面付けで電子部品内蔵モジュールを形成した後、ダイシングにより個々の電子部品内蔵モジュールを得る工程を有することを特徴とする請求項９乃至請求項１１のいずれかに記載の電子部品内蔵モジュールの製造方法。 After forming the electronic component built-in module with multi with method of manufacturing an electronic component built-in module according to any one of claims 9 to 11, characterized in that it comprises the step of obtaining the individual electronic component built-in module by dicing . 前記上下導通ビアを露出し、かつ、前記配線層を被覆するように前記絶縁樹脂層上に絶縁被覆層を形成する工程を有することを特徴とする請求項９乃至請求項１２のいずれかに記載の電子部品内蔵モジュールの製造方法。 Exposing said upper and lower conductive via, and, according to one of claims 9 to 12 characterized by having a step of forming an insulating cover layer on the insulating resin layer so as to cover the wiring layer Manufacturing method of electronic component built-in module. 同じ位置に上下導通ビアを備える電子部品内蔵モジュールを多面付けで形成した後、多面付け状態の電子部品内蔵モジュールを前記上下導通ビアが接続されるように複数積層して固着し、次いで、ダイシングにより個々の電子部品内蔵モジュールを得る工程を有することを特徴とする請求項９乃至請求項１１のいずれかに記載の電子部品内蔵モジュールの製造方法。 After forming the electronic component built-in module having vertical conduction vias at the same position by multi-sided attachment, a plurality of electronic component built-in modules in a multi-sided state are stacked and fixed so that the vertical conduction vias are connected, and then by dicing method of manufacturing an electronic component built-in module according to any one of claims 9 to 11 characterized by having a step of obtaining individual electronic component built-in module. 最外層に位置する電子部品内蔵モジュールの前記配線層が配設されている面に、前記上下導通ビアを露出し、かつ、前記配線層を被覆するように絶縁被覆層を形成する工程を有することを特徴とする請求項１４に記載の電子部品内蔵モジュールの製造方法。 A step of exposing the vertical conductive via to a surface of the electronic component built-in module located in the outermost layer on which the wiring layer is disposed and forming an insulating coating layer so as to cover the wiring layer; The method for manufacturing an electronic component built-in module according to claim 14 . 多面付けを構成する各電子部品内蔵モジュールが有する上下導通ビアの数を、内蔵される電子部品の端子数より多く、積層される複数個の電子部品内蔵モジュールに内蔵される全電子部品の総端子数以下とすることを特徴とする請求項１４または請求項１５に記載の電子部品内蔵モジュールの製造方法。 The number of vertical conduction vias in each electronic component built-in module constituting the multi-sided layout is larger than the number of terminals of the built-in electronic components, and the total terminals of all the electronic components built in a plurality of stacked electronic component built-in modules 16. The method for manufacturing an electronic component built-in module according to claim 14 or 15 , wherein the number is less than or equal to several.
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