JP4369728B2 - Manufacturing method of electronic device - Google Patents

Manufacturing method of electronic device Download PDF

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JP4369728B2
JP4369728B2 JP2003382110A JP2003382110A JP4369728B2 JP 4369728 B2 JP4369728 B2 JP 4369728B2 JP 2003382110 A JP2003382110 A JP 2003382110A JP 2003382110 A JP2003382110 A JP 2003382110A JP 4369728 B2 JP4369728 B2 JP 4369728B2
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layer
electronic component
wiring
conductive
electronic device
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JP2005150185A (en
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悟 倉持
義孝 福岡
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Dai Nippon Printing Co Ltd
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Description

本発明は、電子装置、特にＬＳＩチップ等の電子部品を内蔵するとともに放熱用のヒートシンクを備えた電子装置に関する。   The present invention relates to an electronic device, and more particularly to an electronic device that incorporates an electronic component such as an LSI chip and includes a heat sink for heat dissipation.

従来の多層配線基板は、例えば、サブトラクティブ法等で作製した低密度配線を有する両面基板をコア基板とし、このコア基板の両面にビルドアップ法により高密度配線を形成して作製されたものである。また、最近では、ＬＳＩチップ等を多層配線基板上に直接実装するベアチップ実装法が提案されている。ベアチップ実装法では、予め多層配線基板上に形成された配線の接続パッド部に、ボンディング・ワイヤ、ハンダや金属球等からなるバンプ、異方性導電膜、導電性接着剤、光収縮性樹脂等の接続手段を用いて半導体チップが実装される。そして、作製する半導体装置にキャパシターやインダクター等のＬＣＲ回路部品が必要な場合は、半導体チップと同様に、多層配線基板に外付けで実装されている。   A conventional multilayer wiring board is produced by, for example, using a double-sided board having low-density wiring produced by a subtractive method or the like as a core board, and forming high-density wiring on both sides of the core board by a build-up method. is there. Recently, a bare chip mounting method in which an LSI chip or the like is directly mounted on a multilayer wiring board has been proposed. In the bare chip mounting method, bonding wires, bumps made of solder, metal balls, etc., anisotropic conductive films, conductive adhesives, light-shrinkable resins, etc., are formed on wiring connection pads formed on a multilayer wiring board in advance. A semiconductor chip is mounted using the connecting means. When a semiconductor device to be manufactured requires an LCR circuit component such as a capacitor or an inductor, it is externally mounted on a multilayer wiring board, like a semiconductor chip.

しかし、多層配線基板上に形成された配線の接続パッド部は、半導体チップ等の電子部品の実装部位とは別の部位に設けられるため、多層配線基板の面方向の広がりが必要であった。このため、電子装置の小型化には限界があり、実装される電子部品の数が増えるにしたがって、電子装置の小型化は更に困難となる傾向にあった。
これに対応するために、半導体チップを実装した薄い基板と、上下導通ビアを備えた穴明きの枠基板を、それぞれ複数個作製しておき、電子装置の作製時に、この実装基板と枠基板とを１つのモジュールとして一括で積層することにより、面方向の広がりを抑えて小型化された電子装置が開発されている。
しかし、上述のような電子装置の小型、高密度化や、実装される電子部品数の増大にしたがって、電子装置の発熱による温度上昇が重要な問題となる。そこで、動作時の電子部品の温度を所定の温度以下に保つために、ヒートシンクを備えた電子装置が開発されている（特許文献１）。
特開平５−２１６６５号公報 However, since the connection pad portion of the wiring formed on the multilayer wiring board is provided in a part different from the mounting part of the electronic component such as a semiconductor chip, it is necessary to expand the surface direction of the multilayer wiring board. For this reason, there is a limit to the miniaturization of the electronic device, and the miniaturization of the electronic device tends to become more difficult as the number of electronic components to be mounted increases.
In order to cope with this, a plurality of thin substrates on which semiconductor chips are mounted and a perforated frame substrate having vertical conduction vias are prepared, and when mounting an electronic device, the mounting substrate and the frame substrate are prepared. Have been developed as a single module, and an electronic device that has been reduced in size while suppressing the spread in the surface direction has been developed.
However, an increase in temperature due to heat generation of the electronic device becomes an important issue as the electronic device is reduced in size and density and the number of electronic components to be mounted is increased. Therefore, in order to keep the temperature of the electronic component during operation at a predetermined temperature or lower, an electronic device including a heat sink has been developed (Patent Document 1).
JP-A-5-21665

しかしながら、上記のヒートシンクは耐熱性接着剤を用いて電子装置に固着されるものであり、耐熱性接着剤によるヒートシンクへの熱伝導の阻害が生じ、ヒートシンクによる放熱効果が充分に得られないという問題があった。また、熱履歴によりヒートシンクの脱落等が生じるとういう問題があった。さらに、一般のマルチチップモジュール(ＭＣＭ)では、裏面にヒートシンクを取り付けると、入出力端子の形成部位が表面のチップ実装面の周辺に限定されるため、多ピン化および小型化の対応に限界があった。
本発明は、上記のような実情に鑑みてなされたものであり、電子部品を内蔵し小型化、高密度化が可能で、信頼性の高い多層構造の電子装置を提供することを目的とする。 However, the above heat sink is fixed to an electronic device using a heat-resistant adhesive, and heat conduction to the heat sink is hindered by the heat-resistant adhesive, and the heat dissipation effect by the heat sink cannot be obtained sufficiently. was there. Further, there has been a problem that the heat sink may fall off due to the thermal history. Furthermore, in a general multichip module (MCM), if a heat sink is attached to the back surface, the I / O terminal formation area is limited to the periphery of the chip mounting surface on the front surface, so there is a limit to the support for increasing the number of pins and miniaturization. there were.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly reliable electronic device having a built-in electronic component that can be reduced in size and increased in density and has high reliability. .

このような目的を達成するために、本発明は、熱伝導性基材の一方の面に複数のフィンを備えるヒートシンクと、前記熱伝導性基材の他方の面に形成された多層配線部とを備えた電子装置の製造方法において、電子部品を内蔵するとともに上下導通ビアポストを備えた電子部品内蔵層と、配線層と、電気絶縁層とを所望の積層順序で有し、前記電気絶縁層に設けた上下導通ビアにて前記配線層、前記電子部品内蔵層の電子部品、上下導通ビアポストとの所望の導通がなされており、かつ、前記多層配線部の表面に入出力端子を備える多層配線部を、ビルドアップ法で熱伝導性基材の一方の面に形成する工程と、前記熱伝導性基材の他方の面に複数のフィンを形成してヒートシンクとする工程と、を有するような構成とした。 In order to achieve such an object, the present invention provides a heat sink having a plurality of fins on one surface of a thermally conductive substrate, and a multilayer wiring portion formed on the other surface of the thermally conductive substrate. In an electronic device manufacturing method comprising: an electronic component built-in layer including an electronic component and a vertical conductive via post; a wiring layer; and an electrical insulating layer in a desired stacking order; A multilayer wiring portion in which desired conduction with the wiring layer, the electronic component in the electronic component built-in layer, and the vertical conduction via post is provided by the provided vertical conduction via and an input / output terminal is provided on the surface of the multilayer wiring portion And a step of forming a plurality of fins on the other surface of the thermally conductive substrate to form a heat sink by a build-up method. It was.

本発明の好ましい態様として、電子部品を内蔵するための切欠き部と、上下導通ビアポストを備えた絶縁樹脂層を下層の上に直接形成し、前記切欠き部に電子部品を内蔵させることにより、前記電子部品内蔵層を形成するような構成、あるいは、下層の上に電子部品を載置した後、該電子部品を内蔵するように前記下層の上に上下導通ビアポストを備えた絶縁樹脂層を直接形成することにより、前記電子部品内蔵層を形成するような構成とした。 As a preferred embodiment of the present invention, by forming a notch portion for incorporating an electronic component and an insulating resin layer having a vertical conductive via post directly on the lower layer, and incorporating the electronic component in the notch portion, The structure in which the electronic component built-in layer is formed, or after the electronic component is placed on the lower layer, an insulating resin layer having a vertical conductive via post is directly formed on the lower layer so as to incorporate the electronic component. By forming, it was set as the structure which forms the said electronic component built-in layer.

本発明の好ましい態様として、前記熱伝導性基材として、前記多層配線部との接合面内方向の熱膨張係数が２〜２０ｐｐｍの範囲内である材料を使用するような構成とした。
本発明の好ましい態様として、多層配線部の前記入出力端子上に外部電極部材を形成する工程を有するような構成とした。
本発明の好ましい態様として、前記電子部品として、ＬＳＩチップ、ＩＣチップ、ＬＣＲ電子部品、センサ部品のいずれか１種または２種以上を使用するような構成とした。 As a preferable aspect of the present invention , a material having a thermal expansion coefficient in the range of 2 to 20 ppm in the in-bonding direction with the multilayer wiring portion is used as the thermally conductive base material.
As a preferable aspect of the present invention, a configuration including a step of forming an external electrode member on the input / output terminal of the multilayer wiring portion is adopted.
As a preferred aspect of the present invention, the electronic component is configured to use any one or more of LSI chip, IC chip, LCR electronic component, and sensor component .

本発明の電子装置は、多層配線部に接着剤層を介することなくヒートシンクを一体的に備えるので、多層配線部、特に電子部品内蔵層における発熱がヒートシンクから高い効率で放熱され、チップジャンクション温度を低く抑えることが可能となり、信頼性が高いものであるとともに、ヒートシンクを接着するための耐熱性の高い接着剤を選択して使用する必要がなく、製造が容易であり、さらに、ヒートシンクを一体的に備えた反対面側に、全面格子状に入出力端子を形成することができ多ピン化が可能であるとともに、更なる小型化が可能であるという効果が奏される。   Since the electronic device of the present invention is integrally provided with a heat sink without interposing an adhesive layer in the multilayer wiring portion, heat generated in the multilayer wiring portion, particularly in the electronic component built-in layer, is dissipated from the heat sink with high efficiency, and the chip junction temperature is increased. It is possible to keep it low, it is highly reliable, it is not necessary to select and use a heat-resistant adhesive for bonding the heat sink, it is easy to manufacture, and the heat sink is integrated The input / output terminals can be formed in the form of a full-grid on the opposite surface provided for the above-described structure, enabling an increase in the number of pins and a further reduction in size.

以下、本発明の実施の形態について図面を参照して説明する。
［第１の実施形態］
図１は、本発明の電子装置の一実施形態を示す概略縦断面図である。図１において、本発明の電子装置１は、熱伝導性基材２′の一方の面に複数のフィン３を備えるヒートシンク２と、熱伝導性基材２′の他方の面に形成された多層配線部４とを備えたものである。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a schematic longitudinal sectional view showing an embodiment of an electronic device of the present invention. Referring to FIG. 1, an electronic device 1 according to the present invention includes a heat sink 2 having a plurality of fins 3 on one surface of a heat conductive substrate 2 ', and a multilayer formed on the other surface of the heat conductive substrate 2'. The wiring part 4 is provided.

ヒートシンク２は、熱伝導性基材２′の一方の面２′ａ（多層配線部４が形成されている面２′ｂの反対面）に複数のフィン３が設けられている。このフィン３の形状は板形状、ピン形状等、何れであってもよく、フィンの寸法、個数は、適宜設定することができる。このヒートシンク２を構成する熱伝導性基材２′は、熱伝導性に優れ、かつ、機械研削が容易な材質あれば特に制限はなく、例えば、シリコンや、Ａｌ、Ｃｕ、ＳＵＳ、Ｆｅ−Ｎｉ４２合金、Ｃｕ−Ｗ合金等の金属、ＡｌＮ、ＳｉＣ等の材料からなるものであってよい。特に、後述する電子部品内蔵層５Ａ、５Ｂに内蔵される電子部品８との熱応力歪を考慮して、熱伝導性基材２′のＸＹ方向（熱伝導性基材２′の面２′ｂに平行な平面）の熱膨張係数が２〜２０ｐｐｍ、好ましくは２．５〜１７ｐｐｍの範囲内である材料からなることが望ましい。ここで、本発明では、熱膨張係数はＴＭＡ（サーマルメカニカルアナリシス）により測定するものである。   The heat sink 2 is provided with a plurality of fins 3 on one surface 2'a (the surface opposite to the surface 2'b on which the multilayer wiring portion 4 is formed) of the heat conductive substrate 2 '. The shape of the fin 3 may be any of a plate shape, a pin shape, and the like, and the size and number of fins can be set as appropriate. The heat conductive base material 2 'constituting the heat sink 2 is not particularly limited as long as it is a material excellent in heat conductivity and easy to mechanically grind. For example, silicon, Al, Cu, SUS, Fe-Ni42 It may be made of a metal such as an alloy or a Cu-W alloy, or a material such as AlN or SiC. In particular, in consideration of thermal stress strain with the electronic component 8 incorporated in the electronic component built-in layers 5A and 5B described later, the XY direction of the thermally conductive substrate 2 ′ (the surface 2 ′ of the thermally conductive substrate 2 ′). It is desirable to be made of a material having a coefficient of thermal expansion of 2 to 20 ppm, preferably 2.5 to 17 ppm. Here, in the present invention, the thermal expansion coefficient is measured by TMA (thermal mechanical analysis).

尚、熱伝導性基材２′が導電性を有する金属材料からなる場合、ヒートシンク２と多層配線部４との接合面に絶縁層を介在させる。この場合の絶縁層としては、例えば、金属材料の陽極酸化膜等が好ましい。
多層配線部４は、電子部品を内蔵するとともに上下導通ビアポストを備えた電子部品内蔵層と、配線層と、電気絶縁層とを所望の積層順序で有している。図示例では、多層配線部４は、２層の電子部品内蔵層５Ａ、５Ｂを有している。すなわち、熱伝導性基材２′の一方の面２′ｂに配設された１層目の配線層１０ａ上に電子部品内蔵層５Ａを備えている。この電子部品内蔵層５Ａは、絶縁樹脂層６と、この絶縁樹脂層６に設けられた切欠き部６ａに内蔵された電子部品８と、上下導通ビアポスト７を有している。尚、図示例では、説明を容易にするために、配線層１０ａ、上下導通ビアポスト７や電子部品８の個数、後述する配線層や電気絶縁層の数は簡略化して示している。 When the heat conductive substrate 2 ′ is made of a conductive metal material, an insulating layer is interposed between the heat sink 2 and the multilayer wiring portion 4. As the insulating layer in this case, for example, an anodic oxide film of a metal material is preferable.
The multilayer wiring part 4 has an electronic component built-in layer including an electronic component and a vertical conductive via post, a wiring layer, and an electrical insulating layer in a desired stacking order. In the illustrated example, the multilayer wiring part 4 includes two layers of electronic component built-in layers 5A and 5B. That is, the electronic component built-in layer 5A is provided on the first wiring layer 10a disposed on the one surface 2'b of the heat conductive substrate 2 '. The electronic component built-in layer 5 </ b> A includes an insulating resin layer 6, an electronic component 8 built in a notch 6 a provided in the insulating resin layer 6, and a vertical conductive via post 7. In the illustrated example, for ease of explanation, the number of wiring layers 10a, vertical conductive via posts 7 and electronic components 8, and the number of wiring layers and electrical insulating layers described later are simplified.

電子部品内蔵層５Ａは、電子部品８を内蔵するための切欠き部６ａと上下導通ビアポスト７を備えた絶縁樹脂層６を、配線層１０ａを備えたヒートシンク２上に直接形成し、切欠き部６ａに電子部品８を内蔵させて形成したものである。そして、上下導通ビアポスト７は、それぞれ対応する所定の配線層１０ａに接続されている。尚、電子部品８としては、ＬＳＩチップ、ＩＣチップ、ＬＣＲ電子部品、センサ部品のいずれか１種または２種以上とすることができ、また、複数個の電子部品８を内蔵してもよい。   The electronic component built-in layer 5A is formed by directly forming an insulating resin layer 6 having a notch portion 6a for embedding the electronic component 8 and a vertical conduction via post 7 on the heat sink 2 having the wiring layer 10a. The electronic component 8 is built in 6a. The vertical conduction via posts 7 are respectively connected to the corresponding predetermined wiring layers 10a. The electronic component 8 may be one or more of LSI chip, IC chip, LCR electronic component, and sensor component, and a plurality of electronic components 8 may be incorporated.

上記の電子部品内蔵層５Ａの上には、１層目の電気絶縁層９ａを介し上下導通ビア７ａにて電子部品内蔵層５Ａの上下導通ビアポスト７や電子部品８の端子部８ａに接続されるように形成された２層目の配線層１０ｂと、この２層目の配線層１０ｂ上に２層目の電気絶縁層９ｂを介し上下導通ビア７ｂにて所定の２層目配線層１０ｂに接続されるように形成された３層目の配線層１０ｃとが形成されている。尚、配線層は必要に応じて更に多層にしてもよい。
上記の配線層１０ｃ上には、電子部品内蔵層５Ｂが形成されている。この電子部品内蔵層５Ｂも、電子部品内蔵層５Ａと同様に、絶縁樹脂層６と、この絶縁樹脂層６に設けられた切欠き部６ａに内蔵された電子部品８と、上下導通ビアポスト７を有している。 On the electronic component built-in layer 5A, the vertical conductive via 7a is connected to the vertical conductive via post 7 of the electronic component built-in layer 5A and the terminal portion 8a of the electronic component 8 through the first electrical insulating layer 9a. The second wiring layer 10b formed as described above, and the second wiring layer 10b is connected to the predetermined second wiring layer 10b through the second electrical insulating layer 9b through the vertical conduction via 7b. A third wiring layer 10c formed as described above is formed. The wiring layer may be further multilayered as necessary.
An electronic component built-in layer 5B is formed on the wiring layer 10c. Similarly to the electronic component built-in layer 5A, the electronic component built-in layer 5B includes an insulating resin layer 6, an electronic component 8 built in a notch 6a provided in the insulating resin layer 6, and a vertical conductive via post 7. Have.

電子部品内蔵層５Ｂは、電子部品８を内蔵するための切欠き部６ａと上下導通ビアポスト７を備えた絶縁樹脂層６を３層目の配線層１０ｃ上に直接形成し、切欠き部６ａに電子部品８を内蔵させて形成したものである。そして、上下導通ビアポスト７は、それぞれ所定の３層目の配線層１０ｃに接続されている。電子部品８は、ＬＳＩチップ、ＩＣチップ、ＬＣＲ電子部品、センサ部品のいずれか１種または２種以上とすることができ、また、複数個の電子部品８を内蔵してもよく、電子部品内蔵層５Ａに内蔵される電子部品８と別種のものであってもよい。   The electronic component built-in layer 5B is formed by directly forming a notch portion 6a for embedding the electronic component 8 and an insulating resin layer 6 provided with the vertical conduction via post 7 on the third wiring layer 10c. The electronic component 8 is built in and formed. The vertical conduction via posts 7 are each connected to a predetermined third wiring layer 10c. The electronic component 8 may be any one or more of LSI chip, IC chip, LCR electronic component, and sensor component, and may include a plurality of electronic components 8 or a built-in electronic component. It may be a different type from the electronic component 8 incorporated in the layer 5A.

電子部品内蔵層５Ｂの上には、３層目の電気絶縁層９ｃを介し上下導通ビア７ｃにて電子部品内蔵層５Ｂの上下導通ビアポスト７や電子部品８の端子部８ａに接続されるように形成された４層目の配線層１０ｄが形成されている。この４層目の配線層１０ｄ上に４層目の電気絶縁層９ｄを介し上下導通ビア７ｄにて所定の４層目配線層１０ｄに接続されるように形成された５層目の配線層１０ｅが形成されている。多層配線部４の表面に位置する５層目の配線層１０ｅは入出力端子を有する配線層である。尚、配線層は必要に応じて更に多層にしてもよい。
そして、５層目の配線層（入出力端子）１０ｅには、はんだボール等の外部電極部材（図示例では２点鎖線で示している）が設けられている。 On the electronic component built-in layer 5B, the vertical conductive via 7c is connected to the vertical conductive via post 7 of the electronic component built-in layer 5B and the terminal portion 8a of the electronic component 8 through the third electrical insulating layer 9c. The formed fourth wiring layer 10d is formed. On the fourth wiring layer 10d, a fifth wiring layer 10e is formed so as to be connected to a predetermined fourth wiring layer 10d by a vertical conductive via 7d via a fourth electric insulating layer 9d. Is formed. The fifth wiring layer 10e located on the surface of the multilayer wiring portion 4 is a wiring layer having input / output terminals. The wiring layer may be further multilayered as necessary.
The fifth wiring layer (input / output terminal) 10e is provided with an external electrode member such as a solder ball (indicated by a two-dot chain line in the illustrated example).

上述のような本発明の電子装置１では、電子部品内蔵層５Ａ，５Ｂを積層して備えるので、外付けで電子部品を実装する場合に比べて、小型化が可能となる。また、ヒートシンク２を多層配線部４に一体的に備えるので、多層配線部４の特に電子部品内蔵層５Ａ，５Ｂにおいて発生した熱がヒートシンク２のフィン３から高い効率で放熱され、チップジャンクション温度を低く抑えることが可能となり、信頼性が高い（故障率が低い）ものである。さらに、ヒートシンク２と多層配線部４との間に接着剤層が不要であり、耐熱性の高い接着剤を選択して使用する必要がなく、製造が容易なものとなる。また、ヒートシンク２を一体的に備えた反対面側の全面に、はんだボール等の外部電極部材を格子状に形成することができ、多ピン化が可能であるとともに、更なる小型化が可能である。   In the electronic device 1 of the present invention as described above, the electronic component built-in layers 5A and 5B are provided so as to be reduced in size as compared with the case where electronic components are mounted externally. In addition, since the heat sink 2 is integrally provided in the multilayer wiring part 4, heat generated in the multilayer wiring part 4, particularly in the electronic component built-in layers 5A and 5B, is dissipated with high efficiency from the fins 3 of the heat sink 2, and the chip junction temperature is increased. It can be kept low and has high reliability (low failure rate). Furthermore, an adhesive layer is not required between the heat sink 2 and the multilayer wiring part 4, and it is not necessary to select and use an adhesive having high heat resistance, which facilitates manufacture. In addition, external electrode members such as solder balls can be formed in a lattice pattern on the entire surface on the opposite surface side integrally provided with the heat sink 2, which can increase the number of pins and further reduce the size. is there.

電子部品内蔵層５Ａ，５Ｂを構成する絶縁樹脂層６の材質は、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の有機絶縁性材料、これらの有機材料とガラス繊維等を組み合わせたもの等することができる。電子部品内蔵層５Ａ，５Ｂを構成する上下導通ビアポスト７の材質、上下導通ビア７ａ，７ｂ，７ｃ、７ｄの材質、配線層１０ａ，１０ｂ，１０ｃ，１０ｄ，１０ｅの材質は、銅、銀、金、クロム、アルミニウム等の導電材料とすることができる。
また、電気絶縁層９ａ，９ｂ，９ｃ，９ｄの材質は、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の絶縁材料とすることができる。 The material of the insulating resin layer 6 constituting the electronic component built-in layers 5A and 5B is an organic insulating material such as epoxy resin, benzocyclobutene resin, cardo resin or polyimide resin, or a combination of these organic materials and glass fiber. And so on. The materials of the vertical conduction via posts 7 constituting the electronic component built-in layers 5A, 5B, the materials of the vertical conduction vias 7a, 7b, 7c, 7d, and the materials of the wiring layers 10a, 10b, 10c, 10d, 10e are copper, silver, gold Further, a conductive material such as chromium or aluminum can be used.
The material of the electrical insulating layers 9a, 9b, 9c, and 9d can be an insulating material such as epoxy resin, benzocyclobutene resin, cardo resin, or polyimide resin.

本発明では、熱伝導性基材２′として、多層配線部４を形成する面（２′ｂ）に電子部品を内蔵したものを使用してもよい。このような熱伝導性基材２′への電子部品の内蔵は、熱伝導性基材２′にドリルによるザグリ加工やサンドブラスト加工等により凹部を形成し、この凹部に電子部品を嵌着することができる。この場合の電子部品も、ＬＳＩチップ、ＩＣチップ、ＬＣＲ電子部品、センサ部品のいずれか１種または２種以上とすることができ、また、複数個の電子部品を内蔵してもよい。
また、本発明の電子装置は、上述の実施例における１層目の配線層１０ａを備えないものであってもよい。 In the present invention, as the thermally conductive base material 2 ', one having an electronic component built in the surface (2'b) on which the multilayer wiring portion 4 is formed may be used. Electronic components are incorporated into such a heat conductive base material 2 'by forming a recess in the heat conductive base material 2' by counterboring or sandblasting with a drill, and fitting the electronic component into the recess. Can do. In this case, the electronic component may be any one or more of LSI chip, IC chip, LCR electronic component, and sensor component, and a plurality of electronic components may be incorporated.
The electronic device of the present invention may not include the first wiring layer 10a in the above-described embodiment.

［第２の実施形態］
図２は、本発明の電子装置の他の実施形態を示す概略縦断面図である。図２において、
本発明の電子装置１１は、熱伝導性基材１２′の一方の面に複数のフィン１３を備えるヒートシンク１２と、熱伝導性基材１２′の他方の面に形成された多層配線部１４とを備えている。
ヒートシンク１２は、熱伝導性基材１２′の一方の面１２′ａ（多層配線部１４が形成されている面１２′ｂの反対面）に複数のフィン１３が設けられている。この熱伝導性基材１２′、ヒートシンク１２は、上述の熱伝導性基材２′、ヒートシンク２と同様とすることができ、ここでの説明は省略する。 [Second Embodiment]
FIG. 2 is a schematic longitudinal sectional view showing another embodiment of the electronic device of the present invention. In FIG.
The electronic device 11 of the present invention includes a heat sink 12 having a plurality of fins 13 on one surface of a thermally conductive base material 12 ′, a multilayer wiring portion 14 formed on the other surface of the thermally conductive base material 12 ′, and It has.
The heat sink 12 is provided with a plurality of fins 13 on one surface 12'a (the surface opposite to the surface 12'b on which the multilayer wiring portion 14 is formed) of the heat conductive substrate 12 '. The heat conductive substrate 12 ′ and the heat sink 12 can be the same as the above-described heat conductive substrate 2 ′ and the heat sink 2, and the description thereof is omitted here.

ヒートシンク１２を構成する熱伝導性基材１２′の一方の面１２′ｂ上には、１層目の配線層２０ａと、この１層目の配線層２０ａ上に１層目の電気絶縁層１９ａを介し上下導通ビア１７ａにて所定の１層目配線層２０ａに接続されるように形成された２層目の配線層２０ｂが形成されている。尚、配線層は必要に応じて更に多層にしてもよい。
上記の２層目の配線層２０ｂ上には、電子部品内蔵層１５Ａが形成されている。この電子部品内蔵層１５Ａは、絶縁樹脂層１６と、この絶縁樹脂層１６に内蔵された電子部品１８と、上下導通ビアポスト１７を有している。尚、図示例では、説明を容易にするために、上下導通ビアポスト１７や電子部品１８の個数、配線層や電気絶縁層の数は簡略化して示している。 A first wiring layer 20a is formed on one surface 12'b of the heat conductive substrate 12 'constituting the heat sink 12, and a first electric insulating layer 19a is formed on the first wiring layer 20a. A second wiring layer 20b is formed so as to be connected to a predetermined first wiring layer 20a through vertical conduction vias 17a. The wiring layer may be further multilayered as necessary.
An electronic component built-in layer 15A is formed on the second wiring layer 20b. The electronic component built-in layer 15 </ b> A includes an insulating resin layer 16, an electronic component 18 built in the insulating resin layer 16, and a vertical conductive via post 17. In the illustrated example, the number of vertical conductive via posts 17 and electronic components 18, the number of wiring layers and electrical insulating layers are simplified for easy explanation.

電子部品内蔵層１５Ａは、下層である１層目の電気絶縁層１９ａ上に電子部品１８を載置し、この電子部品１８を内蔵するように電気絶縁層１９ａ上に、上下導通ビアポスト１７を備えた絶縁樹脂層１６を直接形成することにより設けた層である。そして、上下導通ビアポスト１７は、それぞれ対応する所定の２層目配線層２０ｂに接続されている。尚、電子部品１８としては、ＬＳＩチップ、ＩＣチップ、ＬＣＲ電子部品、センサ部品のいずれか１種または２種以上とすることができ、また、複数個の電子部品１８を内蔵してもよい。
上記の電子部品内蔵層１５Ａの上には、２層目の電気絶縁層１９ｂを介し上下導通ビア１７ｂにて電子部品内蔵層１５Ａの上下導通ビアポスト１７や電子部品１８の端子部１８ａに接続されるように形成された３層目の配線層２０ｃと、この３層目の配線層２０ｃ上に３層目の電気絶縁層１９ｃを介し上下導通ビア１７ｃにて所定の３層目配線層２０ｃに接続されるように形成された４層目の配線層２０ｄとが形成されている。尚、配線層は必要に応じて更に多層にしてもよい。 The electronic component built-in layer 15A includes an electronic component 18 placed on the first electrical insulating layer 19a, which is a lower layer, and a vertical conductive via post 17 is provided on the electrical insulating layer 19a so as to incorporate the electronic component 18. This is a layer provided by directly forming the insulating resin layer 16. The vertical conductive via posts 17 are connected to the corresponding second-layer wiring layers 20b. The electronic component 18 may be any one or more of LSI chip, IC chip, LCR electronic component, and sensor component, and a plurality of electronic components 18 may be incorporated.
On the electronic component built-in layer 15A, the vertical conductive via 17b is connected to the vertical conductive via post 17 of the electronic component built-in layer 15A and the terminal portion 18a of the electronic component 18 via the second electrical insulating layer 19b. The third wiring layer 20c formed as described above, and the third wiring layer 20c is connected to the predetermined third wiring layer 20c through the third electrical insulating layer 19c via the vertical conductive via 17c. A fourth wiring layer 20d formed as described above is formed. The wiring layer may be further multilayered as necessary.

上記の配線層２０ｄ上には、電子部品内蔵層１５Ｂが形成されている。この電子部品内蔵層１５Ｂも、電子部品内蔵層１５Ａと同様に、絶縁樹脂層１６と、この絶縁樹脂層１６に内蔵された電子部品１８と、上下導通ビアポスト１７を有している。
電子部品内蔵層１５Ｂは、下層である３層目の電気絶縁層１９ｃ上に電子部品１８を載置し、この電子部品１８を内蔵するように電気絶縁層１９ｃ上に、上下導通ビアポスト１７を備えた絶縁樹脂層１６を直接形成することにより設けた層である。そして、上下導通ビアポスト１７は、それぞれ所定の４層目の配線層２０ｄに接続されている。電子部品１８は、ＬＳＩチップ、ＩＣチップ、ＬＣＲ電子部品、センサ部品のいずれか１種または２種以上とすることができ、また、複数個の電子部品１８を内蔵してもよく、電子部品内蔵層１５Ａに内蔵される電子部品１８と別種のものであってもよい。 An electronic component built-in layer 15B is formed on the wiring layer 20d. Similarly to the electronic component built-in layer 15A, the electronic component built-in layer 15B also includes an insulating resin layer 16, an electronic component 18 built in the insulating resin layer 16, and a vertical conductive via post 17.
The electronic component built-in layer 15B includes an electronic component 18 placed on the third electrical insulating layer 19c, which is a lower layer, and a vertical conductive via post 17 is provided on the electrical insulating layer 19c so as to incorporate the electronic component 18. This is a layer provided by directly forming the insulating resin layer 16. The vertical conduction via posts 17 are each connected to a predetermined fourth wiring layer 20d. The electronic component 18 may be any one or more of LSI chip, IC chip, LCR electronic component, and sensor component, and may include a plurality of electronic components 18 or a built-in electronic component. It may be different from the electronic component 18 built in the layer 15A.

上記の電子部品内蔵層１５Ｂの上には、４層目の電気絶縁層１９ｄを介し上下導通ビア１７ｄにて電子部品内蔵層１５Ｂの上下導通ビアポスト１７や電子部品１８の端子部１８ａに接続されるように形成された５層目の配線層２０ｅが形成されている。この多層配線部１４の表面に位置する５層目の配線層２０ｅは入出力端子を有する配線層である。尚、更に多層の配線層、電気絶縁層を介して入出力端子を形成してもよい。
上記の５層目の配線層（入出力端子）２０ｅには、はんだボール等の外部電極部材（図示例では２点鎖線で示している）が設けられている。 On the electronic component built-in layer 15B, a vertical conductive via 17d is connected to the vertical conductive via post 17 of the electronic component built-in layer 15B and the terminal portion 18a of the electronic component 18 via the fourth electrical insulating layer 19d. A fifth wiring layer 20e formed as described above is formed. The fifth wiring layer 20e located on the surface of the multilayer wiring portion 14 is a wiring layer having input / output terminals. Further, the input / output terminals may be formed through a multilayer wiring layer and an electrical insulating layer.
The fifth wiring layer (input / output terminal) 20e is provided with an external electrode member such as a solder ball (indicated by a two-dot chain line in the illustrated example).

上述のような本発明の電子装置１１では、電子部品内蔵層１５Ａ，１５Ｂを積層して備えるので、外付けで電子部品を実装する場合に比べて、小型化が可能となる。また、ヒートシンク１２を多層配線部１４に一体的に備えるので、多層配線部１４の特に電子部品内蔵層１５Ａ，１５Ｂにおいて発生した熱がヒートシンク１２のフィン１３から高い効率で放熱され、チップジャンクション温度を低く抑えることが可能となり、信頼性が高い（故障率が低い）ものである。さらに、ヒートシンク１２と多層配線部１４との間に接着剤層を介在させる必要がないので、耐熱性の高い接着剤を選択して使用する必要がなく、製造が容易なものとなる。また、ヒートシンク１２を一体的に備えた反対面側の全面に、はんだボール等の外部電極部材を格子状に形成することができ、多ピン化が可能であるとともに、更なる小型化が可能である。   In the electronic device 11 of the present invention as described above, the electronic component built-in layers 15A and 15B are provided so as to be reduced in size as compared with the case where electronic components are mounted externally. In addition, since the heat sink 12 is integrally provided in the multilayer wiring portion 14, heat generated in the electronic component built-in layers 15A and 15B of the multilayer wiring portion 14 is radiated from the fins 13 of the heat sink 12 with high efficiency, and the chip junction temperature is increased. It can be kept low and has high reliability (low failure rate). Furthermore, since it is not necessary to interpose an adhesive layer between the heat sink 12 and the multilayer wiring part 14, it is not necessary to select and use an adhesive having high heat resistance, and the manufacturing becomes easy. Further, an external electrode member such as a solder ball can be formed in a lattice shape on the entire surface on the opposite surface side integrally provided with the heat sink 12, so that it is possible to increase the number of pins and further reduce the size. is there.

上記の電子部品内蔵層１５Ａ，１５Ｂを構成する絶縁樹脂層１６の材質は、上述の第１の実施形態の電子部品内蔵層５Ａ，５Ｂを構成する絶縁樹脂層６と同様とすることができる。また、電子部品内蔵層１５Ａ，１５Ｂを構成する上下導通ビアポスト１７の材質、上下導通ビア１７ａ，１７ｂ，１７ｃ，１７ｄの材質、配線層２０ａ，２０ｂ，２０ｃ，２０ｄ，２０ｅの材質は、上述の第１の実施形態の上下導通ビア、配線層と同様とすることができる。また、電気絶縁層１９ａ，１９ｂ，１９ｃ，１９ｄの材質は、上述の第１の実施形態の電気絶縁層と同様とすることができる。   The material of the insulating resin layer 16 constituting the electronic component built-in layers 15A and 15B can be the same as that of the insulating resin layer 6 constituting the electronic component built-in layers 5A and 5B of the first embodiment. The material of the vertical conductive via posts 17 constituting the electronic component built-in layers 15A and 15B, the material of the vertical conductive vias 17a, 17b, 17c, and 17d, and the material of the wiring layers 20a, 20b, 20c, 20d, and 20e are as described above. This can be the same as the vertical conduction via and the wiring layer of the first embodiment. The material of the electrical insulating layers 19a, 19b, 19c, 19d can be the same as that of the electrical insulating layer of the first embodiment described above.

本実施形態でも、熱伝導性基材１２′として、多層配線部１４形成面（１２′ｂ）側に電子部品を内蔵したものを使用することができる。
また、ヒートシンク１２と電子部品内蔵層１５Ａとの間に配線層、電気絶縁層の層数は図示例に限定されるものではなく、配線層、電気絶縁層を備えないものであってもよい。
本発明の電子装置は、上述の第１および第２の実施形態に示されるものに限定されるものではなく、形成する配線層、電気絶縁層、および、電子部品内蔵層の積層数等には制限はない。また、上述の電子部品内蔵層に代えて、電子部品を実装した薄い基板と、上下導通ビアを備えた穴明きの枠基板とを１つのモジュールとして一括で積層して電子部品内蔵層とした層を備えるものであってもよい。 Also in this embodiment, as the thermally conductive base material 12 ′, a substrate having an electronic component built in the multilayer wiring part 14 formation surface (12 ′ b) side can be used.
The number of wiring layers and electrical insulating layers between the heat sink 12 and the electronic component built-in layer 15A is not limited to the illustrated example, and the wiring layers and electrical insulating layers may be omitted.
The electronic device of the present invention is not limited to those shown in the first and second embodiments described above, and the number of laminated wiring layers, electrical insulating layers, and electronic component built-in layers to be formed, etc. There is no limit. In addition, instead of the electronic component built-in layer described above, a thin substrate on which electronic components are mounted and a perforated frame substrate having vertical conduction vias are collectively stacked as one module to form an electronic component built-in layer. A layer may be provided.

ここで、本発明の電子装置の製造方法を図面を参照しながら説明する。
（製造方法の第１の例）
図３乃至図５は、本発明の電子装置の製造方法の一例を図１に示される電子装置１を例として説明する工程図である。
まず、熱伝導性基材２′の一方の面２′ｂ上に１層目の配線層１０ａを形成し、この配線層１０ａを覆うように給電層３１を形成する（図３（Ａ））。
１層目の配線層１０ａの形成方法には、特に制限はなく、例えば、以下のように形成することができる。すなわち、熱伝導性基材２′の一方の面２′ｂ上に真空成膜法により導電層を形成し、この導電層上にレジスト層を形成し、所望のパターン露光、現像を行うことによりレジストパターンを形成する。その後、このレジストパターンをマスクとして電解めっきにより導電材料を析出させて配線層１０ａを形成し、レジストパターンと導電層を除去する。導電材料としては、銅、銀、金、アルミニウム等を挙げることができる。 Here, an electronic device manufacturing method of the present invention will be described with reference to the drawings.
(First example of manufacturing method)
3 to 5 are process diagrams illustrating an example of a method for manufacturing an electronic device according to the present invention, taking the electronic device 1 shown in FIG. 1 as an example.
First, the first wiring layer 10a is formed on one surface 2'b of the heat conductive substrate 2 ', and the power feeding layer 31 is formed so as to cover the wiring layer 10a (FIG. 3A). .
The method for forming the first wiring layer 10a is not particularly limited, and for example, it can be formed as follows. That is, a conductive layer is formed on one surface 2'b of the heat conductive substrate 2 'by a vacuum film forming method, a resist layer is formed on the conductive layer, and desired pattern exposure and development are performed. A resist pattern is formed. Thereafter, a conductive material is deposited by electrolytic plating using the resist pattern as a mask to form the wiring layer 10a, and the resist pattern and the conductive layer are removed. Examples of the conductive material include copper, silver, gold, and aluminum.

上記の給電層３１は、クロム、チタン等の導電性薄膜を真空成膜法等により形成することができる。
次に、給電層３１上にめっき用マスク３２を形成する（図３（Ｂ））。めっき用マスク３２は、例えば、給電層３１上にドライフィルムレジストをラミネートして所望のパターン露光、現像を行うことにより形成することができる。このめっき用マスク３２は、後述する導電性柱状凸部３７を形成する部位に開口部３２ａ、ブロック体３８を形成する部位に開口部３２ｂを有するものである。めっき用マスク３２の厚みは、導電性柱状凸部３７の高さ、ブロック体３８の厚みを規定するものであり、例えば、２５〜４００μｍの範囲で適宜設定することができる。 The power feeding layer 31 can be formed of a conductive thin film such as chromium or titanium by a vacuum film forming method or the like.
Next, a plating mask 32 is formed over the power supply layer 31 (FIG. 3B). The plating mask 32 can be formed, for example, by laminating a dry film resist on the power feeding layer 31 and performing desired pattern exposure and development. The plating mask 32 has an opening 32a at a portion where a conductive columnar protrusion 37 described later is formed and an opening 32b at a portion where a block body 38 is formed. The thickness of the plating mask 32 defines the height of the conductive columnar convex portion 37 and the thickness of the block body 38, and can be appropriately set within a range of 25 to 400 μm, for example.

次に、めっき用マスク３２を介して電解めっきにより給電層３１上に金属材料を析出させ、その後、めっき用マスク３２を除去することにより、上下導通ビアポスト用の導電性柱状凸部３７、および、電子部品を内蔵するための切欠き部形成用のブロック体３８を形成する（図３（Ｃ））。導電性柱状凸部３７は熱伝導性基材２′上の所望の配線層１０ａ上に位置し、ブロック体３８は熱伝導性基材２′の一方の面２′ｂ上に位置している。
この電解めっきにより形成する導電性柱状凸部３７、ブロック体３８は、銅、銀、金、クロム、アルミニウム等の金属材料等でよく、後述する給電層３１の除去が可能なように、給電層３１の材料を考慮して選択することが好ましい。 Next, by depositing a metal material on the power supply layer 31 by electrolytic plating through the plating mask 32, and then removing the plating mask 32, the conductive columnar protrusions 37 for the vertical conductive via posts, and A block body 38 for forming a notch for incorporating an electronic component is formed (FIG. 3C). The conductive columnar protrusion 37 is located on a desired wiring layer 10a on the heat conductive substrate 2 ', and the block body 38 is located on one surface 2'b of the heat conductive substrate 2'. .
The conductive columnar protrusions 37 and the block bodies 38 formed by this electrolytic plating may be made of a metal material such as copper, silver, gold, chromium, and aluminum, and the power feeding layer so that the power feeding layer 31 described later can be removed. It is preferable to select in consideration of 31 materials.

次に、露出している給電層３１を除去する（図３（Ｄ））。この給電層３１の除去は、導電性柱状凸部３７およびブロック体３８をマスクとしたウエットエッチング、ドライエッチング等により行うことができる。
次いで、導電性柱状凸部３７とブロック体３８を覆うように絶縁樹脂層６を形成し、その後、導電性柱状凸部３７の頂部とブロック体３８の上面のみが露出するように絶縁樹脂層６を研磨する（図４（Ａ））。これにより、導電性柱状凸部３７は上下導通ビアポスト７となる。絶縁樹脂層６の形成は、エポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の有機絶縁性材料、あるいは、これらの有機材料とガラス繊維等を組み合わせたもの等の電気絶縁性樹脂を含有する塗布液を公知の塗布方法で塗布し、その後、加熱、紫外線照射、電子線照射等の所定の硬化処理を施すことにより行うことができる。 Next, the exposed power feeding layer 31 is removed (FIG. 3D). The power supply layer 31 can be removed by wet etching, dry etching, or the like using the conductive columnar protrusions 37 and the block bodies 38 as masks.
Next, the insulating resin layer 6 is formed so as to cover the conductive columnar protrusions 37 and the block body 38, and then the insulating resin layer 6 so that only the top of the conductive columnar protrusions 37 and the upper surface of the block body 38 are exposed. Is polished (FIG. 4A). Thereby, the conductive columnar convex portion 37 becomes the vertical conduction via post 7. The formation of the insulating resin layer 6 includes an organic insulating material such as an epoxy resin, a benzocyclobutene resin, a cardo resin, a polyimide resin, or a combination of these organic materials and glass fibers. The coating liquid to be applied can be applied by a known coating method, and then subjected to a predetermined curing treatment such as heating, ultraviolet irradiation, electron beam irradiation or the like.

次に、ブロック体３８を除去して切欠き部６ａを絶縁樹脂層６に形成する（図４（Ｂ））。尚、ブロック体３８を除去した際に、切欠き部６ａに給電層３１が残存する場合には、これを除去する。
その後、切欠き部６ａに電子部品８を嵌着することにより、電子部品内蔵層５Ａを形成する（図４（Ｃ））。電子部品８は、商品名エイブルボンド３２３０等の耐熱性の高い導電性または絶縁性接着剤により切欠き部６ａ内（熱伝導性基材２′上）に固着してもよい。 Next, the block body 38 is removed, and the notch 6a is formed in the insulating resin layer 6 (FIG. 4B). When the power supply layer 31 remains in the notch 6a when the block body 38 is removed, the power supply layer 31 is removed.
Then, the electronic component built-in layer 5A is formed by fitting the electronic component 8 into the notch 6a (FIG. 4C). The electronic component 8 may be fixed in the notch portion 6a (on the heat conductive base material 2 ') with a highly heat-resistant conductive or insulating adhesive such as trade name Ablebond 3230.

次いで、上記の電子部品内蔵層５Ａを覆うように電気絶縁層９ａ，９ｂを介して各配線層１０ｂ，１０ｃを形成する（図４（Ｄ））。上下導通ビア７ａを有する電気絶縁層９ａと配線層１０ｂの形成は、例えば、以下のように行うことができる。まず、電子部品内蔵層５Ａを覆うように感光性の電気絶縁層９ａを形成する。この電気絶縁層９ａを所定のマスクを介して露光し、現像することにより、電子部品内蔵層５Ａの上下導通ビアポスト７と電子部品８の端子部８ａが露出するように小径の穴部を電気絶縁層９ａの所定位置に形成する。そして、洗浄後、穴部内および電気絶縁層９ａ上に真空成膜法により導電層を形成し、この導電層上にレジスト層を形成し、所望のパターン露光、現像を行うことによりレジストパターンを形成する。その後、このレジストパターンをマスクとして、上記の穴部を含む露出部に電解めっきにより導電材料を析出させて上下導通ビア７ａと配線層１０ｂを形成し、レジストパターンと導電層を除去する。   Next, the wiring layers 10b and 10c are formed through the electrical insulating layers 9a and 9b so as to cover the electronic component built-in layer 5A (FIG. 4D). For example, the electrical insulating layer 9a and the wiring layer 10b having the vertical conduction vias 7a can be formed as follows. First, a photosensitive electrical insulating layer 9a is formed so as to cover the electronic component built-in layer 5A. The electrical insulating layer 9a is exposed through a predetermined mask and developed to electrically insulate the small-diameter hole so that the vertical conductive via post 7 of the electronic component built-in layer 5A and the terminal portion 8a of the electronic component 8 are exposed. It is formed at a predetermined position of the layer 9a. Then, after cleaning, a conductive layer is formed in the hole and on the electrical insulating layer 9a by a vacuum film forming method, a resist layer is formed on the conductive layer, and a resist pattern is formed by performing desired pattern exposure and development. To do. Thereafter, using this resist pattern as a mask, a conductive material is deposited by electrolytic plating on the exposed portion including the hole portion to form the vertical conductive via 7a and the wiring layer 10b, and the resist pattern and the conductive layer are removed.

また、上下導通ビア７ａを有する電気絶縁層９ａと配線層１０ｂの形成は、以下のように行うこともできる。すなわち、電子部品内蔵層５Ａを覆うように電気絶縁層９ａを形成し、炭酸ガスレーザー、ＵＶ−ＹＡＧレーザー等を用いて電子部品内蔵層５Ａの上下導通ビア７と電子部品８の端子部８ａが露出するように小径の穴部を電気絶縁層９ａの所定位置に形成する。そして、洗浄後、穴部内および電気絶縁層９ａに無電解めっきにより導電層を形成し、この導電層上にドライフィルムレジストをラミネートして所望のパターン露光、現像を行うことによりレジストパターンを形成する。その後、このレジストパターンをマスクとして、上記の穴部を含む露出部に電解めっきにより導電材料を析出させて上下導通ビア７ａと配線層１０ｂを形成し、レジストパターンと導電層を除去する。   The formation of the electrical insulating layer 9a and the wiring layer 10b having the vertical conduction vias 7a can also be performed as follows. That is, the electrical insulating layer 9a is formed so as to cover the electronic component built-in layer 5A, and the vertical conduction via 7 of the electronic component built-in layer 5A and the terminal portion 8a of the electronic component 8 are formed using a carbon dioxide laser, UV-YAG laser, or the like. A small-diameter hole is formed at a predetermined position of the electrical insulating layer 9a so as to be exposed. Then, after cleaning, a conductive layer is formed in the hole and in the electrical insulating layer 9a by electroless plating, a dry film resist is laminated on the conductive layer, and a resist pattern is formed by performing desired pattern exposure and development. . Thereafter, using this resist pattern as a mask, a conductive material is deposited by electrolytic plating on the exposed portion including the hole portion to form the vertical conductive via 7a and the wiring layer 10b, and the resist pattern and the conductive layer are removed.

導電材料としては、銅、銀、金、アルミニウム等を挙げることができる。上記の操作と同様にして、上下導通ビア７ｂを有する電気絶縁層９ｂと配線層１０ｃを形成することができる。
次に、２層目の電子部品内蔵層５Ｂを形成する。この電子部品内蔵層５Ｂの形成は、上述の電子部品内蔵層５Ａの形成と同様に行うことができる。
次いで、電子部品内蔵層５Ｂを覆うように電気絶縁層９ｃ，９ｄを介して各配線層１０ｄ，１０ｅ（入出力端子）を形成して、熱伝導性基材２′上への多層配線部４の形成が完了する（図５（Ａ））。上下導通ビア７ｃ，７ｄを有する電気絶縁層９ｃ，９ｄと配線層１０ｄ，１０ｅの形成は、上述の上下導通ビア７ａを有する電気絶縁層９ａと配線層１０ｂの形成と同様に行うことができる。 Examples of the conductive material include copper, silver, gold, and aluminum. In the same manner as described above, the electrical insulating layer 9b having the vertical conductive via 7b and the wiring layer 10c can be formed.
Next, a second electronic component built-in layer 5B is formed. The formation of the electronic component built-in layer 5B can be performed in the same manner as the formation of the electronic component built-in layer 5A described above.
Next, the wiring layers 10d and 10e (input / output terminals) are formed via the electrical insulating layers 9c and 9d so as to cover the electronic component built-in layer 5B, and the multilayer wiring portion 4 on the heat conductive substrate 2 ′ is formed. Is completed (FIG. 5A). The formation of the electrical insulation layers 9c, 9d having the vertical conduction vias 7c, 7d and the wiring layers 10d, 10e can be performed in the same manner as the formation of the electrical insulation layer 9a having the vertical conduction vias 7a and the wiring layer 10b.

次に、熱伝導性基材２′の面２′ａを研削して複数のフィン３を形成する（図５（Ｂ））。
フィン３の形成は、例えば、機械的研削、化学的エッチング等の方法により行うことができ、また、面２′ａにマスクを設けた後、サンドブラストによりフィン３を形成することができる。その後、配線層１０ｅ（入出力端子）上に外部電極部材（図示せず）を配設することにより、図１に示されるような電子装置１を得ることができる。外部電極部材は、例えば、各種はんだ、めっきバンプ（突起）、ならびに、めっきバンプ上へのはんだコート等により形成することができる。 Next, the surface 2'a of the heat conductive substrate 2 'is ground to form a plurality of fins 3 (FIG. 5B).
The fins 3 can be formed by, for example, a method such as mechanical grinding or chemical etching, and the fins 3 can be formed by sandblasting after providing a mask on the surface 2'a. Thereafter, by disposing an external electrode member (not shown) on the wiring layer 10e (input / output terminal), the electronic device 1 as shown in FIG. 1 can be obtained. The external electrode member can be formed by, for example, various solders, plating bumps (protrusions), solder coating on the plating bumps, and the like.

尚、上記のようにして切欠き部６ａを形成する代わりに、以下のように切欠き部６ａを形成してもよい。すなわち、下層の配線層を覆うように絶縁樹脂層６を形成し、この絶縁樹脂層６上にサンドブラスト用のマスクを形成し、このマスクを介して絶縁樹脂層６にサンドブラスト処理を施して電子部品を内蔵するための切欠き部６ａと、上下導通ビアポスト用の貫通孔を形成する。この貫通孔には下層の配線層が露出した状態となっている。次いで、貫通孔に導電材料を充填して上下導通ビアポスト７を形成する。この上下導通ビアポスト７の形成は、例えば、切欠き部６ａと、上下導通ビアポスト用の貫通孔内および絶縁樹脂層６にスパッタリング法により給電層を形成し、めっきレジストにより貫通孔内を除く給電層を被覆し、その後、このめっきレジストをマスクとして、貫通孔内に電解めっきにより導電材料を析出させ、めっきレジストと給電層を除去することにより行うことができる。   Instead of forming the notch 6a as described above, the notch 6a may be formed as follows. That is, the insulating resin layer 6 is formed so as to cover the lower wiring layer, a sand blast mask is formed on the insulating resin layer 6, and the insulating resin layer 6 is subjected to sand blasting through the mask to provide an electronic component. And a through hole for a vertical conductive via post are formed. In this through hole, the lower wiring layer is exposed. Next, the through hole is filled with a conductive material to form the vertical conduction via post 7. The vertical conductive via post 7 is formed, for example, by forming a power feeding layer by a sputtering method in the notch 6a, the through hole for the vertical conductive via post and the insulating resin layer 6, and removing the inside of the through hole by a plating resist. Then, using the plating resist as a mask, a conductive material is deposited in the through hole by electrolytic plating, and the plating resist and the power feeding layer are removed.

また、上下導通ビアポスト７用の導電性柱状凸部３７のみを、上述した給電層３１上に設けたドライフィルムレジストをマスクとしためっき析出で形成し、絶縁樹脂層６への切欠き部６ａの形成を上記のサンドブラスト法にて形成してもよい。
本発明では、上記のフィン３の形成と、配線層１０ｅ（入出力端子）上への外部電極部材の形成の工程順は特に制限はない。 Further, only the conductive columnar protrusions 37 for the vertical conductive via posts 7 are formed by plating deposition using the dry film resist provided on the power feeding layer 31 as a mask, and the notch 6a to the insulating resin layer 6 is formed. The formation may be performed by the sand blast method described above.
In the present invention, the order of the steps of forming the fin 3 and forming the external electrode member on the wiring layer 10e (input / output terminal) is not particularly limited.

（製造方法の第２の例）
図６および図７は、本発明の電子装置の製造方法の他の例を図２に示される電子装置１１を例として説明する工程図である。
まず、熱伝導性基材１２′の一方の面１２′ｂ上に１層目の配線層２０ａを形成し、この配線層２０ａを覆うように電気絶縁層１９ａを介して２層目の配線層２０ｂを形成する（図６（Ａ））。１層目の配線層２０ａは、上述の例における１層目の配線層１０ａと同様にして形成することができ、上下導通ビア１７ａを有する電気絶縁層１９ａと配線層２０ｂの形成は、上述の例における上下導通ビア７ａを有する電気絶縁層９ａと配線層１０ｂの形成と同様に行うことができる。 (Second example of manufacturing method)
6 and 7 are process diagrams illustrating another example of the method for manufacturing an electronic device according to the present invention, taking the electronic device 11 shown in FIG. 2 as an example.
First, a first wiring layer 20a is formed on one surface 12'b of the heat conductive substrate 12 ', and a second wiring layer is formed through the electrical insulating layer 19a so as to cover the wiring layer 20a. 20b is formed (FIG. 6A). The first wiring layer 20a can be formed in the same manner as the first wiring layer 10a in the above example, and the formation of the electrical insulating layer 19a and the wiring layer 20b having the vertical conduction vias 17a is as described above. This can be performed in the same manner as the formation of the electrical insulating layer 9a having the vertical conduction via 7a and the wiring layer 10b in the example.

次に、配線層２０ｂを覆うように給電層５１を形成し、この給電層５１上にめっき用マスク５２を形成する（図６（Ｂ））。給電層５１は、クロム、チタン等の導電性薄膜を真空成膜法等により形成することができる。また、めっき用マスク５２は、例えば、給電層５１上にドライフィルムレジストをラミネートして所望のパターン露光、現像を行うことにより形成することができる。このめっき用マスク５２は、後述する導電性柱状凸部５７を形成する部位に開口部５２ａを有するものである。めっき用マスク５２の厚みは、導電性柱状凸部５７の高さを規定するものであり、例えば、内蔵する電子部品１８の厚みよりも導電性柱状凸部５７の高さを１０μｍ程度高いように設定することができ、３０〜４００μｍの範囲で適宜設定することができる。   Next, a power feeding layer 51 is formed so as to cover the wiring layer 20b, and a plating mask 52 is formed on the power feeding layer 51 (FIG. 6B). The power feeding layer 51 can be formed of a conductive thin film such as chromium or titanium by a vacuum film forming method or the like. The plating mask 52 can be formed, for example, by laminating a dry film resist on the power feeding layer 51 and performing desired pattern exposure and development. The plating mask 52 has an opening 52a at a portion where a conductive columnar convex portion 57 described later is formed. The thickness of the plating mask 52 defines the height of the conductive columnar protrusion 57. For example, the height of the conductive columnar protrusion 57 is about 10 μm higher than the thickness of the built-in electronic component 18. It can set and can set suitably in the range of 30-400 micrometers.

次に、めっき用マスク５２を介して電解めっきにより給電層５１上に金属材料を析出させ、その後、めっき用マスク５２を除去することにより、上下導通ビアポスト用の導電性柱状凸部５７を形成する（図６（Ｃ））。この導電性柱状凸部５７は所定の配線層２０ｂ上に位置している。
このように電解めっきにより形成する導電性柱状凸部５７は、上述の例における導電性柱状凸部３７と同様の材料を用いて形成することができる。
次に、露出している給電層５１を除去し、電気絶縁層１９ａ上に電子部品１８を載置する（図６（Ｄ））。給電層５１の除去は、導電性柱状凸部５７をマスクとしたウエットエッチング、ドライエッチング等により行うことができる。また、電子部品１８の載置では、商品名エイブルボンド３２３０等の耐熱性の高い導電性または絶縁性接着剤により電気絶縁層１９ａ上に固着してもよい。 Next, by depositing a metal material on the power supply layer 51 by electrolytic plating through the plating mask 52, and then removing the plating mask 52, the conductive columnar protrusions 57 for the vertical conductive via posts are formed. (FIG. 6C). The conductive columnar protrusions 57 are located on the predetermined wiring layer 20b.
Thus, the electroconductive columnar convex part 57 formed by electrolytic plating can be formed using the material similar to the electroconductive columnar convex part 37 in the above-mentioned example.
Next, the exposed power feeding layer 51 is removed, and the electronic component 18 is placed on the electrical insulating layer 19a (FIG. 6D). The power feeding layer 51 can be removed by wet etching, dry etching, or the like using the conductive columnar protrusions 57 as a mask. Further, when the electronic component 18 is placed, the electronic component 18 may be fixed on the electrical insulating layer 19a with a highly heat-resistant conductive or insulating adhesive such as the brand name Ablebond 3230.

次いで、電子部品１８と導電性柱状凸部５７を覆うように感光性の絶縁樹脂層１６を形成し、この絶縁樹脂層１６を、導電性柱状凸部５７の頂部が露出するように研磨する（図７（Ａ））。その後、絶縁樹脂層１６を所定のパターンで露光、現像して、電子部品１８の端子部１８ａを露出させる（図７（Ｂ））。これにより、導電性柱状凸部５７は上下導通ビアポスト１７となり、電子部品内蔵層１５Ａが形成される。
絶縁樹脂層１６の形成は、感光性を有するエポキシ樹脂、ベンゾシクロブテン樹脂、カルド樹脂、ポリイミド樹脂等の有機絶縁性材料、あるいは、これらの有機材料とガラス繊維等を組み合わせたもの等を含有した塗布液を公知の塗布方法で塗布し、その後、紫外線照射、電子線照射等を用いて露光し現像することにより行うことができる。 Next, a photosensitive insulating resin layer 16 is formed so as to cover the electronic component 18 and the conductive columnar convex portion 57, and this insulating resin layer 16 is polished so that the top of the conductive columnar convex portion 57 is exposed ( FIG. 7 (A)). Thereafter, the insulating resin layer 16 is exposed and developed with a predetermined pattern to expose the terminal portions 18a of the electronic component 18 (FIG. 7B). Thereby, the conductive columnar convex portion 57 becomes the vertical conduction via post 17 and the electronic component built-in layer 15A is formed.
The formation of the insulating resin layer 16 contained an organic insulating material such as a photosensitive epoxy resin, benzocyclobutene resin, cardo resin, polyimide resin, or a combination of these organic materials and glass fibers. The coating liquid can be applied by a known coating method, and then exposed and developed using ultraviolet irradiation, electron beam irradiation, or the like.

次いで、上記の電子部品内蔵層１５Ａを覆うように電気絶縁層１９ｂ，１９ｃを介して各配線層２０ｃ，２０ｄを形成し、配線層２０ｄ上に上述の図６（Ｂ）から図７（Ｂ）と同様の操作により電子部品内蔵層１５Ｂを形成し、さらに、この電子部品内蔵層１５Ｂを覆うように電気絶縁層１９ｄを介して配線層２０ｅ（入出力端子）を形成して、熱伝導性基材１２′上への多層配線部１４の形成が完了する（図７（Ｃ））。
上下導通ビア１７ｂ，１７ｃ，１７ｄを有する電気絶縁層１９ｂ，１９ｃ，１９ｄと配線層２０ｃ，２０ｄ，２０ｅの形成は、上述の例の上下導通ビア７ａを有する電気絶縁層９ａと配線層１０ｂの形成と同様に行うことができる。 Next, the wiring layers 20c and 20d are formed through the electrical insulating layers 19b and 19c so as to cover the electronic component built-in layer 15A, and the above-described FIGS. 6B to 7B are formed on the wiring layer 20d. The electronic component built-in layer 15B is formed by the same operation as described above, and further, the wiring layer 20e (input / output terminal) is formed through the electrical insulating layer 19d so as to cover the electronic component built-in layer 15B. The formation of the multilayer wiring portion 14 on the material 12 'is completed (FIG. 7C).
The formation of the electrical insulation layers 19b, 19c, 19d having the vertical conduction vias 17b, 17c, 17d and the wiring layers 20c, 20d, 20e is the formation of the electrical insulation layer 9a having the vertical conduction via 7a and the wiring layer 10b in the above example. Can be done as well.

次に、熱伝導性基材１２′の面１２′ａを研磨して複数のフィン１３を形成し、その後、配線層２０ｅ（入出力端子）上に外部電極部材（図示せず）を配設することにより、図２に示されるような電子装置１１を得ることができる。フィン１３の形成は、上述の例におけるフィン３の形成と同様に行うことができる。また、外部電極部材も、上述の例と同様に形成することができる。尚、上記のフィン１３の形成と、配線層２０ｅ（入出力端子）上への外部電極部材の形成の工程順は特に制限はない。
本発明の電子装置は、構成する２層以上の電子部品内蔵層が、上述の製造例で挙げた異なる方法で形成されたものであってもよい。 Next, the surface 12'a of the heat conductive substrate 12 'is polished to form a plurality of fins 13, and then an external electrode member (not shown) is disposed on the wiring layer 20e (input / output terminal). By doing so, the electronic device 11 as shown in FIG. 2 can be obtained. The fin 13 can be formed in the same manner as the fin 3 in the above-described example. The external electrode member can also be formed in the same manner as in the above example. In addition, there is no restriction | limiting in particular in the process order of formation of said fin 13 and formation of the external electrode member on the wiring layer 20e (input / output terminal).
In the electronic device of the present invention, two or more layers of electronic component built-in layers constituting the electronic device may be formed by different methods described in the above-described production examples.

次に、具体的実施例を挙げて本発明を更に詳細に説明する。
［実施例１］
熱伝導性基材として、直径２００ｍｍ、厚み６２５μｍのシリコンウエハを準備した。このシリコンウエハのＸＹ方向（シリコンウエハの表面に平行な平面）の熱膨張係数は、２．５ｐｐｍであった。
このシリコンウエハの一方の面にスパッタリング法によりクロムと銅からなる導電層を形成し、この導電層上に液状レジスト（東京応化工業（株）製ＬＡ９００）を塗布した。次いで、１層目の配線層形成用のフォトマスクを介し露光、現像して配線形成用のレジストパターンを形成した。このレジストパターンをマスクとして電解銅めっき（厚み４μｍ）を行い、その後、レジストパターンと導電層を除去した。これにより、１層目の配線層をシリコンウエハ上に形成した。 Next, the present invention will be described in more detail with specific examples.
[Example 1]
A silicon wafer having a diameter of 200 mm and a thickness of 625 μm was prepared as a thermally conductive substrate. The thermal expansion coefficient of this silicon wafer in the XY direction (a plane parallel to the surface of the silicon wafer) was 2.5 ppm.
A conductive layer made of chromium and copper was formed on one surface of the silicon wafer by sputtering, and a liquid resist (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the conductive layer. Subsequently, the resist pattern for wiring formation was formed by exposing and developing through the photomask for forming the first wiring layer. Electrolytic copper plating (thickness: 4 μm) was performed using this resist pattern as a mask, and then the resist pattern and the conductive layer were removed. As a result, a first wiring layer was formed on the silicon wafer.

次に、１層目の配線層が形成されたシリコンウエハ上に、厚み０．０３μｍのクロム層、厚み０．２μｍの銅層からなる給電層をスパッタリング法により形成した。この給電層上にドライフィルムレジスト（旭化成（株）製ＡＸ−１１０）をラミネートして所望のパターン露光、現像を行うことによりめっき用マスク（厚み６０μｍ）を形成した。このめっき用マスクを介して電解銅めっきを行い、その後、めっき用マスクを除去することにより、上下導通ビアポスト用の導電性柱状凸部（高さ５０μｍ）と、電子部品を内蔵するための切欠き部形成用のブロック体（１５ｍｍ×１５ｍｍ）を給電層上に形成した。形成した導電性柱状凸部は１層目の配線層の所定箇所に位置し、ブロック体はシリコンウエハ上に位置したものであった。   Next, a power feeding layer made of a chromium layer having a thickness of 0.03 μm and a copper layer having a thickness of 0.2 μm was formed on the silicon wafer on which the first wiring layer was formed by a sputtering method. A dry film resist (AX-110 manufactured by Asahi Kasei Co., Ltd.) was laminated on the power feeding layer and subjected to desired pattern exposure and development to form a plating mask (thickness 60 μm). By conducting electrolytic copper plating through this plating mask and then removing the plating mask, conductive columnar protrusions (height 50 μm) for the upper and lower conductive via posts and notches for incorporating electronic components A block body for forming a part (15 mm × 15 mm) was formed on the power feeding layer. The formed conductive columnar convex portions were located at predetermined positions of the first wiring layer, and the block body was located on the silicon wafer.

次に、露出している給電層をエッチングにより除去した。次いで、導電性柱状凸部とブロック体を覆うように絶縁樹脂組成物（新日鉄化学（株）製Ｘ２０５）をダイコートによりシリコンウエハ全面に塗布した。次に、硬化処理（７０℃、５０分間）を施して絶縁樹脂層を形成した後、導電性柱状凸部の頂部とブロック体の上面のみが露出するように絶縁樹脂層を機械研磨した。これにより、上下導通ビアポストを備えた絶縁樹脂層（厚み５０μｍ）を形成した。
次に、ブロック体をエッチングにより除去し、切欠き部を絶縁樹脂層に形成し、この切欠き部に残存する給電層をエッチングにより除去した。次いで、この切欠き部にＬＳＩチップ（１５ｍｍ×１５ｍｍ）を接着剤（エイブルスティック（株）製 エイブルボンド３２３０）を用いて嵌着することにより、電子部品内蔵層を形成した。 Next, the exposed power feeding layer was removed by etching. Next, an insulating resin composition (X205 manufactured by Nippon Steel Chemical Co., Ltd.) was applied to the entire surface of the silicon wafer by die coating so as to cover the conductive columnar convex portions and the block body. Next, after performing a curing process (70 ° C., 50 minutes) to form an insulating resin layer, the insulating resin layer was mechanically polished so that only the tops of the conductive columnar protrusions and the upper surface of the block body were exposed. This formed the insulating resin layer (thickness 50 micrometers) provided with the vertical conduction via post.
Next, the block body was removed by etching, a notch was formed in the insulating resin layer, and the power feeding layer remaining in the notch was removed by etching. Next, an LSI chip (15 mm × 15 mm) was fitted into the notch using an adhesive (Able Bond 3230 manufactured by Able Stick Co., Ltd.) to form an electronic component built-in layer.

次に、上記の電子部品内蔵層上にベンゾシクロブテン樹脂組成物（ダウ・ケミカル社製サイクロテン４０２４）をスピンコーターにより塗布、乾燥して厚み１０μｍの電気絶縁層を形成した。
次に、露光、現像を行って、電子部品内蔵層の上下導通ビアポストおよびＬＳＩチップの端子部が露出するように小径の穴部（内径２０μｍ）を電気絶縁層の所定位置に形成した。そして、洗浄後、穴部内および電気絶縁層上にスパッタリング法によりクロムと銅からなる導電層を形成し、この導電層上に液状レジスト（東京応化工業（株）製ＬＡ９００）を塗布した。次いで、２層目の配線層形成用のフォトマスクを介し露光、現像して配線形成用のレジストパターンを形成した。このレジストパターンをマスクとして電解銅めっき（厚み４μｍ）を行い、その後、レジストパターンと導電層を除去した。これにより、上下導通ビアにより電子部品内蔵層の所定部位と接続された２層目の配線層を電気絶縁層を介して電子部品内蔵層上に形成した。上記の上下導通ビアの径は２０μｍであった。 Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) was applied onto the electronic component built-in layer with a spin coater and dried to form an electrical insulating layer having a thickness of 10 μm.
Next, exposure and development were performed to form a small-diameter hole (inner diameter 20 μm) at a predetermined position of the electrical insulating layer so that the vertical conductive via post of the electronic component built-in layer and the terminal portion of the LSI chip were exposed. After cleaning, a conductive layer made of chromium and copper was formed by sputtering in the hole and on the electrical insulating layer, and a liquid resist (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the conductive layer. Next, a resist pattern for wiring formation was formed by exposure and development through a photomask for forming a second wiring layer. Electrolytic copper plating (thickness: 4 μm) was performed using this resist pattern as a mask, and then the resist pattern and the conductive layer were removed. As a result, a second wiring layer connected to a predetermined portion of the electronic component built-in layer by the vertical conduction via was formed on the electronic component built-in layer via the electrical insulating layer. The diameter of the above vertical conductive via was 20 μm.

更に、同様の操作を行い、電気絶縁層を介して３層目の配線層を２層目配線層上に形成した。
次に、３層目の配線上に、上記の電子部品内蔵層の形成工程と同様の工程により、第２の電子部品内蔵層を形成した。その後、上記の配線層の形成工程と同様にして、電気絶縁層を介して４層目の配線層、５層目の配線層（入出力端子）を第２の電子部品内蔵層上に形成した。これにより、シリコンウエハの一方の面に多層配線部を設けた。 Further, the same operation was performed, and a third wiring layer was formed on the second wiring layer via the electrical insulating layer.
Next, a second electronic component built-in layer was formed on the third-layer wiring by a process similar to the above-described step of forming the electronic component built-in layer. Thereafter, the fourth wiring layer and the fifth wiring layer (input / output terminal) were formed on the second electronic component built-in layer through the electrical insulating layer in the same manner as the wiring layer forming step. . Thus, a multilayer wiring portion was provided on one surface of the silicon wafer.

次に、シリコンウエハの他方の面にドライエッチングにより冷却用のフィンを形成して、ヒートシンクとした。形成したフィンは、厚み０．２ｍｍ、高さ０．４ｍｍ、長さ１０ｍｍの板形状であり、形成ピッチは０．４ｍｍとした。
次いで、多層配線部の５層目の配線層（入出力端子）上に、はんだボールを形成して、図１に示されるような構成の本発明の電子装置（実施例１）を得た。 Next, a cooling fin was formed on the other surface of the silicon wafer by dry etching to obtain a heat sink. The formed fin had a plate shape with a thickness of 0.2 mm, a height of 0.4 mm, and a length of 10 mm, and the formation pitch was 0.4 mm.
Next, solder balls were formed on the fifth wiring layer (input / output terminal) of the multilayer wiring portion to obtain the electronic device (Example 1) of the present invention having the configuration as shown in FIG.

［実施例２］
熱伝導性基材として、１５０ｍｍ×１５０ｍｍ、厚み２００μｍのＦｅ−Ｎｉ４２合金基材を準備し、このＦｅ−Ｎｉ４２合金基材の一方の面に電気絶縁層として、厚み１０μｍのＡｌＮを溶射により形成した。
次に、上記の電気絶縁層上にスパッタリング法によりクロムと銅からなる導電層を形成し、この導電層上に液状レジスト（東京応化工業（株）製ＬＡ９００）を塗布した。次いで、１層目の配線層形成用のフォトマスクを介し露光、現像して配線形成用のレジストパターンを形成した。このレジストパターンをマスクとして電解銅めっき（厚み４μｍ）を行い、その後、レジストパターンと導電層を除去した。これにより、１層目の配線層をＦｅ−Ｎｉ４２合金基材（電気絶縁層）上に形成した。 [Example 2]
An Fe—Ni42 alloy substrate having a size of 150 mm × 150 mm and a thickness of 200 μm was prepared as a heat conductive substrate, and an AlN layer having a thickness of 10 μm was formed by thermal spraying as an electrical insulating layer on one surface of the Fe—Ni42 alloy substrate. .
Next, a conductive layer made of chromium and copper was formed on the electrical insulating layer by sputtering, and a liquid resist (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the conductive layer. Subsequently, the resist pattern for wiring formation was formed by exposing and developing through the photomask for forming the first wiring layer. Electrolytic copper plating (thickness: 4 μm) was performed using this resist pattern as a mask, and then the resist pattern and the conductive layer were removed. Thus, the first wiring layer was formed on the Fe—Ni42 alloy base material (electrical insulating layer).

１層目の配線層を形成したＦｅ−Ｎｉ４２合金基材上にベンゾシクロブテン樹脂組成物（ダウ・ケミカル社製サイクロテン４０２４）をスピンコーターにより塗布、乾燥して厚み１０μｍの電気絶縁層を形成した。
次に、露光、現像を行って、１層目の配線層の所定部位が露出するように小径の穴部（内径２０μｍ）を電気絶縁層の所定位置に形成した。そして、洗浄後、穴部内および電気絶縁層上にスパッタリング法によりクロムと銅からなる導電層を形成し、この導電層上に液状レジスト（東京応化工業（株）製ＬＡ９００）を塗布した。次いで、２層目の配線層形成用のフォトマスクを介し露光、現像して配線形成用のレジストパターンを形成した。このレジストパターンをマスクとして電解銅めっき（厚み４μｍ）を行い、その後、レジストパターンと導電層を除去した。これにより、上下導通ビアにより１層目の配線層の所定部位と接続された２層目の配線層を電気絶縁層を介して形成した。上記の上下導通ビアの径は２０μｍであった。 A benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) is applied to the Fe-Ni42 alloy base material on which the first wiring layer is formed using a spin coater and dried to form an electrical insulating layer having a thickness of 10 μm. did.
Next, exposure and development were performed to form a small-diameter hole (inner diameter 20 μm) at a predetermined position of the electrical insulating layer so that a predetermined portion of the first wiring layer was exposed. After cleaning, a conductive layer made of chromium and copper was formed by sputtering in the hole and on the electrical insulating layer, and a liquid resist (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the conductive layer. Next, a resist pattern for wiring formation was formed by exposure and development through a photomask for forming a second wiring layer. Electrolytic copper plating (thickness: 4 μm) was performed using this resist pattern as a mask, and then the resist pattern and the conductive layer were removed. As a result, the second wiring layer connected to the predetermined portion of the first wiring layer by the vertical conduction via was formed via the electrical insulating layer. The diameter of the above vertical conductive via was 20 μm.

次いで、２層目の配線層を被覆するように厚み０．０３μｍのクロム層、厚み０．２μｍの銅層からなる給電層をスパッタリング法により形成した。この給電層上にドライフィルムレジスト（旭化成（株）製ＡＸ−１１０）をラミネートして所望のパターン露光、現像を行うことにより、めっき用マスク（厚み９０μｍ）を形成した。このめっき用マスクを介して電解銅めっきを行い、その後、めっき用マスクを除去することにより、給電層上に導通ビアポスト用の導電性柱状凸部（高さ６０μｍ）を形成した。
次いで、露出している給電層をエッチングにより除去し、電気絶縁層上の所定位置にＬＳＩチップ（１５ｍｍ×１５ｍｍ、厚み５０μｍ）を接着剤（エイブルスティック（株）製 エイブルボンド３２３０）を用いて固着載置した。 Next, a power feeding layer made of a chromium layer having a thickness of 0.03 μm and a copper layer having a thickness of 0.2 μm was formed by a sputtering method so as to cover the second wiring layer. A dry film resist (AX-110 manufactured by Asahi Kasei Co., Ltd.) was laminated on the power feeding layer and subjected to desired pattern exposure and development, thereby forming a plating mask (thickness: 90 μm). Electrolytic copper plating was performed through this plating mask, and then the plating mask was removed to form conductive columnar protrusions (height 60 μm) for the conductive via posts on the power supply layer.
Next, the exposed power feeding layer is removed by etching, and an LSI chip (15 mm × 15 mm, thickness 50 μm) is fixed to a predetermined position on the electrical insulating layer using an adhesive (Able Bond 3230 manufactured by Able Stick Co., Ltd.). Placed.

次に、ＬＳＩチップと導電性柱状凸部を覆うように感光性の絶縁樹脂組成物（新日鉄化学（株）製 ＰＤ１００）をダイコートにより塗布し、導電性柱状凸部の頂部が露出するように絶縁樹脂層を機械研磨した。次に、フォトマスクを介して露光を行って、ＬＳＩチップの端子部を除く部位に硬化処理を施し、その後、現像をおこなって、ＬＳＩチップの端子部を露出させた。これにより、上下導通ビアポストを備えた絶縁樹脂層（厚み６０μｍ）を形成して第１の電子部品内蔵層を設けた。
次いで、上記の電子部品内蔵層上に、上記の配線層の形成工程と同様にして、電気絶縁層を介して３層目の配線層を形成し、さらに、電気絶縁層を介して４層目の配線層を３層目配線層上に形成した。 Next, a photosensitive insulating resin composition (PD100 manufactured by Nippon Steel Chemical Co., Ltd.) is applied by die coating so as to cover the LSI chip and the conductive columnar protrusions, and insulated so that the tops of the conductive columnar protrusions are exposed. The resin layer was mechanically polished. Next, exposure was performed through a photomask to cure the portion excluding the terminal portion of the LSI chip, and then development was performed to expose the terminal portion of the LSI chip. As a result, an insulating resin layer (thickness 60 μm) provided with vertical conduction via posts was formed to provide the first electronic component built-in layer.
Next, a third wiring layer is formed on the electronic component built-in layer through the electric insulating layer in the same manner as the wiring layer forming step, and further, a fourth layer is formed through the electric insulating layer. The wiring layer was formed on the third wiring layer.

次に、４層目の配線上に、上記の電子部品内蔵層の形成と同様にして、第２の電子部品内蔵層を設けた。
次に、上記の配線層の形成工程と同様にして、電気絶縁層を介して５層目の配線層（入出力端子）を第２の電子部品内蔵層上に形成した。これにより、Ｆｅ−Ｎｉ４２合金基材の電気絶縁層形成面に多層配線部を設けた。
次に、Ｆｅ−Ｎｉ４２合金基材の他方の面にエッチングにより冷却用のフィンを形成して、ヒートシンクとした。形成したフィンは、厚み０．２ｍｍ、高さ０．１ｍｍ、長さ１０ｍｍの板形状であり、形成ピッチは０．４ｍｍとした。
次いで、多層配線部の５層目の配線層（入出力端子）上に、はんだボールを形成して、図２に示されるような構成の本発明の電子装置（実施例２）を得た。 Next, a second electronic component built-in layer was provided on the fourth layer wiring in the same manner as the formation of the electronic component built-in layer.
Next, a fifth wiring layer (input / output terminal) was formed on the second electronic component built-in layer through the electrical insulating layer in the same manner as in the wiring layer forming step. Thereby, the multilayer wiring part was provided in the electric insulation layer formation surface of the Fe-Ni42 alloy base material.
Next, a cooling fin was formed by etching on the other surface of the Fe—Ni42 alloy base material to obtain a heat sink. The formed fin was a plate shape having a thickness of 0.2 mm, a height of 0.1 mm, and a length of 10 mm, and the formation pitch was 0.4 mm.
Next, solder balls were formed on the fifth wiring layer (input / output terminal) of the multilayer wiring portion to obtain the electronic device (Example 2) of the present invention having the configuration as shown in FIG.

［比較例］
直径２００ｍｍ、厚み６２５μｍのシリコンウエハを準備した。このシリコンウエハのＸＹ方向（シリコンウエハの表面に平行な平面）の熱膨張係数は、２．５ｐｐｍであった。
このシリコンウエハの一方の面に、実施例１と同様にして、多層配線部を形成した。
次いで、材質がＡｌからなり、一方の面に複数のフィンを備えたヒートシンクの平坦面側を、上記のシリコンウエハの他方の面に、エポキシ接着剤により接着して配設した。上記のフィンは、厚み０．２ｍｍ、高さ０．４ｍｍ、長さ１０ｍｍの板形状であり、形成ピッチは０．４ｍｍであった。
次いで、多層配線部の５層目の配線層（入出力端子）上に、はんだボールを形成して、電子装置（比較例）を得た。 [Comparative example]
A silicon wafer having a diameter of 200 mm and a thickness of 625 μm was prepared. The thermal expansion coefficient of this silicon wafer in the XY direction (a plane parallel to the surface of the silicon wafer) was 2.5 ppm.
A multilayer wiring portion was formed on one side of the silicon wafer in the same manner as in Example 1.
Next, the flat surface side of the heat sink, which was made of Al and provided with a plurality of fins on one side, was disposed on the other side of the silicon wafer by being bonded with an epoxy adhesive. Said fin was plate shape of thickness 0.2mm, height 0.4mm, and length 10mm, and the formation pitch was 0.4mm.
Next, solder balls were formed on the fifth wiring layer (input / output terminal) of the multilayer wiring portion to obtain an electronic device (comparative example).

［評 価］
上述のように作製した電子装置（実施例１、実施例２、比較例）に対して、下記の熱サイクル試験を行った。
（熱サイクル試験方法）
−５５℃から１２５℃の温度サイクルで、それぞれの温度において３０分間ずつ熱
処理を行い、これを３０００回繰り返した。
上記の熱サイクル試験の結果、実施例１および実施例２の電子装置はヒートシンクの脱落も発生せず、信頼性が高いことが確認された。
これに対して、比較例の電子装置は、ヒートシンクの脱落が発生した。 [Evaluation]
The following thermal cycle test was performed on the electronic devices manufactured as described above (Example 1, Example 2, Comparative Example).
(Thermal cycle test method)
In the temperature cycle from −55 ° C. to 125 ° C., heat treatment was performed at each temperature for 30 minutes, and this was repeated 3000 times.
As a result of the above heat cycle test, it was confirmed that the electronic devices of Examples 1 and 2 did not cause the heat sink to drop and had high reliability.
On the other hand, in the electronic device of the comparative example, the heat sink was dropped.

小型で高信頼性が要求される半導体装置や各種電子機器への用途にも適用できる。   The present invention can also be applied to small semiconductor devices and various electronic devices that require high reliability.

本発明の電子装置の第１の実施形態を示す概略縦断面図である。1 is a schematic longitudinal sectional view showing a first embodiment of an electronic device of the present invention. 本発明の電子装置の第２の実施形態を示す概略縦断面図である。It is a schematic longitudinal cross-sectional view which shows 2nd Embodiment of the electronic device of this invention. 本発明の電子装置の製造例を示す工程図である。It is process drawing which shows the manufacture example of the electronic device of this invention. 本発明の電子装置の製造例を示す工程図である。It is process drawing which shows the manufacture example of the electronic device of this invention. 本発明の電子装置の製造例を示す工程図である。It is process drawing which shows the manufacture example of the electronic device of this invention. 本発明の電子装置の他の製造例を示す工程図である。It is process drawing which shows the other example of manufacture of the electronic device of this invention. 本発明の電子装置の他の製造例を示す工程図である。It is process drawing which shows the other example of manufacture of the electronic device of this invention.

符号の説明Explanation of symbols

１，１１…電子装置
２，１２…ヒートシンク
２′，１２′…熱伝導性基材
３，１３…フィン
４，１４…多層配線部
５Ａ，５Ｂ，１５Ａ，１５Ｂ…電子部品内蔵層
６，１６…絶縁樹脂層
６ａ…切欠き部
７，１７…上下導通ビアポスト
８，１８…電子部品
７ａ，７ｂ，７ｃ，７ｄ，１７ａ，１７ｂ，１７ｃ，１７ｄ…上下導通ビア
９ａ，９ｂ，９ｃ，９ｄ，１９ａ，１９ｂ，１９ｃ，１９ｄ…電気絶縁層
１０ａ，１０ｂ，１０ｃ，１０ｄ，１０ｅ，２０ａ，２０ｂ，２０ｃ，２０ｄ，２０ｅ…配線層
１０ｅ，２０ｅ…入出力端子
３７，５７…導電性柱状凸部
３８…ブロック体 DESCRIPTION OF SYMBOLS 1,11 ... Electronic device 2,12 ... Heat sink 2 ', 12' ... Thermally conductive base material 3,13 ... Fin 4,14 ... Multilayer wiring part 5A, 5B, 15A, 15B ... Electronic component built-in layer 6, 16, ... Insulating resin layer 6a ... Notch 7, 17 ... Vertical conductive via post 8, 18 ... Electronic component 7a, 7b, 7c, 7d, 17a, 17b, 17c, 17d ... Vertical conductive via 9a, 9b, 9c, 9d, 19a, 19b, 19c, 19d ... Electrical insulating layers 10a, 10b, 10c, 10d, 10e, 20a, 20b, 20c, 20d, 20e ... Wiring layers 10e, 20e ... Input / output terminals 37, 57 ... Conductive columnar protrusions 38 ... Block body

Claims (6)

熱伝導性基材の一方の面に複数のフィンを備えるヒートシンクと、前記熱伝導性基材の他方の面に形成された多層配線部とを備えた電子装置の製造方法において、
電子部品を内蔵するとともに上下導通ビアポストを備えた電子部品内蔵層と、配線層と、電気絶縁層とを所望の積層順序で有し、前記電気絶縁層に設けた上下導通ビアにて前記配線層、前記電子部品内蔵層の電子部品、上下導通ビアポストとの所望の導通がなされており、かつ、前記多層配線部の表面に入出力端子を備える多層配線部を、ビルドアップ法で熱伝導性基材の一方の面に形成する工程と、
前記熱伝導性基材の他方の面に複数のフィンを形成してヒートシンクとする工程と、を有することを特徴とする電子装置の製造方法。 In a method for manufacturing an electronic device comprising a heat sink having a plurality of fins on one surface of a thermally conductive substrate, and a multilayer wiring part formed on the other surface of the thermally conductive substrate,
An electronic component built-in layer having a built-in electronic component and provided with a vertically conductive via post, a wiring layer, and an electrical insulating layer in a desired stacking order, and the wiring layer formed by the vertical conductive via provided in the electrical insulating layer A multilayer wiring part having a desired electrical connection with the electronic component in the electronic component built-in layer and the vertical conduction via post and having an input / output terminal on the surface of the multilayer wiring part by a build-up method. Forming on one side of the material;
And a step of forming a plurality of fins on the other surface of the thermally conductive base material to form a heat sink. 電子部品を内蔵するための切欠き部と、上下導通ビアポストを備えた絶縁樹脂層を下層の上に直接形成し、前記切欠き部に電子部品を内蔵させることにより、前記電子部品内蔵層を形成することを特徴とする請求項１に記載の電子装置の製造方法。   Forming a notch for embedding electronic components and an insulating resin layer with vertical conduction via posts directly on the lower layer, and incorporating the electronic components in the notch, forming the electronic component built-in layer The method of manufacturing an electronic device according to claim 1. 下層の上に電子部品を載置した後、該電子部品を内蔵するように前記下層の上に上下導通ビアポストを備えた絶縁樹脂層を直接形成することにより、前記電子部品内蔵層を形成することを特徴とする請求項１に記載の電子装置の製造方法。   After mounting the electronic component on the lower layer, forming the electronic component built-in layer by directly forming an insulating resin layer having vertical conduction via posts on the lower layer so as to incorporate the electronic component The method of manufacturing an electronic device according to claim 1. 前記熱伝導性基材として、前記多層配線部との接合面内方向の熱膨張係数が２〜２０ｐｐｍの範囲内である材料を使用することを特徴とする請求項１乃至請求項３のいずれかに記載の電子装置の製造方法。 The material according to any one of claims 1 to 3 , wherein a material having a thermal expansion coefficient in a range of 2 to 20 ppm in an in-bonding direction with the multilayer wiring portion is used as the thermally conductive base material. The manufacturing method of the electronic device as described in 1 .. 多層配線部の前記入出力端子上に外部電極部材を形成する工程を有することを特徴とする請求項１乃至請求項４のいずれかに記載の電子装置の製造方法。 Method of manufacturing an electronic device according to any one of claims 1 to 4 characterized by having a step of forming an external electrode member on the input and output terminals of the multilayered wiring portion. 前記電子部品として、ＬＳＩチップ、ＩＣチップ、ＬＣＲ電子部品、センサ部品のいずれか１種または２種以上を使用することを特徴とする請求項１乃至請求項５のいずれかに記載の電子装置の製造方法。 Wherein as the electronic component, LSI chips, IC chips, LCR electronic component, an electronic device according to any one of claims 1 to 5, characterized by using one kind or two or more kinds of sensor components Production method.
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