JP2004047666A - Multilayer wiring board, its manufacturing method, and method for manufacturing resin-sealed semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board which can accurately and efficiently manufacture a small-sized thin resin-sealed semiconductor device, and to provide a method for manufacturing the multilayer printed circuit substrate and a method for manufacturing the small-sized thin resin-sealed semiconductor device. <P>SOLUTION: The multilayer wiring board includes a plurality of internal terminal wirings, formed in a disposition corresponding to a placing position of a semiconductor element, and a plurality of external terminal wirings corresponding to the respective internal terminal wirings, in such a manner that the thickness is in the range of 30-150 μm, the internal terminal wirings are formed of one or more layer wirings, formed on the respective external terminal wirings via an electrical insulating layer, the wirings have required continuity with the external terminal wirings or other layer wiring through a via part formed on the insulating layer, the via part has a diameter of 100 μm or smaller and a minimum forming pitch is 200 μm or smaller. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a resin-encapsulated semiconductor device, a multilayer wiring board used for the method, and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, semiconductor devices have been increasingly integrated and improved in performance as represented by LSI ASICs due to the trend of higher performance, smaller size, and thinner electronic devices. In the manufacture of a conventional semiconductor device, a semiconductor element is mounted on each multilayer wiring board, and wire bonding, resin sealing, and the like are performed to assemble the semiconductor device.
A multilayer wiring board used for manufacturing a conventional resin-encapsulated semiconductor device has an internal terminal wiring provided on one surface of a core substrate and an external terminal wiring provided on the other surface. The continuity between the internal terminal wiring and the external terminal wiring is established through the wiring.
[0003]
[Problems to be solved by the invention]
However, the thickness of such a multilayer wiring board is limited by the presence of the core substrate, which hinders the thinning of the semiconductor device. Further, the production of a multilayer wiring board requires a plurality of steps such as a through-hole forming step and a conduction step for the core substrate, and the operation is extremely complicated.
The present invention has been made in view of the above-described circumstances, and provides a multilayer wiring board and a method for manufacturing the same, which can produce a small and thin resin-encapsulated semiconductor device with high accuracy and high efficiency, and It is an object of the present invention to provide a method of manufacturing a small and thin resin-sealed semiconductor device.
[0004]
[Means for Solving the Problems]
In order to achieve such an object, a multilayer wiring board according to the present invention includes a plurality of internal terminal wirings formed in an arrangement corresponding to a mounting position of a semiconductor element and a plurality of external terminal wirings corresponding to each internal terminal wiring. Wherein each of the internal terminal wirings comprises one or more wirings formed on each of the external terminal wirings via an electric insulating layer, and the wirings are formed by the electric insulating layer. The vias formed in the first and second layers provide necessary continuity with external terminal wirings and wirings in other layers, and the vias have a diameter of 100 μm or less and a minimum formation pitch of 200 μm or less.
The method for manufacturing a multilayer wiring board according to the present invention includes a step of forming a metal conductive layer on one surface of a base substrate, and a step of forming a metal conductive layer on the metal conductive layer with an electric insulating layer interposed therebetween and a via portion formed in the electric insulating layer. Forming a plurality of internal terminal wirings in an arrangement corresponding to the mounting position of the semiconductor element by providing at least one layer of wiring with good electrical continuity; removing the base substrate to expose the metal conductive layer; And a step of pattern-etching the metal conductive layer to form a plurality of external terminal wirings corresponding to each internal terminal wiring.
[0005]
As a preferred embodiment of the present invention, a configuration in which a concave portion is formed in advance on one surface of the base substrate so as to correspond to the external terminal of the external terminal wiring, and a metal conductive layer is formed on the surface where the concave portion is formed. did.
In a preferred aspect of the present invention, the base substrate has a configuration in which the coefficient of thermal expansion in the XY directions is in a range of 2 to 20 ppm.
In a preferred aspect of the present invention, the base substrate is made of one of silicon, glass, and 42 alloy.
In a preferred embodiment of the present invention, the metal conductive layer is made of copper.
[0006]
The method of manufacturing a resin-encapsulated semiconductor device of the present invention includes a step of mounting a semiconductor element on each internal terminal wiring of the multilayer wiring board, a step of resin-sealing the semiconductor element, Cutting and separating the resin to obtain individual resin-sealed semiconductor devices.
Further, in the method for manufacturing a resin-encapsulated semiconductor device of the present invention, a step of forming a metal conductive layer on one surface of a base substrate, and a step of forming the metal insulating layer on the metal insulating layer with an electrical insulating layer interposed therebetween. Forming a plurality of internal terminal wirings in an arrangement corresponding to the mounting position of the semiconductor element by providing one or more layers of wiring required for conduction in the via portion, and forming a semiconductor element on each internal terminal wiring And thereafter, the step of resin-sealing the semiconductor element, the step of removing the base substrate and exposing the metal conductive layer, and the step of pattern-etching the metal conductive layer to correspond to each internal terminal wiring. As described above, the method includes a step of forming a plurality of external terminal wirings and a step of cutting and separating the electric insulating layer and the sealing resin to obtain individual resin-sealed semiconductor devices.
[0007]
As a preferred embodiment of the present invention, a configuration in which a concave portion is formed in advance on one surface of the base substrate so as to correspond to the external terminal of the external terminal wiring, and a metal conductive layer is formed on the surface where the concave portion is formed. did.
In a preferred aspect of the present invention, the base substrate has a configuration in which the coefficient of thermal expansion in the XY directions is in a range of 2 to 20 ppm.
In a preferred aspect of the present invention, the base substrate is made of one of silicon, glass, and 42 alloy.
In a preferred embodiment of the present invention, the metal conductive layer is made of copper.
In the present invention as described above, the core substrate is not present in the multilayer wiring substrate, and the multilayer wiring substrate has a small thickness. In addition, the step of conducting is unnecessary.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Multilayer wiring board
FIG. 1 is a partial longitudinal sectional view showing one embodiment of the multilayer wiring board of the present invention. In FIG. 1, a multilayer wiring board 1 according to the present invention includes a plurality of internal terminal wirings 2 formed in a planar shape in an arrangement corresponding to a mounting position of a semiconductor element, and a plurality of external terminal wirings corresponding to each internal terminal wiring 2. 5 is provided.
[0009]
The plurality of internal terminal wirings 2 constituting the multilayer wiring board 1 are multilayer wirings in the illustrated example, and are provided on the external terminal wirings 5 via the first electrical insulating layer 3a at the via portions 4a. A first-layer wiring 2a formed so as to be electrically connected to a predetermined first-layer wiring 2a at a via portion 4b via a second-layer electric insulating layer 3b on the first-layer wiring 2a; The second-layer wiring 2b formed so as to be electrically connected to a predetermined second-layer wiring 2b at the via portion 4c via the third-layer electric insulating layer 3c on the second-layer wiring 2b. And the third-layer wiring 2c formed as described above. Further, an internal terminal (not shown) for mounting a semiconductor element is set in the third layer wiring 2c. A plurality of such internal terminal wirings 2 are formed in a planar manner (along a plane parallel to each wiring layer constituting the internal terminal wirings) in an arrangement corresponding to the mounting position of the semiconductor element. Two sets of 2A and 2B are shown.
[0010]
The plurality of external terminal wirings 5 constituting the multilayer wiring board 1 are formed so as to be electrically connected to predetermined internal terminal wirings 2 (2a) at the via portions 4a via the electric insulating layer 3a. The external terminal wiring 5 is provided with external terminals (not shown) to be mounted on a printed wiring board or the like after being assembled into a semiconductor device. A plurality of such external terminal wirings 5 are formed so as to correspond to the respective internal terminal wirings 2. In the illustrated example, two sets of 5A and 5B are shown. In the present invention, solder balls may be provided on the external terminals of the external terminal wiring 5. Further, as shown in FIG. 2, the external terminal wiring 5 may be integrally provided with a convex external terminal 5a.
[0011]
The material of the first-layer wiring 2a, the second-layer wiring 2b, and the third-layer wiring 2c and the material of the via portions 4a, 4b, and 4c constituting the internal terminal wiring 2 are copper, silver, and gold. , Chromium, nickel or the like. The thickness of the wirings 2a, 2b, 2c can be appropriately set, for example, within a range of 0.5 to 10 μm. The diameter of the via portions 4a, 4b, 4c is 100 μm or less, preferably 10 to 50 μm, and the minimum pitch of the via portions 4a, 4b, 4c in each layer is 200 μm or less, preferably 50 to 180 μm. And If the diameter of the via exceeds 100 μm or the minimum formation pitch exceeds 200 μm, the effect of miniaturizing the semiconductor device cannot be sufficiently obtained.
[0012]
The material of the electric insulating layers 3a, 3b, 3c is an organic insulating material such as an epoxy resin, a benzocyclobutene resin, a cardo resin, a polyimide resin, or an insulating material such as a combination of these organic materials and glass fiber. It can be. In particular, for example, when the second-layer wiring 2b is a ground and the first-layer wiring 2a and the third-layer wiring 2c are signal lines, the second-layer electrical insulation layer 3b and the third-layer electrical insulation are provided. The material of the layer 3c is preferably an insulating material having a low dielectric constant and a low dielectric loss tangent, such as a benzocyclobutene resin, a cardo resin, and a polyimide resin. The thickness of the electric insulating layers 3a, 3b, 3c can be set appropriately, for example, within a range of 1 to 20 μm.
The external terminal wiring 5 can be formed using a conductive material such as copper, nickel, and gold.
Such a multilayer wiring board 1 has a thickness of 30 to 150 μm, preferably 30 to 100 μm. If the thickness of the multilayer wiring board 1 is less than 30 μm, the mechanical strength is insufficient, and if it exceeds 150 μm, the effect of reducing the thickness of the semiconductor device cannot be sufficiently obtained.
[0013]
In the multilayer wiring board 1 of the present invention as described above, the thickness is small because there is no core substrate having through holes. Further, in the conventional multilayer wiring board, a wiring layer is formed on both surfaces of the core substrate to prevent warpage, and the balance is maintained. However, in the present invention, since the core substrate does not exist, wiring formation is limited. Even without this, the occurrence of warpage is prevented. Further, the formation density of the via portion can be increased, and the semiconductor device can be further reduced in thickness and size as compared with a conventional multilayer wiring substrate.
The multilayer wiring board of the present invention is not limited to the one shown in the above embodiment, and the internal terminal wiring may have two or four or more layers.
[0014]
Method for manufacturing multilayer wiring board
Next, a method for manufacturing a multilayer wiring board according to the present invention will be described with reference to the drawings.
3 and 4 are process diagrams showing one embodiment of a manufacturing method using the multilayer wiring board 1 of the present invention shown in FIG. 1 as an example.
In the method for manufacturing a multilayer wiring board of the present invention, first, the metal conductive layer 15 is formed on one surface 11a of the base substrate 11 (FIG. 3A). The base substrate 11 is made of a material having a coefficient of thermal expansion in the XY direction (a plane parallel to the surface 11a of the base substrate 11) of 2 to 20 ppm, preferably 2.5 to 17 ppm, for example, silicon, glass, and 42 alloy. (Iron nickel alloy) or the like can be used. The thickness of the base substrate 11 can be appropriately set, for example, within a range of about 100 to 1000 μm. The metal conductive layer 15 is to be patterned in a later-described step to become an external terminal wiring, and may be made of a material such as copper, nickel, and chromium. The metal conductive layer 15 can be formed by plating, or can be formed as a laminated film of sputtering and plating, and the thickness can be appropriately set, for example, within a range of about 0.1 to 50 μm. it can.
[0015]
Next, a plurality of internal terminal wirings 2 are formed on the metal conductive layer 15 in an arrangement corresponding to the mounting position of the semiconductor element (FIG. 3B). In the illustrated example, two sets of internal terminal wirings 2A and 2B are shown. The internal terminal wiring 2 is formed by, for example, forming an electric insulating layer 3a on the metal conductive layer 15 and using a carbon dioxide gas laser, a UV-YAG laser, or the like to reduce the diameter of the metal conductive layer 15 so that a desired portion is exposed. Is formed at a predetermined position of the electric insulating layer 3a. Then, after washing, a conductive layer is formed by electroless plating in the hole and on the electric insulating layer 3a, a dry film resist is laminated on the conductive layer, and a desired pattern exposure and development are performed to form a resist pattern. I do. Thereafter, using the resist pattern as a mask, a conductive material is deposited by electroplating on the exposed portion including the hole to form the via portion 4a and the first-layer wiring 2a, and the resist pattern and the conductive layer are removed. This operation is repeated to form a plurality of build-up layers. In the illustrated example, a second-layer wiring 2b is formed on the first-layer wiring 2a so as to be connected to a predetermined first-layer wiring 2a at a via portion 4b via a second-layer electric insulating layer 3b. Then, a third-layer wiring 2c is formed on the second-layer wiring 2b so as to be connected to a predetermined second-layer wiring 2b at the via portion 4c via a third-layer electric insulating layer 3c. The wiring has a three-layer structure.
[0016]
Next, the base substrate 11 is removed to expose the metal conductive layer 15 (FIG. 4A). The removal of the base substrate 11 can be performed by polishing with a grinding device or the like. Next, the metal conductive layer 15 is pattern-etched to form a plurality of external terminal wirings 5 corresponding to the respective internal terminal wirings 2 to obtain the multilayer wiring board 1 (FIG. 4B). In the illustrated example, two sets of external terminal wirings 5A and 5B are shown corresponding to the two sets of internal terminal wirings 2A and 2B. The pattern etching of the metal conductive layer 15 can be performed by a known method.
In the method for manufacturing a multilayer wiring board of the present invention as described above, the metal conductive layer 15 is used, and the metal conductive layer 15 is patterned after the removal of the base substrate 11 to become the external terminal wiring 5. The internal terminal wires 2 are electrically connected as required in the step of forming the internal terminal wires 2 on the metal conductive layer 15. Therefore, the steps of forming a through hole and conducting in the through hole, which are required in the conventional method of manufacturing a multilayer wiring board, are not required, and the steps are simplified.
[0017]
When the external terminal wiring 5 is integrally provided with the convex external terminals 5a as described above (see FIG. 2), as shown in FIG. 5, the concave portions 12 correspond to the external terminals of the external terminal wiring. Is formed on one surface 11a of the base substrate 11 in advance, and the metal conductive layer 15 is formed on this surface. As a result, as shown by a chain line in FIG. 4B, the external terminal wiring 5 integrally provided with the convex external terminals 5a can be formed. The formation of the concave portion 12 in the base substrate 11 can be performed by wet etching, sand blasting, or the like, and the size of the concave portion 12 to be formed can be, for example, about 20 to 500 μm in opening diameter and about 10 to 250 μm in depth. .
The method for manufacturing a multilayer wiring board of the present invention is not limited to the method shown in the above-described embodiment, and may be applied to a case where a multilayer wiring board having two or four or more internal terminal wiring layers is manufactured. Can be applied.
[0018]
Method for manufacturing resin-encapsulated semiconductor device
Next, a method for manufacturing the resin-sealed semiconductor device of the present invention will be described with reference to the drawings.
FIG. 6 is a process chart showing one embodiment of a method for manufacturing a resin-encapsulated semiconductor device using the multilayer wiring board 1 of the present invention shown in FIG. 1 as an example.
In the method of manufacturing a resin-encapsulated semiconductor device of the present invention, first, the semiconductor element 22 is mounted on each internal terminal wiring 2 of the multilayer wiring board 1 (FIG. 6A). The semiconductor element 22 can be mounted on the internal terminal of the internal terminal wiring 2 via a metal bump 23 made of solder or the like. In the illustrated example, a semiconductor element 22 is mounted on each of two sets of internal terminal wirings 2A and 2B.
[0019]
Next, the mounted semiconductor element 22 is covered and sealed with a sealing member 24 (FIG. 6B). As the sealing member 24, a conventionally known sealing member can be used. For example, a sealing agent in which silica powder is dispersed in an epoxy resin can be used.
Next, dicing is performed to cut the multilayer wiring board 1 and the sealing member 24 at predetermined positions for each semiconductor element 22, thereby obtaining individual semiconductor devices 21 (FIG. 6C).
In the method of manufacturing a resin-encapsulated semiconductor device of the present invention as described above, since the steps of forming a through-hole and conducting in the through-hole are not required, the steps are simple and the obtained resin encapsulation is achieved. Since the core type semiconductor device does not have a core substrate, the thickness can be reduced. In addition, since the steps from mounting semiconductor elements to resin encapsulation on multiple surfaces are simultaneously performed on the multilayer wiring board, highly accurate resin-encapsulated semiconductor devices can be manufactured.
[0020]
7 and 8 are process diagrams showing another embodiment of the method for manufacturing a resin-encapsulated semiconductor device of the present invention.
In the method for manufacturing a resin-encapsulated semiconductor device of the present invention, first, a metal conductive layer 15 'is formed on one surface 31a of a base substrate 31 (FIG. 7A). The base substrate 31 is made of a material having a coefficient of thermal expansion in the XY direction (a plane parallel to the surface 31a of the base substrate 31) of 2 to 20 ppm, preferably 2.5 to 17 ppm, for example, silicon, glass, and 42 alloy. (Iron nickel alloy) or the like can be used. The thickness of the base substrate 31 can be appropriately set, for example, within a range of about 100 to 1000 μm. The metal conductive layer 35 'is to be patterned into external terminal wiring in a step described later, and may be made of a material such as copper or nickel. The metal conductive layer 35 ′ can be formed by plating, or can be formed as a laminated film of sputtering and plating, and the thickness of the metal conductive layer 35 ′ is appropriately set within a range of, for example, about 0.1 to 50 μm. Can be set.
[0021]
Next, a plurality of internal terminal wirings 32 are formed on the metal conductive layer 35 'in an arrangement corresponding to the mounting position of the semiconductor element (FIG. 7B). In the illustrated example, two sets of internal terminal wirings 32A and 32B are shown. The internal terminal wiring 32 is formed, for example, by forming an electric insulating layer 33a on the metal conductive layer 35 'and exposing a desired portion of the metal conductive layer 35' using a carbon dioxide gas laser, a UV-YAG laser, or the like. Then, a small-diameter hole is formed at a predetermined position in the electric insulating layer 33a. Then, after washing, a conductive layer is formed by electroless plating in the hole and on the electric insulating layer 33a, and a resist pattern is formed by laminating a dry film resist on the conductive layer and performing desired pattern exposure and development. I do. Thereafter, using the resist pattern as a mask, a conductive material is deposited by electroplating on the exposed portion including the hole to form the via portion 34a and the first-layer wiring 32a, and the resist pattern and the conductive layer are removed. This operation is repeated to form a plurality of buildup layers. In the illustrated example, a second-layer wiring 32b is formed on the first-layer wiring 32a so as to be connected to a predetermined first-layer wiring 32a at a via portion 34b via a second-layer electric insulating layer 33b. Then, a third-layer wiring 32c is formed on the second-layer wiring 32b so as to be connected to a predetermined second-layer wiring 32b at a via portion 34c via a third-layer electric insulating layer 33c. The wiring has a three-layer structure.
[0022]
Next, the semiconductor element 42 is mounted on each internal terminal wiring 32 formed as described above (FIG. 7C). The semiconductor element 42 can be mounted on the internal terminals of the internal terminal wiring 32 via metal bumps 43 such as solder. In the illustrated example, a semiconductor element 42 is mounted on each of the two sets of internal terminal wirings 32A and 32B.
Next, the mounted semiconductor element 42 is covered and sealed with a sealing member 44 (FIG. 8A). As the sealing member 44, a conventionally known sealing member can be used. For example, a sealing agent in which silica powder is dispersed in an epoxy resin can be used.
Next, the base substrate 31 is polished and removed to expose the metal conductive layer 35 '(FIG. 8B). The removal of the base substrate 31 can be performed by polishing with a grinding device or the like.
[0023]
Next, the metal conductive layer 35 'is pattern-etched to form a plurality of external terminal wirings 35 corresponding to each internal terminal wiring 32 (FIG. 8C). In the illustrated example, two sets of external terminal wirings 35A and 35B are formed so as to correspond to the two sets of internal terminal wirings 32A and 32B. The pattern etching of the metal conductive layer 35 'can be performed by a known method.
Next, dicing is performed to cut the electrical insulating layers 33a, 33b, 33c and the sealing member 44 at predetermined positions for each semiconductor element 42, whereby individual semiconductor devices can be obtained.
[0024]
In the method of manufacturing a resin-encapsulated semiconductor device of the present invention as described above, the base substrate 31 is removed in a later step, so that the steps of forming a through hole and conducting in the through hole are unnecessary. In addition to being simple, the resulting resin-encapsulated semiconductor device does not have a core substrate and can be made thin. In addition, since the steps from mounting of the semiconductor element to resin encapsulation on multiple surfaces are simultaneously performed on the base substrate 31, a highly accurate resin-encapsulated semiconductor device can be manufactured.
The method for manufacturing the resin-encapsulated semiconductor device of the present invention is not limited to the one described in the above embodiment, and the internal terminal wiring may have two or four or more layers. There is no limitation on the number of semiconductor elements mounted on one semiconductor device.
[0025]
【Example】
Next, the present invention will be described in more detail with reference to specific examples.
[Example 1]
As a base substrate, a 42 μm thick alloy having a thickness of 300 μm was prepared, and a metal conductive layer having a thickness of 30 μm was formed on one surface of the base substrate by electrolytic copper plating. The coefficient of thermal expansion in the XY directions of the used 42 alloy was 8 ppm.
Next, a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co.) was applied on the metal conductive layer by a spin coater and dried to form an electric insulating layer having a thickness of 10 μm.
[0026]
Next, exposure and development were performed to form small-diameter holes (30 μm in inner diameter) at predetermined positions in the electric insulating layer at a formation pitch of 80 to 200 μm so that desired portions of the metal conductive layer were exposed. After washing, a conductive layer made of copper and chromium was formed in the hole and on the electric insulating layer by sputtering, and a dry film resist (APR manufactured by Asahi Kasei Corporation) was laminated on the conductive layer. Next, the resist was exposed and developed through a first layer wiring forming photomask to form a wiring forming resist pattern. Using this resist pattern as a mask, electrolytic copper plating (5 μm thickness) was performed, and then the resist pattern and the conductive layer were removed. Thus, the first-layer wiring was formed on the metal conductive layer via the electric insulating layer. The diameter of the via portion was 30 μm, and the minimum formation pitch of the via portion was 80 μm.
Further, the same operation was performed to form a second-layer wiring on the first-layer wiring via the electric insulating layer, and a third-layer wiring on the second-layer wiring via the electric insulating layer.
As a result, a plurality of internal terminal wirings having a three-layer wiring structure were formed in an arrangement corresponding to the mounting position of the semiconductor element (a grid-like arrangement of 20 mm × 20 mm).
[0027]
Next, the 42 alloy as the base substrate was polished and removed by a grinding device, exposing the metal conductive layer as the copper layer. Next, a photosensitive resist (LA900, manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the exposed metal conductive layer, and exposed and developed through a photomask for external terminal wiring to form a resist pattern. Using this resist pattern as a mask, the metal conductive layer was etched with copper chloride, and then the resist pattern was removed with acetone to form a plurality of external terminal wires corresponding to each internal terminal wire.
Thus, the multilayer wiring board of the present invention was obtained. The thickness of this multilayer wiring board was 30 μm, which was much smaller than the thickness (generally 300 to 1000 μm) of a conventional multilayer wiring board having a core substrate.
[0028]
Next, a resin-sealed semiconductor device was manufactured using the above-described multilayer wiring board. That is, first, a semiconductor element (10 mm × 10 mm, thickness 0.2 mm) was mounted on the internal terminal of each internal terminal wiring of the multilayer wiring board via a solder bump.
Next, sealing was performed with an epoxy-based sealing agent so as to cover the mounted semiconductor element. The thickness of the sealing member was 0.3 mm. Next, dicing was performed to cut the multilayer wiring board and the sealing member at predetermined positions for each semiconductor element, thereby obtaining individual resin-sealed semiconductor devices.
The size of the resin-encapsulated semiconductor device manufactured in this manner was 20 mm × 20 mm and the thickness was 0.33 mm.
[0029]
[Example 2]
A 42 μm-thick alloy having a thickness of 200 μm is prepared as a base substrate, a photosensitive resist (LA900, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied to one surface of the base substrate, and exposed and developed through a photomask of an external terminal. Thus, a resist pattern was formed. Using this resist pattern as a mask, the base substrate was etched with iron chloride to form a recess (for forming external terminals) having an opening diameter of 100 μm and a depth of 30 μm. The coefficient of thermal expansion in the XY directions of the used 42 alloy was 8 ppm.
Next, a photosensitive resist (LA900, manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied onto the base substrate having the concave portions formed thereon, and exposed and developed through a photomask for external terminal wiring to form a resist pattern. . Using this resist pattern as a mask, electrolytic nickel plating (thickness 1 μm), electrolytic gold plating (thickness 0.3 μm), electrolytic nickel plating (thickness 1 μm), and electrolytic copper plating (thickness 5 μm) were sequentially applied to form a metal conductive layer. Thereafter, the recesses were filled with a conductive paste containing copper particles.
[0030]
Next, internal terminal wirings having a three-layer wiring structure are arranged on the metal conductive layer in an arrangement corresponding to the mounting position of the semiconductor element (a lattice-like arrangement of 10 mm × 10 mm) in the same manner as in the first embodiment. Further, a plurality of the external terminals were formed in an arrangement corresponding to the concave portions for forming the external terminals. The diameter of the via portion in this internal terminal wiring was 30 μm, and the minimum formation pitch of the via portion was 90 μm.
Next, a semiconductor element (10 mm × 10 mm, 0.2 mm thick) was mounted on the internal terminals of each internal terminal wiring formed on the metal conductive layer via solder bumps. Thereafter, sealing was performed with an epoxy sealing agent so as to cover the mounted semiconductor element. The thickness of the sealing member was 0.3 mm.
[0031]
Next, the alloy 42 as the base substrate was polished and removed by etching with iron chloride to expose the metal conductive layer as the copper layer. On the surface of the metal conductive layer exposed in this manner, there was a projection (height: 30 μm) corresponding to the above-mentioned depression for forming an external terminal, and an external terminal wiring was also formed at the same time.
Next, dicing was performed to cut the multilayer wiring board and the sealing member at predetermined positions for each semiconductor element, thereby obtaining individual resin-sealed semiconductor devices.
The size of the resin-encapsulated semiconductor device manufactured in this manner was 20 mm × 20 mm and the thickness was 0.33 mm.
[0032]
[Comparative example]
As a multilayer wiring board, a double-sided wiring board based on a polyimide resin film having a thickness of 75 μm was prepared. A semiconductor element was mounted on this double-sided wiring board in the same manner as in the example, and resin-sealing and dicing were performed to obtain a resin-sealed semiconductor device.
However, in the production of the above resin-encapsulated semiconductor device, the workability of mounting the semiconductor element on the film wiring board is poor.
The size of the manufactured semiconductor device was 40 mm × 40 mm and the thickness was 0.375 mm, and the thickness was about the same as that of the resin-sealed semiconductor device manufactured in the example. However, due to the low wiring density of the double-sided wiring board (L / S = 30 μm / 30 μm), the area of the resin-encapsulated semiconductor device was large.
[0033]
【The invention's effect】
As described in detail above, the multilayer wiring board of the present invention has a configuration in which a core board having a through hole does not exist, and unlike a conventional multilayer wiring board having a core board, warpage due to the influence of the number of wiring layers is different from the conventional multilayer wiring board having a core board. No generation occurs, the thickness is small, the formation density of the via portion can be increased, and a small and thin resin-sealed semiconductor device can be manufactured. Further, in the above-described method for manufacturing a multilayer wiring board, a metal conductive layer is used, and this metal conductive layer is patterned after removal of the base substrate to become external terminal wiring. Is unnecessary, and the process becomes simple. Furthermore, in the method of manufacturing a resin-sealed semiconductor device of the present invention, since the steps of forming a through-hole and conducting in the through-hole are not required, the steps are simple and a thin resin-sealed without a core substrate is provided. It is possible to manufacture a semiconductor device with a fixed type, and since it is possible to simultaneously mount semiconductor elements on a multi-layered wiring board (base substrate) and perform resin encapsulation on a multi-layered wiring board (base substrate), it is possible to manufacture a highly accurate resin-encapsulated semiconductor device. It is possible.
[Brief description of the drawings]
FIG. 1 is a partial longitudinal sectional view showing one embodiment of a multilayer wiring board of the present invention.
FIG. 2 is a partial longitudinal sectional view showing another embodiment of the multilayer wiring board of the present invention.
FIG. 3 is a process chart showing one embodiment of a method for manufacturing a multilayer wiring board of the present invention.
FIG. 4 is a process chart showing one embodiment of a method for manufacturing a multilayer wiring board of the present invention.
FIG. 5 is a drawing for explaining another embodiment of the method for manufacturing a multilayer wiring board of the present invention.
FIG. 6 is a process diagram showing one embodiment of a method for manufacturing a resin-sealed semiconductor device of the present invention.
FIG. 7 is a process chart showing another embodiment of the method for manufacturing a resin-sealed semiconductor device of the present invention.
FIG. 8 is a process diagram showing another embodiment of the method for manufacturing a resin-sealed semiconductor device of the present invention.
[Explanation of symbols]
1. Multilayer wiring board
2, 2A, 2B ... internal terminal wiring
2a, 2b, 2c ... wiring
3a, 3b, 3c ... electric insulating layer
4a, 4b, 4c: Via portion
5,5A, 5B ... External terminal wiring
5a ... External terminal
11 Base board
12 ... recess
15 ... Metal conductive layer
21: Resin-sealed semiconductor device
22 ... Semiconductor element
24 sealing member
31 ... Base substrate
35 '... Metal conductive layer
32, 32A, 32B ... internal terminal wiring
32a, 32b, 32c ... wiring
33a, 33b, 33c ... electric insulating layer
34a, 34b, 34c ... via part
35, 35A, 35B ... external terminal wiring
42 ... Semiconductor element
44 sealing member

Claims (12)

A plurality of internal terminal wirings formed in an arrangement corresponding to the mounting position of the semiconductor element, and a plurality of external terminal wirings corresponding to the respective internal terminal wirings; The wiring comprises one or more layers of wiring formed on each external terminal wiring via an electric insulating layer, and the wiring is connected to external terminal wiring and wiring of another layer by a via portion formed in the electric insulating layer. The multilayer wiring board is characterized in that necessary conduction is provided, the via portion has a diameter of 100 μm or less, and the minimum formation pitch is 200 μm or less. Forming a metal conductive layer on one surface of the base substrate;
By providing one or more layers of wiring on the metal conductive layer through an electrical insulating layer and having the necessary conduction at via portions formed in the electrical insulating layer, a plurality of wirings can be arranged in a position corresponding to the mounting position of the semiconductor element. Forming an internal terminal wiring of
Removing the base substrate, exposing the metal conductive layer,
Forming a plurality of external terminal wirings corresponding to each internal terminal wiring by pattern-etching the metal conductive layer. The method according to claim 2, wherein a concave portion is formed in advance on one surface of the base substrate so as to correspond to the external terminal of the external terminal wiring, and a metal conductive layer is formed on the surface where the concave portion is formed. A method for manufacturing a multilayer wiring board. 4. The method according to claim 2, wherein the base substrate has a thermal expansion coefficient in the XY directions within a range of 2 to 20 ppm. 5. The method according to claim 4, wherein the base substrate is made of one of silicon, glass, and 42 alloy. The method according to any one of claims 2 to 5, wherein the metal conductive layer is made of copper. Mounting a semiconductor element on each internal terminal wiring of the multilayer wiring board according to claim 1;
Resin sealing the semiconductor element;
A method of cutting and separating the multilayer wiring board and the sealing resin to obtain individual resin-sealed semiconductor devices. Forming a metal conductive layer on one surface of the base substrate;
By providing one or more layers of wiring on the metal conductive layer through an electrical insulating layer and having the necessary conduction at via portions formed in the electrical insulating layer, a plurality of wirings can be arranged in a position corresponding to the mounting position of the semiconductor element. Forming an internal terminal wiring of
Mounting a semiconductor element on each internal terminal wiring, and thereafter, sealing the semiconductor element with a resin;
Removing the base substrate, exposing the metal conductive layer,
Forming a plurality of external terminal wires so as to correspond to each internal terminal wire by pattern etching the metal conductive layer,
A method of cutting and separating an electric insulating layer and a sealing resin to obtain individual resin-sealed semiconductor devices. 9. The method according to claim 8, wherein a concave portion is formed in advance on one surface of the base substrate so as to correspond to the external terminal of the external terminal wiring, and a metal conductive layer is formed on the surface where the concave portion is formed. A method for manufacturing a resin-sealed semiconductor device. The method of manufacturing a resin-encapsulated semiconductor device according to claim 8, wherein the base substrate has a coefficient of thermal expansion in the XY directions within a range of 2 to 20 ppm. The method according to claim 10, wherein the base substrate is made of any one of silicon, glass, and 42 alloy. 12. The method according to claim 8, wherein the metal conductive layer is made of copper.

Images