CN116825746A

CN116825746A - Semiconductor packaging structure and manufacturing method thereof

Info

Publication number: CN116825746A
Application number: CN202310816667.8A
Authority: CN
Inventors: 叶国梁; 胡胜; 占琼; 谭学聘; 赵常宝
Original assignee: Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Current assignee: Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority date: 2023-07-03
Filing date: 2023-07-03
Publication date: 2023-09-29

Abstract

The application provides a semiconductor packaging structure and a manufacturing method thereof, wherein the semiconductor packaging structure comprises a first adapter plate and a second adapter plate, a first circuit structure is formed in the first adapter plate, a second circuit structure is formed in the second adapter plate, electric connection between a chip and a PCB (printed circuit board) is realized through the architecture of the two adapter plates, and multiple electronic functions are realized through matching of the first circuit structure and the second circuit structure. The adapter plate can be formed by a traditional semiconductor process, and is low in cost and high in process reliability, so that the formed semiconductor packaging structure can be low in cost and high in performance.

Description

Semiconductor packaging structure and manufacturing method thereof

Technical Field

The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor package and a method for manufacturing the same.

Background

In electronic equipment, the chip is generally required to be connected with the PCB through the IC carrier board, so that more electronic functions can be realized through the internal circuit on the IC carrier board, and the chip can be well cooled, so that a certain protection effect is achieved. The IC carrier, also called package substrate, can be divided into BT carrier and ABF carrier according to the difference of the base materials, and compared with BT carrier, ABF carrier has higher operation performance, mainly used for CPU, GPU, FPGA, ASIC etc. high operation performance chips.

Among the upstream materials of integrated circuit packages, the substrate material (simply referred to as the substrate) is the largest cost end of the IC carrier, the ABF carrier, i.e., the substrate is the ABF (flavored plain film) carrier, which is developed by the flavored plain corporation, and the monopoly material sources, and correspondingly, the cost is also more expensive. In addition, the product yield of the ABF carrier plate is greatly reduced along with the increase of the area and the number of layers, thereby further leading to the high price of the ABF carrier plate. In the prior art, in order to prepare a high-performance package structure, an ABF carrier is often required. How to solve this problem, obtaining a low-cost and high-performance package structure has been pursued by those skilled in the art.

Disclosure of Invention

The application aims to provide a semiconductor packaging structure and a manufacturing method thereof, which are used for solving the problem that the semiconductor packaging structure in the prior art cannot have low cost and high performance.

In order to solve the above technical problem, the present application provides a semiconductor package structure, including:

a PCB board;

the first switching board is positioned on the PCB, a first circuit structure is formed in the first switching board, and the first switching board is electrically connected with the PCB;

the second adapter plate is positioned on the first adapter plate, a second circuit structure is formed in the second adapter plate, and the second adapter plate is electrically connected with the first adapter plate; the method comprises the steps of,

and the chips are positioned on the second adapter plate and are electrically connected with the second adapter plate.

Optionally, in the semiconductor package structure, the second interposer is electrically connected to the first interposer through a hybrid bonding structure.

Optionally, in the semiconductor packaging structure, each chip is electrically connected with the second interposer through a micro bump.

Optionally, in the semiconductor package structure, the second circuit structure includes a rewiring layer, and the number of layers of the rewiring layer is between 6 and 9.

Optionally, in the semiconductor packaging structure, a minimum line width of the first interposer and the second interposer is less than or equal to 1 μm.

Optionally, in the semiconductor packaging structure, the semiconductor packaging structure further includes an HDI board located between the PCB board and the first adapter board, where the HDI board is electrically connected to the first adapter board and the PCB board respectively.

Optionally, in the semiconductor package structure, the HDI board is a build-up printing plate.

Optionally, in the semiconductor packaging structure, the semiconductor packaging structure further includes a BT carrier board located between the PCB board and the first adapter board, where the BT carrier board is electrically connected to the first adapter board and the PCB board respectively.

The application also provides a manufacturing method of the semiconductor packaging structure, which comprises the following steps:

providing a first adapter plate and a second adapter plate, wherein a first circuit structure is formed in the first adapter plate, and a second circuit structure is formed in the second adapter plate;

electrically connecting the second adapter plate with the first adapter plate;

a plurality of chips are electrically connected to the second adapter plate; the method comprises the steps of,

and electrically connecting the first adapter plate with the PCB.

Optionally, in the method for manufacturing a semiconductor package, the step of electrically connecting the second interposer on the first interposer includes: and bonding the second adapter plate on the first adapter plate.

In the semiconductor packaging structure and the manufacturing method thereof provided by the application, the semiconductor packaging structure comprises a first adapter plate and a second adapter plate, a first circuit structure is formed in the first adapter plate, a second circuit structure is formed in the second adapter plate, the electric connection between a chip and a PCB (printed circuit board) is realized through the architecture of the two adapter plates, and multiple electronic functions are realized through the matching of the first circuit structure and the second circuit structure. The adapter plate can be formed by a traditional semiconductor process, and is low in cost and high in process reliability, so that the formed semiconductor packaging structure can be low in cost and high in performance.

Drawings

Fig. 1 is a schematic view of a semiconductor package according to an embodiment of the application.

Fig. 2 is a schematic diagram of another semiconductor package structure according to an embodiment of the present application.

Fig. 3 is a schematic diagram of another semiconductor package structure according to an embodiment of the present application.

Fig. 4 is a flow chart illustrating a method for manufacturing a semiconductor package according to an embodiment of the application.

Wherein reference numerals are as follows:

100-a semiconductor package structure; 110-a PCB board; 120-a first adapter plate; 121-a first circuit structure; 130-a second adapter plate; 131-a second line structure; 140-chip; 150-HDI board; 160-BT carrier plate.

Detailed Description

The semiconductor package structure and the method of manufacturing the same according to the present application are described in further detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the application will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise in the present document, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms first, second and the like in the description and in the claims, are not used for any order, quantity or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "upper/upper," "lower/lower," and the like are used for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

In the prior art, the connection between the chip and the PCB is realized through the ABF carrier plate, and the internal circuit on the ABF carrier plate can realize various electronic functions, but the ABF carrier plate has the problems of high price and reduced yield along with the increase of the area and the layer number.

The core idea of the application is to provide a new semiconductor packaging structure, which does not use the ABF carrier to realize the connection between the chip and the PCB, and correspondingly, the problems of the ABF carrier are avoided; meanwhile, a first adapter plate (interser) and a second adapter plate (interser) are adopted, a first circuit structure is formed in the first adapter plate, a second circuit structure is formed in the second adapter plate, electric connection between the chip and the PCB is realized through the framework of the two adapter plates, and multiple electronic functions are realized through matching of the first circuit structure and the second circuit structure, so that the requirements of electric connection and multiple electronic functions can be met. Meanwhile, the adapter plate can be formed through a traditional semiconductor process, and is low in cost and high in process reliability, so that the formed semiconductor packaging structure can be low in cost and high in performance.

Specifically, please refer to fig. 1, which is a schematic diagram of a semiconductor package structure according to an embodiment of the present application. As shown in fig. 1, in an embodiment of the present application, the semiconductor package structure 100 includes: a PCB 110; the first switching board 120 is located on the PCB 110, a first circuit structure 121 is formed in the first switching board 120, and the first switching board 120 is electrically connected with the PCB 110; the second interposer 130 is located on the first interposer 120, a second circuit structure 131 is formed in the second interposer 130, and the second interposer 130 is electrically connected with the first interposer 120; and a plurality of chips 140 disposed on the second interposer 130, wherein each chip 140 is electrically connected to the second interposer 130.

In the embodiment of the present application, the base materials of the first interposer 120 and the second interposer 130 are semiconductor materials and/or dielectric materials, and the first interposer 120 and the second interposer 130 can be obtained through a conventional semiconductor process, so that the process is mature, the cost is low, and the reliability and the yield are higher. Specifically, the substrates of the first interposer 120 and the second interposer 130 may include silicon, germanium-silicon, carbon-silicon, gallium arsenide, gallium nitride, silicon oxide, silicon nitride, and the like, and the substrates may be the same or different. In an embodiment of the present application, the substrates of the first interposer 120 and the second interposer 130 each comprise silicon.

In the embodiment of the present application, the first adapter board 120 has a first circuit structure 121. Further, the first circuit structure 121 may include a plurality of first via structures, and the first via structures may penetrate through the first circuit structure 121 substrate; alternatively, the first circuit structure 121 may include a plurality of first via structures, a rewiring layer electrically connected to the first via structures, and the like, and the rewiring layer may be located above the first circuit structure 121 substrate. For example, the first circuit structure 121 includes a plurality of first via structures, and in particular, the first adapter plate 120 has a plurality of via holes (not shown), and each of the via holes is filled with a conductive material to form the first circuit structure 121. Wherein the conductive material includes but is not limited to gold, silver, copper, aluminum, etc., and in the embodiment of the present application, the conductive material is copper. Wherein the minimum line width of the first transfer plate 120 may be less than or equal to 1 μm, for example, here, the line width of the first via structure may be less than or equal to 1 μm; alternatively, a line spacing between adjacent first via structures may be less than or equal to 1 μm.

Further, pads and/or hybrid bonding structures and/or Micro bumps (Micro bumps) (not shown) may be formed on two opposite surfaces of the first interposer 120, so as to facilitate electrical connection between the first interposer 120 and the second interposer 130, and between the PCB board 110.

With continued reference to fig. 1, in an embodiment of the present application, the second interposer 130 has a second circuit structure 131. Further, the second circuit structure 131 may include a plurality of second via structures (not shown) and a rewiring layer (not shown) electrically connected to the second via structures, where the second via structures may penetrate through the second circuit structure 131 substrate, and the rewiring layer may be located above the second circuit structure 131 substrate. Preferably, the number of rewiring layers in the second circuit structure 131 is between 6 and 9, i.e. the second circuit structure 131 may include 6 to 9 rewiring layers. Further, the minimum line width of the second interposer 130 may be less than or equal to 1 μm, for example, here, the line width of the second via structure may be less than or equal to 1 μm; alternatively, the line spacing between adjacent second via structures may be less than or equal to 1 μm.

In an embodiment of the present application, the second interposer 130 is electrically connected to the first interposer 120 through pads and/or hybrid bonding structures and/or Micro bumps (Micro bumps). Further, the surface of the second interposer 130 opposite to the surface of the first interposer 120 may also form a plurality of pads and/or hybrid bonding structures and/or Micro bumps (Micro bumps), so as to facilitate electrical connection between the two. Specifically, the first circuit structure 121 in the first interposer 120 is electrically connected to the second circuit structure 131 in the second interposer 130.

With continued reference to fig. 1, in an embodiment of the present application, a plurality of chips 140 are electrically connected to the second interposer 130, and two chips 140 are schematically shown in fig. 1. Specifically, the plurality of chips 140 may be chips having the same function or chips having different functions. For example, the plurality of chips 140 may be all memory chips, all logic chips, or part of energy chips and part of communication chips, etc., which is not limited to the present application.

Further, each of the chips 140 is electrically connected to the second interposer 130 through a bonding pad and/or a hybrid bonding structure and/or a Micro Bump (Micro Bump). Specifically, each of the chips 140 is electrically connected to the second circuit structure 131 through a bonding pad and/or a hybrid bonding structure and/or a micro bump.

In the embodiment of the present application, the first interposer 120 and the first circuit structure 121 therein, and the second interposer 130 and the second circuit structure 131 therein can implement various circuit connections and functions, thereby meeting the requirements of complex and high-performance circuit design, and further, matching with different chips 140, thereby implementing various electronic functions.

With continued reference to fig. 1, in an embodiment of the present application, the first adapter board 120 may be electrically connected to the PCB board 110 through a bonding pad and/or a hybrid bonding structure and/or a Micro Bump (Micro Bump).

In other embodiments of the present application, other functional carrier boards may be further included to further enhance the functionality of the semiconductor package 100. As shown in fig. 2, the semiconductor package structure 100 further includes an HDI board 150 located between the PCB 110 and the first adapter board 120, and the HDI board 150 is electrically connected to the first adapter board 120 and the PCB 110, respectively. For example, the HDI board 150 may be electrically connected to the first adapter board 120 through a bump, and electrically connected to the PCB 110 through a solder ball, which is not limited in the present application. Preferably, the HDI board 150 is a single-layered printing plate, so that the cost of the semiconductor package 100 can be avoided, and the requirement of richer electronic functions can be satisfied.

Referring to fig. 3, in another embodiment of the present application, the semiconductor package structure 100 further includes a BT carrier 160 located between the PCB 110 and the first adapter board 120, and the BT carrier 160 is electrically connected to the first adapter board 120 and the PCB 110, respectively. For example, the BT carrier 160 may be electrically connected to the first adapter 120 through a bump, and electrically connected to the PCB 110 through a solder ball, which is not limited in the present application. The BT carrier board 160 has a slightly cheaper price than the ABF board, and at the same time, the matching of the first adapter board 120 and the second adapter board 130 can realize a richer electronic function. Therefore, the cost of the formed semiconductor package structure 100 can be avoided from being higher, and the requirement of richer electronic functions can be met.

In yet another embodiment of the present application, the semiconductor package structure 100 further includes a BT carrier board 160 and an HDI board 150 between the PCB board 110 and the first adapter board 120.

Correspondingly, the application also provides a manufacturing method of the semiconductor packaging structure, please refer to fig. 4, which is a flow chart of the manufacturing method of the semiconductor packaging structure according to the embodiment of the application. As shown in fig. 4, the method for manufacturing the semiconductor package structure includes:

step S10: providing a first adapter plate and a second adapter plate, wherein a first circuit structure is formed in the first adapter plate, and a second circuit structure is formed in the second adapter plate;

step S20: electrically connecting the second adapter plate with the first adapter plate;

step S30: a plurality of chips are electrically connected to the second adapter plate; the method comprises the steps of,

step S40: and electrically connecting the first adapter plate with the PCB.

Specifically, the first adapter plate 120 and the second adapter plate 130 may be prepared simultaneously, or the first adapter plate 120 and the second adapter plate 130 may be prepared sequentially, that is, the first adapter plate 120 may be prepared first, then the second adapter plate 130 may be prepared, or the second adapter plate 130 may be prepared first, then the first adapter plate 120 may be prepared.

Next, step S20 may be performed to electrically connect the second interposer 130 and the first interposer 120 through bonding. Step S30 may be performed before step S20, and a plurality of chips may be electrically connected to the second interposer 130. Alternatively, step S40 may be performed before step S20, so as to electrically connect the first adapter board 120 with the PCB 110. That is, the sequence of steps S20, S30 and S40 is not limited in the present application, and the arrangement can be adjusted according to the line conditions. For example, step S20 and step S40 may be performed simultaneously, and then step S30 may be performed.

As can be seen from the above, in the semiconductor package structure and the method for manufacturing the same provided by the present application, the semiconductor package structure 100 includes the first interposer 120 and the second interposer 130, the first interposer 120 has the first circuit structure 121 formed therein, the second interposer 130 has the second circuit structure 131 formed therein, and the electrical connection between the chip 140 and the PCB 110 is realized by the architecture of the two interposers, and multiple electronic functions are realized by matching the first circuit structure 121 and the second circuit structure 131. The interposer may be formed by conventional semiconductor processes, which are inexpensive and have high process reliability, so that the formed semiconductor package structure 100 can have both low cost and high performance.

Furthermore, in other implementations of the application, various combinations of the claims and the embodiments described above can be made to form different embodiments, the application is not to be enumerated, and one of ordinary skill in the art can make many variations based on the disclosure without undue burden.

The above description is only illustrative of the preferred embodiments of the present application and is not intended to limit the scope of the present application, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. A semiconductor package structure, the semiconductor package structure comprising:

a PCB board;

2. The semiconductor package according to claim 1, wherein the second interposer is electrically connected to the first interposer through a hybrid bond structure.

3. The semiconductor package according to claim 1, wherein each of the chips is electrically connected to the second interposer through a micro bump.

4. A semiconductor package according to any one of claims 1 to 3, wherein the second wiring structure includes a rewiring layer having a number of layers between 6 and 9.

5. The semiconductor package according to any one of claims 1 to 3, wherein a minimum line width of the first interposer and the second interposer is less than or equal to 1 μm.

6. The semiconductor package according to claim 1, further comprising an HDI board between the PCB board and the first interposer, the HDI board being electrically connected to the first interposer and the PCB board, respectively.

7. The semiconductor package according to claim 6, wherein the HDI board is a single build-up printing plate.

8. The semiconductor package according to claim 1, further comprising a BT carrier positioned between the PCB and the first interposer, the BT carrier being electrically connected to the first interposer and the PCB, respectively.

9. A method of manufacturing a semiconductor package, the method comprising:

electrically connecting the second adapter plate with the first adapter plate;

and electrically connecting the first adapter plate with the PCB.

10. The method of manufacturing a semiconductor package according to claim 9, wherein the step of electrically connecting the second interposer on the first interposer comprises: and bonding the second adapter plate on the first adapter plate.