KR100452820B1 - Method of defining electrode for circut device, and chip package and multilayer board using that - Google Patents

Method of defining electrode for circut device, and chip package and multilayer board using that Download PDF

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Publication number
KR100452820B1
KR100452820B1 KR10-2002-0040712A KR20020040712A KR100452820B1 KR 100452820 B1 KR100452820 B1 KR 100452820B1 KR 20020040712 A KR20020040712 A KR 20020040712A KR 100452820 B1 KR100452820 B1 KR 100452820B1
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South Korea
Prior art keywords
method
electrode
formed
characterized
chip
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KR10-2002-0040712A
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Korean (ko)
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KR20040006434A (en
Inventor
안문봉
조광철
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삼성전기주식회사
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Priority to KR10-2002-0040712A priority Critical patent/KR100452820B1/en
Publication of KR20040006434A publication Critical patent/KR20040006434A/en
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Publication of KR100452820B1 publication Critical patent/KR100452820B1/en

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    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Abstract

본 발명은 칩 소자 또는 기판과 같은 회로소자에 전극을 형성하기 위한 방법과 그를 이용한 칩 패키지 및 다층기판에 관한 것으로, 보다 상세하게는 회로소자의 단자 영역에 보호범프 및 절연층을 형성하고 상기 보호범프를 제거하여 비아홀을 만드는 것에 의하여 다른 회로요소와 전기적으로 연결하기 위한 전극을 형성하는 방법 및 그를 이용한 칩 패키지 및 다층기판에 관한 것이다. The present invention forms the, more particularly, to protect the bumps and the insulating layer in the terminal areas of the circuit element to a method and a chip package and a multi-layer substrate using the same for forming an electrode on the circuit element such as a chip device or a substrate on which the protection a method of forming an electrode for electrically coupling to the other circuit elements by being removed to create a via hole and the bump using the same relates to a chip package and a multi-layer substrate.
본 발명은 복수개의 전극을 갖는 회로소자의 전극 상부에 일정두께의 보호 범프를 형성하는 단계; The present invention includes the steps of forming a protective bump having a predetermined thickness on the upper electrode of the circuit element having a plurality of electrodes; 상기 보호 범프 영역을 제외한 상기 회로소자 상에 절연층을 형성하는 단계; Forming an insulating layer on the circuit elements other than the bump protection region; 상기 보호 범프가 외부에 노출되도록 상기 절연층을 연마하는 단계; The protection step is to polish the bumps of the insulating layer so as to be exposed to the outside; 상기 보호 범프를 제거하여 전극이 외부에 노출되도록 하는 단계; Stage such that the electrode is exposed to the outside by removing the protective bumps; 상기 전극에 연결되는 도전층을 상기 절연층 상부에 형성하는 단계; Forming a conductive layer connected to the electrode on the insulating layer; 및 상기 도전층에 상기 전극에 대응하는 패턴을 형성하고, 상기 패턴 상에 외부전극을 형성하는 단계;를 포함하는 회로소자의 전극형성 방법을 제공한다. Provides an electrode forming method of a circuit device including a; and the step of the conductive layer to form a pattern corresponding to the electrode, forming an external electrode on the pattern.

Description

회로소자의 전극형성 방법, 그를 이용한 칩 패키지 및 다층기판{METHOD OF DEFINING ELECTRODE FOR CIRCUT DEVICE, AND CHIP PACKAGE AND MULTILAYER BOARD USING THAT} Circuit forming electrode of the element method, the chip package and a multi-layer substrate using the same {METHOD OF DEFINING ELECTRODE FOR CIRCUT DEVICE, AND CHIP PACKAGE AND MULTILAYER BOARD USING THAT}

본 발명은 칩 소자 또는 기판과 같은 회로소자에 전극을 형성하기 위한 방법과 그를 이용한 칩 패키지 및 다층기판에 관한 것으로, 보다 상세하게는 회로소자의 단자 영역에 보호범프 및 절연층을 형성하고 상기 보호범프를 제거하여 비아홀을 만드는 것에 의하여 다른 회로요소와 전기적으로 연결하기 위한 전극을 형성하는 방법 및 그를 이용한 칩 패키지 및 다층기판에 관한 것이다. The present invention forms the, more particularly, to protect the bumps and the insulating layer in the terminal areas of the circuit element to a method and a chip package and a multi-layer substrate using the same for forming an electrode on the circuit element such as a chip device or a substrate on which the protection a method of forming an electrode for electrically coupling to the other circuit elements by being removed to create a via hole and the bump using the same relates to a chip package and a multi-layer substrate.

최근 칩형 소자의 패키지는 리드 프레임과 몰드 기술을 이용한 패키지에서 칩 스케일 패키지(chip scale package, CSP)로 발전하고 있으며, 이러한 칩 스케일 패키지로는 플립 칩 패키지(flip chip package) 또는 와이어 본드 타입 패키지(wire-bond type package)가 있다. Recent plan of chip-type device has been developed in the package using the lead frame and the mold described in a chip-scale package (chip scale package, CSP), in such a chip-scale package, flip chip packages (flip chip package) or wire bond-type package ( there are wire-bond type package).

도 1에서는 플립 칩 패키지를 도시하고 있다. In Figure 1 shows a flip-chip package. 상기 도 1에서와 같이, 칩(101)의 하면에는 칩의 단자와 연결되는 도전용 범프(111)가 형성되어 있고, 이러한 도전용 범프(111)는 양면 통전된 기판(103)의 상면 전극에 실장하게 된다. FIG as in the first, the upper surface electrode of the chip 101 if there is formed a conductive bump (111) for being connected to the terminals of the chip, these conductive bumps 111 on both sides of the substrate 103 energized for a It is mounted. 따라서 칩의 각각의 단자는 기판(103)의 전극에 연결된다. Thus, each terminal of the chip is connected to the electrode of the substrate 103. 기판(103)에는 비아홀(109)이 형성되어 있어 칩의 단자들이 기판(103)의 다른면에 형성되는 외부전극인 솔더볼(107)에 전기적으로 연결되도록 한다. Board 103, the via hole 109 is formed such that it is electrically connected to an external electrode of a solder ball 107 of the chip terminals are formed on the other surface of the substrate 103. 또한 칩(101) 주위는 기판(103)과 칩(101) 사이를 에폭시 수지와 같은 절연성 보호수지로 채우게 된다. In addition, around the chip 101 is filled between the substrate 103 and chip 101, an insulating protective resin such as epoxy resin.

한편, 도 2는 와이어 본드 타입 패키지를 도시하고 있다. On the other hand, Figure 2 shows a wire-bonding type package. 도 2에서는 칩(201)을 도전된 기판(203)의 상면에 장착하고, 칩(201)의 전극과 양면 도전된 기판(203)의 상면 전극을 와이어(211)를 통하여 연결한다. Figure 2, is mounted on the upper surface of the substrate 203, the conductive chip 201, and connect the top electrode of a double-sided conductive with the electrode of the chip 201, the substrate 203 through a wire 211. 그후 보호용 수지, 특히 에폭시 몰딩 수지(205)로 칩(201) 주위와 와이어(211)를 몰딩하게 된다. Then a protective resin, particularly epoxy resin molding 205 is a molded chip 201 around the wire 211. 이때 역시 기판(203)에는 비아홀(209)이 형성되어 칩의 단자를 기판의 외부단자(207)에 전기적으로 연결되도록 한다. In this case there is also a via hole 209 in substrate 203 is formed to be electrically connected to the terminals of the chip to the external terminals 207 of the substrate.

상기와 같은 칩 스케일 패키지들은 모두 양면 기판을 사용하여 기판의 하부에 형성된 전극을 통해 다른 기판과 같은 회로소자에 실장될 수 있는 구조를 갖고 있다. Chip-scale package as described above can all have a structure that can be mounted on the circuit element, such as another substrate using a double-sided substrate through the electrodes formed at the bottom of the substrate. 이러한 양면 기판(103,203)은 칩(101,201)의 단자와 패키지가 실장되는 메인 기판의 단자(도시하지 않음)를 전기적으로 연결시켜주는 역할과 칩(101,201)을 보호하는 역할을 하게 된다. This double-sided board (103 203) is to serve to protect the role and the chip (101 201) which was electrically connected to a (not shown) terminal of the main board to be mounted and the terminal of the chip package (101 201).

양면 기판(103,203)는 페놀 수지 또는 세라믹 등의 단단한 재질로 된 시트에 드릴이나 레이저를 통하여 비아홀(via hole)을 가공한 후, 비아홀을 포함한 기판의 상하면을 무전해도금하여 통전가능하게 한 구조를 갖는다. After both sides of the substrate (103 203) is through a drill or a laser to the a rigid material such as a phenolic resin or a ceramic sheet processing a via hole (via hole), and electroless plating the upper and lower surfaces of the substrate including a via hole to a structure enabling electrification have. 이후 전해도금과 에칭 등의 공정을 통하여 도금층에 패턴을 형성하고, 단자를 제외한 부분에는 솔더 저항층과 같은 절연 물질로 코팅하게 된다. Since electrolytic plating and portions except for the terminal, and forming a pattern on the plating layer through the processes such as etching, it is coated with an insulating material such as solder resist layer.

또한, 도 3에서와 같이 상기 양면 기판은 최근에는 상기와 같은 고집적, 초소형 패키지를 위한 볼 그리드 배열(ball grid array, BGA) 기판(303)을 사용하고 있다. Further, the double-sided board as shown in Fig. 3 Recently, using a high density, a ball grid array package for an ultra-small (ball grid array, BGA) substrate 303 as described above. 이는 칩(301)은 패키지 윗면에 붙이고 반대편, 즉 아래 면에는 2차원 배열의, 마치 공처럼 보이는 땜납(또는 솔더볼,307)을 붙여 표면실장이 가능도록 한 패키지에 사용되는 기판을 말한다. This chip 301 is attached to the other side of the top package, that is, the lower surface refers to a substrate used in a package can be attached to the mounting surface of the two-dimensional array, the solder (or solder balls, 307) looks like a ball. 이때 볼(307) 간격은 통상적으로 1.5mm이지만 패키지 아래면 전체에 배열할 수 있고,종래의 패키지 방법보다 더 많은 수의 외부 단자와 연결시킬 수 있기 때문에, 결과적으로 칩 패키지의 소형화가 가능한 장점이 있다. The ball 307 interval is typically 1.5mm, but may be arranged on the whole area under the package, it is possible to connect a larger number of external terminals of the package than the conventional method, the possible advantages of miniaturization resulting in chip packages have.

이러한 기판을 사용하게 되는 경우, 칩의 소형화와 이에 따른 패키지의 소형화에 따라서 기판에 형성되는 비아홀이 소형화되어야 한다. If the use of such a substrate, the via holes should be formed in the substrate in accordance with the miniaturization of the chip size of the package in accordance with this size reduction. 그러나, 작은 직경의비아홀을 형성하는 것은 기술적으로 상당히 어렵고, 이러한 정밀한 비아홀을 형성한다 하더라도 비용의 상승 때문에 문제가 있게 된다. However, forming a via hole of a small diameter becomes a problem because technically quite difficult and, even to form these fine via holes increase in cost. 또한 작은 직경의 비아홀을 형성하는 것에 어려움이 있기 때문에 다층, 고집적화된 기판을 사용하기 힘든 문제점이 있게 된다. In addition, because there is difficulty in forming a via hole of a small diameter becomes a difficult problem to use a multi-layered, highly integrated substrate.

따라서 칩의 단자에 외부전극을 연결하기 위하여 상기와 같은 양면기판을 사용하지 않고도 정밀한 비아홀을 형성하여 상기 기판을 대신하게 할 수 있으며, 또한 정밀한 비아홀을 형성하여 기판의 다층화를 가능하게 하는 기술이 요구되어 왔다. Thus it can be made instead of the substrate to form a precise via hole without the use of double-sided boards as described above to connect the external electrodes to the terminals of the chip, and a technique for enabling the multilayer substrate to form a precise via hole required It has been.

또한, 상기 기판을 플렉시블한 기판으로 대신하여 사용하는 경우 화학적인 에칭에 의하여 비아홀을 가공하기 때문에 비아홀의 형성면에서는 단단한 기판을 사용하는 경우보다 우수하게 되나, 칩 패키지 제작 단계에서 열적, 물리적 충격의 방지를 위한 보완공정이 필요하게 되는 문제점이 있게 된다. In addition, when used in place of the substrate as a substrate a flexible because the process via holes by chemical etching, but the formed surface of the via hole to better than when using a solid substrate, the thermal and physical shock on the chip package production stage thereby a problem in that it requires a complementary step for prevention.

따라서 보다 소형이고 정확한 위치에 비아홀을 형성하고, 또한 열적, 물리적으로 충격에도 강한 칩 패키지 및 다층기판의 구조가 요구되어 왔다. Therefore, to form a via hole to a more compact and accurate position, and also has been a strong structure of the chip package and the multilayer substrate needs to thermal shock, physical.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 보호 범프를 형성하고 다시 이를 제거하는 공정에 의하여 정밀하고 소형화된 비아홀을 형성하고, 이에 의해 소형화된 칩 패키지 및 그 제조방법을 제공하는 것을 목적으로 한다. The present invention aims to provide that, protected form the bumps to form a precise and compact the via hole by a process for removing it again, and thereby the chip package and a method of manufacturing miniaturized by for solving the above problems do.

또한, 본 발명은 칩 패키지 공정상에 사용되는 기판을 보호용 절연수지가 대신하도록 하여 보다 저렴한 패키지를 얻을 수 있도록 하며, 열적이나 물리적인 충격에 강하도록 신뢰성있는 패키지 및 다층기판을 얻을 수 있도록 하는 것을 목적으로 한다. In addition, the present invention is that to obtain a package and a multi-layer substrate with reliability, so as to obtain a low-cost package than to be a substrate used in a chip packaging process instead of the protective insulating resin, to steel to thermal and physical shocks The purpose.

또한, 본 발명은 상기와 같은 공정에 의하여 정밀한 비아홀을 형성하도록 하여 집적도가 높고 소형화되며, 그 제조공정이 단순화된 다층기판 및 그 제조방법을 제공하는 것을 목적으로 한다. In addition, the present invention is a high-density miniature-sized so as to form a precise via hole by a process as described above, to provide a production process that is a simplified multi-layer substrate and a manufacturing method for the purpose.

도 1은 종래의 플립 칩 패키지의 단면도이다. 1 is a cross-sectional view of a conventional flip chip package.

도 2는 종래의 와이어 본드 타입 칩 패키지의 단면도이다. Figure 2 is a cross-sectional view of a conventional wire bond-type chip package.

도 3은 종래의 볼 그리드 배열 기판의 단면도이다. 3 is a cross-sectional view of a conventional ball grid array substrate.

도 4는 본 발명에 의한 전극형성방법을 적용한 칩 패키지의 단면도이다. Figure 4 is a cross-sectional view of a chip package, applying the electrode-forming process according to the present invention.

도 5는 본 발명에 의한 전극형성방법을 적용한 일반적인 칩 패키지의 제조방법을 단계별로 도시한 도면이다. 5 is a view showing step by step a method of manufacturing a chip package, applying the general electrode forming method according to the present invention.

도 6은 본 발명에 의한 전극형성방법을 적용한 웨이퍼 레벨 칩 패키지의 제조방법을 단계별로 도시한 도면이다. 6 is a view showing step by step a method of manufacturing the wafer-level chip packages applying the electrode forming method according to the invention.

도 7은 본 발명에 의한 칩 패키지의 일 실시예로써, 다층구조를 적용한 칩 패키지의 단면도이다. 7 is a cross-sectional view of the chip package, apply, the multi-layer structure as an embodiment of a chip package according to the present invention.

도 8는 본 발명에 의한 칩 패키지의 일 실시예로써, 양면에 도전층이 형성된 칩 패키지의 단면도이다. Figure 8 is a cross-sectional view of a chip package having a conductive layer on both sides, as one embodiment of a chip package according to the present invention.

도 9는 도 4의 칩 패키지의 일 실시예로써, 다수개의 칩 배열 구조를 적용한 칩 패키지의 단면도이다. Figure 9 as one embodiment of a chip package of FIG. 4, a cross-sectional view of a chip package, applying a plurality of chip arrangement.

도 10은 본 발명에 의한 칩 패키지의 일 실시예로써, 측면보호를 강화한 칩 패키지의 단면도이다. Figure 10 is a reinforced side protection as one embodiment of a chip package according to the present invention, a cross-sectional view of the chip package.

도 11은 본 발명에 의한 전극형성방법을 적용한 다층기판의 단면도이다. 11 is a cross-sectional view of the multi-layer substrate is applied to the electrode forming method according to the invention.

도 12는 도 11의 다층기판의 제조방법을 각 단계별로 도시한 도면이다. 12 is a view showing a method of manufacturing the multi-layer substrate of Figure 11 for each step.

* 도면의 주요부분에 대한 부호의 설명 * * Description of the Related Art *

1: 칩 패키지 3: 칩 소자 1: Chip Package 3: chip device

4: 절연층 5: 도전층 4: insulating layer 5: conductive layer

6: 절연보호용 수지 7: 외부 전극 6: insulating protective resin 7: outer electrode

50: 웨이퍼 53: 보호범프 50: Wafer 53: bump protection

54: 연마면 55: 절연층 54: polished surface 55: insulating layer

56: 전극보호층 60: 웨이퍼 레벨 칩 패키지 56: Electrode protective layer 60: a wafer-level chip packages

71: 기판 72: 전극 71: substrate 72: electrode

73: 절연층 74: 도전층 73: insulating layer 74: conductive layer

75: 외부전극 76: 전극보호층 75: External electrode 76: Electrode protective layer

77: 보호범프 80: 다층기판 77: Protection bump 80: multilayer board

상기와 같은 목적을 달성하기 위한 구성수단으로서, 본 발명은 복수개의 전극을 갖는 회로소자의 전극 상부에 일정두께의 보호 범프를 형성하는 단계; A configuration means for achieving the above object, the present invention is to form a protective bump having a predetermined thickness on the upper electrode of the circuit element having a plurality of electrodes; 상기 보호 범프 영역을 제외한 상기 회로소자 상에 절연층을 형성하는 단계; Forming an insulating layer on the circuit elements other than the bump protection region; 상기 보호 범프가 외부에 노출되도록 상기 절연층을 연마하는 단계; The protection step is to polish the bumps of the insulating layer so as to be exposed to the outside; 상기 보호 범프를 제거하여 전극이 외부에 노출되도록 하는 단계; Stage such that the electrode is exposed to the outside by removing the protective bumps; 상기 전극에 연결되는 도전층을 상기 절연층 상부에 형성하는 단계; Forming a conductive layer connected to the electrode on the insulating layer; 및 상기 도전층에 상기 전극에 대응하는 패턴을 형성하고, 상기 패턴 상에 외부전극을 형성하는 단계;를 포함하는 회로소자의 전극형성 방법을 제공한다. Provides an electrode forming method of a circuit device including a; and the step of the conductive layer to form a pattern corresponding to the electrode, forming an external electrode on the pattern.

또한, 본 발명은 다수개의 전극을 갖는 칩 소자를 마련하는 단계; In addition, the present invention includes the steps of providing a chip device having a plurality of electrodes; 상기 칩 소자의 전극 상부에 일정두께의 보호 범프를 형성하는 단계; Forming a protective bump having a predetermined thickness on the upper electrode of the chip element; 상기 보호 범프 영역을 제외한 상기 칩 소자의 전극이 형성되어 있는 면 상에 절연층을 형성하는 단계; Forming an insulating layer on the side with the electrode of the chip components other than the bump protection area is formed; 상기 보호 범프가 외부에 노출되도록 상기 절연층을 연마하는 단계; The protection step is to polish the bumps of the insulating layer so as to be exposed to the outside; 상기 보호 범프를 제거하여 전극이 외부에 노출되도록 하는 단계; Stage such that the electrode is exposed to the outside by removing the protective bumps; 상기 전극에 연결되는 도전층을 상기 절연층 상부에 형성하는 단계; Forming a conductive layer connected to the electrode on the insulating layer; 상기 도전층에 상기 전극에 대응하는 추가전극이 형성될 수 있는 패턴을 형성하는 단계; Forming a pattern with a further electrode corresponding to the electrode to the conductive layer may be formed; 및 상기 패턴의 추가 전극 영역 상에 외부전극과 전극보호층을 형성하는 단계;를 포함하는 칩 패키지 제조방법을 제공한다. It provides a chip package manufacturing method comprising; and on the additional electrode area of ​​the pattern forming the outer electrode and the electrode protective layer.

또한 본 발명은 일면에 복수개의 전극을 갖는 복수개의 칩 소자가 형성된 웨이퍼를 마련하는 단계; Further steps of the invention provide a plurality of chip components is formed wafer having a plurality of electrodes on one surface; 상기 칩 소자의 전극 상부에 일정두께의 보호 범프를 형성하는 단계; Forming a protective bump having a predetermined thickness on the upper electrode of the chip element; 상기 보호 범프 영역을 제외한 상기 웨이퍼의 일면에 절연층을 형성하는 단계; Forming an insulating layer on one surface of the wafer except for the bump protection region; 상기 보호 범프가 외부에 노출되도록 상기 절연층을 연마하는 단계; The protection step is to polish the bumps of the insulating layer so as to be exposed to the outside; 상기 보호 범프를 제거하여 전극이 외부에 노출되도록 하는 단계; Stage such that the electrode is exposed to the outside by removing the protective bumps; 상기 전극에 연결되는 도전층을 상기 절연층 상부에 형성하는 단계; Forming a conductive layer connected to the electrode on the insulating layer; 상기 도전층에 상기 전극에 대응하는 추가 전극이 형성될 수 있는 패턴을 형성하는 단계; Forming a pattern with a further electrode corresponding to the electrode to the conductive layer may be formed; 상기 패턴의 추가 전극 영역 상에 외부전극과 전극보호층을 형성하는 단계; Forming an external electrode and the electrode protective layer on the additional electrode area of ​​the pattern; 및 상기 웨이퍼를 칩 패키지 단위로 다이싱하는 단계;를 포함하는 칩 패키지 제조방법을 제공한다. It provides a chip package manufacturing method comprising; and a step of dicing the wafer into chip package unit.

또한 본 발명은 복수개의 전극이 형성되어 있는 기판의 각각의 전극 상에 일정두께의 보호범프를 형성하는 단계; In another aspect, the present invention includes the steps of forming a protective bump having a predetermined thickness on each of the electrodes of the substrate on which the plurality of electrodes are formed; 상기 보호 범프 영역을 제외한 상기 기판의 전극이 형성되어 있는 면에 절연층을 형성하는 단계; Forming an insulating layer on the side with the electrode of the substrate other than the bump protection area is formed; 상기 보호 범프가 외부에 노출되도록 상기 절연층을 연마하는 단계; The protection step is to polish the bumps of the insulating layer so as to be exposed to the outside; 상기 보호 범프를 제거하여 전극이 외부에 노출되도록 하는 단계; Stage such that the electrode is exposed to the outside by removing the protective bumps; 상기 전극에 연결되는 도전층을 상기 절연층 상부에 형성하는 단계; Forming a conductive layer connected to the electrode on the insulating layer; 상기 도전층에 상기 전극에 대응하는 추가 전극이 형성될 수 있는 패턴을 형성하는 단계; Forming a pattern with a further electrode corresponding to the electrode to the conductive layer may be formed; 및 상기 패턴의 추가 전극 영역 상에 외부 전극과 전극보호층을 형성하는 단계;를 포함하는 다층기판 제조방법을 제공한다. Provides a multi-layer substrate manufacturing method that includes; and on the additional electrode area of ​​the pattern forming the outer electrode and the electrode protective layer.

또한 본 발명은 다수개의 전극이 마련된 칩 소자; In addition, the chip device of this invention is provided with a plurality of electrodes; 상기 다수개의 전극영역을 제외한 상기 칩 소자의 전극이 형성되어 있는 면 상에 형성된 절연층; An insulating layer formed on the surface on which the electrodes of the chip components other than the plurality of electrode regions are formed; 상기 전극영역을 채우면서 상기 절연층 상에 형성되며 상기 복수개의 전극영역 각각에 대응하도록 소정의 간격으로 전기적으로 분리되어 형성되는 도전층; The conductive layer, filling said electrode region is formed on the insulating layer to be formed is electrically isolated at a predetermined interval so as to correspond to each of the plurality of electrode regions; 상기 도전층 상면에 형성되는 외부전극; External electrodes formed on an upper surface of the conductive layer; 및 상기 절연층 상면에서 상기 외부전극 주위에 형성되는 전극저항층을 포함하는 칩 패키지를 제공한다. And it provides a chip package including a resistive electrode layer formed around the outer electrode from the upper surface of the insulating layer.

또한 본 발명은 복수개의 전극이 형성되어 있는 기판; The substrate in the invention is a plurality of electrodes are formed; 상기 복수개의 전극영역을 제외한 상기 기판의 전극이 형성되어 있는 면 상에 형성된 절연층; An insulating layer formed on the surface on which the electrode of the substrate other than the plurality of electrode regions are formed; 상기 전극영역을 채우면서 상기 절연층 상에 형성되며 상기 복수개의 전극영역 각각에 대응하도록 소정의 간격으로 전기적으로 분리되어 형성되는 도전층; The conductive layer, filling said electrode region is formed on the insulating layer to be formed is electrically isolated at a predetermined interval so as to correspond to each of the plurality of electrode regions; 상기 도전층 상면에 형성되는 외부전극; External electrodes formed on an upper surface of the conductive layer; 및 상기 절연층 상면에서 상기 외부전극 주위에 형성되는 전극저항층을 포함하는 다층기판을 제공한다. And it provides a multilayer substrate including a resistive electrode layer formed around the outer electrode from the upper surface of the insulating layer.

이하 본 발명에 대하여 바람직한 실시예를 첨부된 도면에 따라서 보다 상세히 설명한다. Or less according to the accompanying drawings, the preferred embodiment for the invention will be described in detail.

도 4는 본 발명에 의한 전극형성방법을 적용한 칩 패키지(1)의 단면도이다. Figure 4 is a cross-sectional view of the chip package (1) applying the electrode forming method according to the invention. 도 4에서 칩 소자(3)는 일면에 다수개의 전극이 형성된 집적회로소자가 되며, 또한 타면에도 다수개의 전극이 형성될 수 있다. In Figure 4, the chip element (3) is an integrated circuit device having a plurality of electrodes formed on a surface, there is also a plurality of electrodes can be also formed on the other surface. 칩 소자(3)의 전극을 제외하고 절연층(4)이 상기 칩 소자(3)의 전극면에 형성되며, 상기 절연층(4)은 절연 및 보호용 수지, 바람직하게는 에폭시 몰딩 수지로 형성될 수 있다. Except for the electrode of the chip element 3 and the insulating layer 4 is formed on the electrode surface of the chip device (3), the insulating layer 4 is isolated and a protective resin, preferably be formed of an epoxy molding resin can. 상기 절연층(4)의빈 공간, 즉 칩 소자(3)의 전극영역은 무전해도금을 통해 통전되며, 다시 전해도금, 에칭과 같은 방법으로 도전층(5)을 형성하게 된다. The electrode area of ​​the insulating layer 4 uibin space, that is, the chip element 3 is energized, and even through the electroless gold, to form the conductive layer 5 by electrolytic plating again, a method such as etching. 도전층(5)에는 칩 소자(3)의 전극에 대응하는 패턴이 형성되며, 외부와 접속되는 부분에는 외부 전극(7)을 형성하게 된다. The conductive layer 5 is formed in a pattern corresponding to the electrode of the chip element 3, there is formed an external electrode (7) portion to be connected to the outside. 상기 외부전극(7)는 솔더 범프일 수 있다. The external electrodes 7 may be a solder bump. 또한 도전층(5)의 절연보호할 부분에는 절연보호용 수지(6)를 형성한다. Also part to protect the insulation of the conductive layer 5 is to form the insulating protective resin (6).

본 발명에 의한 칩 패키지(1)는 상기와 같은 구성에 의하여 기판을 사용하지 않고 칩 소자(1)의 전극에 대응하는 외부전극을 형성하였으며, 이를 위한 새로운 칩 패키지의 구조를 제공하고 있다. Chip package according to the present invention (1) was formed an external electrode corresponding to the electrode of the chip device (1) without the use of the substrate by the configuration as described above, providing the structure of the new chip package therefor.

도 5는 본 발명에 의한 전극형성방법을 적용한 일반적인 칩 패키지의 제조방법에 관한 제1 실시예를 단계별로 도시한 도면이다. 5 is a diagram showing the steps of a first embodiment relates to a process for the preparation of a typical chip package, applying the electrode-forming process according to the present invention. 상기 도 4에서와 같은 칩 패키지를 제조하기 위하여 본 발명에서는 칩 전극 위에 스트리핑에 의하여 제거할 수 있는 보호범프를 형성하고, 다시 이를 제거하는 공정에 의하여 보다 작은 직경의 정밀한 비아홀을 형성할 수 있게 된다. The Figure in the present invention for manufacturing a chip package, such as from 4 it is possible to form a precise via hole of a smaller diameter by a step of forming a protective bumps that can be removed by stripping on the chip electrodes, and again removing it .

이를 위하여 본 발명에서는 아래와 같은 단계들이 적용된다. To this end, the present invention is applied to the following stage. 먼저, 다수개의 단자를 갖는 칩 소자(3)를 마련한다. First, provide a chip element (3) having a plurality of terminals. 칩 소자(3)는 일반적인 회로소자의 하나이며, 상기 칩 소자(3)는 후술하는 바와 같이 기판이 될 수도 있다. The chip element (3) is one of the typical circuit elements, the chip element 3 may be a substrate as described below. 또한 상기 칩 소자(3)는 다수개의 단자를 갖고 있으며, 상기 단자들은 칩 소자(3)의 일면에 형성될 수 있으며, 또한 일면과 그에 대응하는 타면에 동시에 형성되는 것도 가능하다. Also has a plurality of terminals of the chip element 3, the terminals can be formed at the same time may be formed on one side of the chip element 3, and the other surface to the one surface corresponding thereto. 본 실시예에서는 일면에 다수개의 단자가 형성된 칩 소자(3)에 대하여 설명한다. In the present embodiment will be described with respect to the chip element 3 with a plurality of terminals formed on one surface.

다수개의 단자를 갖는 칩 소자(3)를 기판(10)에 부착시킨다(단계 a). The chip element (3) having a plurality of terminals are attached to the substrate 10 (step a). 이때기판(10)에 부착되는 칩 소자(3)의 면은 단자를 갖는 면과 대응하는 타면이된다. The surface of the chip device (3) adhered to the substrate 10 is the other surface corresponding to the surface having the terminal. 기판(10)은 다수개의 칩 소자(3)를 배열하기 위하여 사용되며, 또한 칩의 위치를 고정시키고 칩 패키지의 구조를 지지하는 역할을 하기도 한다. Substrate 10 is used to arrange a plurality of chip components (3), they also serve to secure the position of the chip and supports the structure of the chip package.

다음 단계는 기판(10)에 배열된 칩 소자(3)의 단자영역(2)에 보호범프(11)를 형성하는 단계(b)이다. The next step is step (b) of forming a protection bump 11 to the terminal zone (2) of the chip device (3) arranged on the substrate 10. 보호 범프(11)는 칩 소자(3)의 단자영역(2)을 덮도록 형성되며, 일정한 두께를 갖는다. Protect the bump 11 is formed so as to cover the terminal zone (2) of the chip element 3 has a constant thickness. 통상적으로 0.05 ~ 0.1mm이상의 두께를 갖는 것이 제조공정상 바람직하게 된다. Typically the manufacturing process it is preferable top having at least 0.05 ~ 0.1mm thickness. 상기 보호범프(11)는 감광성 물질을 사용하며, 본 실시예에서는 포토 레지스트(photo-resist, PR)를 사용하게 된다. The protective bumps 11 are used, and the use of a photosensitive material, in the present embodiment, a photoresist (photo-resist, PR). 상기 보호범프(11)를 감광성물질인 포토 레지스트로 사용하는 이유는 다음 단계에서 스트리핑에 의하여 제거할 수 있도록 하기 위함이며, 이러한 제거공정에 의하여 비아홀이 형성된다. The reason for using the protection bump 11 with a photoresist the photosensitive material is intended to be able to be removed by stripping at the next step, a via hole is formed by this removal step.

다음 단계는 상기 보호범프(11)를 제외한 상기 칩 소자(3)의 나머지 부분에 절연층(4)을 형성하는 단계(c)이다. The next step is the step (c) of forming the insulating layer 4 to the rest of the chip element 3, except for the protective bump 11. 절연층(4)은 절연보호용 수지, 바람직하게는 에폭시 몰딩 수지가 되며, 칩 소자(3)의 단자 형성면에 형성되고, 또한 칩 소자의 측면에 형성될 수도 있다. Insulating layer 4 is an insulating protective resin, preferably an epoxy molding resin, is formed on the terminal formation surface of the chip device 3, or may be formed on the side of the chip element. 칩 소자(3)의 측면에 형성되는 절연층은 기판(10) 상에 배열된 다수개의 칩 소자(3)들의 공간을 채우면서 형성된다. Insulating layer formed on the side of the chip element 3 is formed by filling the space of a plurality of chip elements 3 arranged on the substrate 10.

상기 절연층(4)은 상기 보호범프(11)보다 높게 형성되며, 상기 보호범프(11)를 덮을 수도 있다. The insulating layer 4 is formed above the said protective bump 11 may cover the protective bump 11. 이러한 경우 보호범프(11)를 제거하기가 불가능하기 때문에 상기 절연층을 연마하는 단계(c)를 또한 포함한다. In this case it is impossible to remove the protective bump 11 also includes the step (c) for polishing the insulating layer. 연마면(8)은 절연층(4)의 상면, 즉 보호범프(11)가 형성된 면이 되며, 칩 소자(3)의 일면과 평행하도록 연마하는 것이 바람직하게 된다. Polished surface 8 is a plane upper surface, i.e. the protection bump 11 formed in the insulating layer 4, it is preferable for polishing so as to be parallel with one side of the chip element (3). 연마는 화학적 몰드 연마(chemical mold polishing) 기법을사용하며, 보호범프(11)가 외부로 드러나도록 연마한다. Polishing uses a chemical polishing mold (mold chemical polishing) technique, is polished so as to protect the bump 11 is exposed to the outside.

외부로 드러난 보호범프(11)는 식각액으로 스트리핑하여 제거하게 된다. Protect the bump 11 exposed to the outside is removed by stripping the etching liquid. 보호범프(11)를 제거하여 칩 소자(3)의 단자(2)를 외부에 노출되도록 하는 노출단계(c)를 거친다. Subjected to the exposure step of removing the protection to the bumps 11 to expose the terminal 2 of the chip element (3) on the outside (c). 상기 보호범프(11)는 포토 레지스트와 같은 감광성 물질이기 때문에 식각액을 통해 제거될 수 있게 된다. The protective bump 11 is able to be removed by the etchant because the photosensitive material such as photoresist. 상기 보호범프(11)를 제거한 부분은 비아홀(15)이 된다. Partial removal of the said protective bump 11 is a via hole (15).

상기와 같이 보호범프(11)를 제거하여 칩 소자의 단자를 노출시킨 후, 연마면, 비아홀(15) 및 칩 전극(2)에 무전해도금을 하여 통전시키게 된다. After exposing the terminals of the chip elements by removing the protective bump 11 as described above, the polishing surface, the via hole 15, and the electroless plating to the chip electrode 2, thereby energizing the gold. 또한 비아홀을 채우면서 상기 절연층(4)의 상부면에 도전층(5)을 형성한다.(단계 d) 도전층(5)은 칩 소자의 단자(2)에 각각 연결되며, 바람직하게는 구리 등과 같은 금속물질로 이루어진다. In addition, filling the via hole to form a conductive layer 5 on the upper surface of the insulating layer 4 (step d), the conductive layer 5 are respectively connected to the terminal 2 of the chip element, preferably copper It made of a metallic material such as. 상기 도전층(5)은 단자(2)와 연결시키기 위하여 상기와 같은 도금공정을 이용하여 절연층(4)의 빈 공간을 충진시키는 것이 바람직하나, 일정한 층의 두께를 갖도록 형성하기 위하여 전해도금법으로 얇은 도금층을 형성한 후에 그 도금층 위에 적어도 하나의 동박을 적층하는 방식을 사용하는 것도 가능하다. The conductive layer 5 is one preferred to fill an open area of ​​the insulating layer 4 by using a plating process as described above for connecting to the terminals (2), the electrolytic plating method to form so as to have a thickness of certain layers after forming the thin plate layer, it is possible to use a method of laminating at least one copper-plated layer thereon.

상기 도전층(5)에는 다시 칩 소자의 단자(2)에 대응하는 추가단자가 형성될 수 있도록 패턴을 형성한다. To form the pattern so that more terminals may be formed corresponding to the terminal 2 of the chip element, the back of the conductive layer (5). 상기 추가단자 영역 상에 외부단자(7)를 형성하고, 외부단자(7) 주위에 단자보호층(6)을 형성한다. Forming an external terminal 7 on the further terminal region, and around the outside terminal (7) to form a terminal protective layer 6. 본 실시예에서는 상기 외부단자(7)는 솔더 범프를 사용하였다. In this embodiment, the external terminal 7 is used for the solder bumps.

상기와 같은 공정후에 각각의 칩 패키지 단위로 분리하기 위해 다이싱 테입(13)을 기판에 부착시키고, 이를 따라서 다이싱 한다. After the process as described above it was attached to a dicing tape substrate 13 to separate into each chip package unit, and thus washing this die. (단계 e) 그후 제품을분리한다.(단계 f) (Step e) to separate the product is then (step f)

본 발명에 의한 전극형성방법을 사용한 칩 패키지의 제조방법의 제2 실시예가 도 6에 단계별로 도시되어 있다. A second embodiment of the manufacturing method of the chip package with an electrode forming method according to the present invention is shown step by step in Fig. 본 실시예는 웨이퍼 레벨 칩 패키지의 제조방법에 관한 것이다. The present embodiment relates to a method of manufacturing a wafer-level chip packages. 본 실시예에서는 앞서 본 일반적인 칩 패키지의 경우와 같은 단계를 거치게 되나, 칩 소자가 웨이퍼에 형성되어 있으며, 각각의 칩 단위로 절단되기 전에 칩 패키지 제작공정을 거치게 된다. In this embodiment, but go through the same steps as in the case of the common chip package before, and chip elements are formed on the wafer, it is subjected to chip package production process before being cut into individual chip units.

먼저, 일면에 복수개의 단자를 갖는 복수개의 칩 소자가 형성된 웨이퍼(50)를 마련한다.(단계 a) 상기 웨이퍼에 형성된 칩 소자의 단자 영역(61)에 상기 제1 실시예와 같이 보호범프(53)를 형성한다.(단계 b) 보호범프(53)는 마찬가지로 감광성물질이 되는 것이 바람직하며, 상기 감광성물질은 포토 레지스트가 될 수 있다. First, providing a wafer (50) a plurality of chip components is formed having a plurality of terminals on a surface (step a) protecting the bumps, as in the terminal areas 61 of the chip element formed on the wafer in the first embodiment ( 53) to form (step b) protecting the bumps 53 is likewise preferably be a photosensitive material, the photosensitive material may be a photoresist.

상기 보호범프(53) 형성 영역을 제외하고 상기 웨이퍼(50)의 일면에 절연층(55)을 형성한다.(단계 c) 웨이퍼(50)의 일면은 칩 소자의 단자가 형성된 면을 말한다. One surface of the protective bumps 53 except the forming region, and forming an insulating layer 55 on one surface of the wafer 50 (step c) the wafer (50) is the side with terminals of the chip element is formed. 상기 절연층(55)은 상기 보호범프(53)보다 높게 형성되며, 상기 보호범프를 덮게 될 수 있다. The insulating layer 55 is formed higher than the protection bumps 53, it can be said to cover the bump protection. 또한 상기 보호범프(53)가 외부에 노출되도록 상기 제1 실시예에서와 같이 절연층(55)의 상면을 연마하게 된다.(단계c) 이와 같은 연마후에는 상기 보호범프(53)를 식각액에 의하여 제거하는 스트리핑 공정을 수행하게 되며, 이에 의해 칩 소자의 단자가 외부에 노출되도록 한다.(단계 c) In addition to the first embodiment is to polish the upper surface of the insulating layer 55, as in the example (step c) The after such polishing etch the protective bumps 53 so that the protective bumps 53 are exposed to the outside and a stripping step of removing by carried out, so that the terminal is exposed to the outside of the chip device thereby (step c)

이와 같은 공정 후에는 상기 칩 소자의 단자, 보호범프 제거부분, 및 연마면(54) 상에 무전해도금하여 통전시키고, 이에 의해 비아홀(62)을 형성하게 된다. After this the same process was energized by electroless plating on the terminals, removing the bump protection part, and the abrasive face 54 of the chip element, to form a via hole 62 by this. 또한 상기 비아홀(62)을 채우면서 상기 절연층(55) 상에 도전층(58)을 형성하게 되며, 도전층(58)에는 패턴을 형성하여 칩 소자의 단자들이 외부와 연결될 수 있도록 외부전극이 형성되는 영역을 형성한다. In addition, the external electrodes so that the terminal can be connected with the outside of the chip device to form a pattern, by filling the via hole 62 and to form a conductive layer 58 on the insulating layer 55, conductive layer 58 is to form the region to be formed. 상기 영역에 외부전극(57)을 형성하며, 또한 외부전극 주위에 전극보호층(56)을 형성한다. Forming an external electrode 57 in the region, and also form the electrode protection layer 56 around the external electrode. (단계d) (Step d)

제1 실시예에서와 같은 상기의 단계들을 거친 후, 다이싱용 테입을 웨이퍼(50)의 하부면에 부착하고, 이를 따라서 다이싱하여 칩 단위로 패키지를 분리한다. The attachment to the lower surface of the first embodiment after the above steps, the wafer 50 to the dicing tape, as in Example, and by this, Therefore, the dicing to separate the package into chip units. (단계 e) 이와 같은 방법으로 웨이퍼 레벨 칩 패키지(60)를 완성하게 된다. (Step e) this is completed the same way as wafer level chip package 60.

상기의 제1 및 제2 실시예에서와 같은 전극형성방법을 사용한 칩 패키지 제조방법에 있어서, 상기 절연층 및 도전층은 1개 이상이 되는 것도 가능하다. In the chip package manufacturing method using the same electrode forming method in the above-described first and second embodiments, the insulating layer and the conductive layer, it is also possible that one or more of them. 즉, 도전층 상의 패턴의 추가 단자 영역 상에 일정 두께의 보호범프를 다시 형성하고, 상기의 절연층 형성 및 연마 단계, 보호범프 노출 단계, 도전층 형성단계 및 패턴 형성단계를 반복하여 다층 기판을 대용할 수도 있다. That is, by forming a protective bump having a predetermined thickness again in the additional terminal areas of the pattern on the conductive layer, and repeating the forming the insulating layer and the polishing step, a protective bump exposure step, the conductive layer forming step and a pattern forming step of the multi-layer substrate It may be substituted.

이와 같은 칩 패키지의 구조가 도 7에 도시되어 있다. Such a structure of the chip package is shown in Fig. 도 7에서 칩 소자(3)의 단자 형성면에는 절연층(4)과 비아홀(15)이 형성되어 있다. Also terminal-forming surfaces of the chip components 3 at 7 is an insulating layer 4 and the via hole 15 is formed. 이러한 구조는 앞서본 실시예와 같으나, 상기 도전층(5)에는 각 단자에 대응하는 추가단자가 형성될 수 있는 영역이 패턴 형성단계에 의하여 형성되며, 상기 추가단자 영역을 제외하고 다시 절연층(14)이 형성되고, 비아홀(25)이 상기 추가단자 영역 상에 형성된다. This structure before, but with this embodiment, the conductive layer 5 is provided and a region in which the additional terminals can be formed by the pattern forming step corresponding to the respective terminal, and an insulating layer again, except for the additional terminal areas ( 14) is formed, the via hole 25 is formed on the further terminal areas. 또한 도전층(19)이 절연층(14) 상에 형성되며, 도전층(19)은 비아홀(25)을 채우면서칩 소자의 단자가 외부와 통전되도록 하며, 도전층에는 패턴이 형성된다. Also formed on the conductive layer 19, the insulating layer 14, conductive layer 19, and such that the terminals of the chip and the external device energized, filling the via hole 25, a conductive layer is formed with a pattern. 상기 패턴에는 다시 칩 소자의 단자와 대응하는 추가단자가 형성될 수 있는 영역이 형성되며, 이러한 영역 상에 외부전극(7)이 형성된다. The pattern has a back area that can be formed with a more terminals corresponding to the terminals of the chip components is formed, the external electrode 7 is formed on such area. 또한 단자보호층(6)이 외부전극 주위에 형성된다. In addition, the terminal protective layer 6 is formed around the external electrode. 이와 같은 다층기판을 대용할 수 있는 칩 패키지 제조방법에 의하면 소형이고, 고집적된 기판을 구현할 수 있어서 전체적인 칩 패키지의 소형화를 구현할 수 있게 되는 장점이 있다. Thus, according to the same manufacturing a multi-layer in the substrate can be a substitute for chip packaging method is small, there is an advantage of being able to be implemented in a high-density substrate to implement the miniaturization of the whole chip package.

도 8은 상기 실시예들에 의한 칩 패키지 제조방법에 있어서, 양면에 각각 단자가 형성되어 있는 칩 소자를 사용한 경우에 각 면에 전극을 형성하는 방법을 적용한 칩 패키지를 도시하고 있다. 8 shows a chip package, applying the method of forming an electrode on each side in the case of using the chip element, which in the chip package production method according to the above embodiments, is formed in each of the terminals on both sides. 도 8에서 칩 소자(31)는 양면에 단자가 형성되어 있으며, 각 면에는 상기 도 5 및 도 6에서와 같은 방법을 통해 절연층(33,38)과 비아홀(32,37)이 형성된다. In Figure 8, the chip element 31 is the terminal is formed on both surfaces, and each surface has an insulating layer (33,38) and via holes (32,37) through the same procedure as in the Figs. 5 and 6 is formed. 또한 비아홀(32,37)과 절연층의 상면에 각각 도전층(34,39)이 형성된다. In addition, the conductive layers (34,39) respectively on the upper surface of the via hole (32,37) and the insulating layer is formed. 도전층에는 각각의 단자에 대응하도록 패턴이 형성되며, 각 패턴에는 외부전극이 형성될 수 있는 영역이 마련되며, 그 영역 상에 외부전극(36,41)이 형성된다. The conductive layer has a pattern formed to correspond to each of the terminals, each pattern is provided with a region which may be an external electrode is formed, it is formed an external electrode (36,41) on that area. 외부전극(36,41) 주위에는 전극보호층(35,40)이 형성된다. Around the external electrodes (36,41) are formed in the electrode protection layer (35,40). 상기와 같이 양면에 단자가 형성되어 있는 형태의 칩 소자의 경우도 본 발명에 의한 방법을 사용하여 패키지 제작이 가능하게 된다. For elements in the form of chips is formed with terminals on both sides as described above are also to use the method according to the present invention it can be produced package.

도 9는 상기 실시예들에 의한 칩 패키지 제조방법에 있어서, 다수개의 칩을 배열한 칩 배열 구조에 관한 칩 패키지의 단면도이다. Figure 9 is a cross-sectional view of a chip package according to the embodiment of the chip array structure in the chip package manufacturing method, an array with a plurality of chips by. 도 9에서는 칩 소자가 2개인 경우의 칩 패키지를 도시하였으며, 제1 실시예와 같은 일반적인 칩 패키지의 경우 제1 칩(45)과 제2 칩(46)은 기판(47)에 부착되어 있으며, 상기 칩들이 기판에 부착되는 면은 단자가 형성된 면의 반대면이 된다. Figure 9 was shown the chip package in the case where the chip components 2 individuals, in the case of a typical chip packages such as those of the first embodiment the first chip 45 and second chip 46 is attached to the substrate 47, surface on which the chips are attached to the substrate is the surface opposite to the surface formed with terminals. 또한 상기 칩의 각 단자들과 연결되는 외부단자(51) 사이에는 앞서 설명한 방법에 의해 형성되는 절연층(48), 비아홀(50), 도전층(49)이 각각 형성된다. Also formed an insulating layer 48, a via hole 50 is formed by the methods previously described between the external terminals 51 connected to the respective terminals of the chip, the conductive layer 49, respectively. 이러한 칩 배열 구조를 갖는 칩 패키지는 다이싱하는 단계에서 원하는 수의 칩이 하나의 패키지에 포함되도록 하여 제조할 수 있다. Chip package having such a chip arrangement has a desired number of chips in the step of dicing can be produced by inclusion in a package. 또한 제2 실시예에서도 원하는 수의 칩이 하나의 패키지에 포함되도록 다이싱하여 상기와 같은 칩 패키지를 제조할 수 있다. In addition, it is possible to manufacture a chip package as described above by dicing such that the second embodiment also includes a desired number of chips in a single package.

도 10은 상기 실시예들에 의한 칩 패키지에 있어서, 칩 소자의 측면을 보호하기 위하여 칩 소자의 측면에 단차를 형성하고 일부 측면에 절연층을 형성한 구조를 도시하고 있다. Figure 10 according to the chip package according to the above embodiments, by forming a step on the side of the chip device to protect the side of the chip device shown a structure in which an insulating layer in some aspects. 이러한 구조의 칩 패키지는 특히 상기 제2 실시예에서와 같은 웨이퍼레벨 칩 패키지에 유용하게 된다. Chip package of such a construction is particularly useful in a wafer-level chip packages such as in the second embodiment. 이는 웨이퍼레벨 칩 패키지의 경우 칩 패키지의 측면부가 절연층이 되지 않고 칩 소자의 측면이 되어 손상의 우려가 많게 되기 때문이다. This is because there is a risk of wafer-level when the chip package is the side of the chip element is not a side face of the insulating layer chip package damage lot. 이와 같은 구조는 칩 소자가 형성된 웨이퍼에 일차적으로 칩 소자별 절단면을 따라서 홈을 형성하고, 절연층 형성단계에서 이러한 홈에 절연층을 투입하여 일부가 절연층으로 된 측면부를 형성함으로써 제조된다. Such a structure is manufactured by forming a side surface portion in the insulating layer by putting an insulating layer in such a groove in the insulating layer forming step to form a groove along the primary element by chip on the wafer is cut into chip elements formed. 따라서 도 10의 칩 소자(65)는 측면 일부가 파여서 단차가 형성된 구조로 되어 있다. Thus, chip components 65 of Figure 10 is a part side a wave yeoseo has a structure that a step is formed. 절연층(66)은 칩 소자의 단자가 형성된 면 뿐만아니라 칩 소자의 측면 일부에도 형성된다. Insulating layer 66 as well as the side terminals of the chip element is formed is formed in the side portion of the chip components. 이와 같은 경우 칩 패키지 측면부의 일부가 절연층으로 형성될 수 있어 칩 패키지가 견고하게 되고 쉽게 손상되지 않게 된다. In this case it is part of the chip package side can be formed in the insulating layer is not chip package is not securely and easily damaged.

이상에서는 본 발명에 의한 전극형성방법을 칩 소자에 적용하여 칩 패키지를제조하는 방법과 그에 의한 칩 패키지에 관한 실시예를 설명하였다. In the above described embodiment relates to a method and a chip package according thereto for producing a chip package by applying the electrode forming method according to the invention on a chip device. 한편, 본 발명에 의한 전극형성방법은 칩 소자 뿐만아니라 기판에도 적용가능하다. On the other hand, the electrode forming method according to the present invention is also applicable as well as the chip element substrate. 도 11은 본 발명에 의한 전극형성방법을 사용하여 제조한 다층기판의 단면도이고, 도 12는 도 11의 다층기판의 제조방법을 각 단계별로 도시한 도면이다. 11 is a cross-sectional view of a multilayer board produced by using the electrode forming method according to the invention, Figure 12 is a view showing a method of manufacturing the multi-layer substrate of Figure 11 for each step.

먼저, 양면 통전된 기판(71)을 마련한다.(단계 a) 이때 기판(71)은 한면에만 전극이 형성된 기판이 될 수도 있다. First, it is provided on both sides with conducting substrate 71 (step a) wherein the substrate 71 may be the substrate electrode is formed only on one side. 상기 기판(71)의 전극(72) 위에 보호범프(77)를 형성한다. It forms a protective bump 77 on the electrode 72 of the substrate 71. 보호범프(77)는 상기 제1 및 제2 실시예에서와 마찬가지로 감광성물질인 것이 바람직하며, 상기 감광성물질은 포토 레지스트가 될 수 있다. Protection bump 77 is a photosensitive material wherein preferably a first and a photosensitive material, as in the second embodiment, and may be a photoresist. (단계 b) (Step b)

상기 보호범프(77) 형성 영역을 제외하고 상기 기판의 전극형성 면에 절연층(73)을 형성한다.(단계 c) 상기 절연층(73)은 상기 보호범프(77)보다 높게 형성되며, 상기 보호범프를 덮게 될 수 있다. Except for the protective bumps 77 forming region, and forming an insulating layer 73 on the electrode formation surface of the substrate (step c) the insulating layer 73 is formed higher than the protection bump 77, the It may cover the protective bumps. 또한 상기 보호범프(77)가 외부에 노출되도록 상기 제1 및 제2 실시예에서와 같이 절연층(73)의 상면을 연마하게 된다.(단계c) 이와 같은 연마후에는 상기 보호범프(77)를 식각액에 의하여 제거하는 스트리핑 공정을 수행하게 되며, 이에 의해 기판의 전극이 외부에 노출되도록 한다.(단계 c) In addition, the protective bumps 77 is exposed to the outside of the first is to polish the upper surface of the insulating layer 73 as in the first and second embodiments (step c) this After such polishing the protective bumps 77 a is to perform a stripping step of removing by etching solution, such that the electrode exposed to the outside of the substrate by this (step c)

이와 같은 공정 후에는 상기 기판의 전극, 보호범프 제거부분, 및 연마면(78) 상에 무전해도금하여 통전시키고, 이에 의해 비아홀(79)을 형성하게 된다. After this the same process was energized by electroless plating on the electrode of the substrate, protecting the bumps of the removed portion, and the abrasive surface 78, to form a via hole (79) thereby. 또한 상기 비아홀(79)을 채우면서 상기 절연층(73) 상에 도전층(74)을 형성하게 되며, 도전층(74)에는 패턴을 형성하여 기판의 전극들이 외부와 연결될 수 있도록 추가전극이 형성되는 영역을 형성한다. In addition, the additional electrode is formed by filling the via hole 79 and to form a conductive layer 74 on the insulating layer 73, conductive layer 74 is to form a pattern number of electrodes of the substrate are connected with the outside that forms the area. 상기 추가전극 영역에 외부전극(75)을형성하며, 또한 외부전극 주위에 전극보호층(76)을 형성한다.(단계d) 제1 및 제2 실시예에서와 같은 상기의 단계들을 거친 후 다층기판(80)이 형성된다. Forming an outer electrode (75) in said additional electrode area, and thereby forming the electrode protection layer 76 around the outer electrode (step d) the first and after the above steps, such as in the second embodiment the multi-layer the substrate (80).

상기 절연층은 상기 기판이 플렉시블한 기판인 경우 열적 결함이 없는 성형수지를 사용하는 것이 바람직하다. The insulating layer it is preferable to use a molded resin without a thermal fault if the substrate is a flexible substrate. 또한 상기 절연층은 사출성형, 코팅 등의 방법을 통해 형성하게 된다. In addition, the insulating layer is formed by a method such as injection molding, coating.

이와 같은 방법으로 형성되는 다층기판은 4층 기판이 되나, 상기 도전층(74)의 패턴의 추가전극 영역 상에 다시 보호범프를 형성하고, 절연층 형성 및 연마 단계, 노출단계, 도전층 형성단계 및 패턴 형성단계를 적어도 1회이상 반복하여 4층 기판 이상의 다층기판을 구현할 수 있게 된다. The multi-layer substrate formed in this way is termed a four-layer board, the conductive layer 74, the pattern added to form a back protection bump on an electrode area, insulation layer is formed and a polishing step as in the exposure step, the conductive layer forming step and repeating at least once or more the pattern forming step, it is possible to implement a multi-layer substrate or more four-layer board.

이상과 같이 본 발명에 의하면 종래에 칩 패키지 공정 상에 사용되는 기판을 보호용 절연수지가 대신함으로써 패키지의 저비용화가 가능하게 되는 장점이 있다. According to the present invention as described above by replacing the substrate with a protective insulating resin to be used on the chip package to a conventional process it has the advantage of enabling low-cost upset of the package.

또한 본 발명에 의하면, 칩 패키지에 있어서 기판에 기계적인 방법에 의한 비아홀을 형성하는 공정 대신에 보호범프를 형성 및 스트리핑에 의해 제거하여 비아홀을 형성하는 공정을 사용하므로 작은 직경의 비아홀을 얻을 수 있어 칩 패키지의 소형화가 가능하며, 비아홀이 정확한 위치에 형성될 수 있는 효과가 있다. According to the present invention, uses the step of forming the via hole is removed by a via-hole forming and stripping the protective bumps in place of the step of forming the by mechanical means to the substrate in the chip package, it is possible to obtain a via hole of a small diameter enabling a reduction in the size of the chip package, there is an effect that the via hole can be formed in the correct position.

또한 플렉시블한 기판을 사용하여 칩 패키지를 제조하는 종래의 공정의 경우 기판이 플렉시블하게 되어 기판의 신뢰성이 문제가 되나, 본 발명에 의한 칩 패키지 제조의 경우 상기 플렉시블한 기판을 단단한 보호용 수지가 대신할 수 있게 되므로 공정을 단순화하게 되는 효과가 있다. In the case of a conventional process for producing a chip package using the flexible substrate substrate becomes flexible, but the reliability problem of the substrate, in the case of the chip package prepared according to the invention to replace a hard protective resin to the flexible substrate since there is an effect to be able to simplify the process.

또한, 와이어 본드 타입의 칩 패키지는 와이어의 휨, 절단 등의 문제로 칩 패키지의 불량을 초래하게 되는 문제가 있으나, 본 발명에 의한 칩 패키지의 경우 와이어를 사용하지 않게 되므로 상기와 같은 문제를 극복할 수 있는 효과가 있다. The chip package of the wire bond type is a problem that results in the failure of the chip package to problems such as bending, cutting of the wire. However, in the case of a chip package according to the present invention does not use a wire, so overcoming the problems as described above the effect can be.

또한, 본 발명에 의하면 초소형의 칩 패키지를 제조할 수 있게 되며, 다층 회로 구성이 가능하게 되어 다층 기판을 대신하는 저비용 칩 패키지를 제조할 수 있게 된다. Furthermore, according to the invention it becomes possible to manufacture a chip package, a compact, multi-layer circuit construction is possible it is possible to manufacture a low-cost chip package in place of the multi-layer substrate.

또한, 본 발명에 의하면 다층기판의 제조에 있어서 기판에 기계적인 방법에 의한 비아홀을 형성하는 공정 대신에 보호범프를 형성 및 스트리핑에 의해 제거하여 비아홀을 형성하는 공정을 사용하므로 작은 직경의 비아홀을 얻을 수 있어 소형화된 다층기판을 얻을 수 있으며, 비아홀이 정확한 위치에 형성될 수 있는 효과가 있다. Furthermore, according to the invention by removal of the protective bumps in the formation and stripping in place of the step of forming a via hole by mechanical means to a substrate in the production of multi-layer substrates using the process of forming the via hole so to obtain a via hole of a small diameter there can be obtained a multi-layer substrate smaller, there is an effect that the via hole can be formed in the correct position.

또한, 본 발명에 의하면 제조공정이 간단하게 되고 저비용화되며, 고집적화된 다층기판을 얻을 수 있는 효과가 있게 된다. Further, according to the present invention it is to simplify the manufacturing processes and cost reduction, it is possible to get a highly integrated multi-layer substrate effect.

본 발명은 특정한 실시예에 관련하여 도시하고 설명하였지만, 이하의 특허청구범위에 의해 마련되는 본 발명의 정신이나 분야를 벗어나지 않는 한도 내에서 본 발명이 다양하게 개조 및 변화될 수 있다는 것을 당업계에서 통상의 지식을 가진 자는 용이하게 알 수 있음을 밝혀두고자 한다. While the invention has been shown and described with reference to specific embodiments, more than the in the art that there may be modifications and changes to which the present invention vary to the extent not departing from the spirit and aspect of the present invention is provided by the claims with it discovered that one of ordinary skill can readily be seen Here.

Claims (60)

  1. 복수개의 전극을 갖는 회로소자의 전극 상부에 일정두께의 보호 범프를 형성하는 단계; Forming a protective bump having a predetermined thickness on the upper electrode of the circuit element having a plurality of electrodes;
    상기 보호 범프 영역을 제외한 상기 회로소자 상에 절연층을 형성하는 단계; Forming an insulating layer on the circuit elements other than the bump protection region;
    상기 보호 범프가 외부에 노출되도록 상기 절연층을 연마하는 단계; The protection step is to polish the bumps of the insulating layer so as to be exposed to the outside;
    상기 보호 범프를 제거하여 전극이 외부에 노출되도록 하는 단계; Stage such that the electrode is exposed to the outside by removing the protective bumps;
    상기 전극에 연결되는 도전층을 상기 절연층 상부에 형성하는 단계; Forming a conductive layer connected to the electrode on the insulating layer; And
    상기 도전층에 상기 전극에 대응하는 패턴을 형성하고, 상기 패턴 상에 외부전극을 형성하는 단계;를 포함하는 회로소자의 전극형성 방법. The method for forming electrodes of a circuit device including a; step of the conductive layer to form a pattern corresponding to the electrode, forming an external electrode on the pattern.
  2. 제 1항에 있어서, 상기 회로소자는 칩 소자 또는 기판인 것을 특징으로 하는 회로소자의 전극형성 방법. The method of claim 1, wherein the circuit element forming method of the electrode circuit element, characterized in that the chip device or substrate.
  3. 제 2항에 있어서, 상기 다른 회로소자는 칩 소자 또는 기판인 것을 특징으로 하는 회로소자의 전극형성 방법. The method of claim 2, wherein the further circuitry is how to form the electrode of the circuit element, characterized in that the chip device or substrate.
  4. 제 1항에 있어서, 상기 보호범프는 감광성물질인 것을 특징으로 하는 회로소자의 전극형성 방법. The method of claim 1, wherein the protection is a method of forming a bump electrode of the circuit element, characterized in that the photosensitive material.
  5. 제 4항에 있어서, 상기 보호 범프는 빛을 조사하는 스트리핑에 의하여 제거되는 것을 특징으로 하는 회로소자의 전극형성 방법. The method of claim 4, wherein the protection circuit is bump electrode forming method of a device characterized in that the removal by stripping of irradiating the light.
  6. 제 4항에 있어서, 상기 감광성물질은 포토 레지스트인 것을 특징으로 하는 회로소자의 전극형성 방법. 5. The method of claim 4 wherein forming the electrode of the circuit element, characterized in that the photosensitive material is photoresist.
  7. 제 1항에 있어서, 상기 절연층은 상기 보호 범프보다 높게 형성되는 것을 특징으로 하는 회로소자의 전극형성 방법. The method of claim 1, wherein the insulating layer is formed in the electrode of the circuit element, characterized in that the protection is formed above the bump.
  8. 제 1항에 있어서, 상기 도전층은 도금법을 이용하여 형성되는 것을 특징으로 하는 회로소자의 전극형성 방법. The method of claim 1, wherein the conductive circuit layer forming method of the electrode element, characterized in that formed using a plating method.
  9. 제 1항에 있어서, 상기 도전층은 구리를 포함한 금속층인 것을 특징으로 하는 회로소자의 전극형성 방법. The method of claim 1, wherein the conductive layer is formed in the electrode of the circuit, characterized in that a metal layer including a copper element.
  10. 제 1항에 있어서, 상기 절연층은 상기 회로소자의 일면과 수평하게 연마되는 것을 특징으로 하는 회로소자의 전극형성 방법. The method of claim 1, wherein the insulating layer is formed in the electrode of the circuit element, characterized in that the horizontally and polishing one surface of the circuit element.
  11. 다수개의 전극을 갖는 칩 소자를 마련하는 단계; Comprising: providing a chip device having a plurality of electrodes;
    상기 칩 소자의 전극 상부에 일정두께의 보호 범프를 형성하는 단계; Forming a protective bump having a predetermined thickness on the upper electrode of the chip element;
    상기 보호 범프 영역을 제외한 상기 칩 소자의 전극이 형성되어 있는 면 상에 절연층을 형성하는 단계; Forming an insulating layer on the side with the electrode of the chip components other than the bump protection area is formed;
    상기 보호 범프가 외부에 노출되도록 상기 절연층을 연마하는 단계; The protection step is to polish the bumps of the insulating layer so as to be exposed to the outside;
    상기 보호 범프를 제거하여 전극이 외부에 노출되도록 하는 단계; Stage such that the electrode is exposed to the outside by removing the protective bumps;
    상기 전극에 연결되는 도전층을 상기 절연층 상부에 형성하는 단계; Forming a conductive layer connected to the electrode on the insulating layer;
    상기 도전층에 상기 전극에 대응하는 추가 전극이 형성될 수 있는 패턴을 형성하는 단계; Forming a pattern with a further electrode corresponding to the electrode to the conductive layer may be formed;
    상기 패턴의 추가 전극 영역 상에 외부전극과 전극보호층을 형성하는 단계;를 포함하는 칩 패키지 제조방법. Method of producing the chip package, including; on the additional electrode area of ​​the pattern forming the outer electrode and the electrode protective layer.
  12. 제 11항에 있어서, 상기 칩 소자는 집적회로소자인 것을 특징으로 하는 칩 패키지 제조방법. 12. The method of claim 11, wherein the chip device manufacturing method characterized in that the chip package integrated circuit devices.
  13. 제 12항에 있어서, 상기 칩 소자를 마련하는 단계는 상기 칩 소자의 타면이 부착되는 기판을 마련하는 단계를 추가적으로 포함하며, 상기 칩 소자는 적어도 2개 이상인 것을 특징으로 하는 칩 패키지 제조방법. 13. The method of claim 12, wherein providing the chip element comprising the steps of: providing a substrate on which the other surface of the chip elements attached Additionally, the chip element method the chip package, characterized in that two or more at least.
  14. 제 11항에 있어서, 상기 칩 소자는 일면과 그에 대응하는 타면에 다수개의 전극이 형성된 집적회로소자인 것을 특징으로 하는 칩 패키지 제조방법. 12. The method of claim 11, wherein the chip device manufacturing method characterized in that the chip package integrated circuit device having a plurality of electrodes on the other side to one side and corresponding thereto.
  15. 제 11항에 있어서, 상기 보호범프는 감광성물질인 것을 특징으로 하는 칩 패키지 제조방법. 12. The method of claim 11, wherein the protective bumps are method-chip package, characterized in that the photosensitive material.
  16. 제 15항에 있어서, 상기 보호 범프는 빛을 조사하는 스트리핑에 의하여 제거되는 것을 특징으로 하는 칩 패키지 제조방법. The method of claim 15 wherein the protection is a method of manufacturing the chip package bumps characterized in that the removal by stripping of irradiating the light.
  17. 제 15항에 있어서, 상기 감광성물질은 포토 레지스트인 것을 특징으로 하는 칩 패키지 제조방법. The method of claim 15, wherein the photosensitive material A method of manufacturing chip package, characterized in that the photoresist.
  18. 제 11항에 있어서, 상기 절연층은 상기 보호 범프보다 높게 형성되는 것을 특징으로 하는 칩 패키지 제조방법. 12. The method of claim 11, wherein the insulating layer is produced, characterized in that the chip package which is formed higher than the protection bumps.
  19. 제 11항에 있어서, 상기 도전층은 도금법을 이용하여 형성되는 것을 특징으로 하는 칩 패키지 제조방법. 12. The method of claim 11, wherein the conductive layer is produced, characterized in that the chip package is formed using a plating method.
  20. 제 11항에 있어서, 상기 도전층은 구리를 포함한 금속층인 것을 특징으로 하는 칩 패키지 제조방법. 12. The method of claim 11, wherein the conductive layer is produced the chip package, characterized in that the metal layer includes copper.
  21. 제 11항에 있어서, 상기 절연층은 전극이 형성된 칩 소자의 면과 수평하게 연마되는 것을 특징으로 하는 칩 패키지 제조방법. 12. The method of claim 11, wherein the insulating layer is produced the chip package characterized in that the electrode is leveled with the surface of the polishing chip elements formed.
  22. 제 11항에 있어서, 상기 패턴의 추가 전극 영역 상에 일정 두께의 보호범프를 형성하고, 상기 절연층 형성 및 연마 단계, 노출 단계, 도전층 형성단계 및 패턴 형성단계를 적어도 1회이상 반복하는 단계를 추가적으로 포함하는 것을 특징으로 하는 칩 패키지 제조방법. The method of claim 11 wherein the step of forming a protective bump having a predetermined thickness on an additional electrode area of ​​the pattern, repeated at least once or more the insulating layer is formed and a polishing step, the exposing step, the conductive layer forming step and a pattern forming step method of manufacturing the chip package which is characterized in that it comprises additionally.
  23. 일면에 복수개의 전극을 갖는 복수개의 칩 소자가 형성된 웨이퍼를 마련하는 단계; Comprising: a plurality of chip devices having a plurality of electrodes formed on a surface providing a wafer;
    상기 칩 소자의 전극 상부에 일정두께의 보호 범프를 형성하는 단계; Forming a protective bump having a predetermined thickness on the upper electrode of the chip element;
    상기 보호 범프 영역을 제외한 상기 웨이퍼의 일면에 절연층을 형성하는 단계; Forming an insulating layer on one surface of the wafer except for the bump protection region;
    상기 보호 범프가 외부에 노출되도록 상기 절연층을 연마하는 단계; The protection step is to polish the bumps of the insulating layer so as to be exposed to the outside;
    상기 보호 범프를 제거하여 전극이 외부에 노출되도록 하는 단계; Stage such that the electrode is exposed to the outside by removing the protective bumps;
    상기 전극에 연결되는 도전층을 상기 절연층 상부에 형성하는 단계; Forming a conductive layer connected to the electrode on the insulating layer;
    상기 도전층에 상기 전극에 대응하는 추가 전극이 형성될 수 있는 패턴을 형성하는 단계; Forming a pattern with a further electrode corresponding to the electrode to the conductive layer may be formed;
    상기 패턴의 추가 전극 영역 상에 외부전극과 전극보호층을 형성하는 단계; Forming an external electrode and the electrode protective layer on the additional electrode area of ​​the pattern; And
    상기 웨이퍼를 칩 패키지 단위로 다이싱하는 단계;를 포함하는 칩 패키지 제조방법. Method of producing the chip package, including; the step of dicing the wafer into chip package unit.
  24. 제 23항에 있어서, 상기 칩 소자는 일면에 다수개의 전극이 형성된 집적회로소자인 것을 특징으로 하는 칩 패키지 제조방법. The method of claim 23, wherein the chip device manufacturing method characterized in that the chip package integrated circuit device having a plurality of electrodes on one side.
  25. 제 23항에 있어서, 상기 보호범프는 감광성물질인 것을 특징으로 하는 칩 패키지 제조방법. 24. The method of claim 23, wherein said protective bumps are method-chip package, characterized in that the photosensitive material.
  26. 제 25항에 있어서, 상기 보호 범프는 빛을 조사하는 스트리핑에 의하여 제거되는 것을 특징으로 하는 칩 패키지 제조방법. 26. The method of claim 25, wherein the protective bumps method chip package characterized in that the removal by stripping of irradiating the light.
  27. 제 25항에 있어서, 상기 감광성물질은 포토 레지스트인 것을 특징으로 하는 칩 패키지 제조방법. 26. The method of claim 25, wherein the photosensitive material A method of manufacturing chip package, characterized in that the photoresist.
  28. 제 23항에 있어서, 상기 절연층은 상기 보호 범프보다 높게 형성되는 것을 특징으로 하는 칩 패키지 제조방법. 24. The method of claim 23, wherein the insulating layer is produced, characterized in that the chip package which is formed higher than the protection bumps.
  29. 제 23항에 있어서, 상기 도전층은 도금법을 이용하여 형성되는 것을 특징으로 하는 칩 패키지 제조방법. The method of claim 23, wherein the conductive layer is produced, characterized in that the chip package is formed using a plating method.
  30. 제 23항에 있어서, 상기 도전층은 구리를 포함한 금속층인 것을 특징으로 하는 칩 패키지 제조방법. The method of claim 23, wherein the conductive layer is produced the chip package, characterized in that the metal layer includes copper.
  31. 제 23항에 있어서, 상기 절연층은 전극이 형성된 칩 소자의 면과 수평하게 연마되는 것을 특징으로 하는 칩 패키지 제조방법. 24. The method of claim 23, wherein the insulating layer is produced the chip package characterized in that the electrode is leveled with the surface of the polishing chip elements formed.
  32. 제 23항에 있어서, 상기 패턴의 추가 전극 영역 상에 일정 두께의 보호범프를 형성하고, 상기 절연층 형성 및 연마 단계, 노출 단계, 도전층 형성단계 및 패턴 형성단계를 적어도 1회이상 반복하는 단계를 추가적으로 포함하는 것을 특징으로 하는 칩 패키지 제조방법. 24. The method of claim 23, wherein the step of forming a protective bump having a predetermined thickness on an additional electrode area of ​​the pattern, at least a repeating once or more the insulating layer is formed and a polishing step, the exposing step, the conductive layer forming step and a pattern forming step method of manufacturing the chip package which is characterized in that it comprises additionally.
  33. 복수개의 전극이 형성되어 있는 기판의 각각의 전극 상에 일정두께의 보호범프를 형성하는 단계; Forming a protective bump having a predetermined thickness on each of the electrodes of the substrate on which the plurality of electrodes are formed;
    상기 보호 범프 영역을 제외한 상기 기판의 전극이 형성되어 있는 면에 절연층을 형성하는 단계; Forming an insulating layer on the side with the electrode of the substrate other than the bump protection area is formed;
    상기 보호 범프가 외부에 노출되도록 상기 절연층을 연마하는 단계; The protection step is to polish the bumps of the insulating layer so as to be exposed to the outside;
    상기 보호 범프를 제거하여 전극이 외부에 노출되도록 하는 단계; Stage such that the electrode is exposed to the outside by removing the protective bumps;
    상기 전극에 연결되는 도전층을 상기 절연층 상부에 형성하는 단계; Forming a conductive layer connected to the electrode on the insulating layer;
    상기 도전층에 상기 전극에 대응하는 추가 전극이 형성될 수 있는 패턴을 형성하는 단계; Forming a pattern with a further electrode corresponding to the electrode to the conductive layer may be formed; And
    상기 패턴의 추가 전극 영역 상에 외부 전극과 전극보호층을 형성하는 단계;를 포함하는 다층기판 제조방법. The multi-layer substrate manufacturing method that includes; on the additional electrode area of ​​the pattern forming the outer electrode and the electrode protective layer.
  34. 제 33항에 있어서, 상기 기판은 일면에 다수개의 전극이 형성된 것을 특징으로 하는 다층기판 제조방법. The method of claim 33, wherein the multilayer board manufacturing method is characterized in that the substrate is formed with a plurality of electrodes on one side.
  35. 제 33항에 있어서, 상기 기판은 양면이 통전되어 있으며, 일면과 그에 대응하는 타면에 다수개의 전극이 형성된 것을 특징으로 하는 다층기판 제조방법. 34. The method of claim 33, wherein the substrate is a double-sided, and is energized, a surface with a corresponding method of manufacturing the multi-layer substrate, characterized in that a plurality of electrodes are formed on the other surface of it.
  36. 제 33항에 있어서, 상기 패턴의 추가 전극 영역 상에 일정 두께의 보호범프를 형성하고, 상기 절연층 형성 및 연마 단계, 노출 단계, 도전층 형성단계 및 패턴 형성단계를 적어도 1회이상 반복하는 단계를 상기 패턴 형성단계 후에 추가적으로 포함하는 다층기판 제조방법. 34. The method of claim 33 wherein the step of forming a protective bump having a predetermined thickness on an additional electrode area of ​​the pattern, repeated at least once or more the insulating layer is formed and a polishing step, the exposing step, the conductive layer forming step and a pattern forming step method for producing a multi-layer substrate further comprises, after the pattern formation step.
  37. 제 33항에 있어서, 상기 보호범프는 감광성물질인 것을 특징으로 하는 다층기판 제조방법. The method of claim 33, wherein the protection process for producing the multi-layer substrate has bumps, characterized in that the photosensitive material.
  38. 제 37항에 있어서, 상기 보호 범프는 빛을 조사하는 스트리핑에 의하여 제거되는 것을 특징으로 하는 다층기판 제조방법. 38. The method of claim 37, wherein the protection is a method of manufacturing the multi-layer substrate bumps characterized in that the removal by stripping of irradiating the light.
  39. 제 37항에 있어서, 상기 감광성물질은 포토 레지스트인 것을 특징으로 하는다층기판 제조방법. The method of claim 37, wherein said photosensitive material is a method for producing the multi-layer substrate, characterized in that the photoresist.
  40. 제 33항에 있어서, 상기 절연층은 상기 보호 범프보다 높게 형성되는 것을 특징으로 하는 다층기판 제조방법. 34. The method of claim 33, wherein the insulating layer is produced, characterized in that the multi-layer substrate is formed higher than the protection bumps.
  41. 제 33항에 있어서, 상기 도전층은 도금법을 이용하여 형성되는 것을 특징으로 하는 다층기판 제조방법. The method of claim 33, wherein the conductive layer is produced, characterized in that the multi-layer substrate formed by using a plating method.
  42. 제 33항에 있어서, 상기 도전층은 구리를 포함한 금속층인 것을 특징으로 하는 다층기판 제조방법. The method of claim 33, wherein the conductive layer is produced multiple-layer substrate, characterized in that the metal layer includes copper.
  43. 제 33항에 있어서, 상기 절연층은 전극이 형성된 칩 소자의 면과 수평하게 연마되는 것을 특징으로 하는 다층기판 제조방법. The method of claim 33, wherein the insulating layer is a multilayer board manufacturing method characterized in that the electrode is leveled with the surface of the polishing chip elements formed.
  44. 다수개의 전극이 마련된 칩 소자; Chip element provided with a plurality of electrodes;
    상기 다수개의 전극영역을 제외한 상기 칩 소자의 전극이 형성되어 있는 면 상에 형성된 절연층; An insulating layer formed on the surface on which the electrodes of the chip components other than the plurality of electrode regions are formed;
    상기 전극영역을 채우면서 상기 절연층 상에 형성되며 상기 복수개의 전극영역 각각에 대응하도록 소정의 간격으로 전기적으로 분리되어 형성되는 도전층; The conductive layer, filling said electrode region is formed on the insulating layer to be formed is electrically isolated at a predetermined interval so as to correspond to each of the plurality of electrode regions;
    상기 도전층 상면에 형성되는 외부전극; External electrodes formed on an upper surface of the conductive layer; And
    상기 절연층 상면에서 상기 외부전극 주위에 형성되는 전극저항층을 포함하는 칩 패키지. Chip package, including the electrode resistance layer formed around the outer electrode from the upper surface of the insulating layer.
  45. 제 44항에 있어서, 상기 칩 소자는 일면에 다수개의 전극이 형성되어 있는 집적회로소자인 것을 특징으로 하는 칩 패키지. 45. The method of claim 44, wherein the chip components are chip package, characterized in that the integrated circuit device with a plurality of electrodes on one side is formed.
  46. 제 44항에 있어서, 상기 칩 소자는 적어도 2개 이상인 것을 특징으로 하는 칩 패키지. 45. The method of claim 44, wherein the chip components are chip package, characterized in that two or more at least.
  47. 제 46항에 있어서, 상기 칩 패키지는 상기 적어도 2개 이상의 칩 소자의 타면이 부착되는 기판을 추가적으로 포함하는 것을 특징으로 하는 칩 패키지. The method of claim 46 wherein the chip package, the chip package comprising: a substrate on which further attachment surface of the at least two chip components.
  48. 제 44항에 있어서, 상기 칩 소자는 일면과 그에 대응하는 타면에 다수개의 전극이 각각 형성된 집적회로소자인 것을 특징으로 하는 칩 패키지. 45. The method of claim 44, wherein the chip components are chip package, characterized in that a plurality of electrodes on the other side to one side and the corresponding integrated circuit devices are formed, respectively.
  49. 제 44항에 있어서, 상기 절연층은 상기 칩 소자의 측면의 일정부분에 추가적으로 형성되는 것을 특징으로 하는 칩 패키지. 45. The method of claim 44, wherein the insulating layer is characterized in that the chip package which is formed in addition to a portion of the side surface of the chip device.
  50. 제 44항에 있어서, 상기 절연층은 전극이 형성된 칩 소자의 면과 수평한 것을 특징으로 하는 칩 패키지. 45. The method of claim 44, wherein the insulating layer is the chip package, characterized in that the horizontal surface of the chip and the device electrodes.
  51. 제 44항에 있어서, 상기 도전층은 도금법을 이용하여 형성되는 것을 특징으로 하는 칩 패키지. 45. The method of claim 44, wherein the conductive layer, characterized in that the chip package is formed using a plating method.
  52. 제 44항에 있어서, 상기 도전층은 구리를 포함한 금속층인 것을 특징으로 하는 칩 패키지. 45. The method of claim 44, wherein the conductive layer chip package, characterized in that the metal layer includes copper.
  53. 제 44항에 있어서, 상기 칩 패키지는 상기 도전층 상면의 전극영역을 제외한 면 상에 형성되는 추가 절연층 및 상기 전극영역을 채우면서 상기 추가 절연층 상에 형성되며 상기 복수개의 전극영역 각각에 대응하도록 소정의 간격으로 전기적으로 분리되어 형성되는 추가 도전층을 적어도 1쌍 이상 추가로 포함하며, 45. The method of claim 44, wherein the chip package corresponding to each of the additional insulating layer and by filling the electrode area formed on the additional insulating layer of electrode the plurality of areas formed on the surface except for the electrode area of ​​the upper surface of the conductive layer to include an additional conductive layer to be formed is electrically isolated at a predetermined interval in addition at least one pair,
    상기 외부전극는 가장 상부에 형성되는 도전층 상면에 형성되고, 상기 전극저항층은 가장 상부에 형성되는 절연층 상면에 형성되는 것을 특징으로 하는 칩 패키지. Chip package, characterized in that the conductive layer is formed on the upper surface is formed in the upper part of the external jeongeukneun, the electrode resistance layer is formed on the upper surface of the insulating layer to be formed on top.
  54. 복수개의 전극이 형성되어 있는 기판; A substrate with a plurality of electrodes are formed;
    상기 복수개의 전극영역을 제외한 상기 기판의 전극이 형성되어 있는 면 상에 형성된 절연층; An insulating layer formed on the surface on which the electrode of the substrate other than the plurality of electrode regions are formed;
    상기 전극영역을 채우면서 상기 절연층 상에 형성되며 상기 복수개의 전극영역 각각에 대응하도록 소정의 간격으로 전기적으로 분리되어 형성되는 도전층; The conductive layer, filling said electrode region is formed on the insulating layer to be formed is electrically isolated at a predetermined interval so as to correspond to each of the plurality of electrode regions;
    상기 도전층 상면에 형성되는 외부전극; External electrodes formed on an upper surface of the conductive layer; And
    상기 절연층 상면에서 상기 외부전극 주위에 형성되는 전극저항층을 포함하는 다층기판. In the upper surface of the insulating layer multi-layer substrate including a resistive electrode layer formed around the outer electrode.
  55. 제 54항에 있어서, 상기 기판은 일면에 다수개의 전극이 형성된 것을 특징으로 하는 다층기판. 55. The method of claim 54, wherein the substrate is a multilayer substrate, characterized in that a plurality of electrodes formed on one surface.
  56. 제 54항에 있어서, 상기 기판은 양면이 통전되어 있으며, 일면과 그에 대응하는 타면에 다수개의 전극이 형성된 것을 특징으로 하는 다층기판. 55. The method of claim 54, wherein the substrate is double-sided and is energized, the multi-layer substrate, characterized in that a plurality of electrodes are formed on one surface and the other surface corresponding to it.
  57. 제 54항에 있어서, 상기 도전층은 도금법을 이용하여 형성되는 것을 특징으로 하는 다층기판. The method of claim 54, wherein the conductive layer has a multi-layer substrate, characterized in that formed using a plating method.
  58. 제 54항에 있어서, 상기 도전층은 구리를 포함한 금속층인 것을 특징으로 하는 다층기판. The method of claim 54, wherein the conductive layer has a multi-layer substrate, characterized in that the metal layer includes copper.
  59. 제 54항에 있어서, 상기 절연층은 전극이 형성된 칩 소자의 면과 수평하게 연마되는 것을 특징으로 하는 다층기판. The method of claim 54, wherein the insulating layer is a multilayer substrate characterized in that the horizontal and the polishing surface of the element chip electrodes.
  60. 제 54항에 있어서, 상기 다층기판은 상기 도전층 상면의 전극영역을 제외한면 상에 형성되는 추가 절연층 및 상기 전극영역을 채우면서 상기 추가 절연층 상에 형성되며 상기 복수개의 전극영역 각각에 대응하도록 소정의 간격으로 전기적으로 분리되어 형성되는 추가 도전층을 적어도 1쌍 이상 추가로 포함하며, The method of claim 54, wherein the multi-layer substrate, filling the additional insulating layer and the electrode region formed on the surface except for the electrode area of ​​the upper surface of the conductive layer formed on the additional insulating layer corresponding to each of the plurality of electrode regions to include an additional conductive layer to be formed is electrically isolated at a predetermined interval in addition at least one pair,
    상기 외부전극은 가장 상부에 형성되는 도전층 상면에 형성되고, 상기 전극저항층은 가장 상부에 형성되는 절연층 상면에 형성되는 것을 특징으로 하는 다층기판. The outer electrode is the upper portion and formed on the conductive layer top surface is formed on the electrode resistance layer is a multilayer board, characterized in that formed on the top insulating layer to be formed on the top.
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TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW584950B (en) * 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW544882B (en) * 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
US7452803B2 (en) * 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
KR100740358B1 (en) * 2005-02-25 2007-07-16 야마하 가부시키가이샤 Sensor including lead frame and method of forming sensor including lead frame
CN1901162B (en) * 2005-07-22 2011-04-20 米辑电子股份有限公司 Method for fabricating a circuitry component by continuous electroplating and circuitry component structure
KR100762423B1 (en) * 2006-06-27 2007-10-02 박영진 Semiconductor package and method of manufacturing the same
US7569422B2 (en) 2006-08-11 2009-08-04 Megica Corporation Chip package and method for fabricating the same
US7926173B2 (en) * 2007-07-05 2011-04-19 Occam Portfolio Llc Method of making a circuit assembly
JP5581519B2 (en) 2009-12-04 2014-09-03 新光電気工業株式会社 Semiconductor package and manufacturing method thereof
US9991407B1 (en) * 2010-06-22 2018-06-05 Banpil Photonics Inc. Process for creating high efficiency photovoltaic cells
KR101204743B1 (en) 2011-08-03 2012-11-26 하나 마이크론(주) Method of manufacturing a semiconductor package
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Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721155A (en) * 1995-02-13 1998-02-24 Lg Semicon Co., Ltd. Method for forming a via contact of a semiconductor device
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JP3939504B2 (en) * 2001-04-17 2007-07-04 カシオ計算機株式会社 Semiconductor device, method for manufacturing the same, and mounting structure
US20030082906A1 (en) * 2001-10-30 2003-05-01 Lammert Michael D. Via formation in polymers
US20030186536A1 (en) * 2002-03-29 2003-10-02 Brenner Michael F. Via formation in integrated circuits by use of sacrificial structures

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