JP5249132B2 - Wiring board - Google Patents

Description

  The present invention relates to a wiring board used for mounting an electronic component such as a semiconductor element (chip), and in particular, has a core board used as a base substrate, and wiring layers are laminated on both surfaces of the core board. The present invention relates to a wiring board having a structure.

  Such a wiring board is also referred to as “semiconductor package” or simply “package” in the following description for convenience in that it plays a role of mounting a semiconductor element (chip) or the like.

  When manufacturing semiconductor packages such as BGA (Ball Grid Array), LGA (Land Grid Array), and PGA (Pin Grid Array), a core layer (core substrate) generally used as a base material for the package A multilayer wiring structure is formed by sequentially repeating formation of an insulating layer, formation of a via hole in the insulating layer, and formation of a conductor pattern (wiring layer) including the inside of the via hole on both sides or one side by, for example, a build-up method. Finally, the outermost surface is covered with a protective film, and a required portion of the protective film is opened to expose a part (pad) of the conductor pattern. Further, in the case of BGA and PGA, balls and pins as external connection terminals are joined to the exposed pads.

  Such a semiconductor package has a chip component such as a semiconductor element mounted on one surface and is mounted on a mounting substrate such as a mother board via an external connection terminal provided on the other surface. That is, the chip component and the mounting substrate are electrically connected via the semiconductor package. For this reason, in the core substrate used as the base substrate of the package, a through hole is formed as means for electrically conducting both surfaces, and the through hole is filled with a conductive material. Then, on both ends (on the surface of the core substrate) of the conductor filled in the through hole, connection pads (also referred to as “receiving pads”) for facilitating interlayer connection with each wiring layer on both sides of the core substrate. ) Is provided.

  In the conventional method, a base substrate having a predetermined size and thickness (for example, a double-sided copper-clad laminate for a plastic package or an alumina for a ceramic package) according to the type of package and the function of a chip component to be mounted. A green sheet with a powder of aluminum or aluminum nitride bonded with an organic resin), and through holes are drilled in the required locations of the base substrate with a mechanical drill or the like (current technology has a diameter of about 300 μm) In the case of a ceramic package, the surface of the ceramic package is subjected to metallizing. Further, on the surface of the plastic package, electrolytic plating or the like is used. For the ceramic package, a screen printing method using a conductive paste is used. Conductor pattern (filling pad as above) so as to fill through hole Forming a included).

  In other words, a specific core substrate is prepared for each required package, and drilling (through hole formation), metalizing (metal layer formation), hole filling processing (through hole) is performed on the core substrate. It was necessary to fill the inside of the conductor).

  An example of a technique related to the conventional technique is described in Patent Document 1 below. In the structure of the wiring board disclosed in this document, through-filled vias are formed in the core board in the form of a matrix with the same diameter of 300 μm or less and at an equal pitch of 2 mm or less, and the surface of the core board is planar via an insulating layer. A wiring pattern is formed, and each pad portion of the wiring pattern is electrically connected in a one-to-one relationship with each corresponding via of the filled via via a connection via penetrating the insulating layer.

  In addition, as another technique related to this, as described in Patent Document 2 below, there is a wiring board using a substrate made of a porous metal oxide film having a large number of through holes as a base substrate. is there. In each through hole provided in the substrate, a conductive material is embedded in the through hole formed at a position where the electrode of the substrate is disposed, and an insulating material is embedded in the other through hole. Embedded.

JP-A-10-308565 JP 2004-273480 A

  As described above, in the conventional wiring board (package), as a means for electrically connecting the wiring layers on both sides of the core board, a through hole is formed in the core board, and this through hole (filling conductor) is further formed. It was necessary to form receiving pads on both sides of the sheet. In forming this through hole (including the receiving pad), a specific core substrate is prepared one by one in accordance with the type of the package and the function of the chip component to be mounted. Processing such as drilling, metalizing, and hole filling had to be performed.

  For this reason, it takes a long time to manufacture a core substrate suitable for the package, the target core substrate cannot be efficiently manufactured, and the time required to manufacture the core substrate is prolonged. There was a problem that the cost was high.

  On the other hand, it is necessary to increase the diameter of the receiving pad depending on the processing accuracy and alignment accuracy of the through hole with respect to the core substrate, the lamination accuracy of the wiring layer, and the like. For this reason, there is a problem that the degree of freedom in wiring design is hindered and the wiring density is restricted. In particular, with the demand for further downsizing of electronic devices, the current technology has also reached the limit of the diameter and arrangement pitch of the through holes, so that the wiring density of the entire wiring board is further restricted. .

  The present invention was created in view of the problems in the prior art, and can be used for common core substrates, reducing costs, increasing wiring density, and improving the degree of freedom in wiring design. An object is to provide a substrate.

  In order to solve the above-described problems of the prior art, according to the basic form of the present invention, a core substrate having a structure in which a large number of linear conductors penetrating in the thickness direction is densely provided in an insulating base material is provided. A pad made of a part of a wiring layer electrically connected to both ends of the core substrate so as to share a plurality of linear conductors is disposed opposite to both sides of the core substrate, and one of the core substrates is interposed through the pad. A wiring board is provided in which a wiring connection is formed between the first surface side and the other surface side.

  According to the configuration of the wiring board according to the present invention, the pads (a part of the wiring layer) are formed on both sides of the core board so as to share a plurality of linear conductors penetratingly formed in the thickness direction of the insulating base material. Since they are arranged so as to face each other, the wiring on one surface side of the core substrate and the wiring on the other surface side can be electrically connected via the pads arranged so as to face each other.

  In other words, the size and position of each pad arranged on both sides of the core substrate without preparing a specific core substrate one by one according to the type of wiring substrate and the function of the chip component to be mounted as in the past. It is possible to easily connect between both surfaces of the core substrate through the pad and a plurality of linear conductors connected to the pad, by simply changing.

  Thus, according to the present invention, since the core substrate can be shared, the cost can be reduced. In addition, it is not necessary to increase the diameter of the receiving pad depending on the alignment accuracy with respect to the core substrate as was done in the prior art, so the degree of freedom in wiring design can be increased and at the same time the wiring density is improved. Can also be planned.

It is sectional drawing which shows the structure of the wiring board (semiconductor package) which concerns on one Embodiment of this invention. FIG. 2 is an enlarged perspective view schematically showing a configuration of a main part of the wiring board of FIG. 1 (relative relationship between a linear conductor on a core board and a pad connected thereto). It is sectional drawing which shows an example of the manufacturing process of the wiring board of FIG. FIG. 4 is a cross-sectional view showing a step that follows the manufacturing step of FIG. 3. FIG. 5 is a cross-sectional view showing a step that follows the manufacturing step of FIG. 4. It is sectional drawing which shows the state (semiconductor device) which mounted the semiconductor element (chip) on the wiring board of FIG.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings.

  FIG. 1 shows a configuration of a wiring board (semiconductor package) according to an embodiment of the present invention in the form of a sectional view. The wiring substrate (package) 30 of this embodiment has a semiconductor element (silicon chip) mounted on one surface as described later, and is mounted on a mounting substrate such as a mother board via an external connection terminal provided on the other surface. It is intended to be implemented and used.

  The wiring board 30 according to the present embodiment includes a core substrate 10 used as a base substrate as shown in the figure, and a buildup layer 20 that is laminated on the both sides of the core substrate 10 by the required number of layers. Yes. Each build-up layer 20 includes an insulating layer 21 formed on the core substrate 10 and a conductor patterned in a required shape on the insulating layer 21 by filling a via hole formed in a required portion of the insulating layer 21. A layer (first wiring layer) 22, an insulating layer 23 formed on the wiring layer 22, and a via hole formed in a required portion of the insulating layer 23 to fill the insulating layer 23 with the required And a conductor layer (second wiring layer) 24 patterned into a shape, and further, a pad portion defined at a required portion of the wiring layer 24 is exposed to cover the surface. And an insulating layer (solder resist layer) 25 as a protective film. As the material of the wiring layers 22 and 24, copper (Cu) is typically used, and as the material of the insulating layers 21, 23, 25, a resin typified by an epoxy resin or the like is used.

  The core substrate 10 used as the base substrate is a member characterizing the present invention, and a linear conductor 12 having a small diameter penetrating in the thickness direction is provided in an insulating substrate 11 having a predetermined thickness. It has a structure with high density at intervals. That is, the linear conductor 12 is formed such that both ends thereof are exposed on both surfaces of the insulating base material 11.

  As described later, since a part of the core substrate 10 is used as a capacitor as the insulating base material 11, it is desirable to use a material having a dielectric constant as high as possible. For example, an inorganic dielectric such as alumina (aluminum oxide) can be preferably used. Further, by using an inorganic material such as alumina, the coefficient of thermal expansion (CTE) of the core substrate 10 as a whole, and thus the CTE of the package 30 as a whole, can be used as the CTE of the semiconductor (silicon) chip mounted on the package 30. You can get closer. Incidentally, the CTE of silicon constituting the chip is about 3 ppm / ° C., whereas the CTE of alumina constituting the insulating substrate 11 is about 6 to 7 ppm / ° C.

  Furthermore, on both surfaces of the core substrate 10, pads configured by a part of the wiring layer 22 (that is, formed simultaneously with the formation of the wiring layer 22) are disposed at required positions. FIG. 2 schematically shows the arrangement of the pads (relative relationship between the linear conductors 12 on the core substrate 10 and the pads connected thereto).

  That is, as shown in FIG. 2A, the pads formed on both surfaces of the core substrate 10 have a plurality of linear conductors 12 as a group, and the linear conductors 12 are shared by each group at both ends. A pair of pads P1, P2 arranged oppositely (connected) and a plurality of linear conductors 12 as a group as shown in FIG. 2 (b) are connected only to one end side of the linear conductor 12 for each group. Pads P3 and P4. In the arrangement form shown in FIG. 2A, the opposed pads P <b> 1 and P <b> 2 are electrically connected via the plurality of linear conductors 12. On the other hand, in the arrangement shown in FIG. 2B, the pad P3 (P4) formed on one surface and the plurality of linear conductors 12 connected thereto, and the pad P4 formed on the other surface. (P3) and the plurality of linear conductors 12 connected thereto are not electrically connected, and are capacitively coupled only through a dielectric (insulating base material 11).

  As described above with reference to FIG. 2, the plurality of linear conductors 12 provided on the core substrate 10 include a plurality of linear conductors 12 as a group, and each of the pads P1, P2, P3, and P4 is arranged on each group. Also included are isolated linear conductors 12 that are electrically connected but not connected to any of the pads P1-P4, as shown.

  The linear conductor 12 is formed by filling a through hole formed in the insulating base material 11 with a metal material as will be described later. The role of the linear conductor 12 is roughly divided into two in this embodiment. For example, as illustrated in FIG. 2A, one of the linear conductors 12 receives a signal on one end side (pads on one side of the pads P1 and P2 arranged opposite to each other) and receives the signal on the other end side (the other side). To the side pad). That is, it plays a role for electrically connecting the wiring layers 22 and 24 on one side and the wiring layers 22 and 24 on the other side through the core substrate 10. This corresponds to the role of a through hole (a conductor filled in) provided in a conventional core substrate.

  As illustrated in FIG. 2B, the other role is different from (a) in that one of the pads P3 and P4 that are not directly connected is connected to the power supply line and the other is connected to the ground line. Thus, it is intended to function as a capacitor between the two, and to prevent inconvenient signal coupling (noise) from the circuit to the circuit caused through the power supply line. The capacitive component also has a role of supplying an instantaneous current.

  Since the linear conductor 12 provided on the core substrate 10 as described above needs to play an important role, when an arbitrary region on the insulating base material 11 is selected as a signal connection portion during design, In any of the selected regions, it is desirable that an average number of linear conductors 12 be included. Therefore, it is necessary to increase the metal filling density in the insulating base 11 as much as possible. For this reason, as described above, the linear conductors 12 having a small diameter are arranged at a high density.

  In the present embodiment, the linear conductors 12 provided on the core substrate 10 are such that the distance (D) between the adjacent linear conductors 12 is smaller than the diameter (d) of the linear conductors 12 (D <d). Have been placed. More preferably, the diameter (d) of the linear conductor 12 is selected to be about 30 nm to 2 μm. The arrangement of the linear conductors 12 is not particularly limited as long as D <d is satisfied. For example, it may be arranged in a hexagonal shape or may be arranged in a grid shape. In addition, the pads P1, P2, P3, and P4 formed on both surfaces of the core substrate 10 are arranged for each group with the plurality of linear conductors 12 as a group as described above. Is selected to be about 90 to 100 μm, thousands of linear conductors 12 are connected to the pad.

  Insulating layers 21 are formed on both surfaces of the core substrate 10 thus configured so as to cover the region between the pads P1 and P3 and the region between the pads P2 and P4, respectively. To be precise, after the insulating layer 21 is formed on both surfaces of the core substrate 10 as will be described later, a conductive material is filled in a via hole formed in a required portion (position where the pad is to be formed) of the insulating layer 21. As a result, the pad is formed. The first wiring layer 22 is also formed at the same time when the conductive material is filled. That is, the pads P1 to P4 are formed integrally with the corresponding wiring layer 22. Further, an insulating layer 23, a second wiring layer 24, and an outermost insulating layer (solder resist layer) 25 are sequentially formed on each wiring layer 22.

  Hereinafter, a method for manufacturing the wiring board (package) 30 according to the present embodiment will be described with reference to FIGS.

  First, in the first step (see FIG. 3 (a)), as the insulating base 11, a green sheet of alumina (aluminum oxide) (with a thickness of about 70 to 100 μm and a size of about 10 × 10 mm is prepared, A large number of through holes TH are formed in the thickness direction of the entire sheet by punchers, etc. That is, since the through holes TH are filled with the linear conductor 12, the above-mentioned predetermined relationship: D (line The through holes TH are formed at a high density so as to satisfy the distance between the linear conductors 12) <d (diameter of the linear conductor 12).

  In the present embodiment, as described above, the metal filling density in the insulating base material 11 is intended to be as high as possible. For this reason, the diameter (d) of the linear conductor 12 is desirably as small as possible (preferably about 30 nm to 2 μm). Such a small-diameter hole (through hole TH) can be formed by using an anodic oxidation method.

  For example, an aluminum (Al) substrate having an insulating coating on one surface is prepared, and after cleaning the surface of the Al substrate, it is immersed in an electrolytic solution (preferably an aqueous sulfuric acid solution). A platinum (Pd) electrode placed opposite to this is energized as a cathode (pulse voltage is applied), so that a porous metal oxide film (aluminum oxide film in which fine pores are regularly formed) on the surface of the Al substrate. Can be formed. Thereafter, a porous metal oxide film is separated from the Al substrate by applying a voltage having a potential opposite to that of anodic oxidation to each electrode (the Al substrate is used as a cathode and the Pd electrode is used as an anode). As a result, an insulating base material (alumina) 11 in which through holes TH having a desired minute diameter (about 30 nm to 2 μm) are formed at a high density is obtained.

  In addition to alumina (aluminum oxide), an inorganic material such as titanium oxide, aluminum nitride, mullite, and glass ceramics (a composite material of glass and ceramics) can be used as the material for the insulating base material 11. In addition, a metal oxide having a perovskite structure, for example, an inorganic material such as BTO (barium titanate), STO (strontium titanate), BST (barium strontium titanate), or PZT (lead titanium zirconate) may be used. Is possible.

  In this embodiment, since a part of the core substrate 10 is intended to function as a capacitor, such an inorganic material has a relatively high dielectric constant. Is preferred. For example, when mullite is used, the dielectric constant is slightly inferior to that of alumina (the dielectric constant of alumina is about 8 to 10, whereas the dielectric constant of mullite is 6.5). This is advantageous in terms of speeding up, and is particularly useful when used as a core substrate of a package on which a chip component that requires high-speed switching operation is mounted.

  In the next step (see FIG. 3B), the linear conductor 12 is formed by filling the through hole TH formed in the insulating base material 11 with a metal material. For example, the through hole TH is filled with the metal material by a screen printing method or an ink jet method using a conductive paste such as silver (Ag) or copper (Cu).

  Further, both surfaces are polished and flattened by mechanical polishing, chemical mechanical polishing (CMP), or the like as necessary, and both ends of the linear conductor 12 are exposed on both surfaces of the insulating substrate 11. As a result, as shown in the drawing, a structure in which the minute diameter linear conductors 12 penetrating the insulating base material 11 in the thickness direction are provided at a high density, that is, the core substrate 10 is manufactured.

  In the next step (see FIG. 3C), insulating layers 21A are formed on both surfaces of the core substrate 10, respectively. As a material of the insulating layer 21A, an epoxy resin, a polyimide resin, or the like generally used in a build-up multilayer wiring board is used. As the resin type, either a thermosetting resin or a photosensitive resin can be used, but in the present embodiment, a thermosetting epoxy resin is used. In addition, the form of the resin is not limited to a liquid form, and a resin-molded form can also be used. That is, the required insulating layer 21A is formed by coating the core substrate 10 with a thermosetting epoxy resin or laminating a thermosetting epoxy resin film and thermosetting it.

  In the next step (see FIG. 3 (d)), each insulating layer 21A formed on both surfaces of the core substrate 10 is opened at a required location by a carbon dioxide laser, an excimer laser, etc. The reaching via holes VH1 and VH2 are formed (formation of the insulating layer 21). Each via hole VH1, VH2 is formed according to the shape of each pad P1, P3, P2, P4 to be formed on both surfaces of the core substrate 10.

  In the next step (see FIG. 3E), a conductor layer 22A is formed on each insulating layer 21 on both surfaces of the core substrate 10 so as to fill the via holes VH1 and VH2 formed in the insulating layer 21, respectively. . For example, it can be formed as follows.

  First, seed layers are formed on both surfaces (on the insulating layer 21) of the core substrate 10 by sputtering, electroless plating, or the like. For example, a titanium (Ti) conductor layer is formed on both sides by sputtering to a thickness of about 0.1 μm, and a copper (Cu) conductor layer is further formed thereon by sputtering to a thickness of about 0.5 μm. A seed layer having a two-layer structure (Ti / Cu) is formed. The lower Ti layer of the seed layer is a metal layer for improving the adhesion between the lower insulating layer 21 and the insulating substrate 11 and the upper Cu layer. Chrome (Cr) may be used instead of Ti. Next, a conductor (Cu) layer 22A having a required thickness is formed on each seed layer by electrolytic Cu plating using the seed layer as a power feeding layer.

  Of the portions constituting the conductor layer 22A thus formed, the conductor portions filled in the via holes VH1 and VH2 constitute pads P1, P3, P2 and P4, respectively.

  In the next step (see FIG. 4A), each conductor layer 22A (FIG. 3E) formed on both surfaces (on the insulating layer 21) of the core substrate 10 is patterned into a required shape. A first wiring layer 22 is formed. For example, it can be formed as follows.

  First, an etching resist is formed on both surfaces (on the insulating layer 21) of the core substrate 10 by using a patterning material, and respective required portions are opened (formation of a resist layer having an opening). Each opening is patterned so that only the pattern portion remains according to the pattern shape of the wiring layer 22 to be formed. As a patterning material, a photosensitive dry film (a film having a resist material sandwiched between a polyester cover sheet and a polyethylene separator sheet), or a liquid photoresist (for example, a novolak resin, an epoxy resin, etc.) Liquid resist) can be used.

  For example, when using a dry film, after cleaning the surface of each conductor layer 22A, a dry film (separated from the separator sheet) is laminated on the surface by thermocompression bonding, and the dry film is formed into a required shape. Using a patterned mask (not shown), exposure by ultraviolet (UV) irradiation is performed and cured, and after the cover sheet is peeled off, a predetermined developer (in the case of a negative resist, containing an organic solvent) The portion is etched using a developer or an alkaline developer in the case of a positive resist to form a required resist layer (not shown). Similarly, when a liquid photoresist is used, a resist layer (not shown) patterned in a required shape can be formed through the steps of surface cleaning → resist application on the surface → drying → exposure → development. it can.

  Next, using this resist layer as a mask, the exposed portion of the conductor layer (Cu) 22A is removed, and further, the portion of the seed layer (Ti / Cu) exposed after the removal is removed. For example, wet etching using a chemical solution soluble only in Cu is performed, and then wet etching using a chemical solution soluble only in Ti is performed.

  Thereafter, the resist layer used as the etching resist is removed. When a dry film is used as an etching resist, it can be removed using an alkaline chemical such as sodium hydroxide or monoethanolamine. When a liquid resist such as a novolac resin or an epoxy resin is used. Can be removed using acetone, alcohol or the like. Then, predetermined surface cleaning is performed.

  As a result, as shown in the figure, the pads P1 and P2 that are arranged oppositely (connected) so as to share the plurality of linear conductors 12 on both surfaces of the core substrate 10 are exposed, and the plurality of linear conductors 12 are grouped together. A structure in which pads P3 and P4 connected only to one end side are formed integrally with the corresponding wiring layer 22 is produced.

  In the next step (see FIG. 4B), in the same manner as the processing performed in the step of FIG. 3C, the wiring layer 22 on each side and the exposed insulating layer 21 (exposed pad). A thermosetting epoxy resin is coated on (including P1 and P2) or a thermosetting epoxy resin film is laminated and thermally cured to form a required insulating layer 23A.

  In the next step (see FIG. 4 (c)), in the same manner as the process performed in the step of FIG. 3 (d), each insulating layer 23A is opened with a carbon dioxide gas laser, an excimer laser, or the like. Then, the via holes VH3 and VH4 are formed (formation of the insulating layer 23). The via holes VH3 and VH4 are formed in accordance with the shapes of the pads P1 and P2 disposed opposite to both surfaces of the core substrate 10 and the pads (not shown) defined in the wiring layers 22.

  In the next step (see FIG. 5A), via holes VH3 formed in the insulating layer 23 on the respective insulating layers 23 on the respective surface sides in the same manner as the processing performed in the step of FIG. , VH4 (FIG. 4C) is formed to form a conductor (Cu) layer 24A.

  In the next step (see FIG. 5B), in the same manner as the processing performed in the step of FIG. 4A, each conductor layer 24A on each side is patterned into a required shape, and 2 A second wiring layer 24 is formed.

  In the last step (see FIG. 5C), the portions of the pads respectively defined at required portions of each wiring layer 24 are exposed on the wiring layer 24 on each side and the exposed insulating layer 23. Then, a solder resist layer 25 is formed so as to cover the surface. For example, a photosensitive epoxy resin (solder resist) is applied to the surface, and each resin layer is patterned into a required shape (a shape in which the pad portion is exposed), thereby forming the solder resist layer 25. can do.

  Each pad exposed from the opening of each solder resist layer 25 (a part of the wiring layer 24) is used when mounting the electrode terminal of the chip mounted on the package 30 and the package 30 on a mother board or the like. Since external connection terminals (solder balls, metal pins, etc.) are joined, it is desirable to apply Ni plating and Au plating on the pads (Cu) in this order. Here, the Ni layer is provided in order to improve the adhesion between the Cu layer and the Au layer and prevent Cu from diffusing into the Au layer. The outermost Au layer is finally formed on the chip. It is provided to improve contactability when electrode terminals and the like are joined.

  As a result, the wiring board (package) 30 of this embodiment is manufactured as shown in the figure. As described above, the wiring board (package) 30 is used by mounting a semiconductor element on one surface and mounting it on a mounting substrate such as a mother board via an external connection terminal provided on the other surface. Intended.

  FIG. 6 shows an example of the mounting state, and shows a state (semiconductor device 40) in which a semiconductor element (silicon chip 41) is mounted on the wiring board (package) 30. In this semiconductor device 40, the electrode terminals 42 of the chip 41 are electrically connected to the pads of the corresponding wiring layer 24 on the wiring board 30 via a conductive material such as solder bumps (flip chip mounting). Further, the space between the mounted chip 41 and the wiring board 30 is filled with an underfill resin 43 such as a thermosetting epoxy resin, and is thermally cured to mechanically connect the chip 41 and the wiring board 30. Is ensured.

  On the other hand, solder balls 45 used as external connection terminals are joined to pads of the wiring layer 24 exposed from the solder resist layer 25 on the side opposite to the chip mounting surface side. The wiring board 30 is mounted on a mother board or the like via the solder balls 45.

  As described above, according to the configuration of the wiring board (package) 30 according to the present embodiment, the linear conductor 12 having a small diameter penetrating in the thickness direction in the insulating base material 11 of the core substrate 10 is high. Two types of pads (refer to FIG. 2) each composed of a part of the wiring layer 22 at a required location on each side of the core substrate 10, that is, a plurality of linear conductors 12 as a group. One end side of the linear conductor 12 for each group, with the pads P1 and P2 connected (oppositely arranged) at both ends in a form sharing the linear conductor 12 for each group and a plurality of linear conductors 12 as a group. Pads P3 and P4 connected only to are formed.

  Thereby, the wiring layer 22 (and the wiring layer 24 connected thereto) formed on one surface side of the core substrate 10, and the wiring layer 22 (and the wiring layer 24 connected thereto) formed on the other surface side. Can be electrically connected via a pair of pads P1 and P2 arranged opposite to each other on the core substrate 10 and a plurality of linear conductors 12 connected thereto. That is, there is no need to prepare a specific core substrate one by one according to the type of package and the function of the chip component to be mounted as in the conventional case, and the size of the pads P1 and P2 arranged on both surfaces of the core substrate 10 It is possible to easily connect the both surfaces of the core substrate 10 via the minute-diameter linear conductors 12 formed on the core substrate 10 only by appropriately changing the position.

  As described above, according to the present embodiment, since the core substrate 10 can be shared, the manufacturing cost can be reduced. In addition, since it is not necessary to increase the diameter of the receiving pad depending on the alignment accuracy with respect to the core substrate as in the prior art, the degree of freedom in wiring design can be increased, and the entire wiring substrate can be increased. The wiring density can be improved.

  Further, since the pads P3 and P4 are arranged in a specific arrangement form as illustrated in FIG. 2B on both surfaces of the core substrate 10, these pads P3 and P4 are used as capacitor electrodes, and By using the insulating base material 11 in the core substrate 10 as a dielectric, a part of the core substrate 10 (a region where the pads P3 and P4 are formed) can function as a capacitor. That is, the capacitor function can be easily built in the package 30.

  With recent downsizing and thinning of electronic devices such as mobile devices and portable devices, a technology that incorporates a capacitor function in a substrate (package) has been put into practical use. In a method (typically, a capacitor formed in advance in a film is embedded in a substrate and connected to a wiring layer, or a high dielectric layer is formed on an electrode layer (conductor layer) in the substrate). However, a problem has been pointed out that it is difficult to obtain a large capacity sufficient to achieve the required decoupling effect due to design constraints. In particular, in order to increase the facing area of an electrode (a part of a conductor layer) sandwiching a dielectric as a means for obtaining a large capacity, it is necessary to allocate most of the conductor layer exclusively for the electrode. Therefore, the degree of freedom in designing other wiring patterns is hindered.

  On the other hand, according to the configuration of the package 30 of the present embodiment, the capacitor capacitance can be increased by appropriately changing the size and relative position of the capacitor electrodes (pads P3 and P4) arranged on both surfaces of the core substrate 10 and designing the capacitor capacitance. It can be easily changed and can cope with an increase in capacity. Further, since the capacitor is built in the core substrate 10, the design freedom of the wiring pattern in the buildup layer 20 is not affected.

  For example, such a capacitor structure (a part of the core substrate 10) is connected to a pad connected to a wiring layer connected to a power supply terminal of the chip 41 (FIG. 6) mounted on the package 30 and a ground terminal of the chip 41. When it is provided so as to be interposed between the pads connected to the connected wiring layer, the inductance of the wiring connecting the capacitor and the chip 41 can be reduced equivalently. As a result, the power supply line and the like can be effectively decoupled. Such “decoupling” is particularly useful when the mounted chip 41 is a device that requires a high-speed switching operation such as an MPU.

  The material constituting the core substrate 10 (insulating substrate 11) as the base substrate of the package 30 is a coefficient of thermal expansion of the mounted silicon chip 41 (FIG. 6) (CTE: about 3 ppm / ° C.). Is used as much as possible (CTE: about 6 to 7 ppm / ° C.), both of which are caused by the difference in CTE between the chip 41 and the package 30 during chip mounting and during subsequent use (when energized). Even when stress (thermal stress) is generated in the meantime, the generated thermal stress (which may cause a warping of the package) can be effectively absorbed (relieved) in the core substrate 10. This contributes to improving the connection reliability between the chip 41 to be mounted and the package 30.

  In addition, when the pads P1 and P2 arranged oppositely (connected) are used as signal terminals, a line connected to a pad connected to the ground wiring around the plurality of linear conductors 12 connected to the pads P1 and P2 By arranging the conductor 12, a specific effect can be provided. That is, since this configuration has a structure equivalent to a kind of coaxial line, a shielding (shielding) effect can be achieved. In addition, since the ground layer is arranged so as to surround each of the pads P1 and P2, the pads P1 and P2 (signal terminals) and the adjacent signal terminals (similarly arranged facing the pads P1) , P2) can be reduced in electrical coupling (capacitive coupling). As a result, the signal terminal itself can be prevented from becoming a noise source.

  In the above-described embodiment, the case where an inorganic dielectric such as alumina is used as the material constituting the insulating base material 11 of the core substrate 10 has been described as an example. However, the substrate material is not limited to this. . That is, as is clear from the gist of the present invention (increasing the common use of the core substrate, increasing the wiring density, and increasing the degree of freedom in wiring design), when the core substrate does not need to function as a capacitor, It is not always necessary to use an inorganic dielectric as the substrate material. For example, an organic resin typified by an epoxy resin or a polyimide resin can be used.

  However, when an organic resin is used as the material of the insulating substrate 11, it is desirable to use a material in which an inorganic filler such as silica is mixed at a high density. Since the coefficient of thermal expansion (CTE) of silica is as small as 0.5 ppm / ° C., it contributes to lowering the CTE of the entire core substrate 10. That is, by lowering the CTE of the core substrate 10 that is the base substrate of the package 30, the CTE of the entire package 30 is brought closer to the CTE of the semiconductor chip to be mounted. As a result, as in the case of using an inorganic dielectric such as alumina, stress (thermal stress) that can be generated between the two due to the difference in CTE between the chip and the package 30 in the chip mounting state is effective in the core substrate 10. Can be relaxed. In addition to silica, alumina, silicon nitride, aluminum nitride, or the like can be used as the inorganic filler added to the resin.

  Further, when an organic resin is used as the insulating base material 11, the through hole TH provided in the insulating base material 11 in the process of FIG. 3A is drilled using a carbon dioxide laser, an excimer laser, or the like. It is formed by. Further, in the step of FIG. 3B, the filling of the metal material into the through hole TH can be performed by a plating method. As the metal material, Cu, Ni, or the like is preferably used in terms of easy availability and ease of processing. For example, when Cu is used as the metal material, a seed layer is formed on the surface of the insulating substrate 11 (including the inner wall surface of the through hole TH) by electroless Cu plating, and electrolysis using this seed layer as a power feeding layer. The through hole TH is filled with a conductor (Cu) by Cu plating. Instead, it may be filled only with electroless Cu plating.

10: Core substrate (base material),
11 ... Insulating substrate,
12 ... Linear conductor,
20 ... Build-up layer,
21, 23 ... Resin layer (insulating layer),
22, 24 ... conductor layer (wiring layer),
25. Solder resist layer (protective film / insulating layer),
30 ... Wiring board (semiconductor package),
40: Semiconductor device (structure in which a semiconductor element is mounted on a package),
P1, P2, P3, P4... Pads (parts composed of a part of the wiring layer).

Claims (6)

A core substrate having a plurality of linear conductors penetrating inorganic dielectric consists of material insulating base in the thickness direction is provided in close-packed structure,
A first pad formed on one surface of the core substrate and electrically connected to one end of the first plurality of linear conductors of the plurality of linear conductors;
A second pad formed on the other surface of the core substrate, disposed opposite to the first pad, and electrically connected to the other ends of the first plurality of linear conductors;
A third pad formed on one surface of the core substrate and electrically connected to one end of a second plurality of linear conductors of the multiple linear conductors;
Formed on the other surface of the core substrate, arranged adjacent to the third pad in a plan view and without overlapping the third pad, and a third plurality of the plurality of linear conductors A fourth pad electrically connected to one end of the linear conductor;
Have
A wiring connection between one surface side and the other surface side of the core substrate is formed through the first and second pads ,
The third pad and the second plurality of linear conductors, and the fourth pad and the third plurality of linear conductors are capacitively coupled through the insulating base material. Wiring board to be used.   The plurality of linear conductors in the insulating base material of the core substrate are arranged such that the distance between adjacent linear conductors is smaller than the diameter of the linear conductor. The wiring board described. A first insulating layer formed on one surface of the core substrate and covering a region between the first and third pads;
A first wiring layer formed integrally with the first pad on the first insulating layer;
A second wiring layer formed integrally with the third pad on the first insulating layer;
A second insulating layer formed on the other surface of the core substrate and covering a region between the second and fourth pads;
A third wiring layer formed integrally with the second pad on the second insulating layer;
A fourth wiring layer formed integrally with the fourth pad on the second insulating layer;
The wiring board according to claim 2, characterized in that it comprises a. The multiple linear conductors in the insulating base material of the core substrate include isolated linear conductors that are not connected to any of the first, second, third, and fourth pads. The wiring board according to claim 3 . A number of linear conductors in the insulating base material of the core substrate are linear conductors positioned around the first plurality of linear conductors connected to the first and second pads connected to the signal wiring. 5. The wiring board according to claim 4 , further comprising a linear conductor connected to a pad connected to the ground wiring.   The wiring board according to claim 2, wherein the linear conductor is formed within a range of a diameter of 30 nm to 2 μm.

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