JP2007318090A - Method for manufacturing wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board in which the process can be simplified. <P>SOLUTION: In a preparation step, a core substrate 11 and an electronic component 101 are prepared. In an insulation layer forming and securing step; a lowermost resin insulation layer 33 is formed after an electronic component 101 is contained in a containing hole 90, and then the electronic component 101 is secured to the core substrate 11 by filling the clearance between the electronic component 101 and the core substrate 11 with a portion of the lowermost resin insulation layer 33. In an opening forming step, a portion of the lowermost resin insulation layer 33 directly above the clearance between the electronic component 101 and the core substrate 11 is removed to form an opening for exposing part of a core substrate major surface side conductor 51 and a component major surface side electrode 111. In a major surface side connection conductor forming step, a major surface side connection conductor 61 is formed in the opening to connect the core substrate major surface side conductor 51, and the component major surface side electrode 111. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a wiring board in which an electronic component is embedded in a core board and a wiring laminated portion is formed on the surface thereof.

  In recent years, semiconductor integrated circuit elements (IC chips) used for a CPU of a computer have been increased in speed and function, and accordingly, the number of terminals is increased and the pitch between terminals tends to be narrowed. In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In an IC chip mounting wiring board constituting this type of package, it has been proposed to provide a capacitor in order to reduce switching noise of the IC chip and stabilize the power supply voltage. Note that when the wiring connecting the IC chip and the capacitor becomes long, the inductance component of the wiring increases and the above effect cannot be obtained. Therefore, the capacitor is preferably arranged as close to the IC chip as possible. As an example, a wiring board in which a capacitor is arranged in a core substrate located directly under an IC chip has been proposed (see, for example, Patent Document 1).

  If the power supply voltage supplied to the IC chip is insufficient, the IC chip malfunctions, and there is a demand for supplying as much power as possible to the IC chip. Therefore, the conventional wiring board is provided with a plurality of power supply paths for supplying power to the IC chip. As the power supply path, a first power supply path that connects to the IC chip through a through-hole conductor that penetrates the core substrate in the thickness direction, a second power supply path that connects to the IC chip through a via conductor of the capacitor, and the like There is.

The conventional IC chip mounting wiring board is manufactured, for example, by the following procedure. First, a core substrate made of a polymer material having an accommodation hole opening on both the core main surface and the core back surface is prepared. In addition, an embedding capacitor is prepared in which a plurality of electrodes project from the capacitor main surface and the capacitor back surface. Next, the opening on the back side of the core substrate in the accommodation hole is sealed with an adhesive tape or the like, and in this state, the embedding capacitor is accommodated in the accommodation hole, and the capacitor is temporarily fixed. Then, after a gap between the inner surface of the accommodation hole and the side surface of the capacitor is filled with a resin hole filling material, a fixing process is performed to cure the capacitor, and the capacitor is fixed to the core substrate. Thereafter, a resin insulating layer mainly composed of a polymer material and a conductor layer are formed on the front and back surfaces of the composite base material composed of the core substrate and the capacitor. As a result, a desired wiring board is obtained. A wiring board is also proposed in which a plurality of the above capacitors are arranged in the horizontal direction in the housing hole, and the electrodes of some capacitors and the conductor pattern on the core main surface are connected by a connecting conductor. There is a problem that it can only be connected to the electrode of the capacitor on the outer periphery.
Japanese Patent Laying-Open No. 2005-39243 (see FIG. 4 etc.)

  By the way, in order to manufacture a wiring board having the above-described connecting conductor, a process of forming a connecting conductor is required after the capacitor is fixed to the core board and before the resin insulating layer and the conductor layer are formed. Become. However, for forming the connection conductor, a step of forming a plating layer, a step of forming an etching resist on the plating layer, a step of etching the plating layer to form a connection conductor, a step of removing the etching resist, and the like are essential. . This complicates the process and increases the manufacturing cost of the wiring board. In recent years, it has been required to reduce the number of processes in order to reduce costs, and thus it is essential to solve the above problems.

  This invention is made | formed in view of said subject, The objective is to provide the manufacturing method of the wiring board which can simplify a process.

  And as a means (means 1) for solving the above-mentioned problem, a housing hole portion having a core main surface and a core back surface and opening at least on the core main surface side is formed, and the core is formed on the core main surface. A preparation step of preparing a core substrate on which a substrate main surface side conductor is disposed, preparing an electronic component having a component main surface and a component back surface, and having a component main surface side electrode disposed on the component main surface; A fixing step of filling the gap between the electronic component housed in the housing hole and the core substrate with a resin hole filling material and fixing the electronic component to the core substrate; and after the fixing step, An insulating layer forming step of forming a lowermost resin insulating layer forming a lowermost layer of a wiring laminated portion on the surface, the component main surface, and the resin hole filling material; and a position immediately above the gap in the lowermost resin insulating layer. Remove at least part of the core substrate main surface side conductor And an opening forming step for forming an opening exposing a part of the component main surface side electrode, a main surface side connecting conductor is formed in the opening, and the core substrate main surface side conductor and the component main surface side There is a method for manufacturing a wiring board including a main surface side connection conductor forming step for connecting electrodes.

  Therefore, according to the method of manufacturing the wiring board of means 1, the main surface side connecting conductor is formed in the lowermost resin insulating layer in order to form the main surface side connecting conductor in the opening formed in the lowermost resin insulating layer. Can be performed simultaneously with the formation of the conductor. Thereby, since the process is simplified, the wiring board can be easily manufactured, and the manufacturing cost of the wiring board can be reduced. In addition, since the resin filling material is separate from the bottom resin insulation layer, the function of the resin filling material can be specialized for the function of fixing electronic components, and the resin filling material has a stronger fixing force. be able to.

  Further, as another means (means 2) for solving the problems of the present invention, a housing hole portion having a core main surface and a core back surface and opening at least on the core main surface side is formed, and the core Prepare a core substrate in which a core substrate main surface side conductor is disposed on the main surface, and prepare an electronic component having a component main surface and a component back surface, and having the component main surface side electrode disposed on the component main surface And after the electronic component is accommodated in the accommodation hole portion, a lowermost resin insulation layer that forms a lowermost layer of the wiring laminated portion is formed on the core main surface and the component main surface. An insulating layer forming and fixing step of fixing the electronic component to the core substrate by filling a gap between the electronic component and the core substrate with a part of the lowermost resin insulating layer, and the gap in the lowermost resin insulating layer. Removing at least part of the position directly above the core An opening forming step for forming a plate main surface side conductor and an opening for exposing a part of the component main surface side electrode; and a main surface side connecting conductor is formed in the opening, and the core substrate main surface side conductor and There is a method of manufacturing a wiring board including a main surface side connecting conductor forming step for connecting the component main surface side electrodes.

  Therefore, according to the method of manufacturing the wiring board of means 2, the main surface side connecting conductor is formed in the lowermost resin insulating layer in order to form the main surface side connecting conductor in the opening formed in the lowermost resin insulating layer. Can be performed simultaneously with the formation of the conductor. Thereby, since the process is simplified, the wiring board can be easily manufactured, and the manufacturing cost of the wiring board can be reduced.

  In addition, since the electronic component is fixed simultaneously with the formation of the lowermost resin insulating layer, the process can be further simplified. Further, since the material filling the gap is a part of the lowermost resin insulating layer, it is not necessary to prepare a material different from the lowermost resin insulating layer when fixing the electronic component to the core substrate. Therefore, since the material necessary for manufacturing the wiring board is reduced, the cost of the wiring board can be reduced.

  The core substrate constituting the wiring board forms part of the core portion of the wiring board, and is formed in a plate shape having a core main surface and a core back surface located on the opposite side, for example. Such a core substrate has an accommodation hole for accommodating an electronic component. The accommodation hole may be a non-through hole that opens only on the core main surface side, or may be a through hole that opens on both the core main surface side and the core back surface side. The “core portion” is a portion composed of a core substrate and a lowermost resin insulating layer that forms the lowermost layer of the wiring laminated portion. Moreover, the electronic component may be accommodated in the accommodation hole in a completely embedded state, or may be accommodated in the accommodation hole in a state in which a part projects from the opening of the accommodation hole.

  A material for forming the core substrate is not particularly limited, but a preferable core substrate is mainly formed of a polymer material. Specific examples of the polymer material for forming the core substrate include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  The core substrate main surface side conductor is a plain-shaped conductor or a net-shaped conductor formed so as to surround the opening edge of the accommodation hole, and penetrates between the core main surface and the core back surface. It is preferable to be connected to a plurality of through-hole conductors formed. In this way, the cross-sectional area of the core substrate main surface side conductor is increased, and the resistance is reduced. Accordingly, it is easy to supply a large current using an electrical path that connects to the component main surface side electrode through the through-hole conductor, the core substrate main surface side conductor, and the main surface side connection conductor.

  The electronic component that constitutes the wiring board has a component main surface and a component back surface. The electronic component is used in a state of being accommodated in the accommodation hole. The electronic component has a plurality of via conductors penetrating between the component main surface and the component back surface, and is connected to the plurality of via conductors and is laminated by way of a dielectric layer. And a capacitor in which the component main surface side electrode is connected to end portions of the plurality of via conductors on the component main surface. Further, as another electronic component, it has a ceramic sintered body having a component main surface and a component back surface, has a plurality of via conductors penetrating the component main surface and the component back surface, and the component main surface side electrode is Examples include a ceramic chip that is connected to end portions of the plurality of via conductors on the component main surface but does not have a function of a capacitor because the plurality of internal electrode layers are not included. If a capacitor is used as the electronic component, the entire electronic component can be easily downsized, and the entire wiring board can be easily downsized. In addition, if the electronic component is the above-described capacitor, a high electrostatic capacity can be easily achieved although it is small, and more stable power supply can be achieved.

  In addition, the area of the component main surface (and component back surface) of the electronic component is preferably smaller than the area of the opening portion of the accommodation hole, and in particular, slightly smaller than the area of the opening portion of the accommodation hole. preferable. In this way, since the gap between the electronic component housed in the housing hole and the core substrate is reduced, the area having no electrical function in the wiring board can be reduced, and the wiring can be reduced. The size of the substrate can be reduced. Furthermore, the shape of the electronic component in plan view is preferably approximated to the shape of the accommodation hole portion in plan view. For example, when the accommodation hole portion has a rectangular shape in plan view, the electronic component is also rectangular in plan view. It is preferable to make a shape. In this way, the gap is further reduced, so that the area having no electrical function in the wiring board can be further reduced.

  As the dielectric layer, a sintered body of a high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, or the like is preferably used, and alumina for borosilicate glass or lead borosilicate glass is used. A sintered body of a low-temperature fired ceramic such as a glass ceramic to which an inorganic ceramic filler is added is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a capacitor having a large capacitance can be easily realized.

  The material for forming the internal electrode layer and the via conductor is not particularly limited, but it is preferable to use a metal that can be sintered simultaneously with the ceramic, for example, nickel, molybdenum, tungsten, titanium, or the like. When a low-temperature fired ceramic sintered body is selected, copper, silver, or the like can be used as a material for forming the internal electrode layer and the via conductor.

  The wiring laminated portion has a structure in which, for example, an interlayer insulating layer mainly composed of a polymer material and a conductor layer are connected alternately. When a semiconductor integrated circuit element is mounted on the surface of the wiring laminated portion, there is a large difference in the inter-terminal pitch between the terminal group on the semiconductor integrated circuit element side and the terminal group on the electronic component side, but the wiring laminated portion is provided. Thus, both can be easily connected. In addition, the wiring laminated portion is formed only on the core main surface and the component main surface. For example, an interlayer insulating layer and a conductor layer are alternately laminated on the core back surface and the component back surface. A wiring laminated portion having a structure may be further formed. If comprised in this way, since an electric circuit can be formed in both the wiring lamination | stacking parts, the further functional enhancement of a wiring board can be achieved.

  In addition, the said component main surface side electrode can be arrange | positioned in the suitable location on a component main surface. However, it is preferable that the component main surface side electrode is disposed on the outer peripheral portion on the electronic component. In this way, the distance between the component main surface side electrode and the main surface side connection conductor is shortened, so that the connection between the core substrate main surface side conductor and the component main surface side electrode by the main surface side connection conductor is facilitated. .

  When the electronic component has a substantially rectangular shape in plan view, the main surface side connection conductor may be a belt-like pattern arranged on at least one side of the electronic component, or the electronic component A plurality of belt-like patterns arranged on each side may be used. Furthermore, the main surface side connection conductor may be a rectangular frame pattern arranged so as to cover the entire gap between the electronic component and the core substrate. When the main surface side connection conductor is a belt-like pattern and at least one belt-like pattern is arranged on each side, the number of main surface side connection conductors increases and the number of electrical paths connected to the component main surface side electrodes increases. Therefore, the resistance can be reduced. In addition, variations in potential are less likely to occur on each side of the electronic component. On the other hand, when the main surface side connection conductor is a belt-like pattern and a plurality of belt-like patterns are arranged on each side, the number of the main surface side connection conductors further increases and the number of the electrical paths further increases. You can plan. Further, when the main surface side connection conductor is a rectangular frame-shaped pattern, the number of the electrical paths does not increase, but the cross-sectional area of the main surface side connection conductor is larger than that of the band-shaped pattern. Low resistance can be achieved.

  Hereinafter, a method for manufacturing a wiring board will be described.

  In the preparation step, an electronic component and a core substrate having an accommodation hole for accommodating and fixing the electronic component are prepared by a conventionally known technique and prepared in advance. For example, the electronic component is manufactured as follows. That is, the paste is printed on the component main surface of the electronic component main body to form the component main surface side electrode. Furthermore, if baking is performed for a predetermined time at a predetermined temperature, the electronic component main body and the paste are simultaneously sintered to complete the electronic component. The core substrate is produced as follows, for example. First, the sub-base material is formed on the upper surface and the lower surface of the base material, and the core substrate main surface side conductor is patterned on the upper surface of the upper sub-base material. Next, the laminated body composed of the base material and the sub-base material is drilled using a router to form through holes serving as accommodation holes at predetermined positions to obtain a core substrate.

  After the preparatory process, the manufacturing method of means 1 performs the following processes. That is, a fixing process is performed, and a masking material such as an adhesive tape is pasted on the back side of the core substrate to seal the back side opening of the accommodation hole in advance, and then the electronic component is accommodated in the accommodation hole. In this state, a resin hole filling material made of a polymer material is filled in the gap between the inner surface of the housing hole and the side surface of the electronic component. A thermosetting resin is suitable as the resin hole filling material, and when this is used, heat treatment is performed after filling. As a result, the electronic component is fixed in the accommodation hole by the cured resin hole filling material. After the fixing step, an insulating layer forming step is performed, and the lowermost resin insulation is performed on the main surface (core main surface, component main surface, and main surface side wiring forming portion of the resin hole filling material) of the composite base material. Form a layer.

  Here, as a method of filling the gap with the resin hole filling material, the gap is filled with the resin hole filling material using a dispenser device, or the gap is filled with the resin hole filling material by paste printing. Is mentioned. In performing the insulating layer forming step, the main surface of the composite base material may be polished to flatten the main surface of the composite base material.

  On the other hand, in the manufacturing method of means 2, the following steps are performed after the preparation step. That is, after the insulating layer forming and fixing steps are performed and the electronic component is accommodated in the accommodating hole by the same method as the above means 1, the main surface (the core main surface and the component main surface) of the composite base material is formed. A bottom resin insulation layer is formed on the substrate. At the same time, the gap between the inner surface of the accommodation hole and the side surface of the electronic component is filled with a part of the lowermost resin insulating layer. As a result, the electronic component is fixed in the accommodation hole by a part of the lowermost resin insulating layer.

  After the insulating layer forming step or the insulating layer forming and fixing step, the opening forming step is performed. Specifically, in the lowermost resin insulating layer, at least a part of the position directly above the gap is removed, and an opening is formed to expose the core substrate main surface side conductor and a part main surface side electrode. . Examples of the method for forming the opening include drilling using a drilling machine, router processing, laser processing, photolithography for performing exposure and development, etc. If laser processing is used, the opening forming process is performed. The core substrate main surface side conductor and the component main surface side electrode exposed in the step are less likely to be damaged. In the opening forming step, it is preferable that the opening is formed by laser processing on the lowermost resin insulating layer, and a via hole that exposes the component main surface side electrode is formed. In this way, it is not necessary to form the opening and the via hole separately, so that the process can be further simplified and the manufacturing cost of the wiring board can be reduced.

  Furthermore, a main surface side connection conductor forming step is performed, a main surface side connection conductor is formed in the opening, and the core substrate main surface side conductor and the component main surface side electrode are connected.

  Here, examples of the main surface side connection conductor include a plating layer, a metal paste layer, a metal foil adhesion layer, a sputtering layer, a vapor deposition layer, and an ion plating layer. Among these, a plating layer (for example, a copper layer) Plating layer) is preferred. This is because the plating layer can form a relatively thick layer in a short time and is advantageous in reducing the cost of the wiring board. In addition, when the main surface side connection conductor is a plating layer, in the main surface side connection conductor forming step, the main surface side connection conductor is formed by electroless plating.

  Further, in the main surface side connecting conductor forming step, an etching resist is formed after electroless plating is performed on the lowermost resin insulating layer and the inner surface of the opening, and then electrolytic plating is performed, and then the etching resist is removed. Then, by performing soft etching, it is preferable to form the main surface side connection conductor in the opening and pattern the conductor layer constituting the wiring laminated portion on the lowermost resin insulating layer. By doing so, the main surface side connection conductor is composed of the electroless plating layer and the electrolytic plating layer and becomes thick, so that the resistance of the main surface side connection conductor is reduced and the voltage drop during power supply is reduced. . Thereby, a large current can be passed through the main surface side connection conductor. Further, since the formation of the main surface side connection conductor and the pattern formation of the conductor layer are simultaneously performed, the process can be further simplified, and the manufacturing cost of the wiring board can be reduced.

  Note that if the contact area between the main surface side connection conductor and the core substrate main surface side conductor is increased, the connection reliability between the main surface side connection conductor and the core substrate main surface side conductor is increased. As a method for increasing the contact area between the two, for example, the main surface side connecting conductor may be joined on two surfaces of the core substrate main surface side conductor, that is, a side surface and an upper surface. Similarly, if the contact area between the main surface side connection conductor and the component main surface side electrode is increased, the connection reliability between the main surface side connection conductor and the component main surface side electrode is increased. As a method for increasing the contact area between the two, for example, the main surface side connection conductor may be joined on two sides of the component main surface side electrode, that is, a side surface and an upper surface.

  By the way, in the main surface side connection conductor forming step, when the main surface side connection conductor is joined to the core substrate main surface side conductor and the component main surface side electrode on a plurality of surfaces, the upper surface of the main surface side connection conductor is obtained. There is a possibility that a concave portion is formed. In this case, after the main surface side connection conductor forming step, it is preferable to perform a filling step of filling a concave portion formed in the location of the main surface side connection conductor and flatten the upper surface. In this way, it is possible to form a conductor layer on the upper surface of the main surface side connecting conductor that has been flattened with the recesses removed, and the degree of freedom of wiring in the wiring laminated portion is improved. Furthermore, the hollow portions of the plurality of through-hole conductors formed so as to penetrate the core substrate and the lowermost resin insulating layer are filled with an insulating resin material, and at the same time, the main surface side connection conductors can be formed. It is preferable to perform a hole filling step for filling the concave portion. In this way, it is not necessary to separately fill the hollow portion and the concave portion, so that the process can be further simplified and the manufacturing cost of the wiring board can be reduced.

[First Embodiment]

  Hereinafter, a first embodiment in which a wiring board of the present invention is embodied will be described in detail with reference to the drawings.

  As shown in FIG. 1, the wiring board 10 of this embodiment is a wiring board for mounting an IC chip, and includes a substantially rectangular plate-like core board 11 and a core main surface 12 of the core board 11 (in FIG. 1). The first wiring laminated portion formed on the upper surface) and the second wiring laminated portion formed on the core back surface 13 (lower surface in FIG. 1) of the core substrate 11. The first wiring laminated portion is constituted by an epoxy resin lowermost resin insulating layer 33 that forms the lowermost layer of the first wiring laminated portion, and a first buildup layer 31 formed on the lowermost resin insulating layer 33. Has been. On the other hand, the second wiring laminated portion is composed of an uppermost resin insulating layer 34 made of epoxy resin that forms the uppermost layer of the second wiring laminated portion, and a second buildup layer 32 formed on the uppermost resin insulating layer 34. Has been.

  Via conductors 47 are formed at a plurality of locations in the lowermost resin insulation layer 33 constituting the first wiring laminated portion. The first buildup layer 31 constituting the first wiring laminated portion has a structure in which resin insulating layers 35 (so-called interlayer insulating layers) made of epoxy resin and conductor layers 42 made of copper are alternately laminated. ing. The conductor layer 42 is electrically connected to the via conductor 47 and the like. In addition, via conductors 43 are formed at a plurality of locations in the resin insulation layer 35, and terminal pads 44 are formed in an array on the surface of the resin insulation layer 35 at the upper end of each via conductor 43. ing. Further, the surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 (semiconductor integrated circuit element). The IC chip 21 has a rectangular flat plate shape and is made of silicon. Each terminal pad 44 and each solder bump 45 are located in a region immediately above the ceramic capacitor 101 in the first buildup layer 31, and this region becomes the IC chip mounting region 23. The IC chip mounting area 23 is set on the surface 39 of the first buildup layer 31. That is, the IC chip 21 can be mounted on the surface 39.

  As shown in FIG. 1, the second wiring laminated portion has substantially the same structure as the first wiring laminated portion described above. That is, via conductors 47 are formed at a plurality of locations in the uppermost resin insulation layer 34 constituting the second wiring laminated portion. Further, the second buildup layer 32 constituting the second wiring laminated portion has a structure in which a resin insulating layer 36 (so-called interlayer insulating layer) made of an epoxy resin and a conductor layer 42 are alternately laminated. . The conductor layer 42 is electrically connected to the via conductor 47 and the like. In addition, via conductors 43 are formed at a plurality of locations in the resin insulation layer 36, and the conductor layer 42 is disposed on the lower surface of the resin insulation layer 36 at the lower end of each via conductor 43 via the via conductors 43. BGA pads 48 that are electrically connected to each other are formed in a grid pattern. Further, the lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 are provided for electrical connection with a mother board (not shown). The wiring board 10 is mounted on a mother board (not shown) by each solder bump 49. That is, a mother board can be connected to the surface of the second buildup layer 32.

  As shown in FIG. 1, the core substrate 11 includes a base material 201 made of glass epoxy and a sub-base material made of an epoxy resin formed on the upper and lower surfaces of the base material 201 and added with an inorganic filler such as silica filler. 204 and the conductor layer 203 made of copper, which is also formed on the upper and lower surfaces of the base material 201. In the core substrate 11, a plurality of through-hole conductors 16 are formed so as to penetrate the core main surface 12, the core back surface 13, and the conductor layer 203. The through-hole conductor 16 connects and conducts the core main surface 12 side and the core back surface 13 side of the core substrate 11, and is electrically connected to the conductor layer 203. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. The upper end of the through-hole conductor 16 is electrically connected to a part of the conductor layer 42 on the surface of the lowermost resin insulation layer 33, and the lower end of the through-hole conductor 16 is on the lower surface of the uppermost resin insulation layer 34. Is electrically connected to a part of the conductor layer 42. In addition, the core substrate 11 has one accommodation hole 90 that is rectangular in a plan view that opens at the center of the core main surface 12 and the center of the core back surface 13. That is, the accommodation hole 90 is a through hole.

  As shown in FIGS. 1 to 3, a core substrate main surface side power source pattern 51 (core substrate main surface side conductor) made of copper is disposed on the core main surface 12 of the core substrate 11. 11, a core substrate back surface side ground pattern 52 (core substrate back surface side conductor) which is also made of copper is disposed. The core substrate main surface side power supply pattern 51 and the core substrate back surface side ground pattern 52 are electrically connected to the through-hole conductor 16. The core substrate main surface side power supply pattern 51 and the core substrate back surface side ground pattern 52 are formed to be thicker than the conductor layer 42. In the present embodiment, the thickness of the conductor layer 42 is set to 25 μm, and the thicknesses of the core substrate main surface side power supply pattern 51 and the core substrate back surface side ground pattern 52 are set to 35 μm. The core substrate main surface side power supply pattern 51 and the core substrate back surface side ground pattern 52 are plain conductors formed in a rectangular frame shape so as to surround the opening edge of the accommodation hole 90 (see FIG. 2). The outer peripheral edges of the core substrate main surface side power supply pattern 51 and the core substrate rear surface side ground pattern 52 are located inside the outer peripheral edges of the core main surface 12 and the core back surface 13 of the core substrate 11, and The inner peripheral edges of the surface-side power supply pattern 51 and the core substrate rear surface side ground pattern 52 are located on the outer peripheral side of the core substrate 11 with respect to the opening edge of the accommodation hole 90.

  The ceramic capacitor 101 shown in FIGS. 4 to 6 and the like is housed in the housing hole 90 in an embedded state. The ceramic capacitor 101 of the present embodiment has a substantially rectangular plate shape in plan view of 6.0 mm length × 12.0 mm width × 0.8 mm thickness. In addition, it is preferable that the thickness of the ceramic capacitor 101 is 0.2 mm or more and 1.0 mm or less. If the thickness is less than 0.2 mm, the stress at the time of bonding the IC chip 21 onto the IC chip mounting region 23 cannot be reduced by the ceramic capacitor 101, which is insufficient as a support. On the other hand, if it is larger than 1.0 mm, the wiring board 10 becomes thick. More preferably, the thickness of the ceramic capacitor 101 is 0.4 mm or more and 0.8 mm or less. The ceramic capacitor 101 is arranged in a region immediately below the IC chip mounting region 23 in the core substrate 11. The area of the IC chip mounting region 23 (the area of the surface on which the surface connection terminals 22 are formed in the IC chip 21) is set to be smaller than the area of the capacitor main surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the capacitor main surface 102 of the ceramic capacitor 101. Note that the size relationship of the areas is not limited, and the area of the IC chip mounting region 23 may be larger than the area of the capacitor main surface 102.

  As shown in FIGS. 1, 4 to 6, etc., the ceramic capacitor 101 (electronic component) of the present embodiment is a so-called via array type ceramic capacitor. A ceramic sintered body 104 constituting the ceramic capacitor 101 is a plate-like object having a capacitor main surface 102 (upper surface in FIG. 1) as a component main surface and a capacitor back surface 103 (lower surface in FIG. 1) as a component back surface. is there. The lowermost resin insulation layer 33 is formed on the capacitor main surface 102 of the ceramic sintered body 104, and the uppermost resin insulation layer 34 is formed on the capacitor back surface 103 of the ceramic sintered body 104. The ceramic sintered body 104 has a structure in which the first internal electrode layers 141 and the second internal electrode layers 142 are alternately stacked via the ceramic dielectric layer 105. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the first internal electrode layer 141 and the second internal electrode layer 142. Each of the first internal electrode layer 141 and the second internal electrode layer 142 is a layer formed mainly of nickel, and is disposed every other layer inside the ceramic sintered body 104.

  A large number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface of the ceramic sintered body 104. In each via hole 130, a plurality of via conductors 131 and 132 that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. The upper end surfaces of the via conductors 131 and 132 are located on the capacitor main surface 102, and the lower end surfaces of the via conductors 131 and 132 are located on the capacitor back surface 103. Each power supply via conductor 131 passes through each first internal electrode layer 141 and electrically connects them to each other. Each ground via conductor 132 passes through each second internal electrode layer 142 and electrically connects them to each other. Each power supply via conductor 131 and each ground via conductor 132 are arranged in an array as a whole. For convenience of explanation, the via conductors 131 and 132 are illustrated in 5 columns × 5 columns, but there are actually more columns.

  As shown in FIGS. 2, 4 to 6, and the like, on the capacitor main surface 102 of the ceramic sintered body 104, an upper surface side power supply electrode 111 (component main surface side electrode) and a plurality of upper surface side grounds are provided. A working electrode 112 (component main surface side electrode) is projected. A plurality of backside power supply electrodes 121 (component backside electrodes) and backside ground electrodes 122 (component backside electrodes) protrude from the capacitor back surface 103 of the ceramic sintered body 104. . Here, the upper surface side power supply electrode 111 is a plain conductor that covers substantially the entire capacitor main surface 102, and has a plurality of holes for avoiding the upper surface side ground electrodes 112. Similarly, the back surface side power supply electrode 121 is a plain conductor that covers substantially the entire capacitor back surface 103, and has a plurality of holes for avoiding each back surface side ground electrode 122. Note that the outer peripheral edges of the upper surface side power supply electrode 111 and the rear surface side power supply electrode 121 are located inside the outer peripheral edges of the capacitor main surface 102 and the capacitor back surface 103 of the ceramic capacitor 101 (see FIG. 2). The upper surface side ground electrodes 112 are band-shaped patterns arranged in parallel with each other on the capacitor main surface 102, and the rear surface side ground electrodes 122 are band-shaped patterns arranged in parallel with each other on the capacitor back surface 103. . The electrodes 111 and 112 on the capacitor main surface 102 side include the via conductor 47, the first buildup layer 31 (conductor layer 42, via conductor 43), the terminal pad 44, the solder bump 45, and the surface connection terminal 22 of the IC chip 21. And is electrically connected to the IC chip 21. On the other hand, the electrodes 121 and 122 on the capacitor back surface 103 side pass through via conductors 47, conductor layers 42, via conductors 43, BGA pads 48, and solder bumps 49 with respect to electrodes (contactors) of a mother board (not shown). Are electrically connected. The upper surface side power supply electrode 111 is directly connected to the end surface of the plurality of power supply via conductors 131 on the capacitor main surface 102 side, and the upper surface side ground electrode 112 is connected to the plurality of ground via conductors 132. It is directly connected to the end surface on the capacitor main surface 102 side. On the other hand, the back side power supply electrode 121 is directly connected to the end face of the plurality of power supply via conductors 131 on the capacitor back side 103 side, and the back side ground electrode 122 is a capacitor in the plurality of ground via conductors 132. It is directly connected to the end surface on the back surface 103 side. Therefore, the power supply electrodes 111 and 121 are electrically connected to the power supply via conductor 131 and the first internal electrode layer 141, and the ground electrodes 112 and 122 are electrically connected to the ground via conductor 132 and the second internal electrode layer 142. Yes.

  As shown in FIG. 4 and the like, the electrodes 111 and 112 are made of nickel as a main material, and the surface is entirely covered with a copper plating layer (not shown). Similarly, the electrodes 121 and 122 are also made of nickel as a main material, and the surfaces thereof are covered with a copper plating layer (not shown). The electrodes 121 and 122 and the via conductors 131 and 132 are disposed immediately below the central portion of the IC chip 21. The upper surface side power supply electrode 111 and the upper surface side ground electrode 112 are formed from a position just below the central portion of the IC chip 21 to the outer peripheral direction of the ceramic capacitor 101. The upper surface side power supply electrode 111 and the rear surface side ground electrode 122 are also arranged on the outer periphery of the capacitor.

  For example, when energization is performed from the motherboard side via the electrodes 121 and 122 and a voltage is applied between the first internal electrode layer 141 and the second internal electrode layer 142, for example, positive charges are accumulated in the first internal electrode layer 141. For example, negative charges accumulate in the second internal electrode layer 142. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the power supply via conductors 131 and the ground via conductors 132 are alternately arranged adjacent to each other, and the directions of the currents flowing through the power supply via conductors 131 and the ground via conductors 132 are opposite to each other. It is set to be. Thereby, the inductance component is reduced.

  As shown in FIGS. 1 to 3, etc., the gap between the inner surface of the accommodation hole 90 and the side surface of the ceramic capacitor 101 is filled with a resin filling portion 33 a constituting a part of the lowermost resin insulating layer 33. ing. The resin filling portion 33a has a function of fixing the ceramic capacitor 101 to the core substrate 11 and absorbing the deformation of the ceramic capacitor 101 and the core substrate 11 in the surface direction and the thickness direction by its own elastic deformation. . The ceramic capacitor 101 has a substantially square shape in plan view, and has a taper of C0.6 at the four corners. Thereby, when the resin filling portion 33a is deformed due to a temperature change, stress concentration on the corner portion of the ceramic capacitor 101 can be relieved, so that occurrence of cracks in the resin filling portion 33a can be prevented.

  The resin filling portion 33 a has a main surface side wiring formation portion 93 located on the core main surface 12 of the core substrate 11 and the capacitor main surface 102 side of the ceramic capacitor 101. Further, the resin filling portion 33 a has a back surface side wiring forming portion 94 located on the core back surface 13 of the core substrate 11 and the capacitor back surface 103 side of the ceramic capacitor 101. An upper surface side connection pattern 61 (main surface side connection conductor) is arranged on the main surface side wiring formation portion 93. The upper surface side connection pattern 61 is a belt-like pattern arranged on each side of the ceramic capacitor 101 (see FIG. 2), and the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111 are connected to each other. It comes to connect. More specifically, one end of the upper surface side connection pattern 61 is bonded to the side surface 53 (inner peripheral surface) and the upper surface 54 of the core substrate main surface side power supply pattern 51, and the other end of the upper surface side connection pattern 61 is used for the upper surface side power supply. The electrodes 111 are joined at the side surface (outer peripheral surface) and the upper surface (see FIG. 3). In addition, the upper surface side connection pattern 61 of this embodiment consists of a copper plating layer, and the upper surface is flat.

  As shown in FIGS. 1 and 3, a back side connection pattern 62 (back side connection conductor) is arranged on the back side wiring formation portion 94. The back surface side connection pattern 62 has substantially the same configuration as the top surface side connection pattern 61. That is, the back surface side connection pattern 62 is a belt-like pattern arranged on each of the four sides of the ceramic capacitor 101 so as to connect the core substrate back surface side ground pattern 52 and the back surface side ground electrode 122. It has become. More specifically, the back surface side connection pattern 62 is bonded at the side surface (inner peripheral surface) and the lower surface of the core substrate back surface side ground pattern 52 and at the side surface (outer peripheral surface) and the lower surface of the back surface side ground electrode 122. is doing. In addition, the back surface side connection pattern 62 of this embodiment consists of a copper plating layer, and the lower surface is flat.

  With the above configuration, a plurality of electrical paths (a first power path and a second power path) for supplying power to the IC chip 21 are formed in the wiring board 10. The first power supply path is a path that connects to the upper surface side power supply electrode 111 through the through-hole conductor 16, the core substrate main surface side power supply pattern 51, and the upper surface side connection pattern 61. The second power supply path is a path connected to the upper surface side power supply electrode 111 through the via conductor 131. The upper surface side power supply electrode 111 is connected via the via conductor 47, the first buildup layer 31 (conductor layer 42, via conductor 43), the terminal pad 44, the solder bump 45, and the surface connection terminal 22 of the IC chip 21. It is electrically connected to the IC chip 21.

  Next, a method for manufacturing the wiring board 10 of this embodiment will be described.

  In the preparation step, the core substrate 11 and the ceramic capacitor 101 are respectively prepared by a conventionally known technique and prepared in advance.

  The core substrate 11 is manufactured as follows. First, a copper clad laminate (see FIG. 7) in which a copper foil 202 having a thickness of 35 μm is attached to both surfaces of a base material 201 having a length of 400 mm, a width of 400 mm, and a thickness of 0.8 mm is prepared. In addition, it is preferable that the thickness of the base material 201 is 0.2 mm or more and 1.0 mm or less. Next, the copper foil 202 on both sides of the copper-clad laminate is etched to pattern the conductor layer 203 by, for example, a subtractive method (see FIG. 8). Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil 202 are removed by etching. Thereafter, the dry film is peeled off. Next, after roughening the upper and lower surfaces of the base material 201 and the conductor layer 203, an epoxy resin film (thickness 600 μm) to which an inorganic filler is added is pasted on the upper and lower surfaces of the base material 201 by thermocompression bonding. Then, the sub-base material 204 is formed (see FIG. 9).

  Next, the core substrate main surface side power supply pattern 51 is formed on the upper surface of the upper sub base material 204, and the core substrate back surface side ground pattern 52 is formed on the lower surface of the lower sub base material 204 (FIG. 10). reference). Specifically, after performing electroless copper plating on the upper surface of the upper sub-substrate 204 and the lower surface of the lower sub-substrate 204, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Next, the laminated body composed of the base material 201 and the sub-base material 204 is drilled using a router to form through holes to be the accommodation hole portions 90 at predetermined positions, thereby obtaining the core substrate 11 (FIG. 11). In addition, the through-hole used as the accommodation hole part 90 is a hole of 14.0 mm in length x 30.0 mm in width | variety, and a cross-sectional substantially square shape which has a radius of 1.5 mm in four corners.

  The ceramic capacitor 101 is manufactured as follows. That is, a ceramic green sheet is formed, and nickel paste for internal electrode layers is screen printed on the green sheet and dried. As a result, a first internal electrode portion that later becomes the first internal electrode layer 141 and a second internal electrode portion that becomes the second internal electrode layer 142 are formed. Next, the green sheets on which the first internal electrode portions are formed and the green sheets on which the second internal electrode portions are formed are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, paste is printed on the upper surface of the green sheet laminate, and the upper surface side power supply electrode 111 and the upper surface side ground electrode 112 are formed so as to cover the upper end surface of each conductor portion on the upper surface side of the green sheet laminate. To do. Further, a paste is printed on the lower surface of the green sheet laminate, and the back-side power supply electrode 121 and the back-side ground electrode 122 are formed so as to cover the lower end surface of each conductor portion on the lower surface side of the green sheet laminate. .

  Thereafter, the green sheet laminate is dried to solidify the electrodes 111, 112, 121, and 122 to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, electroless copper plating (thickness of about 10 μm) is performed on each electrode 111, 112, 121, 122 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each of the electrodes 111, 112, 121, 122, and the ceramic capacitor 101 is completed.

  In the subsequent insulating layer formation and fixing step, the ceramic capacitor 101 is accommodated in the accommodation hole 90 using a mounting device (manufactured by Yamaha Motor Co., Ltd.) (see FIG. 12). At this time, the opening on the core back surface 13 side of the accommodation hole 90 is sealed with a peelable adhesive tape 210. The adhesive tape 210 is supported by a support base (not shown). The ceramic capacitor 101 is affixed and temporarily fixed to the adhesive surface of the adhesive tape 210.

  Thereafter, a photosensitive epoxy resin is deposited on the core main surface 12 and the capacitor main surface 102, and the lowest resin insulation layer 33 is formed by performing exposure and development. In addition, the gap between the inner surface of the accommodation hole 90 and the side surface of the ceramic capacitor 101 is filled with the resin filling portion 33a which is a part of the lowermost resin insulating layer 33 (see FIG. 13). Thereafter, when heat treatment is performed, the lowermost resin insulating layer 33 and the resin filling portion 33 a are cured, and the ceramic capacitor 101 is fixed to the core substrate 11. At this point, the adhesive tape 210 is peeled off.

  Next, a photosensitive epoxy resin is applied to the core back surface 13 and the capacitor back surface 103, and exposure and development are performed to form the uppermost resin insulating layer 34 (see FIG. 14). In the subsequent opening forming step, laser drilling is performed on the lowermost resin insulating layer 33 using a YAG laser or a carbon dioxide gas laser, and a main surface side opening 221 is formed at a position where the upper surface side connection pattern 61 is to be formed. (See FIG. 15). Further, laser drilling is performed on the uppermost resin insulation layer 34 to form a back surface side opening 222 at a position where the back surface side connection pattern 62 is to be formed. Specifically, the main surface side opening pattern 221 is formed by entirely removing the position immediately above the gap in the lowermost resin insulating layer 33, and the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode. A part of 111 is exposed. When the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111 are different in height, the bottom surface of the main surface side opening 221 is made lower than the lower upper surface to expose both. Similarly, the position immediately below the gap in the uppermost resin insulation layer 34 is entirely removed to form a back surface side opening 222, and the core substrate back surface side ground pattern 52 and a part of the back surface side ground electrode 122 are formed. Expose. When the heights of the core substrate back surface side ground pattern 52 and the back surface side ground electrode 122 are different, the bottom surface of the back surface side opening 222 is made higher than the higher lower surface to expose both. In addition, via holes 223 for exposing the upper surface side power supply electrode 111 and the upper surface side ground electrode 112 are formed at positions where the via conductors 47 are to be formed in the lowermost resin insulating layer 33. Also, via holes 224 that expose the back-side power supply electrode 121 and the back-side ground electrode 122 are formed at positions where the via conductors 47 are to be formed in the uppermost resin insulation layer 34.

  Further, drilling is performed using a drill machine, and a through hole 231 that penetrates the core substrate 11 and the resin insulating layers 33 and 34 is formed in advance at a predetermined position (see FIG. 16). And a main surface side connection conductor formation process and a back surface side connection conductor formation process are implemented (refer FIG. 17). Specifically, after performing electroless copper plating on the lowermost resin insulating layer 33, the uppermost resin insulating layer 34, the inner surfaces of the openings 221, 222, and the inner surfaces of the through holes 231, an etching resist is formed, and then electrolysis is performed. Perform copper plating. Further, the etching resist is removed and soft etching is performed. As a result, the upper surface side connection pattern 61 is formed in the main surface side opening 221, and the back surface side connection pattern 62 is formed in the back surface side opening 222, and the uppermost resin insulating layer 33 and the uppermost resin insulating layer are formed. A conductor layer 42 is patterned on 34. At the same time, the through-hole conductor 16 is formed in the through hole 231, and the via conductor 47 is formed inside each via hole 223, 224. As a result, the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111 are connected by the upper surface side connection pattern 61, and the core substrate back surface side ground pattern 52 and the back surface side ground electrode 122 are connected by the back surface side connection pattern 62. Is done.

  After the main surface side connecting conductor forming step and the back surface side connecting conductor forming step, a hole filling step is performed. Specifically, the cavity of the through-hole conductor 16 is filled with an insulating resin material (epoxy resin) to form a closing body 17 (see FIG. 18).

  Next, a buildup layer forming step is performed. In the buildup layer forming step, the first buildup layer 31 is formed on the lowermost resin insulation layer 33 and the second buildup layer 32 is formed on the uppermost resin insulation layer 34 based on a conventionally known method. To do. Specifically, a resin epoxy layer having blind holes 251 and 252 at positions where via conductors 43 are to be formed by depositing a photosensitive epoxy resin on resin insulation layers 33 and 34, and performing exposure and development. 35 and 36 are formed (see FIG. 18). Next, electrolytic copper plating is performed according to a conventionally known method to form via conductors 43 in the blind holes 251 and 252, and terminal pads 44 are formed on the resin insulation layer 35, and the resin insulation layer 36 is formed on the resin insulation layer 36. A BGA pad 48 is formed.

  Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the resin insulating layers 35 and 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. As a result, the wiring substrate 10 including the core substrate 11 and the buildup layers 31 and 32 is completed.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) According to the method for manufacturing the wiring substrate 10 of the present embodiment, the upper surface side connection pattern 61 is formed in the main surface side opening 221 formed in the lowermost resin insulating layer 33. The formation can be performed simultaneously with the formation of the via conductor 47 in the lowermost resin insulating layer 33. Similarly, in order to form the back surface side connection pattern 62 in the back surface side opening 222 formed in the uppermost resin insulation layer 34, the formation of the back surface side connection pattern 62 is performed simultaneously with the formation of the via conductor 47 in the uppermost resin insulation layer 34. It can be carried out. As described above, a plating layer forming step for forming a plating layer, a resist forming step for forming an etching resist on the plating layer, an etching step for etching the plating layer to form an upper surface side connection pattern 61 and a back surface side connection pattern 62, etching The stripping process for stripping the resist is simplified. For this reason, the wiring board 10 can be easily manufactured, and the manufacturing cost of the wiring board 10 can be reduced.

  Moreover, since the ceramic capacitor 101 is fixed simultaneously with the formation of the lowermost resin insulating layer 33, the process can be further simplified. In addition, since the material filling the gap between the inner surface of the accommodation hole 90 and the side surface of the ceramic capacitor 101 is the resin filling portion 33 a constituting a part of the lowermost resin insulating layer 33, the ceramic capacitor 101 is fixed to the core substrate 11. In doing so, it is not necessary to prepare a material different from that of the lowermost resin insulating layer 33. Therefore, since the material necessary for manufacturing the wiring board 10 is reduced, the cost of the wiring board 10 can be reduced.

  (2) By the way, after the ceramic capacitor 101 is fixed to the core substrate 11 and before the lowermost resin insulating layer 33 and the uppermost resin insulating layer 34 are formed, the upper surface side connection pattern 61 and the rear surface side connection pattern 62 are formed. It is conceivable to form. In this case, the upper surface side connection pattern 61 and the back surface side connection pattern 62 are formed by performing a plating layer forming process, a resist forming process, an etching process, a peeling process, and the like. However, since the ceramic capacitor 101 includes the electrodes 111, 112, 121, and 122, there are many irregularities, and the ceramic sintered body 104 may be warped. Therefore, it is difficult to form the upper surface side connection pattern 61 and the back surface side connection pattern 62 by forming or etching the plating layer.

  On the other hand, in this embodiment, after the lowermost resin insulating layer 33 and the uppermost resin insulating layer 34 are formed, the openings 221 and 222 are formed to form the upper surface side connection pattern 61 and the rear surface side connection pattern 62. . Thereby, the upper surface side connection pattern 61 and the back surface side connection pattern 62 can be formed without being affected by the unevenness of the ceramic capacitor 101 and the warp of the ceramic sintered body 104.

  (3) By the way, when the upper surface side connection pattern 61 and the back surface side connection pattern 62 are formed after the ceramic capacitor 101 is fixed and before the resin insulation layers 33 and 34 are formed, the resin insulation layers 33 and 34 are formed. There is a possibility that the upper surface side connection pattern 61 and the rear surface side connection pattern 62 may be damaged due to thermal stress generated during the formation. However, in this embodiment, since the upper surface side connection pattern 61 and the rear surface side connection pattern 62 are formed after the resin insulating layers 33 and 34 are formed, the upper surface side connection pattern 61 and the rear surface side connection pattern 62 are damaged due to thermal stress or the like. Is prevented. Therefore, the connection reliability of the upper surface side connection pattern 61 and the back surface side connection pattern 62 is improved.

  (4) Conventionally, there has also been proposed a wiring board in which a plurality of capacitors are arranged in the horizontal direction in the housing hole, and the electrodes of some capacitors and the conductor pattern on the core main surface are connected by connecting conductors. However, since the connection conductor can only be connected to the electrode of the capacitor in the outer peripheral portion of the accommodation hole portion, there is a problem that power cannot be supplied to the capacitor at the center portion (the central portion of the accommodation hole portion).

  On the other hand, as a result of manufacturing the wiring substrate 10 by the manufacturing method of the present embodiment, one ceramic capacitor 101 is disposed in the accommodation hole 90, and the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111 are formed on the upper surface. The connection is made by the side connection pattern 61. Here, since the upper surface side power supply electrode 111 is a plain conductor covering substantially the entire capacitor main surface 102, power is supplied from the core substrate 11 side to the central portion of the ceramic capacitor 101 (the central portion of the accommodation hole portion 90). it can. Further, the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111 are connected by the upper surface side connection pattern 61, whereby the core substrate main surface side power supply pattern 51, the upper surface side connection pattern 61, and the upper surface side power supply An electrical path (first power supply path) that connects to the IC chip 21 through the electrode 111 and the first wiring laminated portion is formed. As a result, the number of electrical paths connected to the IC chip 21 increases, so that the resistance in the wiring board 10 is reduced and the voltage drop is reduced. Therefore, since the power can be reliably supplied to the IC chip 21, the IC chip 21 can be sufficiently operated, and the malfunction of the IC chip 21 can be prevented. Therefore, the wiring board 10 having excellent electrical characteristics and reliability can be obtained.

(5) Since the upper surface side connection pattern 61 of this embodiment becomes a three-dimensional shape by being formed in the opening portions 221 and 222, the thickness can be increased. As a result, the resistance of the upper surface side connection pattern 61 is reduced, and the voltage drop during power supply is also reduced. As a result, a large current can flow through the upper surface side connection pattern 61, so that sufficient power can be supplied to the IC chip 21.
[Second Embodiment]

  Hereinafter, a second embodiment embodying the wiring board of the present invention will be described in detail with reference to the drawings.

  As shown in FIGS. 19 and 20, the wiring board 10 </ b> A of the present embodiment is not a resin filling portion 33 a constituting a part of the lowermost resin insulating layer 33, but a resin different from the lowermost resin insulating layer 33. The difference from the first embodiment is that the hole filling material 92 is used to fill a gap between the inner surface of the accommodation hole 90 and the side surface of the ceramic capacitor 101. The resin hole filling material 92 is made of a polymer material (in this embodiment, a thermosetting resin such as epoxy). Therefore, the manufacturing method of the wiring board 10A of the present embodiment is also different from that of the first embodiment.

  That is, in this embodiment, when the ceramic capacitor 101 is temporarily fixed, the fixing step is performed without forming the lowermost resin insulating layer 33 on the core main surface 12 of the core substrate 11 and the capacitor main surface 102 of the ceramic capacitor 101. I do. Specifically, a resin hole filling material 92 made of a thermosetting resin (under NAMICS Co., Ltd.) is used in the gap between the inner surface of the accommodation hole 90 and the side surface of the ceramic capacitor 101 using a dispenser device (manufactured by Asymtek). Fill material) (see FIG. 19). At this time, the resin hole filling material 92 is filled until the main surface side wiring formation portion 93 becomes the same height as the core main surface 12 and the capacitor main surface 102. Thereafter, when heat treatment is performed, the resin hole filling material 92 is cured and the ceramic capacitor 101 is fixed in the accommodation hole 90.

  Next, an insulating layer forming step is performed to form the lowermost resin insulating layer 33 on the core main surface 12, the capacitor main surface 102, and the resin hole filling material 92 (see FIG. 19). Further, an opening forming step is performed. Specifically, laser drilling is performed on the lowermost resin insulating layer 33 to form the main surface side opening 221 and the via hole 223 (see FIG. 20). At this time, the adhesive tape 210 is peeled off, and the uppermost resin insulation layer 34 is formed on the core back surface 13 of the core substrate 11 and the capacitor back surface 103 of the ceramic capacitor 101.

  Accordingly, in the present embodiment, the process is simplified by performing the formation of the upper surface side connection pattern 61 simultaneously with the formation of the via conductor 47 in the lowermost resin insulating layer 33, so that the wiring board 10 can be easily manufactured, The manufacturing cost of the wiring board 10 can be reduced. Further, since the resin hole filling material 92 is separate from the lowermost resin insulating layer 33, the resin hole filling material 92 can be formed of a material optimal for fixing the ceramic capacitor 101. Therefore, since the ceramic capacitor 101 is firmly fixed, the connection reliability of the upper surface side connection pattern 61 formed on the resin hole filling material 92 is improved.

  Further, in the opening forming step, the main surface side opening 221 is formed by performing laser drilling on the lowermost resin insulating layer 33. The resin hole filling material 92 on the lower side of the lowermost resin insulating layer 33 is harder than the lowermost resin insulating layer 33 because it is cured in the previous stage of the opening forming step. For this reason, it becomes easy to adjust the output of the laser to such an extent that only the lowermost resin insulating layer 33 is processed and the resin hole filling material 92 is not processed. Therefore, the depth of the main surface side opening 221 can be easily controlled.

  In addition, you may change this embodiment as follows.

  In the second embodiment, after the filling of the resin hole filling material 92 and the formation of the lowermost resin insulating layer 33 are completed, the main surface side opening 221 is formed in the lowermost resin insulating layer 33 to connect the upper surface side. A pattern 61 was formed. However, when the filling of the resin hole filling material 92 is completed (see FIG. 21), on the main surface side wiring formation portion 93 (between the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111). Alternatively, the upper surface side connection pattern 61 may be formed (see FIG. 22), and then the lowermost resin insulating layer 33 may be formed. In this case, the upper surface side connection pattern 61 has a flat plate shape and has the same thickness as the core substrate main surface side power supply pattern 51 and the upper surface side power supply electrode 111. That is, one end of the upper surface side connection pattern 61 is bonded only to the side surface 53 of the core substrate main surface side power supply pattern 51, and the other end of the upper surface side connection pattern 61 is bonded only to the side surface of the upper surface side power supply electrode 111.

  The accommodation hole 90 in the above embodiment is a through hole that opens on both the core main surface 12 side and the core back surface 13 side of the core substrate 11, but the wiring substrate of another embodiment shown in FIG. The non-through-hole part opened only in the core main surface 12 like 10B may be sufficient.

  In the first embodiment, the gap between the inner surface of the accommodation hole 90 and the side surface of the ceramic capacitor 101 is filled only with the resin filling portion 33 a that constitutes a part of the lowermost resin insulating layer 33. However, like the wiring board 10C of another embodiment shown in FIG. 24, the gap constitutes a resin filling portion 33a constituting a part of the lowermost resin insulating layer 33 and a part of the uppermost resin insulating layer 34. It may be filled with the resin filling portion 33b.

  In this case, with the ceramic capacitor 101 temporarily fixed, the lowermost resin insulating layer 33 is formed on the core main surface 12 of the core substrate 11 and the capacitor main surface 102 of the ceramic capacitor 101, and the housing hole is formed by the resin filling portion 33a. The upper half of the gap between the inner surface of the portion 90 and the side surface of the ceramic capacitor 101 is filled (see FIG. 25). At this point, the adhesive tape 210 is peeled off. Next, the uppermost resin insulation layer 34 is formed on the core back surface 13 of the core substrate 11 and the capacitor back surface 103 of the ceramic capacitor 101, and the lower half of the gap is filled with the resin filling portion 33b (see FIG. 26). In this way, it becomes easy to completely spread the resin into the accommodation hole 90, so that the ceramic capacitor 101 can be reliably fixed to the core substrate 11. Further, when only the resin filling portion 33a is filled in the accommodation hole 90, the lowermost resin insulating layer 33 needs to be formed thick, but the resin filling portion 33a and the resin filling portion 33b are filled in the accommodation hole 90. By doing so, it is not necessary to form the lowermost resin insulating layer 33 thickly.

  In the above embodiment, when the openings 221 and 222 are formed at the positions where the upper surface side connection pattern 61 and the rear surface side connection pattern 62 are to be formed, respectively, the inner surfaces of the accommodation holes 90 and the resin insulating layers 33 and 34 The position directly above and below the gap with the side surface of the ceramic capacitor 101 has been entirely removed. However, when forming the openings 221, 222, the resin insulation layers 33, 34 may be partially removed at positions directly above and below the gap. That is, if at least a part of the position immediately above and the position immediately below is removed, the upper surface side connection pattern 61 and the back surface side connection pattern 62 can be formed.

  In the hole filling step of the above embodiment, the hollow portions of the plurality of through-hole conductors 16 are filled with an insulating resin material. And the upper surface side connection pattern 61 and the back surface side connection pattern 62 to be formed had a flat upper surface (or lower surface). However, like the wiring board 10D shown in FIG. 27, the upper surface side connection pattern 61 and the back surface side connection pattern 62 may be conductors having a recess 63. In this case, in the hole filling step, each recess 63 is filled with the same insulating material as the insulating resin material (blocking body 17) for filling the cavity, and the upper surface thereof is flattened together with filling the through-hole conductor 16. Good. In this way, the conductor layer 64 can be formed on the upper surface of the upper surface side connection pattern 61 and the rear surface side connection pattern 62, and the degree of freedom of wiring in the wiring laminated portion is improved. Further, since the process can be simplified as compared with the case where the filling of the hollow portion and the filling of the concave portion 63 are performed separately, the manufacturing cost of the wiring board 10D can be reduced.

  -Instead of the manufacturing method of the said embodiment, you may manufacture the wiring board 10E with the manufacturing method as shown below, for example.

  First, after carrying out the steps up to the insulating layer formation and fixing step according to the manufacturing method of the above embodiment to obtain the state shown in FIG. 13, the adhesive tape 210 is then peeled off from the ceramic capacitor 101. The core substrate back surface side ground pattern 52 and the ground electrode 122 exposed at this time have the same height and almost no step, and are in a so-called flush state (see FIG. 28). The core back surface 13 of the core substrate 11, the ground electrode 122, and the capacitor back surface 103 of the ceramic capacitor 101 have the same relationship.

  And here, without forming the lowermost resin insulation layer 34 on the core back surface 13 and the capacitor back surface 103, drilling is performed using a drill machine, and a through-hole penetrating the core substrate 11 and the resin insulation layer 33 is formed. A through hole 231 for forming a hole is formed at a predetermined position. And a main surface side connection conductor formation process and a back surface side connection conductor formation process are implemented. Specifically, after performing electroless copper plating, an etching resist is formed at a predetermined site, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed to remove unnecessary electroless copper plating. Thereby, on the core main surface 12 side, the upper surface side connection pattern 61 is formed in the main surface side opening 221, and the conductor layer 42 is patterned on the lowermost resin insulating layer 33. On the core back surface 13 side, a lower surface side connection pattern 62 that connects the core substrate back surface side ground pattern 52 and the ground electrode 122 is formed. At the same time, the through-hole conductor 16 is formed in the through hole 231 and the via conductor 47 is formed in each via hole 223 (see FIG. 29).

  Then, after the main surface side connecting conductor forming step and the back surface side connecting conductor forming step as described above, a hole filling step is performed, and a buildup layer forming step is further performed to complete the wiring board 10E.

  In the wiring board 10E manufactured in this way, for example, the lower surface side in FIGS. 28 and 29 is preferably used as the chip mounting surface side. In this case, high flatness is ensured on the surface of the buildup layer. Can do. Therefore, the coplanarity of the surface of the terminal pad 44 exposed on the chip mounting surface is increased, and as a result, the connection reliability of the IC chip 21 can be improved. Further, according to this manufacturing method, the formation of the lowermost resin insulating layer 34 on the core back surface 13 side and the formation of the main surface side opening 221 and the via hole 224 can be omitted. Can be reduced. Also, according to this method, it is relatively easy to form the wide lower surface side connection pattern 62.

  Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the embodiment described above are listed below.

  (1) A core substrate having a core main surface and a core back surface, in which an accommodation hole opening at least on the core main surface side is formed, and a core substrate main surface side conductor is disposed on the core main surface is prepared. And having a capacitor main surface and a capacitor back surface, having a plurality of via conductors whose ends are located on the capacitor main surface, connected to the plurality of via conductors and arranged in a plurality of layers via a dielectric layer. A preparation step of preparing a via array type capacitor having a plurality of internal electrode layers, wherein a capacitor main surface side electrode connected to end portions of the plurality of via conductors is disposed on the capacitor main surface; After the capacitor is accommodated in the hole, a lowermost resin insulating layer that forms a lowermost layer of the wiring laminated portion is formed on the core main surface and the capacitor main surface, and the capacitor and the core substrate are also formed. An insulating layer forming and fixing step of filling the gap with a part of the lowermost resin insulating layer and fixing the capacitor to the core substrate; and removing at least a part of the lowermost resin insulating layer immediately above the gap And forming an opening for exposing the core substrate main surface side conductor and part of the capacitor main surface side electrode, forming a main surface side connection conductor in the opening, The manufacturing method of a wiring board including the surface side conductor and the main surface side connection conductor formation process which connects the said capacitor main surface side electrode.

  (2) A core substrate having a core main surface and a core back surface, having an accommodation hole opening at least on the core main surface side, and having a core substrate main surface side conductor disposed on the core main surface is prepared. And preparing a ceramic capacitor having a capacitor main surface and a capacitor back surface, and a capacitor main surface side electrode disposed on the capacitor main surface, and after accommodating the ceramic capacitor in the accommodating hole, On the core main surface and the capacitor main surface, a lowermost resin insulating layer that forms a lowermost layer of a wiring laminated portion is formed, and a gap between the ceramic capacitor and the core substrate is combined with the lowermost resin insulating layer. Insulating layer formation and fixing step for fixing the ceramic capacitor to the core substrate by filling in part, and at least a position immediately above the gap in the lowermost resin insulating layer Forming an opening that exposes a part of the core substrate main surface side conductor and the capacitor main surface side electrode, and forming a main surface side connection conductor in the opening, The manufacturing method of a wiring board including the main surface side connection conductor formation process which connects a core substrate main surface side conductor and the said capacitor main surface side electrode.

  (3) Having a core main surface and a core back surface, an accommodation hole opening at the core main surface side and the core back surface side is formed, and a core substrate main surface side conductor is disposed on the core main surface, A core substrate having a core substrate back side conductor disposed on the core back surface is prepared, has a component main surface and a component back surface, and a component main surface side electrode is disposed on the component main surface, A preparation step of preparing an electronic component having a component back side electrode disposed thereon, and after housing the electronic component in the housing hole, on the core main surface and the component main surface, An insulating layer that forms a lowermost resin insulating layer that forms a lower layer and also fixes the electronic component to the core substrate by filling a gap between the electronic component and the core substrate with a part of the lowermost resin insulating layer. After the forming and fixing step and the insulating layer forming and fixing step, (A) forming an uppermost resin insulation layer that forms the uppermost layer of the second wiring laminated portion on the rear surface and the rear surface of the component, and removing at least a portion of the lowermost resin insulation layer immediately above the gap And forming a main surface side opening that exposes a part of the core substrate main surface side conductor and the component main surface side electrode, and removing at least a portion of the uppermost resin insulation layer immediately below the gap. An opening forming step of forming a back side opening that exposes a part of the core substrate back side conductor and the component back side electrode, and a main surface side connecting conductor is formed in the main surface side opening, and the core A main surface side connection for connecting the substrate main surface side conductor and the component main surface side electrode, forming a back surface side connection conductor in the back surface side opening, and connecting the core substrate back surface side conductor and the component back surface side electrode. Conductor formation process A method for manufacturing a wiring board comprising.

  (4) Having a core main surface and a core back surface, an accommodation hole opening on the core main surface side and the core back surface side is formed, and a core substrate main surface side conductor is disposed on the core main surface, Preparing a core substrate in which a core substrate back surface side conductor is disposed on the core back surface, having a capacitor main surface and a capacitor back surface, and having a plurality of via conductors whose ends are located on the capacitor main surface; A capacitor main surface side electrode connected to a plurality of via conductors and having a plurality of internal electrode layers arranged via a dielectric layer and connected to the end portions of the plurality of via conductors on the capacitor main surface Is prepared, and a step of preparing a capacitor in which a capacitor back surface side electrode is disposed on the capacitor back surface, and after accommodating the capacitor in the housing hole, on the core main surface and the capacitor main surface, A lowermost resin insulation layer is formed as a lowermost layer of the wiring laminated portion, and a gap between the capacitor and the core substrate is filled with a part of the lowermost resin insulation layer to fix the capacitor to the core substrate. An insulating layer forming and fixing step, and after the insulating layer forming and fixing step, an insulating layer forming step of forming an uppermost resin insulating layer forming the uppermost layer of the second wiring laminated portion on the core back surface and the capacitor back surface, And removing at least a part of the lowermost resin insulation layer at a position directly above the gap to form a main surface side opening that exposes a part of the core substrate main surface side conductor and the capacitor main surface side electrode. Removing at least a portion of the uppermost resin insulation layer at a position immediately below the gap to form a back-side opening that exposes a portion of the core-substrate back-side conductor and the capacitor back-side electrode. Forming a main surface side connection conductor in the main surface side opening and connecting the core substrate main surface side conductor and the capacitor main surface side electrode; and A back surface side connection conductor forming step of forming a back surface side connection conductor in the back surface side opening and connecting the core substrate back surface side conductor and the capacitor back surface side electrode, wherein the via conductor is A plurality of power supply via conductors and a plurality of ground via conductors, and the plurality of internal electrode layers are connected to the plurality of power supply via conductors, and the plurality of grounds A first capacitor main surface including a plurality of second internal electrode layers connected to the via conductor, wherein the capacitor main surface side electrode is disposed on the capacitor main surface and is connected to end portions of the plurality of power supply via conductors. Side electrodes and the key A second capacitor main surface side electrode disposed on the capacitor main surface and connected to ends of the plurality of ground via conductors, and the capacitor back surface side electrode is disposed on the capacitor back surface and the plurality of power supplies A first capacitor back surface side electrode connected to an end portion of the via conductor for use, and a second capacitor back surface side electrode disposed on the back surface of the capacitor and connected to the end portions of the plurality of ground via conductors, In the surface side connection conductor forming step, the main surface side connection conductor connects the core substrate main surface side power supply pattern, which is the core substrate main surface side conductor, and the first capacitor main surface side electrode, and the back surface side connection In the conductor forming step, the back surface side connection conductor connects the core substrate back surface side ground pattern, which is the core substrate back surface side conductor, and the second capacitor back surface side electrode. Method of manufacturing a substrate.

1 is a schematic sectional view showing a wiring board according to a first embodiment embodying the present invention. Similarly, the schematic plan view which shows the relationship between a core board | substrate, a ceramic capacitor, an upper surface side connection pattern, etc. FIG. Similarly, principal part sectional drawing for demonstrating the connection by an upper surface side connection pattern. Similarly, the schematic sectional drawing which shows a ceramic capacitor. Similarly, the schematic plan view which shows the upper surface of a ceramic capacitor. Similarly, the schematic plan view which shows the lower surface of a ceramic capacitor. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of the wiring board in 2nd Embodiment. Similarly, explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of the wiring board in other embodiment. Explanatory drawing of the manufacturing method of the wiring board in other embodiment. The schematic sectional drawing which shows the wiring board of other embodiment. The schematic sectional drawing which shows the wiring board of other embodiment. Explanatory drawing of the manufacturing method of the wiring board in other embodiment. Explanatory drawing of the manufacturing method of the wiring board in other embodiment. The schematic sectional drawing which shows the wiring board of other embodiment. Explanatory drawing of the manufacturing method of the wiring board in other embodiment. Explanatory drawing of the manufacturing method of the wiring board in other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10A, 10B, 10C, 10D, 10E ... Wiring board 11 ... Core board 12 ... Core main surface 13 ... Core back surface 16 ... Through-hole conductor 31 ... 1st buildup layer 33 which comprises wiring laminated part ... Wiring laminated part The lowermost resin insulation layer 42 constituting the wiring layer ... The conductor layer 51 constituting the wiring laminated portion ... The core substrate main surface side power supply pattern 61 as the core substrate main surface side conductor ... The upper surface side connection pattern 63 as the main surface side connecting conductor ... Recessed portion 90 ... Accommodating hole 92 ... Resin hole filling material 101 ... Ceramic capacitor 102 as electronic component and capacitor ... Capacitor main surface 103 as component main surface ... Capacitor back surface 105 as component back surface ... Ceramic dielectric as dielectric layer Layer 111 ... Upper surface side power supply electrode 112 as a component main surface side electrode ... Upper surface side ground electrode 131 as a component main surface side electrode ... Via conductor Via conductor for power supply 132... Ground via conductor as a via conductor 141. First internal electrode layer 142 as an internal electrode layer... Second internal electrode layer 221 as an internal electrode layer. Opening 223 ... via hole

Claims (7)

While having a core main surface and a core back surface, an accommodation hole that opens at least on the core main surface side is formed, and preparing a core substrate in which a core substrate main surface side conductor is disposed on the core main surface, A preparatory step of preparing an electronic component having a component main surface and a component back surface, wherein a component main surface side electrode is disposed on the component main surface;
A fixing step of filling the gap between the electronic component housed in the housing hole and the core substrate with a resin hole filling material and fixing the electronic component to the core substrate;
After the fixing step, an insulating layer forming step of forming a lowermost resin insulating layer forming a lowermost layer of a wiring laminated portion on the core main surface, the component main surface, and the resin hole filling material;
An opening forming step of removing at least a portion of the lowermost resin insulating layer at a position directly above the gap and exposing an opening of the core substrate main surface side conductor and the component main surface side electrode; ,
A method for manufacturing a wiring board, comprising: forming a main surface side connection conductor in the opening, and connecting the core substrate main surface side conductor and the component main surface side electrode. While having a core main surface and a core back surface, an accommodation hole opening at least on the core main surface side is formed, and preparing a core substrate in which a core substrate main surface side conductor is arranged on the core main surface, A preparatory step of preparing an electronic component having a component main surface and a component back surface, wherein a component main surface side electrode is disposed on the component main surface;
After the electronic component is accommodated in the accommodation hole portion, a lowermost resin insulating layer that forms a lowermost layer of a wiring laminated portion is formed on the core main surface and the component main surface, and the electronic component and the Insulating layer formation and fixing step of fixing the electronic component to the core substrate by filling a gap with the core substrate with a part of the lowermost resin insulating layer,
An opening forming step of removing at least a portion of the lowermost resin insulating layer at a position immediately above the gap and forming an opening exposing the core substrate main surface side conductor and the component main surface side electrode; ,
A method of manufacturing a wiring board, comprising: a main surface side connection conductor forming step of forming a main surface side connection conductor in the opening and connecting the core substrate main surface side conductor and the component main surface side electrode.   The electronic component has a plurality of via conductors penetrating between the component main surface and the component back surface, and is connected to the plurality of via conductors and stacked with a plurality of internal electrode layers via a dielectric layer 3. The wiring board according to claim 1, wherein the component main surface side electrode is a capacitor connected to end portions of the plurality of via conductors on the component main surface. Production method.   2. The opening forming step includes forming the opening by laser processing on the lowermost resin insulating layer and forming a via hole that exposes the component main surface side electrode. The manufacturing method of the wiring board of any one of thru | or 3.   5. The method for manufacturing a wiring board according to claim 1, wherein in the main surface side connection conductor forming step, the main surface side connection conductor is formed by electroless plating. 6.   In the main surface side connection conductor forming step, after performing electroless plating on the lowermost resin insulating layer and the inner surface of the opening, an etching resist is formed, then electrolytic plating is performed, and the etching resist is further removed. 2. The main surface side connection conductor is formed in the opening by performing soft etching, and a conductor layer constituting a wiring laminate is patterned on the lowermost resin insulation layer. The manufacturing method of the wiring board of any one of thru | or 5.   After the main surface side connecting conductor forming step, the cavity portions of the plurality of through-hole conductors formed so as to penetrate the core substrate and the lowermost resin insulating layer are filled with an insulating resin material, and the main surface side connecting conductor forming step is also performed. The method for manufacturing a wiring board according to claim 1, wherein a hole filling step of filling a concave portion formed at the location of the surface-side connection conductor is performed.

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