JP4591100B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a SiP (system in package) type semiconductor device having a built-in passive element and incorporating a matching circuit and a filter, and a manufacturing method thereof.

  The demand for downsizing, thinning, and weight reduction of portable electronic devices such as digital video cameras, digital mobile phones, and notebook personal computers is increasing. While an electronic circuit device in which such a semiconductor device is mounted on a printed wiring board has been realized by 70% reduction year by year, how can the component mounting density on the mounting substrate (printed wiring substrate) be improved? Has been researched and developed as an important issue.

  For example, the package form of a semiconductor device has shifted from a lead insertion type such as DIP (Dual Inline Package) to a surface mount type, and furthermore, bumps (projection electrodes) made of solder, gold, etc. are applied to pad electrodes of a semiconductor chip A flip-chip mounting method has been developed in which a face-down connection is made to the wiring board via bumps.

  Further, development has progressed to a package having a complicated form called SiP that incorporates a passive element such as an inductance or a capacitor and incorporates a matching circuit or a filter. For example, Patent Document 1 discloses the above-described SiP-type semiconductor device. The configuration is disclosed.

In the SiP type semiconductor device as described above, an inductance is required to form a filter and a matching circuit. For example, it is known to form an inductance using aluminum wiring on a chip.
However, even if the inductance of the aluminum wiring is formed on the chip, it is difficult to form an inductance having a large Q value in terms of size. For example, since the aluminum wiring is formed of a thin film having a film thickness of 1 μm or less, the specific resistance becomes high, and even if the inductance is constituted by the aluminum wiring, the Q value in the high frequency region due to the skin effect at high frequency. 15 was the limit.

  For the above reasons, when configuring a high-frequency module with a SiP-type semiconductor device, an external inductance component having a large Q value must be used, and the module itself becomes large due to the use of the external component. It cannot meet the demands for miniaturization / thinning.

  Further, when a ceramic substrate such as an LTCC (low temperature co-fired ceramic) substrate is used, a method of forming an inductance with a wiring of tungsten or silver by a printing method, for example, is known. However, the active element is bonded by wire bonding or flip chip, and the active element cannot be embedded.

For example, it is known that rewiring on a chip is performed by copper plating, and an inductance is formed using the same layer as this rewiring. However, it is difficult to ensure a large Q value because the rewiring has a maximum thickness of about 10 μm and is close to the silicon substrate.
JP 2005-5549 A

  The problem to be solved is that it is difficult to realize an inductance having a large Q value in a semiconductor device of the SiP type.

  The semiconductor device of the present invention is a semiconductor device packaged including an active element, and is formed by embedding a substrate, an insulating layer formed by laminating a resin layer on the substrate, and the insulating layer. A redistribution layer, an insulating buffer layer formed on the insulating layer, a conductive post connected to the redistribution layer and penetrating the buffer layer, and in the buffer layer And an inductance embedded and connected to the rewiring layer.

In the semiconductor device according to the present invention, an insulating layer is formed by laminating a resin layer on a substrate, and a rewiring layer is formed by being embedded in the insulating layer.
Here, an insulating buffer layer is formed above the insulating layer, and a conductive post is formed through the buffer layer connected to the rewiring layer, and also embedded in the buffer layer for rewiring. An inductance is formed in connection with the layers.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device packaged including an active element, a step of forming an insulating layer by laminating a resin layer on a substrate, and embedding in the insulating layer. Forming a rewiring layer; connecting the rewiring layer; forming a conductive post on the insulating layer; and connecting the rewiring layer to form an inductance on the insulating layer. Forming a buffer layer by covering the conductive post and the inductance on the insulating layer, and removing the buffer layer from the upper surface until the top of the conductive post is exposed. .

In the method for manufacturing a semiconductor device according to the present invention, a resin layer is laminated on a substrate to form an insulating layer, which is embedded in the insulating layer to form a rewiring layer.
Next, a conductive post is formed on the insulating layer in connection with the rewiring layer, and an inductance is formed.
Next, a buffer layer is formed by covering the upper layer of the insulating layer with the conductive post and the inductance, and the buffer layer is removed from the upper surface until the top of the conductive post is exposed.

  The semiconductor device according to the present invention is a SiP-type semiconductor device in which an inductance is provided in the buffer layer through which the conductive post penetrates, so that the thickness of the conductive post can be easily increased to a meander type. Therefore, a semiconductor device having an inductance having a large Q value can be realized.

  In the method of manufacturing a semiconductor device of the present invention, an inductance is formed in the buffer layer through which the conductive post penetrates, so that the thickness of the conductive post can be easily increased to increase the thickness of the meander type. A semiconductor device that can be formed and has an inductance having a large Q value can be manufactured.

  Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment.
For example, a base insulating film 11 made of silicon oxide is formed on a silicon substrate 10, and a lower electrode 12 made of, for example, aluminum or copper, Ta ₂ O ₅ , BST, PZT, BaTiO ₃ , silicon nitride, polyimide is formed thereon. A dielectric film 13 made of resin or silicon oxide, a lower electrode take-out electrode 14a and an upper electrode 14b made of aluminum or copper are laminated, and the lower electrode 12 and the upper electrode 14b face each other with the dielectric film 13 in between. The part which has become an electrostatic capacitance element ( _Ca , _Cb ).

A first insulating layer 15 made of polyimide resin, epoxy resin, acrylic resin or the like is formed so as to cover the capacitive element.
The first insulating layer 15 has openings reaching the lower electrode extraction electrode 14a and the upper electrode 14b, and is integrated with a plug portion embedded in the opening and connected to the lower electrode extraction electrode 14a and the upper electrode 14b. Thus, the first wiring 16 composed of the barrier metal layer 16 a and the copper layer 16 b is formed on the first insulating layer 15.
A part of the first wiring 16 is formed in a spiral shape, and an inductance (L _a , L _b ) is configured.

In addition, a second insulating layer 17 made of the same polyimide resin as the first insulating layer 15 is formed so as to cover the first wiring 16, and an opening reaching the first wiring 16 is formed. A second wiring 18 composed of a barrier metal layer 18 a and a copper layer 18 b is formed on the second insulating layer 17 so as to be integrated with the plug portion embedded and connected to the first wiring 16.
A part of the second wiring 18 is formed in a spiral shape, and an inductance L _c is configured.

Further, a third insulating layer 19 made of the same polyimide resin as that of the first insulating layer 15 is formed so as to cover the second wiring 18, and an opening reaching the second wiring 18 is formed. A third wiring 20 including a barrier metal layer 20a and a copper layer 20b is formed on the third insulating layer 19 so as to be integrated with a plug portion that is buried and connected to the second wiring 18.
A part of the third wiring 20 is formed in a spiral shape, and an inductance (L _d , _Le ) is configured.

  A semiconductor chip 21 provided with active elements is bonded to the upper layer of the third insulating layer 19 and the third wiring 20 by a die attach film 22. The semiconductor chip 21 has a structure in which a pad 21b is formed on a semiconductor body portion 21a, and a region excluding the pad 21b is covered with a silicon oxide protective layer 21c, and is face-up, that is, on the opposite side of the pad 21b formation surface. Mounted from the front side.

A fourth insulating layer 23 made of the same polyimide resin as the first insulating layer 15 is formed so as to cover the third wiring 20 and the semiconductor chip 21.
In the fourth insulating layer 23, openings reaching the pads 21b of the semiconductor chip 21 and the surface of the third wiring 20 are formed.
A fourth wiring 24 composed of a barrier metal layer 24a and a copper layer 24b is formed on the fourth insulating layer 23 integrally with the plug portion embedded in the opening and connected to the pad 21b and the third wiring 20. ing.

  Further, a conductive post in which a first conductive post 25 and a second conductive post 26 made of copper or the like are laminated is formed connected to the fourth wiring 24.

On the other hand, a meander-type inductance L _m formed of a columnar conductive layer made of a low-resistance material such as copper connected to the fourth wiring 24 and formed at the same height as the first conductive post 25 is provided. Is formed. To a part of the upper portion of the inductance L _m, a second conductive posts 26 are formed.

A conductive post formed of the first conductive post 25 and the second conductive post 26, the upper layer of the fourth insulating layer 23 in the gap of the second conductive posts formed on the inductance L _m and the upper portion of the meander type, An insulating buffer layer 27 made of polyamideimide resin, polyimide resin, epoxy resin, phenol resin, polyparaphenylene benzobisoxazole resin or the like is formed.
Further, bumps (projection electrodes) 28 are formed on the surface of the buffer layer 27 so as to be connected to the second conductive posts 26.

In the semiconductor device of this embodiment, the first insulating layer 15, the second insulating layer 17, the third insulating layer 19, and the fourth insulating layer 23 made of a resin layer are stacked on the silicon substrate 10 to form an insulating layer. A rewiring layer made up of the first wiring 16, the second wiring 18, the third wiring 20, the fourth wiring 24 and the like is formed by being embedded in the insulating layer.
Here, an insulating buffer layer 27 is formed above the insulating layer. The conductive buffer layer 27 is connected to the redistribution layer, penetrates the buffer layer 27, and is composed of first and second conductive posts (25, 26). sex post is formed, also embedded in the buffer layer 27 has a configuration in which the inductance L _m of the meander are connected to the redistribution layer is formed.

In the semiconductor device of the present embodiment, in the SiP type semiconductor device, by providing an inductance in the buffer layer through which the conductive post penetrates, the film thickness can be easily increased within the range of the height of the conductive post. For example, a meander type inductance by copper plated wiring having an aspect ratio of 1.0 or more is advantageous in terms of specific resistance and skin effect, can realize an inductance having a large Q value, and is a semiconductor device compatible with high frequencies. is there.
In addition, by insulating layers between the inductance and the substrate are formed, to secure the distance between the high silicon substrate and the inductance L _m of conductivity, to reduce the influence of the inductance L _m of the silicon substrate The Q value of the inductance can be further increased.

In the semiconductor device of the present embodiment, preferably, the conductive post includes a first conductive post and a second conductive post formed in an upper layer of the first conductive post.
Since the conductive post penetrates the buffer layer and the inductance is embedded in the buffer layer, it is necessary to make the conductive post higher than the inductance. However, as described above, the conductive post is connected to two of the first and second conductive posts. With the layer configuration, the first conductive post portion and the inductance can be formed in one step.

Preferably, the inductance embedded in the buffer layer is a meander type, and the constituent material of the inductance includes copper.
With such a configuration, it is possible to further increase the Q value of the inductance embedded in the buffer layer and cope with high frequencies.

Preferably, a part of the rewiring layer constitutes a passive element.
As in this embodiment, the rewiring layer rewires the silicon substrate or the semiconductor chip, and a part of the rewiring layer preferably constitutes a passive element, and the inductance L embedded in the buffer layer in addition to _m, by combining the electrostatic capacitance element (C _a, C _b) and the inductance _{(L a, L b, L} c, L d, L e) a passive element such as, for example, LPF (Low Pass Filter) BPF (Band Pass Filter) or HPF (High Pass Filter) can be configured, and a combination of these and active elements provided in the semiconductor chip 21 or the like constitutes a so-called SiP type semiconductor device. be able to.

In the semiconductor device of the present embodiment, the semiconductor chip is preferably embedded in the insulating layer so as to be connected to the rewiring layer, and more preferably, an active element is formed in the semiconductor chip. Alternatively, preferably, the substrate is a semiconductor substrate and an active element is formed, and the redistribution layer is formed in connection with the semiconductor substrate. Alternatively, active elements may be provided on both the semiconductor chip and the substrate.
A SiP semiconductor device can be configured in combination with the above passive elements.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. In the present embodiment, for example, all processes shown in FIGS. 2 to 10 can be performed at the wafer level.
First, as shown in FIG. 2A, for example, silicon oxide having a thickness of 300 nm is deposited on a silicon substrate 10 having a thickness of 725 μm by a CVD (chemical vapor deposition) method, a thermal diffusion method, or a sputtering method. Then, the base insulating film 11 is formed.

Next, as shown in FIG. 2B, for example, aluminum or copper is deposited by sputtering or the like, and patterned to form the lower electrode 12.
Next, for example, Ta ₂ O ₅ , BST, PZT, BaTiO ₃ , silicon nitride or silicon oxide is deposited by CVD or the like, or polyimide resin is applied by spin coating or the like to form the dielectric film 13. Then, the lower electrode outlet is opened in the obtained dielectric film 13.
Next, for example, aluminum or copper is deposited by sputtering or the like, and patterned to form a lower electrode take-out electrode 14a and an upper electrode 14b.
Capacitance elements (C _a , C _b ) in which the lower electrode 12 and the upper electrode 14 b face each other through the dielectric film 13 are configured.

Next, as shown in FIG. 2C, a photosensitive insulating material such as polyimide resin, epoxy resin, polyolefin resin, silicone resin, phenol resin, or acrylic resin is supplied by, for example, spin coating, The first insulating layer 15 is formed with a film thickness of about 10 μm.
In the case of a photosensitive polyimide resin, for example, the film is formed under the following conditions.
Spin coating: 50 rpm (1 second) + 50 rpm (20 seconds) + 300 rpm (5 seconds) + 1000 rpm (10 seconds)
Pre-bake: 90 ° C (120 seconds) + 100 ° C (120 seconds) + room temperature (30 seconds)

Next, pattern exposure and development are performed at an exposure amount of 150 mJ, and an opening reaching the extraction electrode 14 a and the upper electrode 14 b of the lower electrode is formed in the first insulating layer 15. The aspect ratio of the opening is set to 1.7 or less in consideration of the coverage of seed sputtering in the next process.
After the development, for example, the first insulating layer 15 is cured (cured) under the following conditions.
Post cure: 150 ° C. (20 minutes) + 150 ° C. (30 minutes) + 300 ° C. (20 minutes) + 300 ° C. (120 minutes)

Next, as shown in FIG. 3A, for example, a 160 nm Ti layer / 600 nm Cu layer stack or CrCu is formed by seed sputtering, and the inner wall of the opening formed in the first insulating layer 15 is formed. Then, a barrier metal layer 16a is formed on the entire surface and treated with O ₂ asher (300 W) for 5 minutes.

  Next, as shown in FIG. 3B, for example, in order to prevent plating other than the opening formed in the first insulating layer 15 and the formation region of the first wiring, resist coating and development processing are performed. Then, a resist film R1 having a pattern that opens the opening formed in the first insulating layer 15 and the formation region of the first wiring is formed.

  Next, as shown in FIG. 3C, for example, the film thickness on the first insulating layer 15 is obtained by 1.5 A, 90 minutes of electrolytic plating using the resist film as a mask and the barrier metal layer 16a as a seed. Is plated to have a thickness of about 5 μm to form a copper layer 16b in the opening formed in the first insulating layer 15 and the first wiring formation region.

Next, as shown in FIG. 4A, the resist film R1 is removed by, for example, ashing, and the barrier metal layer 16a is etched using the copper layer 16b as a mask, as shown in FIG. 4B. To do. In order to prevent undercut in this seed etching, the overlap portion of the opening formed in the first insulating layer 15 and the pattern of the resist film R1 is at least 5 μm.
As described above, the first wiring 16 including the barrier metal layer 16a and the copper layer 16b is formed on the first insulating layer 15 integrally with the plug portion connected to the lower electrode extraction electrode 14a and the upper electrode 14b. At this time, the inductance (L _a , L _b ), which is one of the passive elements, is simultaneously patterned as part of the first wiring 16.

Next, the formation of the wiring by the semi-additive method as described above is repeated three times, three insulating films are stacked, and wiring is formed in each layer. That is, after the steps of forming the first insulating layer 15, opening the opening with respect to the first insulating layer 15, and forming the first wiring 16, forming the second insulating layer 17 and opening the opening with respect to the second insulating layer 17 are performed. The stacked body shown in FIG. 5A is formed by performing the steps of forming the opening, forming the second wiring 18, forming the third insulating layer 19, opening the opening with respect to the third insulating layer 19, and forming the third wiring. And At this time, the inductance L _c, which is one of the passive elements, is also patterned simultaneously as part of the second wiring 18, and the inductances (L _d , _Le ) are also patterned simultaneously as part of the third wiring 20.

The total thickness of the first to third insulating layers (16, 18, 20) is preferably about 50 μm, for example. For example, when this film thickness is realized by a single insulating layer, it can be formed under the following conditions when using photosensitive polyimide.
Spin coating: 7000 rpm (25 seconds) + 1000 rpm (125 seconds) + 1000 rpm (10 seconds) + 1500 rpm (10 seconds)
Pre-bake: 60 ° C (240 seconds) + 90 ° C (240 seconds) + 110 ° C (120 seconds)
After the film thickness of 78 μm is obtained by the above treatment, it can be cured at 150 ° C. (30 minutes) + 250 ° C. (120 minutes) to a film thickness of 50 ± 5 μm.

Next, as shown in FIG. 5B, for example, a semiconductor chip 21 having an active element previously formed in a separate process in a separate process in an upper layer of the third insulating layer 19 and the third wiring 20. Mount.
The semiconductor chip 21 has a configuration in which a pad 21b is formed on a semiconductor body portion 21a, and a region excluding the pad 21b is covered with a protective layer 21c made of silicon oxide. For example, the semiconductor chip 21 is a chip on which an active element is formed. Before thinning / dividing into pieces. Grinding to a thickness of 25 μm in the case of silicon and 50 μm in the case of GaAs, laminating an adhesive layer on this, and dicing it into thin semiconductor chips.
The semiconductor chip 21 having the above-described structure is laminated face-up using a high-precision die bonder, that is, from the side opposite to the surface on which the pad 21b is formed, via the die attach film 22, and is formed at a temperature of 160.degree. A 6N load is applied for 2 seconds. By offsetting the alignment mark provided on the mounting surface of the semiconductor chip 21 and the electrode of the semiconductor chip 21 from the tool, it can be recognized by one camera. For example, it can be mounted with a mounting accuracy of ± 1 μm.

Next, as shown in FIG. 6A, a photosensitive insulating material such as a polyimide resin, an epoxy resin, or an acrylic resin is supplied by, for example, a spin coating method in the same manner as the first to third insulating layers. Then, the fourth insulating layer 23 is formed. For example, it is formed so as to have a film thickness of, for example, 50 μm after curing, and this may be a thickness that covers the semiconductor chip 21.
In the case of a photosensitive polyimide resin, for example, the film is formed under the following conditions.
Spin coating: 7000 rpm (25 seconds) + 1000 rpm (125 seconds) + 1000 rpm (10 seconds) + 1500 rpm (10 seconds)
Pre-baking: 60 ° C (240 seconds) + 90 ° C (240 seconds) + 110 ° C (240 seconds)
A film thickness of 78 μm is obtained by the above treatment.

Next, pattern exposure and development with an exposure amount 300 mJ / cm ^2, the second opening H _b reaching the first opening H _a and the third wiring 20 reaches the pad 21b of the semiconductor chip 21 in the fourth insulating layer 23 Form.
After development, post cure is performed to make the fourth insulating layer 23 have a thickness of 50 μm.

Next, as shown in FIG. 6B, for example, a 160 nm-thick Ti layer / 600 nm-thickness Cu layer stack or CrCu is formed by seed sputtering, and the pad 21b of the semiconductor chip 21 is formed. the inner wall of the second opening H _b reaching the first opening H _a and the third wiring 20 reaches the coated, formed on the entire surface of the barrier metal layer 24a, treating 5 min O ₂ asher (300 W).
Next, the resist coating and developing processing, the pattern for opening the second opening H _b and forming region of the fourth wiring reaching the first opening H _a and the third wiring 20 reaches the pad 21b of the semiconductor chip 21 A resist film (not shown) is formed, using this as a mask, copper is plated by electrolytic plating at 400 mA and 50 minutes using the barrier metal layer 24a as a seed, and a first opening reaching the pad 21b of the semiconductor chip 21 in H _a and the second opening reaches the third wiring 20 H _b and forming region of the fourth wiring forming the copper layer 24b. Thereafter, the resist film is removed.

Next, as shown in FIG. 7A, for example, a photosensitive dry film is bonded, or a resist film R2 is formed with a film thickness of, for example, 75 μm, and pattern exposure and development are performed for the first conductive post. An opening H _c and a meander-type inductance opening H _d are formed.

Next, as shown in FIG. 7B, the first conductive having a height of 80 μm and a diameter of 180 μm is formed in the opening H _c for the first conductive post by electrolytic plating of copper using the barrier metal film 24a. Posts 25 are formed.
Furthermore, by electrolytic plating described above is formed in the opening H _d of the inductance of the meander type, a width 80 [mu] m, a meander-type inductance L _m of height 80 [mu] m.

Next, as shown in FIG. 8A, a photosensitive dry film or resist film R3 is formed to a thickness of, for example, 75 μm on the above photosensitive dry film or resist film R2, and pattern exposure and development are performed. Thus, an opening H _c ′ for the second conductive post connected to the first conductive post and an opening H _d ′ for the second conductive post connected to the inductance L _m are formed.

Next, as shown in FIG. 8B, a height of 80 μm is formed in the openings (H _c ′, H _d ′) for the second conductive posts by electrolytic plating of copper using the barrier metal film 24a. The second conductive post 26 is formed.

  Next, as shown in FIG. 9A, the dry film or the resist film (R2, R3) is removed.

Next, as shown in FIG. 9 (b), the first and second conductive posts (25, 26), is etched barrier metal layer 24a of the inductance L _m and the copper layer 24b as a mask. Thereby, the 4th wiring 24 which consists of barrier metal layer 24a and copper layer 24b is formed.

Next, as shown in FIG. 10A, for example, an epoxy resin, a polyimide resin, a silicone resin, a polyamideimide resin, a polyimide resin, a phenol resin, or a polyparaphenylene benzobisoxazole resin is spin-coated. and the deposited printed or mold to form the first and second conductive posts (25, 26) and the inductance L _m buffer layer 27 of insulating a thickness as to completely cover the.
For example, when using a polyimide resin, the paste is formed by using a paste having an NV value of 27.5 by a printing method and printing with a squeegee. Curing is performed at, for example, 100 ° C. (10 minutes) + 150 ° C. (10 minutes) + 200 ° C. (10 minutes) + 250 ° C. (60 minutes).

  Next, as shown in FIG. 10B, after the resin hardening of the buffer layer 27, cueing of the second conductive post 26 is performed by grinding. The conditions at this time are set to 3500 rpm and 0.5 mm / second using, for example, a # 600 wheel.

Next, bumps (projection electrodes) 27 are formed so as to be connected to the second conductive posts 26 by, for example, mounting solder balls, printing LGA, or solder bumps.
In the case of printing solder bumps, for example, lead-free solder is printed with a diameter of 0.2 mm and reflowed at a temperature of 260 ° C. or lower to form bumps.
After that, for example, the silicon substrate 10 is half-cut and diced by thinning, thereby having secondary connection reliability and having a buffer layer that can relieve stress, and therefore can be repaired without an underfill. A wafer-level SiP semiconductor device having the configuration shown in FIG. 1 can be obtained.

According to the method of manufacturing a semiconductor device according to the above-described embodiment, when the SiP type semiconductor device is manufactured, an inductance is formed in the buffer layer through which the conductive post penetrates, so that the height of the conductive post is increased. Can be easily increased to a meander-type inductance with copper-plated wiring with an aspect ratio of 1.0 or more, which is advantageous in terms of specific resistance and skin effect, and realizes an inductance with a large Q value. And a semiconductor device corresponding to high frequency can be manufactured.
In addition, since an insulating layer is formed between the inductance and the substrate, a distance between the silicon substrate having high conductivity and the inductance L _m is ensured, and the influence on the inductance L _{m of the} silicon substrate is reduced. The Q value can be further increased.

In the method of manufacturing a semiconductor device according to the present embodiment, preferably, the step of forming the conductive post includes the step of forming the first conductive post and the second conductive post on the first conductive post. More preferably, simultaneously with the step of forming the first conductive post and the step of forming the inductance.
Since the conductive post penetrates the buffer layer and the inductance is embedded in the buffer layer, it is necessary to make the conductive post higher than the inductance. However, as described above, the conductive post is connected to two of the first and second conductive posts. By forming the layers, the first conductive post portion and the inductance can be formed in one step.

Preferably, in the step of forming the inductance embedded in the buffer layer, the inductance including meander type copper is formed.
With such a configuration, it is possible to further increase the Q value of the inductance embedded in the buffer layer and cope with high frequencies.

Preferably, in the step of forming the rewiring layer, a part of the rewiring layer is formed to constitute a passive element.
As in this embodiment, the rewiring layer rewires the silicon substrate or the semiconductor chip, and a part of the rewiring layer preferably constitutes a passive element, and the inductance L embedded in the buffer layer in addition to _m, by combining the electrostatic capacitance element (C _a, C _b) and the inductance _{(L a, L b, L} c, L d, L e) a passive element such as, for example, LPF (Low Pass Filter) BPF (Band Pass Filter) or HPF (High Pass Filter) can be configured, and a combination of these and active elements provided in the semiconductor chip 21 or the like constitutes a so-called SiP type semiconductor device. be able to.

The semiconductor device of the present embodiment preferably further includes a step of mounting a semiconductor chip connected to the redistribution layer, and more preferably, an active element is formed in the step of mounting the semiconductor chip. It is equipped with a semiconductor chip. Alternatively, preferably, a semiconductor substrate on which an active element is formed is used as the substrate, and in the step of forming the rewiring layer, the rewiring layer is formed by connecting to the semiconductor substrate. Alternatively, active elements may be provided on both the semiconductor chip and the substrate.
A SiP semiconductor device can be configured in combination with the above passive elements.

The present invention is not limited to the above description.
For example, the inductance embedded in the buffer layer may be an inductance other than the meander type.
It is also possible to provide a semiconductor device having no passive element other than the inductance embedded in the buffer layer.
Further, although four layers of wiring (first wiring, second wiring, third wiring, and fourth wiring) are formed as the wiring in the insulating layer, the present invention is not limited to this.
The resin used for the buffer layer and the first to fourth insulating layers is not limited to the above, and other resins can also be used.
In addition, various modifications can be made without departing from the scope of the present invention.

  The semiconductor device of the present invention can be applied to a semiconductor device in a system in package form.

  The semiconductor device manufacturing method of the present invention can be applied to a system-in-package semiconductor device manufacturing method.

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2A to 2C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 3A to 3C are cross-sectional views illustrating the manufacturing process of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 4A and FIG. 4B are cross-sectional views showing manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 5A and FIG. 5B are cross-sectional views showing manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 6A and FIG. 6B are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 7A and FIG. 7B are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the embodiment of the present invention. FIG. 8A and FIG. 8B are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 9A and FIG. 9B are cross-sectional views showing manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 10A and FIG. 10B are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 11 ... Base insulating film, 12 ... Lower electrode, 13 ... Dielectric film, 14a ... Lower electrode taking-out electrode, 14b ... Upper electrode, 15 ... 1st insulating layer, 16 ... 1st wiring, 16a, 18a , 20a, 24a ... barrier metal layer, 16b, 18b, 20b, 24b ... copper layer, 17 ... second insulating layer, 18 ... second wiring, 19 ... third insulating layer, 20 ... third wiring, 21 ... semiconductor chip 21a ... Semiconductor body portion, 21b ... Pad, 21c ... Protective layer, 22 ... Die attach film, 23 ... Fourth insulating layer, 24 ... Fourth wiring, 25 ... Conductive post, 26 ... Buffer layer, 27 ... Bump, L _m ... meander type inductance, C _a , C _b ... capacitance element, L _a , L _b , L _c , L _d , L _e ... inductance, H _a ... first opening, H _b ... second opening

Claims (17)

And the base plate,
An insulating layer formed by laminating a resin layer on the substrate;
A rewiring layer formed embedded in the insulating layer;
An insulating buffer layer formed on the insulating layer; and
Conductive posts formed through the buffer layer connected to the redistribution layer;
An inductance embedded in the buffer layer and connected to the redistribution layer;
Have a bump formed so as to be connected to the conductive post on a surface of the buffer layer, a semiconductor device which is packaged include active devices. The semiconductor device according to claim 1, wherein the conductive post includes a first conductive post and a second conductive post formed in an upper layer of the first conductive post. The semiconductor device according to claim 1, wherein the inductance is a meander type. The semiconductor device according to claim 1, wherein the inductance material includes copper. The semiconductor device according to claim 1, wherein a part of the redistribution layer constitutes a passive element. The semiconductor device according to claim 1, wherein a semiconductor chip is embedded in the insulating layer so as to be connected to the redistribution layer. The semiconductor device according to claim 6, wherein the active element is formed on the semiconductor chip. The substrate is a semiconductor substrate, and the active element is formed;
The semiconductor device according to claim 1, wherein the rewiring layer is connected to the semiconductor substrate. Forming an insulating layer by laminating a resin layer on a plate,
Forming a rewiring layer by embedding in the insulating layer;
Connecting the rewiring layer to form a conductive post on the insulating layer; and
Connecting to the redistribution layer and forming an inductance in an upper layer of the insulating layer;
Forming a buffer layer on the insulating layer by covering the conductive post and the inductance; and
Removing the buffer layer from the top surface until the top of the conductive post is exposed;
Possess and forming bumps to be connected to the conductive post on a surface of the buffer layer,
A semiconductor device manufacturing method for manufacturing a packaged semiconductor device including an active element . The semiconductor device according to claim 9, wherein the step of forming the conductive post includes a step of forming a first conductive post and a step of forming a second conductive post on an upper layer of the first conductive post. Manufacturing method. The method for manufacturing a semiconductor device according to claim 10, wherein the method is performed simultaneously with the step of forming the first conductive post and the step of forming the inductance. The method for manufacturing a semiconductor device according to claim 9, wherein a meander type inductance is formed in the step of forming the inductance. The method for manufacturing a semiconductor device according to claim 9, wherein the constituent material forms an inductance containing copper in the step of forming the inductance. The method of manufacturing a semiconductor device according to claim 9, wherein in the step of forming the rewiring layer, a part of the rewiring layer is formed to constitute a passive element. The method for manufacturing a semiconductor device according to claim 9, further comprising a step of embedding in the insulating layer and mounting a semiconductor chip connected to the rewiring layer. The method of manufacturing a semiconductor device according to claim 15, wherein in the step of mounting the semiconductor chip, a semiconductor chip on which the active element is formed is mounted. As the substrate, a semiconductor substrate on which the active element is formed,
The method for manufacturing a semiconductor device according to claim 9, wherein in the step of forming the redistribution layer, the redistribution layer is formed by connecting to the semiconductor substrate.

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