JP2002270712A - Semiconductor element integrated multi-layer wiring board, semiconductor element integrated device, and manufacturing method therefor - Google Patents

Semiconductor element integrated multi-layer wiring board, semiconductor element integrated device, and manufacturing method therefor

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Publication number
JP2002270712A
JP2002270712A JP2001072800A JP2001072800A JP2002270712A JP 2002270712 A JP2002270712 A JP 2002270712A JP 2001072800 A JP2001072800 A JP 2001072800A JP 2001072800 A JP2001072800 A JP 2001072800A JP 2002270712 A JP2002270712 A JP 2002270712A
Authority
JP
Japan
Prior art keywords
wiring board
semiconductor element
prepreg
semiconductor device
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001072800A
Other languages
Japanese (ja)
Inventor
Nobuhiro Hanai
Yoshihiko Imai
Toshihiro Murayama
Akimasa Okaji
義彦 今井
昭昌 岡地
敏宏 村山
信洋 花井
Original Assignee
Sony Corp
ソニー株式会社
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Publication date
Application filed by Sony Corp, ソニー株式会社 filed Critical Sony Corp
Priority to JP2001072800A priority Critical patent/JP2002270712A/en
Publication of JP2002270712A publication Critical patent/JP2002270712A/en
Application status is Pending legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element incorporating multi-layer wiring board or a semiconductor element incorporating device at low cost without a trouble caused by stress in the perefahery of the incorporated semiconductor element.
SOLUTION: A lower wiring board 11 made up of an epoxy resin and glass fiber and a semiconductor element 16 are bonded with prepreg 13 having almost the same component as the lower wiring board 11. An intermediate wiring board 21 having a hole corresponding to the position of the semiconductor element 16 and an upper wiring board 31 are overlapped thereon through the prepreg 13 and stored in a vacuum treatment container 41. While the overlapped members are heated under pressure and put under low-pressure atmosphere, the lower wiring board 11, the intermediate wiring board 21, the upper wiring board 31 are laminated and hardened by applying the prepreg 13 into a space around the semiconductor element 16.
COPYRIGHT: (C)2002,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は半導体素子内蔵多層配線基板と半導体素子内蔵装置、およびそれらの製造方法に関するのものであり、更に詳しくは、熱ストレスや機械的ストレスを受け難く、かつ低コストである半導体素子内蔵多層配線基板と半導体素子内蔵装置、およびそれらの製造方法に関するものである。 BACKGROUND OF THE INVENTION The present invention is a semiconductor element built multilayer wiring board and the semiconductor element built device, and are of about the methods for their preparation, more particularly, less susceptible to thermal stress or mechanical stress, and low cost the semiconductor device built multilayer wiring board and the semiconductor element-containing apparatus is, and is intended to processes for their preparation.

【0002】 [0002]

【従来の技術】近年、電子機器の小型化が進んでおり、 In recent years, it is progressing miniaturization of electronic devices,
モーバイル情報端末やモーバイル通信機器の普及によって半導体素子を含む配線基板は一層の小型化が要求され、かつ信頼性の向上、低コスト化が要請されている。 Wiring board including the semiconductor device by the spread of Mobile computing information terminals and Mobile computing communications equipment is required further miniaturization and improved reliability, and lower cost is demanded.
図8、図9は従来例の半導体素子内蔵多層配線基板10 8 and 9 are conventional semiconductor device built multilayer wiring board 10 of the
0の製造方法のステップを示す図である。 It is a diagram illustrating the 0 steps of the manufacturing method of the. 図8のAに示すように、下層配線基板11上の接着領域に導電性粒子を配合した異方性または等方性の半導体素子用接着材1 As shown in A of FIG. 8, the lower layer wiring substrate 11 anisotropically or isotropically for a semiconductor element adhesive material blended with conductive particles to the adhesive regions on the 1
9を適用し、図8のBに示すように、下層配線基板11 9 was applied, as shown in B of FIG. 8, the lower layer wiring board 11
の配線パターンp上の接続部12にベアの半導体素子1 The semiconductor device 1 of the bare in the connecting portion 12 on the wiring pattern p
6の電極端子17を接続し、加熱・加圧して半導体素子16を実装する。 Connect the sixth electrode terminal 17, for mounting a semiconductor element 16 heated and pressed. そして、図8のCに示すように、半導体素子16に対応する部分をくり抜いた中間配線基板2 Then, as shown in C of FIG. 8, the intermediate wiring board 2 hollowed out portion corresponding to the semiconductor element 16
1の下面にプリプレグ13を適用したものを下層配線基板11に重ね合わせ、更に上層配線基板31の下面にプリプレグ13を適用したものを中間配線基板21の上面に重ね合わせている。 Superposing an application of the prepreg 13 to the lower surface of the 1 in the lower layer wiring substrate 11, are superimposed and further applying the prepreg 13 to the lower surface of the upper wiring board 31 on the upper surface of the intermediate wiring board 21.

【0003】次いで、図9のAに示すように、下層配線基板11、中間配線基板21、上層配線基板31を重ね合わせたものを加熱・加圧してプリプレグを一括して硬化させることにより、図9のBに示すように、半導体素子16を内蔵した多層配線基板100が形成されている。 [0003] Then, as shown in A of FIG. 9, the lower layer wiring substrate 11, an intermediate wiring substrate 21, it is cured by collectively prepreg by applying heat and pressure to the superposition of the upper wiring board 31, FIG. as shown in 9 of B, the multilayer wiring substrate 100 with a built-in semiconductor element 16 is formed. なお上記において、下層配線基板11、中間配線基板21、上層配線基板31には一般的にはエポキシ樹脂からなるものが使用され、その場合には半導体素子用接着材(または接着フィルム)13もエポキシ樹脂系のものが使用される。 Note in the above, lower wiring board 11, an intermediate wiring board 21, it is generally used those made of epoxy resin in the upper layer wiring board 31, also the adhesive for a semiconductor device in the case (or adhesive film) 13 Epoxy those of the resin system is used.

【0004】そのほか、特開平11−45955号公報には、図10に示すように、絶縁層201、207、2 [0004] In addition, Japanese Patent Laid-Open No. 11-45955, as shown in FIG. 10, the insulating layer 201,207,2
08からなり、配線回路層204、ビアホール導体20 It made 08, the wiring circuit layer 204, the via-hole conductors 20
9を備えた絶縁基板213の内部に空隙部203を形成させて半導体素子等の電気素子205を実装収納した素子内蔵多層配線基板200が開示されている。 Element built multilayer wiring board 200 that implements accommodating the electric element 205 such as a semiconductor device to form a gap portion 203 is disclosed in the insulating substrate 213 having a nine. また、特開平9−199856号公報には、図10に示すように、ベースとなる配線板301、接着シート304、半導体素子搭載のための空所303を有するプリント配線板302、および2枚の熱可塑性樹脂フィルム305、 JP-A-9-199856, as shown in FIG. 10, the wiring board 301 as a base, the adhesive sheet 304, the printed wiring board 302 having a cavity 303 for a semiconductor element mounting and two thermoplastic resin film 305,
305の間にプリプレグ306を配したクッション材3 305 cushion material 3 which arranged prepregs 306 between
07を重ねて、加熱・加圧することにより、空所303 And piled up 07, by applying heat and pressure, the cavity 303
にも加圧力が均等に伝えられ、空所303内に樹脂が流出することを防止した半導体素子搭載用キャビティ付きプリント配線板300が開示されている。 Also transmitted evenly applied pressure, the element mounting cavity with a printed circuit board 300 which prevents the resin from flowing out is disclosed in the cavity 303.

【0005】 [0005]

【発明が解決しようとする課題】本来、半導体素子はシリコン等の無機物を原材料とするものであり、配線基板は一般的には熱膨張係数の大きい高分子材料が使用されることから、熱膨張係数を近付けるために、配線基板には無機物、例えばガラス材料が大量に配合されたものとなっている。 [SUMMARY OF THE INVENTION Originally, the semiconductor device is for the raw material inorganic substances such as silicon, a wiring board that is generally used high polymer material of the thermal expansion coefficient, thermal expansion to approximate the coefficient, the wiring board has a one inorganic, for example a glass material is blended in large quantities. 一方、半導体素子の電極端子を配線基板の配線パターンに接続するための半導体素子用接着材は導電性を配慮して異方性導電粒子または等方性導電粒子を配合したものとなっている。 On the other hand, the adhesive for a semiconductor device for connecting the electrode terminals of the semiconductor element to the wiring pattern of the wiring board is made to those formulated anisotropic conductive particles or isotropic conductive particles in consideration of conductivity. 従って、配線基板の主材料と半導体素子用接着材の主材料とが同一(例えばエポキシ樹脂)であっても、図8、図9に示した従来例の半導体素子内蔵多層配線基板100は、下層配線基板11と半導体素子16を下層配線基板11に接続する接着材1 Therefore, even with the main material of the main material of the wiring substrate and the semiconductor element adhesive material is the same (e.g., epoxy resin), 8, conventional semiconductor devices built multilayer wiring board 100 of the shown in FIG. 9, the lower layer adhesive 1 for connecting the wiring board 11 and the semiconductor element 16 to the lower layer wiring board 11
9とでは、熱膨張系数、弾性率、吸水率等が異なることから、半導体素子内蔵多層配線基板100の製造中や、 In the 9, thermal expansion Coefficient, elastic modulus, the water absorption and the like are different, and in the production of semiconductor elements built multilayer wiring board 100,
ユーザーでの使用中の熱ストレス、機械的ストレスによって配線基板に「そり」を生ずると、例えば5μm程度の「そり」であっても接続部分がオープンしたりする。 Heat stress during use of the user, the result in "warp" the wiring substrate by mechanical stress, for example, connect a "sled" portion of about 5μm or open.
そのほか半導体素子16の外周部に配線基板や接着材からのアウトガスが溜まり易い上、繰り返しの応力によってクラックを発生し易い、空間内に結露を生じ易い等の問題があり、長期間の使用によってトラブルを発生する場合がある。 On easily outgas accumulate from outer peripheral portions on the wiring substrate and the adhesive of the other semiconductor element 16, tends to generate cracks by stress of repeated, there is a problem of easily such formation of the condensate into the space, the trouble by prolonged use there is a case that generates. そして、上記の半導体素子用接着材はその導電性の故に高価でもある。 The adhesive for the semiconductor device is also expensive because of its conductivity.

【0006】また、特開平11−45955号公報の素子内蔵多層配線基板200、特開平9−199856号公報の半導体素子搭載用キャビティ付きプリント配線板300はそれぞれ半導体素子の周囲に空隙部203または空所303を有しているものであり、それらの空隙部203または空所303は周囲の絶縁基板213またはプリント配板線302と異なった部分であるから、半導体素子の周囲が密封されている場合には上記のようなストレスを発生させる。 Further, JP-device built-in multilayer wiring board 200 of 11-45955, JP-gap portion 203 or empty around each Japanese Unexamined 9-199856 Patent element mounting cavity with the printed wiring board 300 of the Japanese semiconductor element it is intended to have a place 303, because their air gap 203 or space 303 which is a different part surrounding insulating substrate 213 or the printed wiring board line 302, if the periphery of the semiconductor element is sealed to generate a stress, such as described above.

【0007】本発明は上述の問題に鑑みてなされ、半導体素子の内蔵に際して、配線基板と半導体素子との接着に物性値の異なるものが使用されることによって発生するストレスや、半導体素子の周囲に空隙が存在することにより発生するストレスを可及的に抑制した低コストの半導体素子内蔵多層配線基板と半導体素子内蔵装置、およびそれらの製造方法を提供することを課題とする。 [0007] The present invention has been made in view of the above problem, when the built-in semiconductor devices, stress and generated by different physical properties value is used for bonding the wiring substrate and the semiconductor element, the periphery of the semiconductor element gap semiconductor element built multilayer wiring board and the semiconductor element-containing apparatus of suppressed as much as possible the cost of the stress generated by the presence, and an object of the present invention to provide a process for their preparation.

【0008】 [0008]

【課題を解決するための手段】上記の課題は請求項1と請求項5、または請求項4と請求項8の構成によって解決されるが、それらの解決手段を説明すれば次の如くである。 While the above problems BRIEF SUMMARY OF THE INVENTION can be solved in claim 1 and claim 5 or claim 4, the configuration of claim 8, is as follows if explain their solutions .

【0009】請求項1の半導体素子内蔵多層配線基板は、熱硬化性樹脂からなる積層された複数の配線基板と、配線基板の表面および内部に形成された配線パターンと、配線パターン間のビアホール接続部を備え、内部に半導体素子が実装された半導体素子内蔵多層配線基板において、配線基板の積層に使用される配線基板とほぼ同一組成のプリプレグが、加熱・加圧下における雰囲気の減圧によって、半導体素子の周囲に形成されている空間に充填され硬化されている配線基板である。 [0009] Semiconductor devices built multilayer wiring board according to claim 1, a plurality of wiring boards stacked made of a thermosetting resin, and a wiring pattern formed on the surface and inside of the wiring board, via-hole connection between the wiring patterns comprising a part, in the semiconductor device built multilayer wiring board in which a semiconductor element is mounted inside, a prepreg having substantially the same composition as the wiring substrate used in the lamination of the wiring substrate, the reduced pressure atmosphere in the heating and pressure, the semiconductor element it is filled in the space formed around the a wiring substrate that has been cured. このような半導体素子内蔵多層配線基板は、内蔵の半導体素子の周囲に空間が存在しないことから、空間の存在によって発生するストレスとは無縁であり、長期間の使用によってもトラブルを生ずることのない安定な半導体素子内蔵多層配線基板を提供する。 Such semiconductor devices built multilayer wiring board, since the space around the internal of the semiconductor device is not present, is free from stress generated by the presence of the space, no causing trouble by prolonged use to provide a stable semiconductor device built multilayer wiring board.

【0010】請求項1に従属する請求項2の半導体素子内蔵多層配線基板は、半導体素子の電極端子が配線基板に適用された配線基板とほぼ同一組成のプリプレグを貫通して配線パターン上の接続部と接続された後、加熱・ [0010] Semiconductor devices built multilayer wiring board of claim 2 dependent on claim 1, the connection on the wiring pattern through the prepreg having substantially the same composition as the wiring board on which the electrode terminals of the semiconductor element is applied to the wiring substrate after being connected to the part, heating and
加圧されプリプレグが硬化されて半導体素子が実装されている配線基板である。 Pressurized prepreg is cured semiconductor element is a wiring board is mounted. このような配線基板は、配線基板と半導体素子とが配線基板とほぼ同一組成のプリプレグを接着材として適用されているので、下層配線基板と接着材との物性値の差に基づくようなトラブルは発生しない。 Such wiring board, since the wiring board and the semiconductor element is applied to a prepreg having substantially the same composition as the wiring substrate as an adhesive, the trouble such as those based on the difference in physical properties between the underlying wiring board and the adhesive material It does not occur. また、高価な導電性の半導体素子用接着材が使用されていないので低コストである。 Further, it is inexpensive because expensive conductive semiconductor element adhesive material is not used.

【0011】請求項1に従属する請求項3の半導体素子内蔵多層配線基板は、半導体素子の電極端子が配線基板の配線パターン上の接続部に適用された異方性または等方性導電粒子を含有する半導体素子用接着材を貫通して配線パターン上の接続部と接続された後、加熱・加圧され半導体素子用接着材が硬化されて半導体素子が実装されている配線基板である。 [0011] Semiconductor devices built multilayer wiring board according to claim 3 dependent on claim 1, the applied anisotropic or isotropic conductive particles in the connection portion of the wiring pattern of the electrode terminal wiring substrate of a semiconductor device after being connected to the connection portion of the wiring pattern through an adhesive for a semiconductor device containing, adhesive for a semiconductor device is heated and pressurized is wiring board is cured semiconductor element is mounted. このような配線基板は半導体素子用接着材の使用が半導体素子の電極端子の周囲のみに限られているので、半導体素子用接着材と下層配線基板との物性値に差があっても大きいトラブルには結びつかない。 The use of such a wiring board adhesive for semiconductor devices is limited only around the electrode terminals of the semiconductor device, large trouble even if there is a difference in physical properties between the adhesive material and the lower layer wiring substrate for a semiconductor element not lead to.

【0012】請求項4の半導体素子内蔵装置は、熱硬化性樹脂からなる積層された複数の配線基板と、配線基板の表面および内部に形成された配線パターンと、配線パターン間のビアホール接続部を備え、内部に半導体素子が実装された半導体素子内蔵多層配線基板に電子部品が実装された半導体素子内蔵装置において、配線基板の積層に使用される配線基板とほぼ同一組成のプリプレグが、加熱・加圧下における雰囲気の減圧によって、半導体素子の周囲に形成されている空間に充填され硬化されて形成される半導体素子内蔵多層配線基板の外面に電子部品が実装された装置である。 [0012] The semiconductor element-containing apparatus according to claim 4, a plurality of wiring boards stacked made of a thermosetting resin, and a wiring pattern formed on the surface and inside of the wiring board, the via-hole connection portion between the wiring patterns comprising, in a semiconductor device containing apparatus in which electronic components are mounted on the semiconductor device built multilayer wiring board in which a semiconductor element is mounted inside, a prepreg having substantially the same composition as the wiring substrate used in the lamination of the wiring board, heat and pressure the atmosphere in the pressure vacuum is a device on which the electronic components are mounted on the outer surface of the semiconductor device built multilayer wiring board is formed by being filled cured in a space which is formed around the semiconductor element. このような半導体素子内蔵装置は、半導体素子の周囲に空間が存在しないことから、空間の存在によって発生するストレスとは無縁であり、長期間の使用によってもトラブルを発生しない。 Such semiconductor element-containing apparatus, since there is no space around the semiconductor element is free from stress generated by the presence of space, does not generate trouble by prolonged use.

【0013】請求項5の半導体素子内蔵多層配線基板の製造方法は、熱硬化性樹脂からなる積層された複数の配線基板と、配線基板の表面および内部に形成された配線パターンと、配線パターン間のビアホール接続部を備え、内部に半導体素子が実装された半導体素子内蔵多層配線基板の製造方法において、下層配線基板の上面に半導体素子を実装する工程と、半導体素子に対応する部分をくり抜いた中間配線基板の少なくとも下面に配線基板とほぼ同一組成のプリプレグを適用して下層配線基板に重ね合わせる工程と、上層配線基板の下面に同様にプリプレグを適用して中間配線基板に重ね合わせる工程と、 [0013] manufacturing process of the semiconductor device built multilayer wiring board according to claim 5, a plurality of wiring boards stacked a thermosetting resin, a wiring patterns formed on the surface and inside of the wiring substrate, between the wiring patterns comprising a via hole connecting portion, an intermediate for the manufacturing method of the semiconductor device built multilayer wiring board in which a semiconductor element is mounted inside, hollowed a step of mounting the semiconductor element on the upper surface of the lower layer wiring substrate, a portion corresponding to the semiconductor element a step of superimposing the lower layer wiring board by applying a prepreg having substantially the same composition as at least a lower surface in the wiring substrate of the wiring substrate, a step of superposing the intermediate wiring board by applying the same manner prepreg on the lower surface of the upper layer wiring substrate,
加熱・加圧下に雰囲気を減圧して下層配線基板と中間配線基板と上層配線を積層すると共に半導体素子の周囲に形成されている空間にプリプレグを充填させて硬化させる工程と、からなる製造方法である。 And curing by prepreg is filled in the space which is formed around the semiconductor element with in the atmosphere in the heating-pressure and vacuum laminating lower layer wiring board and the intermediate circuit board and the upper wiring, the manufacturing process comprising is there. このような半導体素子内蔵多層配線基板の製造方法は、得られる半導体素子内蔵配線基板の半導体素子の周囲に空間が存在しないことから、空間の存在によって発生するストレスとは無縁であり、長期間の使用によってもトラブルを生ずることのない安定な半導体素子内蔵多層配線基板を提供する。 Method of manufacturing such a semiconductor device built multilayer wiring board, since there is no space around the semiconductor element of the semiconductor device built-in wiring board obtained is free from stress generated by the presence of spaces, the long-term also it provides no stable semiconductor element built multilayer wiring substrate may arise problems by the use.

【0014】請求項5に従属する請求項6の半導体素子内蔵多層配線基板の製造方法は、下層配線基板に半導体素子を実装する工程が、下層配線基板の上面にプリプレグを適用し、プリプレグを貫通して半導体素子の電極端子を配線パターン上の接続部と接続させた後、加熱・加圧してプリプレグを硬化させる工程とされている製造方法である。 [0014] The method of manufacturing a semiconductor device built multilayer wiring board according to claim 6 dependent on claim 5, the step of mounting a semiconductor element on the lower layer wiring board, applying a prepreg on the upper surface of the lower layer wiring board, through prepreg after the electrode terminals of the semiconductor element was connected to the connection portion of the wiring pattern by a manufacturing method of heating and pressurizing is a step of curing the prepreg. このような製造方法は、配線基板とほぼ同一組成のプリプレグを接着材として適用して硬化させるので、下層配線基板と接着材との物性値の差に基づくようなトラブルは発生しない。 This manufacturing method, since cured by applying a prepreg having substantially the same composition as the wiring substrate as an adhesive, problems such as those based on differences in physical properties of the lower layer wiring board and the adhesive material does not occur. また、高価な導電性の半導体素子用接着材を使用しないので低コスト化し得る。 Also be lower cost because it does not use expensive conducting semiconductor element adhesive material.

【0015】請求項5に従属する請求項7の半導体素子内蔵多層配線基板の製造方法は、下層配線基板に半導体素子を実装する工程が、配線パターン上の接続部に異方性または等方性導電粒子を含有する半導体素子用接着材を適用し、半導体素子の電極端子が半導体素子用接着材を貫通して配線パターン上の接続部と接続させた後、加熱・加圧して半導体素子用接着材を硬化させる工程とされている製造方法である。 [0015] The method of manufacturing a semiconductor device built multilayer wiring board according to claim 7 dependent on claim 5, the step of mounting a semiconductor element on the lower layer wiring board, anisotropic or isotropic in connections on the wiring pattern applying the adhesive for a semiconductor device containing a conductive particle, after the electrode terminals of the semiconductor element through the bonding material for a semiconductor element is connected to the connecting portion of the wiring pattern, heat-pressurizing the adhesive for a semiconductor device it is a manufacturing method which is a curing the wood. このような製造方法は、半導体素子用接着材の使用が半導体素子の電極端子の周囲のみに限られるので、半導体素子用接着材と下層配線基板との物性値に差があっても大きいトラブルには結びつかない。 This manufacturing method, since the use of the adhesive for a semiconductor device is limited only around the electrode terminals of the semiconductor element, the greater the trouble even if there is a difference in physical properties between the adhesive material and the lower layer wiring substrate for a semiconductor element not lead is.

【0016】請求項8の半導体素子内蔵装置の製造方法は、熱硬化性樹脂からなる積層された複数の配線基板と、配線基板の表面および内部に形成された配線パターンと、配線パターン間のビアホール接続部を備え、内部に半導体素子が実装された半導体素子内蔵多層配線基板に電子部品が実装されてなる半導体素子内蔵装置の製造方法において、下層配線基板の上面に半導体素子を実装する工程と、半導体素子に対応する部分をくり抜いた中間配線基板の少なくとも下面に下層配線基板とほぼ同一組成のプリプレグを適用して下層配線基板に重ね合わせる工程と、上層配線基板の下面に同様にプリプレグを適用して中間配線基板に重ね合わせる工程と、加熱・加圧下に雰囲気を減圧して、下層配線基板と中間配線基板と上層配線基板を接着 The method of manufacturing a semiconductor device containing apparatus according to claim 8, a plurality of wiring boards stacked made of a thermosetting resin, and a wiring pattern formed on the surface and inside of the wiring board, via holes between wiring patterns includes a connection portion, in the manufacturing method of the semiconductor device built-device electronic component to the semiconductor device built multilayer wiring board in which a semiconductor element is mounted inside, which are mounted, a step of mounting a semiconductor element on the upper surface of the lower wiring board, a step of superimposing the lower layer wiring board by applying a prepreg having substantially the same composition as the lower layer wiring substrate on at least the lower surface of the intermediate wiring board hollowed out portion corresponding to the semiconductor element, similarly applies the prepreg on the lower surface of the upper wiring board bonding a step of superimposing the intermediate wiring board, by reducing the pressure of an ambient in heating and under pressure, the lower wiring board and the intermediate circuit board and the upper wiring board Te せて積層すると共に、半導体素子の周囲に形成されている空間にプリプレグを充填させて硬化させる工程と、形成される半導体素子内蔵多層配線基板の外面に電子部品を実装する工程と、からなるからなる製造方法である。 With allowed laminating, and curing by filling the prepreg space formed around the semiconductor element, a step of mounting an electronic component on the outer surface of the semiconductor device built multilayer wiring board is formed, because consists is a manufacturing method to be. このような半導体素子内蔵装置の製造方法は、半導体素子の周囲に空間が存在しないことから、空間の存在によって発生するストレスとは無縁であり、長期間の使用によってもトラブルを生ずることのない安定な半導体素子内蔵装置を提供する。 Method of manufacturing such a semiconductor device containing apparatus, since there is no space around the semiconductor element is free from stress generated by the presence of space, stable without causing trouble even by long-term use providing a semiconductor element-containing apparatus.

【0017】 [0017]

【発明の実施の形態】本発明の半導体素子内蔵多層配線基板は、上述したように、配線基板とほぼ同一組成のプリプレグが、加熱・加圧下における雰囲気の減圧によって、配線基板を積層すると共に、半導体素子の周囲に形成されている空間に充填され硬化されることにより製造され、本発明の半導体素子内蔵装置は上記のような半導体素子内蔵多層配線基板の外表面に電子部品を実装することによって製造される。 The semiconductor device built multilayer wiring board of the embodiment of the present invention, as described above, with a prepreg having substantially the same composition as wiring board, by vacuum atmosphere in the heating-pressure to the laminated wiring board, produced by that be filled and cured in the space formed in the periphery of the semiconductor element, a semiconductor element built according to the present invention by implementing the electronic component on the outer surface of the semiconductor device built multilayer wiring board as described above It is produced.

【0018】使用される配線基板の積層、および積層時における半導体素子周囲の空間の充填を考慮して、配線基板は熱硬化性合成樹脂を主体とし、その熱膨張係数を可及的に半導体素子の熱膨張係数に近づけるべく無機物を配合したものが使用される。 The multilayer wiring substrate used, and taking into account the filling of the space around the semiconductor element when stacked, the wiring substrate is mainly composed of a thermosetting synthetic resin, the semiconductor element and the thermal expansion coefficient as much as possible those obtained by blending an inorganic material to approximate the thermal expansion coefficient is used. 熱硬化性合成樹脂としては広く使用されているエポキシ樹脂のほか、ポリイミド樹脂、フェノール樹脂、不飽和ポリエステル樹脂等が使用される。 In addition to an epoxy resin widely used as a thermosetting synthetic resins, polyimide resin, phenol resin, unsaturated polyester resin or the like is used. また、配合される無機物としてはガラス繊維がチョップ、マット、またはクロスとして使用されるが、ガラス以外の無機物繊維を使用してもよい。 Also, chopped glass fibers as the inorganic material to be blended, a mat, or are used as a cross, may be used inorganic fibers other than glass. また、 Also,
熱硬化性合成樹脂にガラス繊維を配合したものを使用する場合、その配合比は容積比で示して熱硬化性合成樹脂30〜50%、ガラス繊維70〜50%の組成比とされる。 When using a material obtained by blending a glass fiber thermosetting synthetic resin, its blending ratio is 30-50% thermosetting synthetic resin shown in volume ratio, are glass fibers 70-50 percent of the composition ratio. 勿論、これ以外の組成比の採用を妨げるものではない。 Of course, it does not preclude the adoption of other composition ratio.

【0019】内蔵させる半導体素子にはベアのものを使用するが、このベアの半導体素子を配線基板に接着させる一つの方法として、本発明は接着材に配線基板とほぼ同一組成のプリプレグを使用する。 [0019] The semiconductor device to be built is to use a bare, as a method for bonding a semiconductor device of the bare wiring board, the present invention uses a prepreg having substantially the same composition as the wiring board in the adhesive . すなわち、配線基板がエポキシ樹脂である場合には、接着材には配線基板とほぼ同一の組成を有する未硬化エポキシ樹脂とガラス繊維の配合物であるプリプレグが使用される。 That is, when the wiring substrate is an epoxy resin, the prepreg in the adhesive is a blend of uncured epoxy resin and glass fibers having a substantially same composition as the wiring substrate is used. プリプレグを配線基板に適用するには塗布してもよく、ディスペンサで供給してもよく、適用方法は特に限定されない。 To apply the prepreg to the wiring board may be applied may be supplied by dispenser application method is not particularly limited. そして、半導体素子の電極端子(例えばバンプ)をあてがい貫通させて配線基板の配線パターンの接続部(例えばパッド)と接続する。 Then, to connect the connection portion of the wiring pattern through the so wiring substrate Ategai the electrode terminals of the semiconductor element (e.g., bumps) (for example a pad).

【0020】プリプレグ中の未硬化のエポキシ樹脂を加熱し硬化させ接着させる加熱温度は150〜250℃の間であり、通常的には180〜210℃とされる。 The heating temperature for bonding an uncured epoxy resin heated and cured in the prepreg is between 150 to 250 ° C., usually, as are 180-210 ° C.. その時の加熱時間は10秒から5分の間であり、通常的には30〜60秒が採用される。 Heating time at that time is between 5 minutes and 10 seconds, usually, it employed 30 to 60 seconds. また加圧力は半導体素子に設けられる電極端子の個数によって異り、例えばバンプ1個当り0.3〜0.6ニュートン(N)の力が加えられる。 The applied pressure Ili by the number of electrode terminals provided on the semiconductor element, for example a force of bumps per 0.3-0.6 Newtons (N) are added. 従って、例えば10mm角の半導体素子に200 Thus, for example, a semiconductor device of 10mm square 200
個のバンプが設けられている場合、ほぼ60〜120N If the number of the bumps are provided, almost 60~120N
の力が加えられる。 The power of is added. この力の大きさは、接着操作が完了した後に半導体素子と配線基板との間隔が10μm以上、好ましくは20μm程度を確保されているかどうかの確認によって決定され、最低限の力の大きさは半導体素子と配線基板との間の電気的な導通の有無の確認によって設定される。 The magnitude of this force, the interval between the semiconductor element after the bonding operation is complete and the wiring substrate is 10μm or more, preferably is determined by the confirmation of whether it is ensured about 20 [mu] m, the size of the minimum force semiconductor It is set by the confirmation of the presence or absence of electrical conduction between the element and the wiring board. そして、接着材に使用したプリプレグは加熱・加圧され硬化されて配線基板と一体化されるので、当然のことながら、物性値の異なるものが共存する場合のようなトラブルを発生しない。 Since the prepreg used in the adhesive is heated and pressed integrated with cured wiring board, of course, it does not generate troubles such as the case of coexisting different ones of physical properties.

【0021】半導体素子を配線基板に接着させる本発明の他の方法は、半導体素子の電極端子の周囲のみに限って導電性を配慮した半導体素子用接着材を使用する方法である。 [0021] Other methods of the present invention to bond a semiconductor element on the wiring substrate is a method of using an adhesive for a semiconductor device in consideration of the conductivity only only around the electrode terminals of the semiconductor element. 例えば配線基板の配線パターン上の接続部にのみ半導体素子用接着材を適用し、その上へ半導体素子の電極端子をあてがい貫通させて配線パターンの接続部に接続させた後、加熱・加圧して半導体素子用接着材を硬化させる。 For example by applying the adhesive for a semiconductor device only the connections on the wiring pattern of the wiring substrate, after being connected to the connecting portion of the wiring pattern on Ategai passed through the electrode terminals of the semiconductor element to the heating-pressurizing It is curing the adhesive material for a semiconductor device. このようにして半導体素子用接着材の使用量を少量に抑える。 Thus suppressed to a small amount the amount of adhesive for semiconductor element. 半導体素子はその後に周囲を配線基板とほぼ同一組成のプリプレグで充填されて硬化されることにより、使用した半導体素子用接着材と配線基板との物性値が異なることの影響は殆ど現れなくなる。 By the semiconductor device is to be cured by subsequent filling in the prepreg having substantially the same composition around the wiring board, the influence of the physical properties are different between the adhesive and the wiring substrate for a semiconductor device used was hardly appear.

【0022】半導体素子が接着された下層配線基板の上へ、半導体素子に対応する部分をくり抜いた中間配線基板を重ね、更にその上へ上層配線基板を重ねて積層し、 [0022] onto the lower layer wiring board in which a semiconductor element is bonded, superimposed intermediate wiring board hollowed out portion corresponding to the semiconductor element, and further laminating overlapping the upper layer wiring board to thereon
半導体素子を内蔵させるが、積層用の接着材としても配線基板とほぼ同一組成のプリプレグを使用する。 Although to incorporate the semiconductor elements, also uses a prepreg having substantially the same composition as the wiring substrate as an adhesive for lamination. プリプレグは中間配線基板、上層配線基板それぞれの下面側に適用されるが、中間配線基板については上下の両面に適用してもよく、プリプレグを適用する面は任意に選択し得る。 The prepreg intermediate wiring board, but is applied to the lower surface side of each upper-layer wiring board, for intermediate wiring board may be applied to both surfaces of the upper and lower surfaces of applying a prepreg may be selected arbitrarily.

【0023】半導体素子を内蔵し、プリプレグを介して重ね合わされた下層配線基板、中間配線基板、上層配線基板の加熱・加圧は真空ポンプで減圧することができ、 The built-in semiconductor element, the lower layer wiring board superimposed over the prepreg, intermediate wiring board, the heat and pressure of the upper layer wiring board can be reduced in pressure by the vacuum pump,
かつ加熱・加圧の可能な真空処理容器内で行われる。 And carried out in a vacuum processing container capable of heating and pressing. すなわち加熱・加圧によって下層配線基板、中間配線基板、上層配線基板を積層させると同時に、積層用のプリプレグを半導体素子の周囲に空間を残さないように充填して硬化させるためである。 That lower layer wiring board by heating and pressurizing, the intermediate wiring board, simultaneously with the laminated upper layer wiring board, in order to cure and filled so as not to leave space prepreg laminate around the semiconductor element. 減圧時の真空度は0.1〜 The degree of vacuum during the decompression is 0.1
1パスカル(Pa)とする。 1 and Pascal (Pa). このようにして得られる半導体素子内蔵配線基板は丁度ベアの半導体素子が配線基板でパッケージされた形態となる。 Such semiconductor device built-in wiring board thus obtained is a just form a bare semiconductor device is packaged in the wiring board.

【0024】上記のようにして形成される半導体素子内蔵多層配線基板の外表面に形成されている配線パターンにコンデンサ素子、抵抗素子、フィルター素子、発振素子、その他、各種の電子部品を表面実装することによって、各種の機能を備えた小容積で、長期間をトラブルなく作動する半導体素子内蔵装置を製造することができる。 [0024] The way the semiconductor devices built multilayer interconnection capacitor element to a wiring pattern formed on an outer surface of a substrate to be formed, the resistance element, filter element, oscillator, other surfaces mounted various electronic parts it allows a small volume with various functions, we are possible to manufacture the semiconductor device built-device operating without trouble for a long time.

【0025】 [0025]

【実施例】次に、本発明の半導体素子内蔵多層配線基板、半導体素子内蔵装置、およびこれらの製造方法を実施例によって図面を参照して具体的に説明する。 EXAMPLES Next, the semiconductor device built multilayer wiring board of the present invention, a semiconductor element-containing apparatus, and will be specifically described with reference to examples drawings these manufacturing methods.

【0026】(実施例1)図1、図2は実施例1による半導体素子内臓多層配線基板10の製造方法を示す図である。 [0026] (Embodiment 1) FIG. 1, FIG. 2 is a diagram showing a method of manufacturing a semiconductor device visceral multilayer wiring board 10 according to Example 1. 図1に示す下層配線基板11、中間配線基板2 Lower wiring board 11 shown in FIG. 1, the intermediate wiring board 2
1、上層配線基板31はそれぞれ複数枚の積層からなる160mm×160mサイズの配線基板であり、表面と内部に銅箔をエッチングして形成された配線パターンp、および配線パターンp間を接続するビアホール接続部vが予め形成されたものである。 1, each of the upper wiring board 31 is a wiring board of 160 mm × 160 m size made from a plurality of stacked, a via hole for connecting the surface and the inside is formed a copper foil is etched into a wiring pattern p, and between the wiring patterns p in which connection part v is preformed. なお、図1、図2 Incidentally, FIG. 1, FIG. 2
(以降も同様である)においては内部を説明するために厚さを拡大して示しており、厚さの実寸は積層された時点で約1mmである。 In (hereinafter versa) shows an enlarged thickness to illustrate the interior, the actual size of the thickness is about 1mm when it is stacked. また、中間配線基板21には内蔵させるベアの半導体素子16に対応する部分をくり抜いた貫通穴hが形成されている。 The through hole h is formed with hollowed portions corresponding to the semiconductor device 16 of the bare to be incorporated in the intermediate circuit board 21. なお、これら下層配線基板11、中間配線基板21、上層配線基板31の上、 It should be noted that these lower-layer wiring substrate 11, an intermediate wiring board 21, on the upper wiring board 31,
中、下は積層時における相対的な位置関係であり、特別な意味はない。 Among the lower is the relative positional relationship at the time of lamination, there is no special meaning.

【0027】図1のAに示すように、ガラス繊維を配合し硬化させたエポキシ樹脂からなる下層配線基板11の接着領域に下層配線基板11と同一組成のプリプレグ1 As shown in A of FIG. 1, the prepreg having the same composition and the lower wiring board 11 in the bonding area of ​​the lower layer wiring board 11 made of an epoxy resin cured by blending glass fibers 1
3を適用し、半導体素子16の電極端子(例えばバンプ)17を貫通させて下層配線基板11の配線パターンpの接続部(例えばパッド)12に接続する。 3 was applied, and connected by through electrodes pin (e.g. bumps) 17 of the semiconductor element 16 connecting portion of the wiring pattern p of the lower layer wiring board 11 (e.g., pad) 12. 続いて、 continue,
図1のBに示すように、加熱・加圧してプリプレグ13 As shown in B of FIG. 1, heating and pressurizing the prepreg 13
を硬化させ、半導体素子16を接着させる。 Curing the, adhering a semiconductor element 16. 加熱温度は180〜200℃、時間30〜60秒の条件で行われ、 Heating Temperature is carried out under conditions of 180 to 200 ° C., time 30 to 60 seconds,
加圧は半導体素子16の電極端子17の個数が200である半導体素子16に対して60から120ニュートン(N)の力が加えられる。 Pressurization force 60 from 120 Newton to the semiconductor element 16 the number of the electrode terminals 17 of the semiconductor element 16 is 200 (N) are added.

【0028】次に、図1のCに示すように、半導体素子16に対応する部分をくり抜いた中間配線基板21の下面に同様のプリプレグ13を適用して下層配線基板11 Next, as shown in C of FIG. 1, lower by applying the same prepreg 13 on the lower surface of the intermediate interconnection substrate 21 which hollowed out portion corresponding to the semiconductor element 16 wiring board 11
に重ね合わせ、更に、上層配線基板31の下面に、同様のプリプレグ13を適用して中間配線基板21に重ね合わせる。 Superimposed, further to the lower surface of the upper wiring board 31, superimposed on the intermediate wiring board 21 using an analogous prepregs 13. この時、半導体素子16の周囲には必然的に空間18が形成される。 At this time, inevitably the space 18 is formed around the semiconductor element 16. なお、図1において、硬化前のプリプレグ13は左上方から右下方へのハッチ(斜線)で示し、加熱硬化させたプリプレグ13は右上方から左下方へのハッチで示している。 In FIG. 1, the prepreg 13 before curing shows by hatching from upper left to lower right (oblique lines), the prepreg 13 is heated and cured is indicated by hatching from upper right to lower left.

【0029】そして、図2のAに示すように、下層配線基板11、中間配線基板21、上層配線基板31を重ね合わせたものを真空処理容器41内において、加熱・加圧して雰囲気を減圧することにより、プリプレグ13が硬化されて下層配線基板11、中間配線基板21、上層配線基板31を一体的に積層すると共に、プリプレグ1 [0029] Then, as shown in A of FIG. 2, the lower layer wiring substrate 11, an intermediate wiring board 21, the upper wiring board 31 in the vacuum processing vessel 41 a superposition of, reducing the pressure of an ambient heating and pressurizing by, lower wiring board 11 prepreg 13 is cured, an intermediate wiring board 21, the upper wiring board 31 with laminated integrally, prepreg 1
3は半導体素子16の周囲の空間18に充填されて熱硬化される。 3 is filled in the space 18 surrounding the semiconductor element 16 is thermally cured. この時の加熱・加圧は図1のBの加熱・加圧と同様の条件であり、雰囲気を0.1〜1パスカル(P Heat and pressure at this time was the same condition as the heating and pressing of the B 1, the atmosphere 0.1-1 Pascal (P
a)程度に減圧して行われる。 a) it is carried out under reduced pressure to a degree. なお、以降に述べるエポキシ樹脂系の加熱・加圧ないしは減圧下の加熱・加圧もこれに準ずる。 Also heat and pressure of the heating and pressurizing or vacuum of epoxy resin described later equivalent thereto. その結果、図2のBに示すように、半導体素子16が周囲に空間を残すことなく埋め込まれたサイズ160mm×160m、厚さ約1mmの多層配線基板10が得られる。 As a result, as shown in B of FIG. 2, no embedded size 160 mm × 160 m to the semiconductor device 16 leaves a space around, the multi-layer wiring substrate 10 having a thickness of about 1mm is obtained.

【0030】(実施例2)図3、図4は実施例2による半導体素子内臓多層配線基板10'の製造方法を示す図である。 [0030] (Embodiment 2) FIG. 3, FIG. 4 is a diagram showing a method of manufacturing a semiconductor device visceral multilayer wiring board 10 'according to the second embodiment. 実施例2においては、図3のAに示すように下層配線基板11の配線パターンpを含む接着領域に下層配線基板11と同一組成のプリプレグ13を適用することは実施例1と同様であるが、図3のBに示すように、 In Example 2, but applying the lower layer wiring substrate 11 and the prepreg 13 having the same composition in the adhesive region including the wiring pattern p of the lower layer wiring board 11 as shown in A of FIG. 3 are the same as in Example 1 , as shown in B of FIG. 3,
ベアの半導体素子16の電極端子17を配線パターンp Wire electrode terminals 17 of the bare semiconductor chip 16 patterns p
のパッド12に接続した後、加熱・加圧してプリプレグ13を半硬化させて半導体素子16を仮接着させることが実施例1と異なる。 After connecting to the pad 12, heated and pressed by a semi-cured prepreg 13 thereby provisionally bonding the semiconductor element 16 is different from example 1 in. その後、図3のCに示すように、 Thereafter, as shown in C in FIG. 3,
下層配線基板11にプリプレグ13を介して中間配線基板21を重ね、その上へプリプレグ13を介して上層配線基板31を重ね合わせる。 Superimposed intermediate interconnection substrate 21. on the lower wiring board 11. via a prepreg 13, via prepreg 13 overlapping the upper wiring substrate 31. onto it.

【0031】そして、図4のAに示す真空処理容器41 [0031] Then, vacuum processing chamber 41 shown in A of FIG
内で加熱・加圧し、減圧することにより、半導体素子1 Heat and pressure at the inner and vacuum, the semiconductor element 1
6を仮接着させている半硬化のプリプレグ13、および積層用のプリプレグ13が硬化されて下層配線基板1 6 the semi-cured that is temporarily bonded prepregs 13, and the prepreg 13 for lamination is cured lower wiring board 1
1、中間配線基板21、上層配線基板31が積層されると共に、積層用のプリプレグ13が半導体素子16の周囲の空間18へ充填されて硬化される。 1, the intermediate wiring board 21, the upper wiring board 31 are stacked, the prepreg 13 for lamination is cured is filled into the space 18 surrounding the semiconductor element 16. その後、真空処理容器41から取り出して、図4のBに示すように、半導体素子内蔵多層配線基板10'が得られる。 Then removed from the vacuum processing vessel 41, as shown in B of FIG. 4, the semiconductor device built multilayer wiring board 10 'is obtained.

【0032】実施例2のように、半導体素子16を最初の段階では仮接着だけとする方法は、実施例1のよう硬化させると時間を要するので(実施例1では硬化反応を2回行っている)、製造時間を短縮するためである。 [0032] As in Example 2, the semiconductor element 16 in the first stage process for the temporary adhesion only performs so requires Curing time as (in the first embodiment the curing reaction twice Example 1 It has), in order to shorten the manufacturing time. しかし、使用するプリプレグの種類によっては、仮接着では半導体素子16と下層配線基板11との導通がその後の処理によって失われる場合があるので、実施に当っては細心の配慮を要する。 However, depending on the type of prepreg to be used, since the temporary adhesion in some cases conduction between the semiconductor element 16 and the lower wiring board 11 is lost by subsequent processing, it is the practice requires careful consideration.

【0033】(実施例3)図5、図6は実施例1、実施例2の製造方法とは異なる半導体素子内蔵多層配線基板の製造方法を示す図である。 [0033] (Embodiment 3) FIG. 5, 6 Example 1 is a diagram showing a manufacturing method of the different semiconductor elements built multilayer wiring board and a manufacturing method of Example 2. 実施例1、実施例2においては、プリプレグ13によって下層配線基板11にベアの半導体素子16とを全面で接着させたが、実施例3では半導体素子16の電極端子17部分のみに限定して導電性の半導体素子用接着材19を使用し、下層配線基板11と半導体素子16とを接着させる方法である。 Example 1, in Example 2, although the semiconductor device 16 of the bare the lower wiring board 11 is bonded on the entire surface by a prepreg 13, conductor and limited to the electrode terminal 17 parts of Example 3, the semiconductor device 16 use sexual semiconductor element adhesive material 19, a method of adhering the lower wiring board 11 and the semiconductor device 16.

【0034】図5のAに示すように、半導体素子16を接合すべき下層配線基板11の配線パターンp上の接続部12のみに半導体素子用接着材13を適用し、図5のBに示すように、半導体素子16の電極端子17を半導体素子用接着材19内に埋め込み貫通させて配線パターンp上の接続部12と接触させ、加熱・加圧することにより半導体素子用接着材19を硬化させて半導体素子1 As shown in A of FIG. 5, to apply the semiconductor device for adhesive 13 only to the connecting portion 12 on the wiring pattern p of the lower layer wiring substrate 11 to be bonded to the semiconductor device 16, shown in B of FIG. 5 as described above, the electrode terminals 17 of the semiconductor element 16 by embedding penetrated into the semiconductor element adhesive material 19 is contacted with the connecting portion 12 on the wiring pattern p, to cure the bonding material 19 for a semiconductor device by heating and pressing semiconductor element Te 1
6を接着させる。 6 to adhere. 次に、図5のCに示すように、半導体素子16に対応する部分をくり抜いた中間配線基板21 Next, as shown in C in FIG. 5, middle wiring board 21 having hollowed out portions corresponding to the semiconductor element 16
の下面に配線基板とほぼ同一組成のプリプレグ13を適用して下層配線基板11に重ね合わせ、更に、上層配線基板31の下面に、同様のプリプレグ13を適用して中間配線基板21に重ね合わせる。 Almost not by applying the prepreg 13 having the same composition overlaid on the lower layer wiring substrate 11 and the wiring board to the lower surface of the further, the lower surface of the upper wiring board 31, by applying the same prepreg 13 superimposed on the intermediate wiring board 21. この時、半導体素子1 At this time, the semiconductor element 1
6の周囲には必然的に空間18が形成される。 Around the 6 inevitably space 18 is formed.

【0035】そして、図6のAに示すように、下層配線基板11、中間配線基板21、上層配線基板31を重ね合わせたものを真空処理容器41内に装填して、加熱・ [0035] Then, as shown in A of FIG. 6, the lower layer wiring substrate 11, an intermediate wiring board 21, and loaded into the vacuum processing chamber 41 that superimposed upper wiring board 31, heat and
加圧し雰囲気を減圧にして各配線基板11、21、31 Each wiring board pressurized atmosphere in the vacuum 11, 21 and 31
を積層すると共に、プリプレグ13を空間18内に充填させ硬化させることにより、図6のBに示すように、空間を残すことなく半導体素子16が埋め込まれた半導体素子内蔵多層配線基板10”が得られるが、この過程は実施例1の場合と全く同様である。 With laminating, by curing to fill the prepreg 13 in the space 18, as shown in B of FIG. 6, obtained semiconductor device built multilayer wiring board 10 'on which the semiconductor element 16 is embedded without leaving a space is, this process is the same as that in the first embodiment.

【0036】(実施例4)図7は実施例2で得られた半導体素子内蔵多層配線基板10の外表面の配線パターンp上にコンデンサ素子5、抵抗素子6、フィルタ素子7 [0036] (Embodiment 4) FIG. 7 is a capacitor element 5 on the wiring pattern p of the outer surface of the semiconductor device built multilayer wiring board 10 obtained in Example 2, the resistance element 6, the filter element 7
を通常の表面実装技術によって実装して得られた半導体素子内蔵装置20を示す図である。 The is a diagram illustrating a semiconductor device containing apparatus 20 obtained by implementing by conventional surface mount technology.

【0037】以上、本発明を実施例によって説明したが、勿論、本発明はこれらに限られることなく、本発明の技術的思想に基づいて種々の変形が可能である。 [0037] While the invention has been described by examples, of course, the present invention is not limited thereto, and various modifications are possible within the spirit of the invention.

【0038】例えば本実施例においては、例えば160 [0038] For example, in this embodiment, for example, 160
mm×160mmサイズの平板状の半導体素子内蔵多層配線基板10についての製造ステップを図によって説明したが、実際の工程においては、下層配線基板、中間配線基板、上層配線基板は例えば160mm×160mm Having described the manufacturing steps for the flat plate-shaped semiconductor element built multilayer wiring board 10 of the mm × 160 mm size by figure, in the actual process, the lower layer wiring board, the middle wiring board, the upper layer wiring board, for example 160 mm × 160 mm
サイズの半導体素子内蔵多層配線基板10を複数枚(例えば6〜24枚)取りし得るサイズのシートによって製造してもよい。 A semiconductor element built multilayer wiring board 10 size may be produced by the size of sheets that can take a plurality (e.g., 6 to 24 pieces). また、複数枚取りのシートで加工し、半導体素子を内蔵させるステップにおいて単離するようにしてもよい。 Also, processed in a sheet of a plurality up, it may be isolated in step to incorporate the semiconductor elements.

【0039】また本実施例においては、積層された多層の配線基板内に半導体素子を1個のみ内蔵させる場合を示したが、2個以上の複数の半導体素子を内蔵させるようにしてもよい。 Further in this embodiment, a case where a semiconductor element is built only one in stacked multilayer wiring board, may be allowed to contain two or more of the plurality of semiconductor elements. また半導体素子と他の電子部品を独立して内蔵させるようにしてもよい。 Or it may be caused to built independently semiconductor element and other electronic components. また本実施例においては、下層配線基板、中間配線基板、上層配線基板が重ね合わされ積層される場合において、半導体素子を下層配線基板に接着させる場合を示したが、積層が3層以上である場合には、半導体素子を接着させる配線基板は当然のことながら下層配線基板以外の配線基板であってもよい。 In this embodiment also, the lower layer wiring board, when the intermediate wiring board, the upper wiring board are stacked overlapped, the case of bonding the semiconductor element to the lower layer wiring board, when laminated is 3 or more layers the wiring board to bond the semiconductor element may be a wiring board other than the lower-layer wiring board of course.

【0040】また本実施例においては、下層配線基板、 [0040] In the present embodiment, the lower layer wiring board,
中間配線基板、上層配線基板の銅箔配線パターンについて、対向する配線基板との接着性を向上させるための粗面化は示さなかったが、必要に応じて行われるものとする。 Intermediate wiring board, the copper foil wiring pattern of the upper wiring board, roughening to improve the adhesion between the opposing circuit board showed no shall be performed as necessary. また実施例4においては、半導体素子内蔵多層配線基板の両面に電子部品を実装する場合を示したが、片面のみの実装でもよいことは言うまでもない In the fourth embodiment, although the case of mounting electronic components on both sides of the semiconductor device built multilayer wiring board, it is needless to say that may be an implementation of one side only

【0041】 [0041]

【発明の効果】本発明の半導体素子内蔵多層配線基板と半導体素子内蔵装置、およびそれらの製造方法は以上に説明したような形態で実施され、次に述べるような効果を奏する。 Effect of the Invention Semiconductor devices built multilayer wiring board and the semiconductor element-containing apparatus of the present invention, and methods for their preparation are carried out in the form as described above, it exhibits the following described effects.

【0042】請求項1の半導体素子内蔵多層配線基板によれば、内蔵されている半導体素子の周囲に空間が存在せず、かつ半導体素子は配線基板とほぼ同一組成の材料で囲われているので、半導体素子の周囲に空間が存在することや、異なった物性値を有する材料が共存することによるストレス、例えば曲げ等によって発生する機械的ストレスや、上下する温度によって発生する熱的ストレスとは無縁であり、半導体素子内蔵多層配線基板の製造中およびエンドユ−ザ−での実用中において、上記のようなストレスに起因するトラブルを発生させない。 According to the semiconductor device built multilayer wiring board according to claim 1, there is no space around the semiconductor element is incorporated, and the semiconductor element is surrounded by material having substantially the same composition as the wiring substrate , and that there is a space around the semiconductor element, the stress caused by materials having different physical properties coexist, and mechanical stresses caused by eg bending, etc., free from thermal stress generated by the upper and lower temperature , and the preparation and during Endoyu semiconductor elements built multilayer wiring board - the - in practice in at, not cause problems resulting from stress, such as described above.

【0043】請求項2の半導体素子内蔵多層配線基板によれば、配線基板と半導体素子とが配線基板とほぼ同一組成のプリプレグを接着材として接着されているので、 [0043] According to the semiconductor device built multilayer wiring board according to claim 2, since the wiring board and the semiconductor element are bonded to prepreg having substantially the same composition as the wiring substrate as an adhesive,
接着材と配線基板との間に物性値の差がなく、物性値の差に基づくようなトラブルは発生しない。 Difference in physical properties between the adhesive and the wiring board without, does not occur troubles such as those based on differences in physical properties. また、高価な導電性の半導体素子用接着材が使用されていないので低コストである。 Further, it is inexpensive because expensive conductive semiconductor element adhesive material is not used. 請求項3の半導体素子内蔵多層配線基板によれば、導電性を配慮した半導体素子用接着材が半導体素子の電極端子の周囲のみに限って使用されているので、半導体素子の内蔵が完了した時点で、半導体素子の周囲の殆どは配線基板とほぼ同一組成の熱硬化性樹脂配合物で覆われており、半導体素子用接着材と配線基板との間に物性値の差があっても、それによるトラブルは殆ど発生しない。 Point according to the semiconductor device built-multilayered wiring board according to claim 3, since the adhesive for a semiconductor device in consideration of conductivity is used only only around the electrode terminals of the semiconductor device, the built-in semiconductor element is completed in, most around the semiconductor element is covered with substantially thermosetting resin formulations of the same composition as the wiring board, even if there is difference in physical properties between the adhesive material for a semiconductor element and the wiring substrate, it by trouble it is hardly generated.

【0044】請求項4の半導体素子内蔵装置によれば、 [0044] According to the semiconductor element-containing apparatus according to claim 4,
内蔵されている半導体素子の周囲に空間が存在しないので、空間が存在することによって発生するストレス、例えば曲げ等による機械的ストレスや、上下する温度による熱的ストレスとは無縁である。 Since space around the semiconductor element that is built not present, and the mechanical stress due to stress, for example, bending or the like generated by the presence of space is free from thermal stresses due to vertical temperature.

【0045】請求項5の半導体素子内蔵多層配線基板の製造方法によれば、半導体素子の周囲に空間を残さずに半導体素子を内蔵させることができ、かつ半導体素子を配線基板とほぼ同一組成の材料で囲うことができるので、製造される半導体素子内蔵多層配線基板は、半導体素子の周囲に空間が存在することや異なった物性値を有する材料が共存することによるストレス、例えば曲げ等によって発生する機械的ストレスや、上下する温度によって発生する熱的ストレスとは無縁であり、半導体素子内蔵多層配線基板の製造中およびエンドユ−ザ−での実用中において、上記のようなストレスに起因するトラブルを発生させない。 [0045] According to the manufacturing method of the semiconductor device built multilayer wiring board of claim 5, it is possible to incorporate the semiconductor elements without leaving a space around the semiconductor element, and having substantially the same composition as the wiring substrate a semiconductor element it is possible to enclose in the material, the semiconductor element built multilayer wiring board produced is generated by stress, for example, bending or the like due to the material having the or different physical properties space exists around the semiconductor element coexist and mechanical stress, is free from thermal stress generated by the upper and lower temperature, the semiconductor element built multilayer wiring board manufacturing and in Endoyu - the - in practice in, the trouble caused by stress, such as the It does not occur.

【0046】請求項6の半導体素子内蔵多層配線基板の製造方法によれば、下層配線基板と半導体素子との接着に際し、配線基板とほぼ同一組成のプリプレグを接着材として使用するので、製造される半導体素子内蔵多層配線基板は配線基板と接着材との物性値が同等であり、物性値の差に基づくようなトラブルを発生しない。 [0046] According to the manufacturing method of the semiconductor device built multilayer wiring board according to claim 6, the occasion of adhesion of the lower layer wiring board and the semiconductor element, since the prepreg having substantially the same composition as the wiring board for use as an adhesive, is prepared the semiconductor device built multilayer wiring board is equivalent physical properties values ​​of the wiring board adhesive, they do not generate troubles such as those based on differences in physical properties. また高価な導電性の半導体素子用接着材を使用しないので低コスト化し得る。 Also it may cost does not use expensive conductive semiconductor element adhesive material. 請求項7の半導体素子内蔵多層配線基板の製造方法によれば、下層配線基板と半導体素子との接着に際し、導電性を配慮した半導体素子用接着材を半導体素子の電極端子の周囲のみに限って使用するので、得られる半導体素子内蔵多層配線基板は、半導体素子の周囲の殆どが配線基板とほぼ同一の組成物で覆われており半導体素子用接着材と配線基板との間に物性値の差が多少あっても、それによるトラブルは殆ど発生しない。 According to the manufacturing method of the semiconductor device built multilayer wiring board according to claim 7, when adhesion between the lower wiring board and the semiconductor element, only an adhesive for a semiconductor device in consideration of the conductivity only around the electrode terminals of the semiconductor element since use, the semiconductor device built multilayer wiring substrate obtained, the difference between physical properties between substantially identical composition covered with and an adhesive material for a semiconductor element wiring substrate mostly the wiring board around the semiconductor element but even somewhat, it by the trouble is hardly generated.

【0047】請求項8の半導体素子内蔵装置の製造方法によれば、内蔵され半導体素子の周囲に空間を残さないので、製造される半導体素子内蔵装置は、空間が存在することによって発生するストレス、例えば曲げ等によって発生する機械的ストレスや、上下する温度によって発生する熱的ストレスとは無縁であり、半導体素子内蔵装置の製造中およびエンドユ−ザ−での実用中において、 [0047] According to the manufacturing method of the semiconductor element-containing apparatus of claim 8, since leaving no space around the built-in semiconductor element, the semiconductor element-containing apparatus to be manufactured, the stress generated by the presence of space, for example, mechanical stress caused by bending or the like, is free from thermal stress generated by the upper and lower temperature, during manufacture and Endoyu semiconductor elements built device - in practice in at - the
ストレスに起因するトラブルを発生させない。 It does not cause trouble due to stress.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】図2と共に実施例1の方法による半導体素子内蔵多層配線基板の製造方法のステップを示す断面図であり、Aは半導体素子の接着のためにプリプレグを下層配線基板に適用した状態、Bは半導体素子を所定の位置に接続して加熱・加圧しプリプレグを硬化させた状態、C Figure 1 is a cross sectional view showing a step of the manufacturing method of the semiconductor device built multilayer wiring board according to the method of FIG. 2 with Example 1, the state A is obtained by applying the prepreg the lower wiring board for adhesion of semiconductor elements, B was cured with heating and pressurizing the prepreg by connecting a semiconductor element to a predetermined position state, C
はそれぞれプリプレグを適用した中間配線基板と上層配線基板を重ね合わせる状態を示す。 It shows a state of superimposing the intermediate wiring board and the upper wiring board according to the respective prepregs.

【図2】図1に続くステップを示し、Aは重ね合わせた下層配線基板、中間配線基板、上層配線基板を真空処理容器内で加熱・加圧して雰囲気を減圧させている状態、 Figure 2 shows a step following FIG. 1, A is lower wiring board superimposed, the middle wiring board, and the atmosphere upper wiring board by applying heat and pressure in the vacuum processing vessel is depressurized,
Bは得られた半導体素子内蔵多層配線基板を示す。 B denotes a semiconductor element built multilayer wiring substrate obtained.

【図3】図4と共に実施例2の方法による半導体素子内蔵多層配線基板の製造方法のステップを示す断面図であり、Aは半導体素子の接着のために下層配線基板にプリプレグを適用した状態、Bは半導体素子を所定の位置に接続して半硬化させた状態、Cはそれぞれプリプレグを適用した中間配線基板と上層配線基板を重ね合わせる状態を示す。 3 is a cross-sectional view showing a step of the manufacturing method of the semiconductor device built multilayer wiring board according to the method of Example 2 in conjunction with FIG. 4, state A of applying the prepreg the lower wiring board for adhesion of semiconductor elements, B shows a state in which the superposed state is semi-cured by connecting the semiconductor element to a predetermined position, an intermediate wiring board and the upper wiring board C is according to the prepreg, respectively.

【図4】図3に続くステップを示し、図2と同様、Aは真空処理容器内で加熱・加圧して減圧させている状態、 Figure 4 shows a step following FIG. 3, similar to FIG. 2, A is is vacuum heated and pressed in a vacuum processing chamber state,
Bは得られた半導体素子内蔵多層配線基板を示す。 B denotes a semiconductor element built multilayer wiring substrate obtained.

【図5】図6と共に実施例3の方法による半導体素子内蔵多層配線基板の製造方法のステップを示す断面図であり、Aは半導体素子を接着させるための導電性接着材を下層配線基板の所定の部分にのみ適用した状態、Bは半導体素子を所定の位置に接続して加熱・加圧して導電性接着材を硬化させた状態、Cはそれぞれプリプレグを適用した中間配線基板と上層配線基板を重ね合わせる状態を示す。 [Figure 5] is a sectional view showing a step of the manufacturing method of the semiconductor device built multilayer wiring board according to the method of Example 3 in conjunction with FIG. 6, A is a predetermined lower wiring substrate a conductive adhesive for bonding the semiconductor element state has been applied to parts only, the state B is obtained by curing the conductive adhesive by applying heat and pressure to connect the semiconductor device to a predetermined position, an intermediate wiring board and the upper wiring board C is obtained by respectively applying the prepreg It shows a state in which the superimposed.

【図6】図5に続くステップを示し、図2と同様、Aは真空処理容器内で加熱・加圧して減圧させている状態、 6 shows a step subsequent to FIG. 5, similarly to FIG. 2, A is is vacuum heated and pressed in a vacuum processing chamber condition,
Bは得られた半導体素子内蔵多層配線基板を示す。 B denotes a semiconductor element built multilayer wiring substrate obtained.

【図7】半導体素子内蔵多層配線基板の外表面に電子部品を実装した半導体素子内蔵装置を示す断面図である。 7 is a sectional view showing a semiconductor device containing apparatus mounted with electronic components on the outer surface of the semiconductor element built multilayer wiring board.

【図8】図9と共に従来例の方法による半導体素子内蔵多層配線基板の製造方法のステップを示す断面図であり、Aは半導体素子の接着のために下層配線基板に導電性接着材を適用した状態、Bは半導体素子を所定の位置に接続して加熱・加圧し導電性接着材を硬化させた状態、Cはそれぞれプリプレグを適用した中間配線基板と上層配線基板を重ね合わせる状態を示す。 8 is a sectional view showing the steps of the prior art method of manufacturing a semiconductor device built multilayer wiring board according to along with FIG. 9, A applied the conductive adhesive to the lower layer wiring board for adhesion of the semiconductor element state, B shows a state of superimposing the intermediate wiring board and the upper wiring board to which the cured state a heating and pressurizing the conductive adhesive to connect the semiconductor device to a predetermined position, C is respectively prepreg.

【図9】図8に続くステップを示し、図2と同様、Aは真空処理容器内で加熱・加圧して減圧させている状態、 9 shows a step subsequent to FIG. 8, similarly to FIG. 2, A is is vacuum heated and pressed in a vacuum processing chamber state,
Bは得られた半導体素子内蔵多層配線基板を示す。 B denotes a semiconductor element built multilayer wiring substrate obtained.

【図10】他の従来例による素子内蔵多層配線基板の断面図である。 10 is a cross-sectional view of the head protection multilayer wiring board according to another conventional example.

【図11】もう一つ他の従来例による半導体素子搭載用キャビティ付きプリント基板の断面図である。 11 is a cross-sectional view of a printed circuit board with a semiconductor element-mounting cavity according to another another conventional example.

【符号の説明】 DESCRIPTION OF SYMBOLS

11……下層配線基板、13……プリプレグ、16…… 11 ...... lower wiring board, 13 ...... prepreg 16 ......
半導体素子、17……電極端子、18……空間、19… Semiconductor element, 17 ...... electrode terminal, 18 ...... space, 19 ...
…導電性の半導体素子用接着材、21……中間配線基板、31……上層配線基板、41……真空処理容器。 ... conductive semiconductor element adhesive material, 21 ...... intermediate wiring board, 31 ...... upper wiring board, 41 ...... vacuum processing vessel.

フロントページの続き (51)Int.Cl. 7識別記号 FI テーマコート゛(参考) H05K 3/46 H01L 23/12 N (72)発明者 花井 信洋 岐阜県美濃加茂市本郷町9丁目15番22号 ソニー美濃加茂株式会社内 (72)発明者 村山 敏宏 東京都品川区北品川6丁目7番35号 ソニ ー株式会社内 Fターム(参考) 5E346 AA02 AA04 AA12 AA22 AA43 BB16 CC04 CC08 CC09 CC10 CC12 CC13 CC32 CC42 DD32 EE02 EE06 EE07 EE09 EE18 FF01 GG28 HH11 HH32 5F044 KK07 LL09 RR17 RR18 RR19 Of the front page Continued (51) Int.Cl. 7 identification mark FI theme Court Bu (Reference) H05K 3/46 H01L 23/12 N (72 ) inventor Nobuhiro Hanai Gifu Prefecture Minokamo Hongo-cho, 9-chome 15th No. 22 Sony Minokamo within Co., Ltd. (72) inventor Toshihiro Murayama Shinagawa-ku, Tokyo Kita 6-chome No. 7 No. 35 Sony over Co., Ltd. in the F-term (reference) 5E346 AA02 AA04 AA12 AA22 AA43 BB16 CC04 CC08 CC09 CC10 CC12 CC13 CC32 CC42 DD32 EE02 EE06 EE07 EE09 EE18 FF01 GG28 HH11 HH32 5F044 KK07 LL09 RR17 RR18 RR19

Claims (8)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 熱硬化性樹脂からなる積層された複数の配線基板と、前記配線基板の表面および内部に形成された配線パターンと、前記配線パターン間のビアホール接続部を備え、内部に半導体素子が実装された半導体素子内蔵多層配線基板において、 前記配線基板の積層に使用される前記配線基板とほぼ同一組成のプリプレグが、加熱・加圧下における雰囲気の減圧によって、前記半導体素子の周囲に形成されている空間に充填され硬化されていることを特徴とする半導体素子内蔵多層配線基板。 1. A plurality of wiring substrates laminated made of a thermosetting resin, and a wiring pattern formed on the surface and inside of the wiring substrate includes a via-hole connection portion between the wiring pattern, the semiconductor element therein in the semiconductor device built multilayer wiring board but mounted, the prepreg having substantially the same composition as the wiring substrate that is used in the lamination of the wiring substrate, the reduced pressure atmosphere in the heating and pressure, formed around the semiconductor element the semiconductor device built multilayer wiring board, characterized by being filled and cured in space it is.
  2. 【請求項2】 前記半導体素子の電極端子が前記配線基板に適用された前記プリプレグを貫通して前記配線パターン上の接続部と接続された後、加熱・加圧され前記プリプレグが硬化されて前記半導体素子が実装されていることを特徴とする請求項1に記載の半導体素子内蔵多層配線基板。 After wherein electrode terminals of the semiconductor element is connected to the connection portion on the wiring pattern through the applied the prepreg on the wiring substrate, and cured the prepreg is heated and pressed is the the semiconductor device built multilayer wiring board according to claim 1, characterized in that the semiconductor element is mounted.
  3. 【請求項3】 前記半導体素子の電極端子が前記配線パターン上の接続部に適用された異方性または等方性導電粒子を含有する半導体素子用接着材を貫通して前記配線パターン上の接続部と接続された後、加熱・加圧して前記半導体素子用接着材が硬化されて前記半導体素子が実装されていることを特徴とする請求項1に記載の半導体素子内蔵多層配線基板。 3. A connection on said electrode terminals of the semiconductor element through the bonding material for a semiconductor device containing the applied anisotropic or isotropic conductive particles in the connection portion on the wiring pattern wiring pattern after being connected to the part, the semiconductor device built multilayer wiring board according to claim 1, the adhesive for a semiconductor device heating and pressurizing, characterized in that the said hardened semiconductor devices are mounted.
  4. 【請求項4】 熱硬化性樹脂からなる積層された複数の配線基板と、前記配線基板の表面および内部に形成された配線パターンと、前記配線パターン間のビアホール接続部を備え、内部に半導体素子が実装された半導体素子内蔵多層配線基板に電子部品が実装されてなる半導体素子内蔵装置において、 前記配線基板の積層に使用される前記配線基板とほぼ同一組成のプリプレグが、加熱・加圧下における雰囲気に減圧によって、前記半導体素子の周囲に形成されている空間に充填され硬化されて形成される前記半導体素子内蔵多層配線基板の外表面に電子部品が実装されたものであることを特徴とする半導体素子内蔵装置。 4. A plurality of wiring substrates laminated made of a thermosetting resin, and a wiring pattern formed surface and inside of the wiring substrate includes a via-hole connection portion between the wiring pattern, the semiconductor element therein atmosphere but in the semiconductor device built-device electronic component to the semiconductor device built multilayer wiring board mounted is made by mounting the prepreg having substantially the same composition as the wiring substrate that is used in the lamination of the wiring substrate, the heat-pressure by vacuum, the wherein the one in which the electronic component on the outer surface of the semiconductor device built multilayer wiring board is filled in a space formed around is formed by curing a semiconductor element mounted semiconductor element built-in devices.
  5. 【請求項5】 熱硬化性樹脂からなる積層された複数の配線基板と、前記配線基板の表面および内部に形成された配線パターンと、前記配線パターン間のビアホール接続部を備え、内部に半導体素子が実装された半導体素子内蔵多層配線基板の製造方法において、 下層配線基板の上面に前記半導体素子を実装する工程と、 前記半導体素子に対応する部分をくり抜いた中間配線基板の少なくとも下面に前配線基板とほぼ同一組成のプリプレグを適用して前記下層配線基板に重ね合わせる工程と、 上層配線基板の下面に同様に前記プリプレグを適用して、前記中間配線基板に重ね合わせる工程と、 加熱・加圧下に雰囲気を減圧して、前記下層配線基板と前記中間配線基板と前記上層配線基板を積層すると共に、前記半導体素子の周囲に形成され A plurality of wiring substrate stacked consists 5. thermosetting resin, and a wiring pattern formed surface and inside of the wiring substrate includes a via-hole connection portion between the wiring pattern, the semiconductor element therein in but implemented method of manufacturing a semiconductor device built multilayer wiring board, a step of mounting the semiconductor element on the upper surface of the lower layer wiring board, at least the lower surface prior to the wiring substrate of the intermediate wiring board hollowed out portion corresponding to the semiconductor element When a step of superimposing the lower layer wiring board by applying a prepreg having substantially the same composition, by applying the same manner the prepreg on the lower surface of the upper wiring board, comprising the steps of superimposing on the intermediate wiring board, the heat-pressure by reducing the pressure of an ambient, with laminating the upper layer wiring board and the lower layer wiring board and the intermediate circuit board, formed around the semiconductor element いる空間に前記プリプレグを充填させて硬化させる工程と、からなることを特徴とする半導体内蔵多層配線基板の製造方法。 A step of curing by filling the prepreg in a space are, manufacturing method of the semiconductor-embedded multilayer wiring substrate characterized by comprising the.
  6. 【請求項6】 前記下層配線基板に前記半導体素子を実装する工程が、前記下層配線基板の上面に前記プリプレグを適用し、前記プリプレグを貫通して前記半導体素子の電極端子を前記配線パターン上の接続部と接続させた後、加熱・加圧して前記プリプレグを硬化させる工程であることを特徴とする請求項5に記載の半導体素子内蔵多層配線基板の製造方法。 6. A step of mounting the semiconductor element to the lower layer wiring board, wherein the prepreg is applied to the upper surface of the lower layer wiring board, through said prepreg on the wiring pattern of the electrode terminals of the semiconductor element after connecting the connection portion, the method of manufacturing a semiconductor device built multilayer wiring board according to claim 5, wherein the heating and pressurizing is a step of curing the prepreg.
  7. 【請求項7】 前記下層配線基板に前記半導体素子を実装する工程が、前記配線パターン上の接続部に異方性または等方性導電粒子を含有する半導体素子用接着材を適用し、前記半導体素子の電極端子が前記半導体素子用接着材を貫通して前記配線パターン上の接続部と接続された後、加熱・加圧して前記半導体素子用接着材を硬化させる工程であることを特徴とする請求項5に記載の半導体素子内蔵多層配線基板の製造方法。 7. A step of mounting the semiconductor element on the lower wiring board, and applying the semiconductor element adhesive material containing anisotropic or isotropic conductive particles in the connection portion on the wiring pattern, said semiconductor after the electrode terminals of the elements connected to the connection portion on the wiring pattern through an adhesive for the semiconductor element, wherein the heating and pressurizing is a step of curing the bonding material for the semiconductor element the method of manufacturing a semiconductor device built multilayer wiring board according to claim 5.
  8. 【請求項8】 熱硬化性樹脂からなる積層された複数の配線基板と、前記配線基板の表面および内部に形成された配線パターンと、前記配線パターン間のビアホール接続部を備え、内部に半導体素子が実装された半導体素子内蔵多層配線基板に電子部品が実装されてなる半導体素子内蔵装置の製造方法において、 下層配線基板の上面に前記半導体素子を実装する工程と、 前記半導体素子に対応する部分をくり抜いた中間配線基板の少なくとも下面に前記下層配線基板とほぼ同一組成のプリプレグを適用して、前記下層配線基板に重ね合わせる工程と、 上層配線基板の下面に同様に前記プリプレグを適用して、前記中間配線基板に重ね合わせる工程と、 加熱・加圧下に雰囲気を減圧して、前記下層配線基板と前記中間配線基板と前記上層配線 A plurality of wiring substrate stacked consisting 8. thermosetting resin, and a wiring pattern formed surface and inside of the wiring substrate includes a via-hole connection portion between the wiring pattern, the semiconductor element therein in the method for manufacturing but the semiconductor element-containing apparatus which electronic components in the semiconductor device built multilayer wiring board mounted is implemented, the steps of mounting the semiconductor element on the upper surface of the lower layer wiring board, the portion corresponding to the semiconductor element hollowed was by applying the prepreg having substantially the same composition as the lower layer wiring board at least on the lower surface of the intermediate interconnection substrate, a step of overlaying the lower layer wiring substrate, using an analogous to the prepreg to the lower surface of the upper wiring board, wherein a step of superimposing the intermediate wiring board, and vacuum atmosphere in heating and under pressure, the upper wiring and the lower wiring board and the intermediate circuit board 板とを接着させて積層すると共に、前記半導体素子の周囲に形成されている空間に前記プリプレグを充填させて硬化させる工程と、 形成される半導体素子内蔵多層配線基板の外表面に電子部品を実装する工程とからなることを特徴とする半導体素子内蔵装置の製造方法。 With laminated by bonding the plate, mounting an electronic component on the and curing by filling the prepreg in a space formed around the semiconductor element, the outer surface of the semiconductor device built multilayer wiring substrate formed the method of manufacturing a semiconductor device containing apparatus characterized by comprising the steps of.
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Cited By (23)

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