JP2007294609A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SiP-type (system in package) semiconductor device capable of suppressing noises acting between chips when two or more semiconductor chips are integrated in a stack. <P>SOLUTION: The semiconductor device is packaged including a semiconductor. The device has a configuration in which on a substrate 10, a first semiconductor chip 18 having a first circuit surface with an active element formed thereon is mounted so that the first circuit surface faces the substrate 10, and a second semiconductor chip 20 having a second circuit surface with an active element formed thereon is laminated and mounted on the upper part of the first semiconductor chip 18 so that the second circuit surface faces a side opposite to the substrate 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a SiP (system in package) type semiconductor device incorporating an active element and a passive element and incorporating a matching circuit and a filter, and a manufacturing method thereof.

  The demand for downsizing, thinning, and weight reduction of portable electronic devices such as digital video cameras, digital mobile phones, and notebook personal computers is increasing. While an electronic circuit device in which such a semiconductor device is mounted on a printed wiring board has been realized by 70% reduction year by year, how can the component mounting density on the mounting substrate (printed wiring substrate) be improved? Has been studied and developed as an important issue.

  For example, as a package form of a semiconductor device, a transition from a lead insertion type such as DIP (Dual Inline Package) to a surface mounting type is performed, and furthermore, bumps (projection electrodes) made of solder, gold, or the like are provided on a pad electrode of a semiconductor chip. A flip-chip mounting method has been developed in which a face-down connection is made to the wiring board via bumps.

  Furthermore, development is progressing into a package of a complicated form called SiP that incorporates passive elements such as inductances and capacitors and incorporates a matching circuit and a filter.

  Among the semiconductor devices of the SiP type as described above, for example, a semiconductor device in which two or more chips including active elements such as a digital chip and a digital chip, a digital chip and an analog chip, and an analog chip and an analog chip are integrated is known. For example, Patent Document 1 discloses the configuration of the above-described SiP-type semiconductor device.

  Among the semiconductor devices of the SiP type as described above, a semiconductor device in which two or more chips including active elements such as a digital chip and a digital chip, a digital chip and an analog chip, and an analog chip and an analog chip are integrated is known. Yes.

  For example, in a semiconductor device in which an analog chip and a digital chip are stacked, there is an influence of digital noise particularly from the digital chip to the analog chip. Therefore, the distance between the digital chip and the analog chip needs to be sufficiently long.

In order to reduce the influence of the above-mentioned noise, as described in Patent Document 1, a structure that is laid flat on the same plane is often taken.
However, the structure in which two or more semiconductor chips as described above are laid flat increases the size of the entire semiconductor device, and does not satisfy the demand for miniaturization.

Patent Document 2 describes a semiconductor device in which an analog chip and a digital chip are stacked.
In the case of a stack structure in which two or more semiconductor chips are placed vertically, it is possible to provide a structure that shields noise. For example, a noise shielding sheet may be interposed, but the noise shielding sheet has a thickness. However, it is practically impossible to adopt a stack structure while realizing a reduction in thickness.

  For this reason, analog and digital chips are mounted on both sides of the organic substrate, respectively, but it is necessary to form external electrodes on the substrate through-hole and one side, which increases the overall thickness. Thinning has become difficult.

In the above, a semiconductor device having an analog chip and a digital chip has been particularly described. However, it is desired to reduce the influence of noise between chips even in a combination of a digital chip and a digital chip, or an analog chip and an analog chip. This is a problem when integrating into a stack type.
Japanese Patent Laid-Open No. 5-114693 JP 2003-124236 A

  The problem to be solved is that it is difficult to suppress noise acting between chips when two or more semiconductor chips are integrated into a stack type in a semiconductor device of SiP type.

  The semiconductor device of the present invention is a semiconductor device packaged including a semiconductor, and has a substrate and a first circuit surface on which an active element is formed, so that the first circuit surface faces the substrate side. A first semiconductor chip mounted on the substrate and a second circuit surface on which an active element is formed, and the second circuit surface is located above the first semiconductor chip so that the second circuit surface faces away from the substrate. A second semiconductor chip stacked and mounted.

  The semiconductor device of the present invention is a semiconductor device packaged including a semiconductor, wherein the first semiconductor chip having a first circuit surface on which an active element is formed is provided on the substrate, and the first circuit surface is provided on the substrate. The second semiconductor chip having the second circuit surface on which the active element is formed is mounted above the first semiconductor chip with the second circuit surface facing away from the substrate. Stacked and mounted.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device packaged including a semiconductor, wherein a first semiconductor chip having a first circuit surface on which an active element is formed is provided on a substrate. Mounting the first circuit surface to face the substrate, and stacking the second semiconductor chip on the first semiconductor chip and having a second circuit surface on which an active element is formed. Mounting so that the surface faces away from the substrate.

The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device packaged including a semiconductor, wherein a first semiconductor chip having a first circuit surface on which an active element is formed is formed on a substrate. Mount so that the first circuit surface faces the substrate.
Next, the second semiconductor chip having the second circuit surface on which the active element is formed is mounted so as to be stacked above the first semiconductor chip so that the second circuit surface faces away from the substrate.

  The semiconductor device of the present invention is mounted in a SiP-type semiconductor device such that the first circuit surface of the first semiconductor chip faces the substrate side, while the second circuit surface of the second semiconductor chip faces away from the substrate. Stacked and mounted above the first semiconductor chip so that they face each other, and mounted so that the circuit surfaces of the two semiconductor chips face in different directions. Noise can be suppressed.

  In the semiconductor device manufacturing method of the present invention, in the SiP type semiconductor device, the first circuit surface of the first semiconductor chip is mounted so as to face the substrate side, while the second circuit surface of the second semiconductor chip is mounted on the substrate. Mounted facing the opposite side and mounted so that the circuit surfaces of the two semiconductor chips are in different directions, manufacturing a semiconductor device that can suppress noise acting between the chips even when integrated as a stack type can do.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment.
A base insulating film 11 made of, for example, silicon oxide is formed on the silicon substrate 10, and a substrate electrode E formed by laminating a seed layer 12 made of TiCu, a copper layer 14, and a nickel gold layer 15 is formed thereon with a predetermined electrode. It is formed with a pattern.
For example, a first semiconductor chip 18 having a first circuit surface on which an active element is formed is mounted on the substrate electrode E. In the first semiconductor chip 18, a pad 18b is formed on the first circuit surface of the semiconductor body portion 18a, a region excluding the pad 18b is covered with a protective layer 18c such as silicon oxide, and bumps (projection electrodes) are further formed on the pad 18b. ) 18d is formed, and is mounted face down, that is, with the first circuit surface on which the bump 18d is formed facing the substrate 10 side.

  Further, for example, the conductive post 17 is formed on the substrate electrode E, and is electrically connected to the bump of the first semiconductor chip 18. For example, the height of the conductive post 17 is preferably equal to or higher than the height of the surface of the first semiconductor chip 18.

For example, a first resin layer 19 made of polyimide resin, epoxy resin, acrylic resin, or the like is formed so as to cover the first semiconductor chip 18, the conductive post 17, and the substrate electrode.
For example, the surface of the first resin layer 19 is polished until the upper surface of the conductive post 17 is exposed.

  Further, for example, a second semiconductor chip 20 having a second circuit surface on which an active element is formed is mounted above the first semiconductor chip 18 and above the first resin layer 19. The second semiconductor chip 20 has a configuration in which a pad 20b is formed on the second circuit surface of the semiconductor body portion 20a, and a region excluding the pad 20b is covered with a protective layer 20c such as silicon oxide, and is formed by a die attach film 20e. It is mounted face-up, that is, with the second circuit surface, which is the formation surface of the pad 20b, facing away from the substrate 10.

Further, for example, the second resin layer 21 made of the same polyimide resin as the first resin layer 19 is formed so as to cover the upper surface of the conductive post 17 and the second semiconductor chip 20.
In the second resin layer 21, an opening 21 a reaching the upper surface of the conductive post 17 and the pad 20 b of the second semiconductor chip 20 is formed.
A seed layer 22 made of TiCu or the like is formed on the second resin layer 21 so as to be integrated into the opening 21 a and integrated with the plug portion connected to the upper surface of the conductive post 17 and the pad 20 b of the second semiconductor chip 20. And the 1st wiring which consists of a copper layer 24 is formed.

Further, for example, a third resin layer 25 made of the same polyimide resin as the first resin layer 19 is formed so as to cover the first wiring made of the seed layer 22 and the copper layer 24.
In the third resin layer 25, an opening 25a reaching the first wiring is formed.
A second wiring made of a seed layer 26 such as TiCu and a copper layer 28 is formed on the third resin layer 25 so as to be embedded in the opening 25a and integrated with the plug portion connected to the first wiring. ing.

In addition, a conductive post 30 made of copper or the like is formed in connection with the second wiring.
An insulating buffer layer 31 made of polyamideimide resin, polyimide resin, epoxy resin, phenol resin, polyparaphenylene benzobisoxazole resin, or the like is formed on the upper layer of the third resin layer 25 in the gap between the conductive posts 30. .
Further, bumps (projection electrodes) 32 are formed on the surface of the buffer layer 31 so as to be connected to the conductive posts 30.

In the semiconductor device of the present embodiment, the first semiconductor chip 18 is, for example, a digital chip, while the second semiconductor chip 20 is, for example, an analog chip.
A resin layer is laminated on the substrate 10 to form an insulating layer (19, 21, 25), and the first semiconductor chip 18 and the second semiconductor chip 20 are embedded in the insulating layer.

  The semiconductor device of the present embodiment is a stack type in which two semiconductor chips are stacked and integrated on a substrate in the SiP type semiconductor device, but the first circuit surface of the first semiconductor chip 18 is the substrate. The second semiconductor chip 20 is stacked and mounted above the first semiconductor chip 18 so that the second circuit surface of the second semiconductor chip 20 faces the opposite side of the substrate 10. Noise has a property of being strongly propagated to the circuit surface side of the semiconductor chip, and as described above, the configuration is such that the circuit surfaces of the two semiconductor chips are mounted so that they face in different directions. However, noise acting between the chips can be suppressed.

  Even if the first semiconductor chip 18 and the second semiconductor chip 20 are a combination in which the above-mentioned vertical relationship is reversed, or both are digital chips or analog chips, it is possible to suppress noise between chips in the same manner as described above. .

In the semiconductor device according to this embodiment configured as described above, the first semiconductor chip 18 and the second semiconductor are separated from each other by 150 μm or more between the first circuit surface of the first semiconductor chip 18 and the second circuit surface of the second semiconductor chip 20. The chip 20 is preferably mounted on the substrate 10.
By ensuring a certain distance or more between the first circuit surface and the second circuit surface, the influence of noise can be further reduced.

  In addition, in the case of a structure in which two chips are stacked as in the semiconductor device of the present embodiment, the step difference between the chip and the other part is more than twice as compared with the case of only one chip, and in the upper layer In the formation process of the rewiring layer to be formed, the coverage of the resist film, etc. deteriorates, causing disconnection, or the height of the conductive post contributing to stress relaxation with the mounting board varies depending on the package position However, in the semiconductor device of this embodiment, the conductive post is formed in the same layer as the first semiconductor chip, and the resin layer covering the first semiconductor chip and the conductive post is flat. As a result, the difference in level due to the incorporation of the semiconductor chip is substantially the same as that of the second semiconductor chip, and two or more semiconductor chips are stacked. Even if it is integrated into the mold, it is possible to suppress disconnection, and to reduce stress variations by reducing the variation in the height of the conductive posts that contribute to stress relaxation that occurs between the mounting substrate and the mounting substrate. Function can be secured.

Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. In the present embodiment, for example, all processes shown in FIGS. 2 to 12 can be performed at the wafer level.
First, as shown in FIG. 2A, for example, a base insulation made of silicon oxide having a thickness of 30 nm is formed on a silicon substrate 10 having a thickness of 725 μm by a thermal oxidation method or a CVD (chemical vapor deposition) method. A film 11 is formed.

  Next, as shown in FIG. 2B, for example, a TiCu layer is formed on the entire surface by sputtering to form the seed layer 12. The film thickness is, for example, 300 nm for Ti and 300 nm for Cu.

  Next, as shown in FIG. 2C, for example, a resist film 13 is formed by spin coating or the like, and exposure and development are performed by a photolithography process to form a substrate electrode for mounting the first semiconductor chip. An opening reaching the surface of the seed layer 12 is formed in the formation region.

  Next, as shown in FIG. 2D, the copper layer 14 constituting the substrate electrode is formed in the opening region of the resist film 13 by, for example, electrolytic plating using the seed layer 12 as one electrode.

  Next, as shown in FIG. 3A, the nickel gold layer 15 constituting the substrate electrode is formed on the copper layer 14 in the opening region of the resist film 13 by, for example, electrolytic plating or electroless plating. To do.

  Next, as shown in FIG. 3B, for example, after the resist film 13 is removed, a resist film 16 is formed by spin coating or the like, and exposure and development are performed by a photolithography process. An opening reaching the surface of the nickel gold layer 15 is formed in the formation region.

  Next, as shown in FIG. 3C, the conductive post 17 is formed in the upper layer of the nickel gold layer 15 in the opening region of the resist film 16 by, for example, electrolytic plating using the seed layer 12 as one electrode. To do. The height of the conductive posts is preferably about the same as or higher than the height of the surface when the first semiconductor chip is mounted in the next step, for example, 120 μm.

Next, as shown in FIG. 4A, for example, the resist film 16 is removed, and further, as shown in FIG. 4B, for example, the seed layer 12 is etched using the nickel gold layer 15 and the copper layer 14 as a mask. Process.
Thereby, the substrate electrode formed by laminating the seed layer 12, the copper layer 14, and the nickel gold layer 15 is formed in a predetermined pattern.

  Next, as shown in FIG. 4C, for example, a pad 18b is formed on the first circuit surface on which the active element of the semiconductor body portion 18a is formed in a separate process, and the region excluding the pad 18b is formed. Is covered with a protective layer 18c such as silicon oxide, and the bump (projection electrode) 18d is further formed on the pad 18b. The first semiconductor chip 18 is face-down, that is, the surface on which the bump 18d is formed. The first circuit surface is mounted on the substrate electrode such that the first circuit surface faces the substrate 10 side.

In the manufacturing method of the first semiconductor chip 18, for example, Au stud bumps or Au plated bumps are formed as bumps 18 d at a height of 30 μm, the semiconductor body portion is thinned to 80 μm by a grinding method, and full cut dicing is performed. In order to reduce the thickness of individual pieces.
The bump 18d and the substrate electrode are bonded by, for example, ultrasonic bonding or a thermocompression bonding method using a conductive resin.

  Next, as shown in FIG. 5A, an insulating material such as a polyimide resin, a silicone-modified polyimide resin, an epoxy resin, a BCB resin, or a PBO resin is supplied by, for example, a spin coating method or a printing method. A first resin layer 19 that covers the semiconductor chip 18 and the conductive post 17 is formed.

  Next, as shown in FIG. 5B, the first resin layer 19 is flattened by, for example, a flattening process such as a grinder, a bite, or CMP (chemical mechanical polishing), and the upper surface of the conductive post 17 is formed. Expose.

  Next, as shown in FIG. 5C, for example, the pad 20b is formed on the second circuit surface on which the active element of the semiconductor body portion 20a is formed in a separate process in advance, and the region excluding the pad 20b is formed. The second semiconductor chip 20 covered with a protective layer 20c such as silicon oxide is face-up by a die attach film 20e above the first semiconductor chip 18 and above the first resin layer 19. That is, the mounting is performed such that the second circuit surface, which is the formation surface of the pad 20b, faces the side opposite to the substrate 10. At this time, for example, the upper surface of the conductive post 17 is used as an alignment mark to simultaneously recognize the pads of the second semiconductor chip and perform mounting with high accuracy.

In the manufacturing method of the second semiconductor chip 20, for example, the thickness is reduced to 25 to 50 μm by a grinding method or the like, the die attach film 20 e as an adhesive is laminated on the back surface, and the individual pieces are thinned by full-cut dicing. .
The mounting conditions are a temperature of 160 ° C., a load of 1.6 N, and a time of 2 seconds when the chip size is 1.5 mm □. The mounting load is adjusted according to the chip size.
After mounting, a curing process is performed at 170 ° C. for 1 hour or longer to cure the die attach film 20e.

Next, as shown in FIG. 6A, a photosensitive insulating material such as BCB resin, polyimide resin, epoxy resin, or PBO resin is supplied by, for example, a spin coating method or a printing method, and the second resin layer 21 Form. For example, it is formed to have a film thickness of 50 μm after curing.
In the case of a photosensitive polyimide resin, for example, the film is formed under the following conditions.
Spin coating: 700 rpm (25 seconds) + 1000 rpm (125 seconds) + 1000 rpm (10 seconds) + 1500 rpm (10 seconds)
Pre-bake: 60 ° C (240 seconds) + 90 ° C (240 seconds) + 110 ° C (120 seconds)

Next, as shown in FIG. 6B, for example, pattern exposure and development are performed at an exposure amount of 300 mJ / cm ² , and the opening 21 a reaching the upper surface of the conductive post 17 and the pad 20 b of the second semiconductor chip 20 is formed. Two resin layers 21 are formed.
After the development, post-curing treatment at 300 ° C. (60 minutes) is performed to cure the second resin layer 21.

  Next, as shown in FIG. 6C, for example, a descum treatment is performed, a pretreatment etching of sputtering is performed, and the inside of the opening 21a of the second resin layer 21 is further coated by sputtering to form a TiCu film on the entire surface. A seed layer 22 is formed by film formation. For example, the film thickness is 160 nm for Ti and 600 nm for Cu.

  Next, as shown in FIG. 7A, for example, in order to prevent plating other than the opening 21a formed in the second resin layer 21 and the formation region of the first wiring, resist coating and development processing are performed. Then, a resist film 23 having a pattern that opens the opening 21a of the second resin layer 21 and the formation region of the first wiring is formed.

  Next, as shown in FIG. 7B, for example, an opening formed in the second resin layer 21 by plating copper by electrolytic plating using the resist film 23 as a mask and the seed layer 22 as one electrode. A copper layer 24 is formed in the formation region of 21a and the first wiring.

  Next, as shown in FIG. 7C, the resist film 23 is removed by, for example, an ashing process.

Next, as shown in FIG. 8A, for example, the seed layer 22 is etched using the copper layer 24 as a mask.
Thus, the first wiring composed of the seed layer 22 and the copper layer 24 is formed on the second resin layer 21 so as to be integrated with the upper surface of the conductive post 17 and the plug portion connected to the pad 20b of the second semiconductor chip 20. The

  Next, as illustrated in FIG. 8B, for example, the third resin layer 25 is formed so as to cover the first wiring. The film forming conditions are the same as those for the first insulating film 19 and the like.

  Next, as shown in FIG. 8C, for example, a predetermined pattern exposure and development are performed, an opening 25a reaching the surface of the first wiring is formed in the third resin layer 25, and post-cure processing is performed.

  Next, as shown in FIG. 9A, for example, the inside of the opening 25 a of the third resin layer 25 is covered by sputtering, and a TiCu film is formed on the entire surface to form the seed layer 26.

  Next, as shown in FIG. 9B, for example, in order to prevent plating in areas other than the opening 25a formed in the third resin layer 25 and the formation area of the second wiring, resist coating and development processing are performed. Then, a resist film 27 having a pattern opening the opening 25a of the third resin layer 25 and the formation region of the second wiring is formed.

  Next, as shown in FIG. 9C, for example, an opening formed in the third resin layer 25 by plating copper by electrolytic plating using the resist film 27 as a mask and the seed layer 26 as one electrode. A copper layer 28 is formed in the formation region of 25a and the first wiring.

  Next, as shown in FIG. 10A, the resist film 27 is removed by, for example, an ashing process.

  Next, as shown in FIG. 10B, for example, a resist film 29 is formed or a photosensitive dry film is bonded, and pattern exposure and development are performed to form openings 29a for conductive posts.

  Next, as shown in FIG. 10C, the conductive posts 30 are formed in the openings 29a for the conductive posts by, for example, electrolytic plating of copper using the seed layer 26 as one electrode. The conductive post 30 has a diameter of 180 to 300 μm and a height of 80 to 180 μm, for example.

  Next, as shown in FIG. 11A, for example, the resist film 29 or the dry film is removed, and as shown in FIG. 11B, the seed layer 26 is formed using the conductive posts 30 and the copper layer 28 as a mask. Etching process. Thereby, the second wiring composed of the seed layer 26 and the copper layer 28 is formed.

  Next, as shown in FIG. 11C, for example, a resin such as an epoxy resin, a polyimide resin, a silicone resin, a polyamideimide resin, a polyimide resin, a phenol resin, or a polyparaphenylene benzobisoxazole resin is spun. A film is formed by coating, printing, molding, or the like, and the insulating buffer layer 31 is formed with a film thickness that completely covers the conductive post 30.

  Next, as shown in FIG. 12A, for example, after the resin hardening of the buffer layer 31, cueing of the conductive post 30 is performed by grinding. The conditions at this time are set to 3500 rpm and 0.5 mm / second using, for example, a # 600 wheel.

  Next, as shown in FIG. 12C, bumps (projection electrodes) 32 are formed by, for example, mounting solder balls or printing solder paste so as to be connected to the conductive posts 30.

  Next, as shown in FIG. 12B, for example, the silicon substrate 10 is thinned to a desired thickness by BGR from the back side of the silicon substrate 10, and the silicon substrate 10 is diced by the blade B to be thinly divided into individual pieces.

  According to the method of manufacturing a semiconductor device according to the above-described embodiment, in the SiP type semiconductor device, the first semiconductor chip is mounted so that the first circuit surface faces the substrate side, while the second semiconductor chip of the second semiconductor chip is mounted. Mounting with the two circuit faces facing away from the substrate, and mounting so that the circuit faces of the two semiconductor chips face different directions, suppresses noise acting between chips even when integrated as a stack type Possible semiconductor devices can be manufactured.

  In the semiconductor device manufacturing method according to the present embodiment, the first circuit surface of the first semiconductor chip 18 and the second circuit surface of the second semiconductor chip 20 are separated from each other by 150 μm or more, and the second semiconductor chip 18 and the second circuit surface are separated. The semiconductor chip 20 is preferably mounted on the substrate 10. In order to realize this, for example, the height of the conductive post 17 and the film thickness of the first insulating film 19 can be adjusted.

As the semiconductor chip incorporated in the semiconductor device according to the above-described embodiment, a stack type thin structure that does not interfere with each other in the combination of digital, digital chip, analog, combination of analog chip, and combination of digital and analog chip is possible. .
Further, the chip size of the first layer and the second layer is not restricted by the size relationship because of the rewiring structure. Since none of the chips is connected by wire bonding, it is not necessary to increase the thickness of the insulating film by the wire loop height, and a thin stack structure is realized.
Even if no shield material or ground pattern is formed between the stacked chips, noise between chips can be suppressed.

(Modification)
In the above embodiment, a shield material or a ground pattern is not formed between the stacked first semiconductor chip and the second semiconductor chip, but a dielectric layer serving as a shield material or a conductive layer serving as a ground pattern is provided. It may be done.
For example, a dielectric layer or a conductive layer is patterned in a predetermined region on the first resin layer 19 in the upper layer of the first semiconductor chip 18, and in the case of the conductive layer, the electric potential is fixed to a constant potential such as ground. Can be connected to each other.
Thus, when a dielectric layer serving as a shielding material or a conductive layer serving as a ground pattern is provided, noise between chips can be further suppressed.

The present invention is not limited to the above description.
For example, passive elements such as inductances and capacitors may be formed on the first and second wirings.
In the embodiment, two layers of wiring (first wiring and second wiring) are formed as the wiring in the insulating layer, but the present invention is not limited to this. The number of resin insulation layers is not limited to the number of layers as described above.
An electronic circuit including an active element or the like may be formed on the silicon substrate 10 itself.
In addition, various modifications can be made without departing from the scope of the present invention.

  The semiconductor device of the present invention can be applied to a semiconductor device in a system in package form.

  The semiconductor device manufacturing method of the present invention can be applied to a system-in-package semiconductor device manufacturing method.

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2A to 2D are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 3A to 3C are cross-sectional views illustrating the manufacturing process of the method for manufacturing a semiconductor device according to the embodiment of the present invention. 4A to 4C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 5A to 5C are cross-sectional views illustrating the manufacturing process of the method for manufacturing a semiconductor device according to the embodiment of the present invention. 6A to 6C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 7A to 7C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8A to 8C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 9A to 9C are cross-sectional views illustrating the manufacturing process of the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIGS. 10A to 10C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 11A to 11C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 12A to 12C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 11 ... Base insulating film, 12 ... Seed layer, 13 ... Resist film, 14 ... Copper layer, 15 ... Nickel gold layer, 16 ... Resist film, 17 ... Conductive post, 18 ... 1st semiconductor chip, 18a ... Semiconductor body portion, 18b ... Pad, 18c ... Protection layer, 18d ... Bump, 19 ... First resin layer, 20 ... Second semiconductor chip, 20a ... Semiconductor body portion, 20b ... Pad, 20c ... Protection layer, 20e ... Die attach film, 21 ... second resin layer, 21a ... opening, 22 ... seed layer, 23 ... resist film, 24 ... copper layer, 25 ... third resin layer, 25a ... opening, 26 ... seed layer, 27 ... Resist film, 28 ... copper layer, 29 ... resist film, 30 ... conductive post, 31 ... buffer layer, 32 ... bump, B ... blade, E ... substrate electrode

Claims (12)

A semiconductor device packaged including a semiconductor,
A substrate,
A first semiconductor chip having a first circuit surface on which an active element is formed, and mounted on the substrate such that the first circuit surface faces the substrate side;
And a second semiconductor chip mounted on the first semiconductor chip so that the second circuit plane faces the opposite side of the substrate. Semiconductor device. A protruding electrode is formed on the first circuit surface of the first semiconductor chip,
A substrate electrode is formed on the substrate;
The semiconductor device according to claim 1, wherein the first semiconductor chip is mounted on the substrate such that the protruding electrode is connected to the substrate electrode and the first circuit surface faces the substrate side. Having an insulating layer formed by laminating a resin layer on the substrate;
The semiconductor device according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are embedded in the insulating layer. The semiconductor device according to claim 1, wherein a dielectric layer is formed between the first semiconductor chip and the second semiconductor chip. The semiconductor device according to claim 1, wherein a conductive layer is formed between the first semiconductor chip and the second semiconductor chip. The first circuit surface of the first semiconductor chip and the second circuit surface of the second semiconductor chip are separated from each other by 150 μm or more, and the first semiconductor chip and the second semiconductor chip are mounted on the substrate. The semiconductor device described. A method of manufacturing a semiconductor device packaged including a semiconductor,
Mounting a first semiconductor chip having a first circuit surface on which an active element is formed on a substrate so that the first circuit surface faces the substrate;
Mounting a second semiconductor chip having a second circuit surface on which an active element is formed, stacked over the first semiconductor chip so that the second circuit surface faces away from the substrate. A method for manufacturing a semiconductor device. Forming a protruding electrode on the first circuit surface of the first semiconductor chip;
Forming a substrate electrode on the substrate, and
The step of mounting the first semiconductor chip includes mounting the first semiconductor chip on the substrate such that the protruding electrode is connected to the substrate electrode and the first circuit surface faces the substrate side. 8. A method for producing a semiconductor device according to 7. Further comprising the step of laminating a resin layer on the substrate to form an insulating layer;
The method for manufacturing a semiconductor device according to claim 7, wherein the first semiconductor chip and the second semiconductor chip are formed by being embedded in the insulating layer. After the step of mounting the first semiconductor chip and before the step of mounting the second semiconductor chip, further comprising a step of forming a dielectric layer above the first semiconductor chip;
The method for manufacturing a semiconductor device according to claim 7, wherein in the step of mounting the second semiconductor chip, the second semiconductor chip is mounted above the dielectric layer. After the step of mounting the first semiconductor chip and before the step of mounting the second semiconductor chip, further comprising a step of forming a conductive layer above the first semiconductor chip;
The method for manufacturing a semiconductor device according to claim 7, wherein in the step of mounting the second semiconductor chip, the second semiconductor chip is mounted above the conductive layer. The first semiconductor chip and the second semiconductor chip are mounted on the substrate so that the first circuit surface of the first semiconductor chip and the second circuit surface of the second semiconductor chip are separated by 150 μm or more. The manufacturing method of the semiconductor device of description.

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