TWI470708B - Electronic device package and fabrication method thereof - Google Patents

Description

Electronic component package and manufacturing method thereof

The present invention relates to an electronic component package, and more particularly to an isolation layer for an electronic component package fabricated using a wafer scale package (WSP) process and a method of fabricating the same.

In a conventional electronic component package, a periphery of the wafer is usually surrounded by an insulating layer to be isolated from a subsequently formed wiring layer. The conventional insulating layer has a good resolution to form an opening therein for forming a subsequently formed wiring layer. Electrically connected to the wafer. However, conventionally, an insulating layer having a good resolution is usually thin in thickness, and thus it is impossible to balance the requirements of surface flatness, mechanical strength, and thermal expansion coefficient. Conversely, surface insulation (coplanar), mechanical strength, and coefficient of thermal expansion (CTE) matching performance of the barrier layer requires a large thickness, and thus cannot achieve good resolution requirements.

Therefore, there is a need for an insulation layer for an electronic component package that satisfies the above needs and a method of manufacturing the same.

In view of the above, an embodiment of the present invention provides a method for fabricating an electronic component package, comprising: providing a carrier wafer; and disposing an electronic component wafer above the carrier wafer, wherein a plurality of conductive pads are disposed thereon; a first isolation layer covering the carrier wafer and the electronic component wafer, wherein the first isolation layer has a plurality of first openings to respectively expose the conductive pads; compliance on the first isolation layer and the above Forming a second insulating layer in the first openings, wherein the second insulating layer has a plurality of second openings corresponding to the positions of the first openings to expose the conductive pads respectively; compliance is performed by the second isolation Forming a plurality of isolated wiring patterns on the layer and the second openings to electrically connect the conductive pads; forming a plurality of conductive bumps electrically connected to the conductive pads on the plurality of repeating line patterns Piece.

Another embodiment of the present invention provides an electronic component package including a carrier wafer; an electronic component wafer disposed above the carrier wafer, wherein the electronic component wafer is provided with a plurality of conductive pads; a layer comprising a first isolation layer of a lower layer and a second isolation layer of an upper layer, wherein the first isolation layer covers the carrier wafer and the electronic component wafer, wherein the isolation laminate has a plurality of openings to respectively expose The plurality of conductive pads are respectively formed on the insulating laminate and the openings, and are electrically connected to the conductive pads respectively; and the plurality of conductive bumps are respectively formed on the conductive pads The wiring pattern is redistributed and electrically connected to the conductive pads.

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

The electronic component packaging system of the embodiment of the present invention utilizes a wafer level chip scale package (WLCSP) process package to package various active or passive elements, digital circuits or analog circuits. The electronic components of an integrated circuit, for example, are related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or utilizing heat and light. A physical sensor that measures physical quantities such as pressure. In particular, wafer scale package (WSP) processes can be used for image sensors, light-emitting diodes, solar cells, RF circuits, accelerators. Semiconductor wafers such as gyroscopes, micro actuators, surface acoustic wave devices, process sensors, or ink printer heads are packaged.

The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also applicable to an electronic component package in which a plurality of wafers having integrated circuits are arranged by a stack to form multi-layer integrated circuit devices.

1b, 2b, 3b, 4b, 5b, and 6b are schematic top views showing the fabrication of an electronic component package 500a according to an embodiment of the present invention. Figures 1a, 2a, 3a, 4a, 5a, and 6a are cross-sectional views taken along line A-A' of the first, second, third, third, fourth, fifth, and fourth, respectively. As shown in Figures 1a and 1b, a carrier wafer 200 is provided. In an embodiment of the invention, the carrier wafer 200 may include a bare silicon wafer having no element pattern, having an upper surface 201 and a lower surface 203. An electronic component wafer 204 is disposed on the upper surface 201 of the carrier wafer 200. In an embodiment of the invention, the electronic component wafer 204 is disposed on the carrier wafer 200 via an adhesive layer 202, such as a conductive silver paste. As shown in Figures 1a and 1b, the upper surface 206 of the electronic component wafer 204 is provided with a plurality of conductive pads 208. The conductive pad 208 is used to transfer an input/output (I/O) signal, a ground signal, a power signal, and the like of the electronic component chip 204.

2a, 2b to 3a, 3b illustrate the manner in which the isolation stack 216 is formed in accordance with an embodiment of the present invention. The isolation stack 216 is used to isolate the periphery of the electronic component wafer 204 from the subsequently formed redistribution trace pattern. Next, referring to FIGS. 2a and 2b, a first isolation layer 210 is formed to cover the upper surface 206 of the carrier wafer 200 and the electronic component wafer 204. In an embodiment of the invention, the first isolation layer 210 is mainly used to planarize the surface of the carrier wafer 200 and the electronic component wafer 204, which may be a dry film photoresist formed by vacuum bonding or thermocompression bonding. (dry film photoresist). The first isolation layer 210 may form a plurality of first openings 212 at a formation position of the conductive pads 208 by using a lithography process to expose the conductive pads 208, respectively.

Next, referring to the figures 3a and 3b, a second insulating layer 214 is formed on the first insulating layer 210 and in the first opening 212 in compliance. In an embodiment of the invention, the second insulating layer 214 is mainly formed to expose the opening of the conductive pad 208 to facilitate the formation of subsequent wire windings, and the material thereof may include an epoxy resin, a solder resist layer, a tantalum oxide layer, and a tantalum nitride layer. Layer, bismuth oxynitride layer, metal oxide, polyimide, butylcyclobutene (BCB, Dow Chemical Company), parylene, polynaphthalenes, Fluorocarbons, accrylates or combinations thereof. The second isolation layer 214 can be formed by spin coating, spray coating, curtain coating, liquid phase deposition, physical vapor deposition (physical vapor deposition). Deposition; PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), Rapid thermal chemical vapor deposition (RTCVD) or atmospheric pressure chemical vapor deposition (APCVD). The second isolation layer 214 may also form a plurality of second openings 218 at the formation locations of the first openings 212 by photolithography to expose the conductive pads 208, respectively. After the above process, an isolation combo layer 216 including a first insulating layer 210 and a second insulating layer 214 is formed.

In an embodiment of the invention, the insulating laminate 216 is formed by laminating a lower first insulating layer 210 and an upper second insulating layer 214, wherein the first insulating layer 210 and the second insulating layer 214 have different functions, respectively. The first isolation layer 210 is mainly used to planarize the surface of the carrier wafer 200 and the electronic component wafer 204. Therefore, the first isolation layer 210 such as a dry film photoresist has a good surface compared to the second isolation layer 214. Coplanar, preferably mechanical strength, and thus the thickness of the first insulating layer 210 is greater than the thickness of the second insulating layer 214. Alternatively, for example, silica particles may be added to the first insulating layer 210 to increase thermal conductivity or adjust its coefficient of thermal expansion (CTE) to match the coefficient of thermal expansion of the electronic component wafer 204. In order to accurately form the opening of the exposed conductive pad 208 to facilitate the formation of subsequent wire windings, the second insulating layer 214 needs to have a better resolution than the first insulating layer 210, and the second insulating layer 214 The coefficient of viscosity is lower than the viscosity coefficient of the first insulating layer 210. The insulating laminate 216 which is formed by laminating the first insulating layer 210 having a flattening function and the second insulating layer 214 having a good resolution can have the advantages of different insulating layers.

Thereafter, please refer to FIGS. 4a and 4b, which show the manner in which the redistribution line pattern 220a and the Under Bump Metallurgy (UBM) 220b are formed. The deposition and lithography process can be utilized to form a plurality of isolated wiring patterns 220a and under bump metal layers (UBM) 220b on the second isolation layer 214 and the second opening 218. The ends of each of the redistribution circuit patterns 220a are electrically connected to a conductive pad 208 and a solder ball under metal layer (UBM) 220b, respectively. The under-ball metal layer (UBM) 220b is an optional component. In other embodiments, the under-ball metal layer (UBM) 220b may be replaced by a lengthened redistribution trace pattern 220a.

In the embodiment of the present invention, in order to transmit the signal of the electronic component wafer 204 to the outside, the redistribution wiring pattern 220a may redistribute the positions of the subsequently formed conductive bumps, for example, from the peripheral area of the electronic component wafer 204 to the whole. The electronic component wafer 204, and thus the redistribution wiring pattern 220a, may thus extend from the peripheral region of the electronic component wafer 204 to the central region of the electronic component wafer 204. It should be noted that, as shown in FIG. 4a, in order to maintain the minimum spacing required between subsequently formed conductive bumps in the case where the number of conductive pads is increased, it is formed on any two adjacent conductive pads. The redistribution line patterns 220a on 208 extend toward the inner side and the outer side of the electronic component wafer 204, respectively. For example, the redistribution line patterns 220a ₁ and 220a ₂ electrically connected to any two adjacent conductive pads 208 are respectively The inner and outer sides of the electronic component wafer 204 are extended, and thus the under-bump metal layers (UBM) 220b ₁ and 220b ₂ respectively connected to the redistribution wiring patterns 220a ₁ and 220a ₂ are located inside and outside the electronic component wafer 204, respectively. For example, the redistribution wiring pattern 220a and the under-ball metal layer (UBM) 220b composed of a conductive material may be a metal or a metal alloy such as a nickel layer, a silver layer, an aluminum layer, a copper layer or an alloy thereof; or Materials such as heteropolycrystalline germanium, single crystal germanium, or conductive glass layers. Further, a refractory metal material such as titanium, molybdenum, chromium, or a layer of titanium tungsten may be used alone or in combination with other metal layers. In a particular embodiment, the nickel/gold layer can be formed locally or comprehensively on the surface of the metal layer.

Next, please refer to Figures 5a and 5b, which show how the protective layer 222 is formed. In the embodiment of the present invention, the protective layer 222 is, for example, a solder mask, and the protective layer 222 can be formed by applying a solder resist material. The protective layer 222 is then patterned to form a plurality of terminal contact pad openings 224 that expose portions of the under-bump metal layer (UBM) 220b.

Then, please refer to the figures 6a and 6b, solder plating by the patterned photoresist layer or by soldering, filling the terminal contact pad opening 224 of the protective layer 222 by means of screen printing, etc., and finally removing the species. The crystal layer or the photoresist layer is reflowed to form a solder ball or a solder paste to form a plurality of conductive bumps 228 over the electronic component wafer 204. The conductive bump 228 is adjacent to the protective layer 222 and covers a portion of the under-bump metal layer (UBM) 220b. The conductive bump 228 is electrically connected to the conductive pad 208 of the electronic component wafer 204 by the redistribution circuit pattern 220a and the under bump metal layer (UBM) 220b, wherein any two adjacent conductive bumps 228 are respectively disposed on the electronic component. The inside and the outside of the wafer 214. In an embodiment of the invention, conductive bumps 228 are used to transfer input/output (I/O) signals, ground signals, or power signals in electronic component wafer 204. Finally, the carrier wafer 200 is divided along the scribe line SC to separate the electronic component wafers 204, and the electronic component package 500a according to an embodiment of the present invention is completed.

Fig. 7 is a schematic cross-sectional view showing an electronic component package 500b according to another embodiment of the present invention. In another embodiment of the invention, the carrier wafer 200 has a cavity 232 therein to accommodate the electronic component wafer 204 to reduce the overall height of the electronic component package. In addition, the carrier wafer 200 may be provided with an alignment pattern 238 adjacent to the top surface 201 of the recess 232. The electronic component wafer 204 may be used to form the electronic component wafer 204 prior to the step of disposing the electronic component wafer 204 in the recess 232. The formation of the recess 232 is aligned to facilitate placement of the electronic component wafer 204 in the recess 232. As shown in FIG. 7, the first insulating layer 210 for planarization is filled in the recess 232, covering the bottom surface and the side surface of the recess 232, the side surface of the electronic component wafer 204, and a portion of the top surface 206, and covering the supporting crystal. The top surface 204 of the circle 200.

8a and 9a are top plan views of electronic component packages of different embodiments of the present invention showing different opening patterns of the first insulating layer 210. Figures 8b to 9b are cross-sectional views taken along line B-B' of Figs. 8a and 9a, respectively. As shown in FIGS. 8a, 8b, the opening 212a of the first isolation layer 210 may expose a plurality of conductive pads 208. As shown in Figures 9a and 9b, each of the openings 212b of the first insulating layer 210 exposes a conductive pad 208, respectively.

The insulating laminate 216 of the electronic component package 500a or 500b of the embodiment of the present invention for isolating the periphery of the electronic component wafer 204 from the subsequently formed redistribution wiring pattern is mainly composed of two layers of different functional isolation layers. The first isolation layer 210 located in the lower layer is mainly used to planarize the surface of the carrier wafer 200 and the electronic component wafer 204. The second insulating layer 214 located in the upper layer is mainly used to form an opening exposing the conductive pad 208 to facilitate the formation of subsequent wire windings. Therefore, the first insulating layer 210 has good surface flatness, good mechanical strength, and thermal expansion coefficient matching. In addition, the second insulating layer 214 has a better resolution and a lower coefficient of viscosity. Therefore, the isolation laminate 216 formed by laminating the first isolation layer 210 having the planarization function and the second isolation layer 214 having good resolution can have the advantages of different material isolation layers.

In addition, in the electronic component package 500a or 500b of the embodiment of the present invention, in order to maintain the minimum spacing required between the subsequently formed conductive bumps in the case where the number of conductive pads is increased, it is formed in any two The redistribution trace patterns 220a on the adjacent conductive pads 208 extend toward the inner and outer sides of the electronic component wafer 204, respectively, such that any two adjacent conductive bumps 228 are disposed on the inner side and the outer side of the electronic component wafer 214, respectively. To meet the requirements of high-density electronic component packages.

Furthermore, since the electronic component package 500a or 500b of the above embodiment is fabricated in a wafer level packaging process, the electronic component package has a relatively small size. In addition, in the electronic component package, the conductive pads of the wafer are electrically connected by using a redistribution wiring pattern or a conductive bump, which is not a wire bond, and therefore, the size of the electronic component package can also be reduced. In addition, the carrier wafer for carrying the electronic component wafer can be a bare wafer without any component pattern, which can reduce the process cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is defined as defined in the scope of the patent application.

200. . . Carrier wafer

202. . . Adhesive layer

204. . . Electronic component chip

201, 206. . . Upper surface

208. . . Conductive pad

210. . . First insulation layer

212, 212a, 212b, 218, 224. . . Opening

214. . . Second insulation layer

216. . . Isolated laminate

220a, 220a ₁ , 220a ₂ . . . Redistributed line pattern

220b, 220b ₁ , 220b ₂ . . . Solder ball under metal layer

222. . . The protective layer

228. . . Conductive bump

232. . . pit

238. . . Alignment pattern

500a, 500b. . . Electronic component package

SC. . . cutting line

1a, 2a, 3a, 4a, 5a, and 6a are diagrams showing a top view of an electronic component package in accordance with an embodiment of the present invention.

Figures 1b, 2b, 3b, 4b, 5b, and 6b are cross-sectional views taken along line A-A' of the 1a, 2a, 3a, 4a, 5a, and 6a, respectively.

Fig. 7 is a schematic cross-sectional view showing an electronic component package according to another embodiment of the present invention.

8a and 9a are top plan views of electronic component packages of other embodiments of the present invention, showing different opening patterns of the first insulating layer.

Figures 8b to 9b are cross-sectional views taken along line B-B' of Figs. 8a and 9a, respectively.

200‧‧‧bearing wafer

204‧‧‧Electronic component chip

208‧‧‧Electrical mat

212, 218, 224‧‧

220a‧‧‧Re-route pattern

220b‧‧‧metal under the solder ball

222‧‧‧Protective layer

228‧‧‧Electrical bumps

500a‧‧‧Electronic component package

Claims (26)

A method for fabricating an electronic component package includes the steps of: providing a carrier wafer; disposing an electronic component wafer above the carrier wafer, wherein a plurality of conductive pads are disposed thereon; forming a first isolation layer covering the carrier The wafer and the electronic component wafer, wherein the first isolation layer has a plurality of first openings to respectively expose the conductive pads; compliance is formed on the first isolation layer and the second openings form a second An insulating layer, wherein the second insulating layer has a plurality of second openings corresponding to the positions of the first openings to respectively expose the conductive pads; compliance on the second insulating layer and the second openings And forming a plurality of isolated wiring patterns electrically connected to the conductive pads; and forming a plurality of conductive bumps electrically connected to the conductive pads on the redistribution circuit patterns. The method of fabricating the electronic component package of claim 1, further comprising forming a protective layer on the redistribution line patterns before forming the conductive bumps, wherein the protective layer has a plurality of third openings To expose a portion of the redistributed line patterns, respectively. The method of fabricating an electronic component package according to claim 1, wherein the first insulating layer is a dry film photoresist. The method for fabricating an electronic component package according to claim 1, wherein the first isolation layer is formed by vacuum bonding or thermocompression bonding. The method of fabricating an electronic component package according to claim 1, wherein the first insulating layer further comprises cerium oxide particles. The method for fabricating an electronic component package according to claim 1, wherein the second insulating layer comprises an epoxy resin, a solder resist layer, a tantalum oxide layer, a tantalum nitride layer, a hafnium oxynitride layer, a metal oxide layer. Polyimine resin, benzocyclobutene, parylene, naphthalene polymer, fluorocarbon, acrylate or a combination thereof. The method for fabricating an electronic component package according to claim 1, wherein the second isolation layer is formed by spin coating, spray coating, curtain coating, liquid deposition, physical vapor deposition, chemical gas. Phase deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition or atmospheric pressure chemical vapor deposition. The method of fabricating an electronic component package according to claim 1, wherein the carrier wafer has a cavity therein, and the electronic component chip is disposed in the cavity. The method of fabricating an electronic component package according to claim 8, wherein the first isolation layer is filled in the recess and covers a top surface of the carrier wafer. The method of manufacturing the electronic component package of claim 8, wherein the electronic component chip is disposed in the cavity further comprises: using an alignment pattern disposed on the carrier wafer The component wafer is aligned with the formation location of the recess; and the electronic component wafer is placed in the recess. The method of fabricating an electronic component package according to claim 1, wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer. The method of fabricating an electronic component package according to claim 1, wherein each of the first and second openings exposes at least one of the conductive pads. The method of fabricating an electronic component package according to claim 1, wherein the conductive bumps electrically connected to any two adjacent conductive pads are respectively disposed on the inner side and the outer side of the electronic component wafer. . An electronic component package includes: a carrier wafer; an electronic component wafer disposed on the carrier wafer, wherein the electronic component wafer is provided with a plurality of conductive pads; and an isolation stack includes a lower layer An isolation layer and a second isolation layer of the upper layer, the first isolation layer covering the carrier wafer and the electronic component wafer, wherein the isolation laminate has a plurality of openings to respectively expose the conductive pads; The re-distributed circuit pattern is formed on the isolation stack and the opening, and electrically connected to the conductive pads respectively; and a plurality of conductive bumps are respectively formed on the re-route patterns, and Electrically connecting the conductive pads. The electronic component package of claim 14, further comprising a protective layer covering a portion of the redistributed wiring patterns. The electronic component package of claim 14, wherein the first insulating layer is a dry film photoresist. The electronic component package of claim 14, wherein the first insulating layer further comprises cerium oxide particles. The electronic component package of claim 14, wherein the second insulating layer comprises an epoxy resin, a solder resist layer, a ruthenium oxide layer, a tantalum nitride layer, a ruthenium oxynitride layer, a metal oxide layer, and a polyfluorene layer. Imine resin, benzocyclobutene, parylene, naphthalene polymer, fluorocarbon, acrylate or a combination thereof. The electronic component package of claim 14, wherein the carrier wafer has a cavity therein, and the electronic component chip is disposed in the cavity. The electronic component package of claim 19, wherein the first insulating layer is filled in the recess and covers a top surface of the carrier wafer. The electronic component package of claim 19, wherein the carrier wafer has an alignment pattern adjacent to a top surface of the cavity. The electronic component package of claim 14, wherein the first insulating layer has a thickness greater than a thickness of the second insulating layer. The electronic component package of claim 14, wherein each of the openings exposes at least one of the conductive pads. The electronic component package of claim 14, wherein the conductive bumps electrically connected to any two adjacent conductive pads are respectively disposed on inner side and outer side of the electronic component wafer. The electronic component package of claim 14, wherein the second insulating layer has a viscosity coefficient lower than a viscosity coefficient of the first insulating layer. The electronic component package of claim 14, wherein the first insulating layer has a mechanical strength greater than a mechanical strength of the second insulating layer.