JP2016213371A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
JP2016213371A
JP2016213371A JP2015097217A JP2015097217A JP2016213371A JP 2016213371 A JP2016213371 A JP 2016213371A JP 2015097217 A JP2015097217 A JP 2015097217A JP 2015097217 A JP2015097217 A JP 2015097217A JP 2016213371 A JP2016213371 A JP 2016213371A
Authority
JP
Japan
Prior art keywords
photosensitive resin
semiconductor element
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015097217A
Other languages
Japanese (ja)
Other versions
JP6569288B2 (en
Inventor
一行 満倉
Kazuyuki Mitsukura
一行 満倉
蔵渕　和彦
Kazuhiko Kurabuchi
和彦 蔵渕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP2015097217A priority Critical patent/JP6569288B2/en
Publication of JP2016213371A publication Critical patent/JP2016213371A/en
Application granted granted Critical
Publication of JP6569288B2 publication Critical patent/JP6569288B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that enables high density transmission with a good yield at low cost.SOLUTION: A method of manufacturing a semiconductor device includes the following steps of: (I) fixing a plurality of first semiconductor elements on a carrier; (II) encapsulating the first semiconductor elements with a photosensitive resin material as a block to form a photosensitive resin film; (III) exposing and developing the photosensitive resin film to form openings that open electrode parts of the first semiconductor elements; and (IV) electrically connecting the electrodes of the first semiconductor elements with the second semiconductor elements via connection electrodes astride two or more semiconductor elements of the plurality of first semiconductor elements, at the openings.SELECTED DRAWING: Figure 5

Description

本発明は、半導体装置の製造方法及び当該製造方法により得られる半導体装置に関する。より詳しくは、微細化や高密度化の要求が高い半導体装置を充分に効率よく、低コストに製造するための半導体装置の製造方法、及び当該製造方法により得られる半導体装置に関する。   The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device obtained by the manufacturing method. More specifically, the present invention relates to a semiconductor device manufacturing method for manufacturing a semiconductor device that is highly demanded for miniaturization and high density sufficiently efficiently and at low cost, and a semiconductor device obtained by the manufacturing method.

半導体装置の高密度化、高性能化を目的に、異なる性能の半導体素子を一つのパッケージに混載する実装形態が提案されており、低コスト化の観点から、半導体素子間の高密度インターコネクト技術が重要になっている。   For the purpose of increasing the density and performance of semiconductor devices, a mounting form in which semiconductor elements with different performances are mixedly mounted in a single package has been proposed. From the viewpoint of cost reduction, high-density interconnect technology between semiconductor elements has been proposed. It has become important.

３次元実装形態には、パッケージ上に異なるパッケージをフリップチップ実装によって積層することで接続するパッケージ・オン・パッケージ構造がスマートフォンやタブレット端末に広く採用されている（例えば非特許文献１及び非特許文献２参照）。さらに高密度で実装するための形態として、高密度配線を有する有機基板を用いたパッケージ技術、シリコン又はガラスインターポーザーを用いたパッケージ技術、シリコン貫通電極（ＴＳＶ）を用いたパッケージ技術、基板に埋め込まれた半導体素子を半導体素子間伝送に用いるパッケージ技術等が提案されている（例えば特許文献１参照）。   In the three-dimensional mounting mode, a package-on-package structure in which different packages are stacked on each other by flip chip mounting is widely used for smartphones and tablet terminals (for example, Non-Patent Document 1 and Non-Patent Document). 2). As a form for mounting at higher density, packaging technology using an organic substrate having high-density wiring, packaging technology using silicon or glass interposer, packaging technology using a through silicon via (TSV), embedded in a substrate There has been proposed a package technology or the like that uses the semiconductor element for transmission between semiconductor elements (see, for example, Patent Document 1).

また、半導体素子同士を高密度で導通させるために、半導体素子間の電気接続部のピッチをより狭く設計する傾向にある。   In addition, in order to conduct the semiconductor elements at high density, the pitch of the electrical connection portions between the semiconductor elements tends to be designed to be narrower.

特表２０１２−５２９７７０号公報Special table 2012-529770 gazette

Ａｐｐｌｉｃａｔｉｏｎ ｏｆ Ｔｈｒｏｕｇｈ Ｍｏｌｄ Ｖｉａ（ＴＭＶ） ａｓ ＰｏＰ Ｂａｓｅ Ｐａｃｋａｇｅ，Ｅｌｅｃｔｒｏｎｉｃ Ｃｏｍｐｏｎｅｎｔｓ ａｎｄ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏｎｆｅｒｅｎｃｅ （ＥＣＴＣ），２００８Application of Through Mold Via (TMV) as PoP Base Package, Electronic Components and Technology Conference (ECTC), 2008 Ａｄｖａｎｃｅｄ Ｌｏｗ Ｐｒｏｆｉｌｅ ＰｏＰ Ｓｏｌｕｔｉｏｎ ｗｉｔｈ Ｅｍｂｅｄｄｅｄ Ｗａｆｅｒ Ｌｅｖｅｌ ＰｏＰ （ｅＷＬＢ−ＰｏＰ） Ｔｅｃｈｎｏｌｏｇｙ，ＥＣＴＣ，２０１２Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology, ECTC, 2012

高密度配線を有する有機基板を用いたパッケージは微細配線の積層が必要なことから充分な歩留まりを得ることが難しい。また、シリコン又はガラスインターポーザーを用いたパッケージは大面積のインターポーザが必要となるため、反りの抑制や低コスト化といった課題がある。さらに、高密度化のためにシリコン又はガラス貫通電極を用いても、歩留まりや低コスト化といった問題がある。
加えて、電気接続部が狭い半導体素子間に用いられるアンダーフィルは、充填不足と半導体素子へのダメージの点から、半導体素子搭載後にキャピラリーアンダーフィルを充填する従来方式の適用は困難である。
また、一方の半導体素子上にアンダーフィルを塗布した後にもう一方の半導体素子を圧着して接続する方式であっても、バンプ間に樹脂が噛みこみ導通不良となったり、事前にアンダーフィル付の半導体素子を作製する工程が必要となりプロセスが煩雑になったりと課題があった。 A package using an organic substrate having a high-density wiring is difficult to obtain a sufficient yield because fine wiring needs to be stacked. Further, since a package using a silicon or glass interposer requires a large area interposer, there are problems such as warpage suppression and cost reduction. Furthermore, even if a silicon or glass through electrode is used for high density, there are problems such as yield and cost reduction.
In addition, underfill used between semiconductor elements with narrow electrical connections is difficult to apply in the conventional method in which the capillary underfill is filled after mounting the semiconductor elements because of insufficient filling and damage to the semiconductor elements.
In addition, even when the underfill is applied on one semiconductor element and the other semiconductor element is crimped and connected, the resin may get caught between the bumps, leading to poor conduction, or with an underfill in advance. There is a problem that a process for manufacturing a semiconductor element is required and the process becomes complicated.

本発明の目的は、高密度伝送が可能な半導体装置を良好な歩留まり、かつ低コストで製造できる製造方法を提供することである。   An object of the present invention is to provide a manufacturing method capable of manufacturing a semiconductor device capable of high-density transmission with good yield and low cost.

本発明によれば、以下の半導体装置の製造方法等が提供される。
１．（Ｉ）キャリア上に複数の第１の半導体素子を固定する工程と、
（II）前記第１の半導体素子を感光性樹脂材料で一括封止して感光性樹脂膜を形成する工程と、
（III）前記感光性樹脂膜を露光及び現像して、前記第１の半導体素子の電極部分を開口する開口部を形成する工程と、
（IV）前記開口部において、前記複数の第１の半導体素子の２以上の半導体素子に跨るように、第１の半導体素子の電極と第２の半導体素子を接続用電極を介して電気的に接続する工程とを備える半導体装置の製造方法。
２．さらに、前記キャリアを剥離する工程を備える１に記載の半導体装置の製造方法。
３．前記感光性樹脂材料が、フィルム状材料又はシート状材料である１又は２に記載の半導体装置の製造方法。
４．前記（III）の工程で形成するパターン硬化膜の膜厚が５０〜４００μｍである１〜３のいずれかに記載の半導体装置の製造方法。
５．前記感光性樹脂材料がネガ型である１〜４のいずれかに記載の半導体装置の製造方法。
６．１〜５のいずれかに記載の製造方法を用いて製造された半導体装置。 According to the present invention, the following semiconductor device manufacturing method and the like are provided.
1. (I) fixing a plurality of first semiconductor elements on a carrier;
(II) forming a photosensitive resin film by collectively sealing the first semiconductor element with a photosensitive resin material;
(III) exposing and developing the photosensitive resin film to form an opening for opening the electrode portion of the first semiconductor element;
(IV) In the opening, the electrode of the first semiconductor element and the second semiconductor element are electrically connected via the connection electrode so as to straddle two or more semiconductor elements of the plurality of first semiconductor elements. A method for manufacturing a semiconductor device comprising the step of connecting.
2. Furthermore, the manufacturing method of the semiconductor device of 1 provided with the process of peeling the said carrier.
3. 3. The method for producing a semiconductor device according to 1 or 2, wherein the photosensitive resin material is a film-like material or a sheet-like material.
4). The manufacturing method of the semiconductor device in any one of 1-3 whose film thickness of the pattern cured film formed at the process of said (III) is 50-400 micrometers.
5. The manufacturing method of the semiconductor device in any one of 1-4 whose said photosensitive resin material is a negative type.
The semiconductor device manufactured using the manufacturing method in any one of 6.1-5.

本発明によれば、高密度伝送が可能な半導体装置を歩留まりよく、かつ低コストで製造できる製造方法が提供できる。   According to the present invention, it is possible to provide a manufacturing method capable of manufacturing a semiconductor device capable of high-density transmission with high yield and low cost.

キャリアに第１の半導体素子を複数固定した状態を模式的に示す断面図である。It is sectional drawing which shows typically the state which fixed the several 1st semiconductor element to the carrier. 複数の第１の半導体素子を感光性樹脂材料で一括封止して感光性樹脂膜を形成した状態を模式的に示す断面図である。It is sectional drawing which shows typically the state which sealed the some 1st semiconductor element with the photosensitive resin material, and formed the photosensitive resin film. 感光性樹脂膜を露光及び現像して、前記第１の半導体素子の電極部分を開口する開口部を形成した状態を模式的に示す断面図である。It is sectional drawing which shows typically the state which exposed and developed the photosensitive resin film and formed the opening part which opens the electrode part of a said 1st semiconductor element. 前記複数の第１の半導体素子の２以上の半導体素子に跨るように、第１の半導体素子の電極と第２の半導体素子を接続用電極を介して電気的に接続した状態を模式的に示す断面図である。The state which electrically connected the electrode of the 1st semiconductor element and the 2nd semiconductor element via the electrode for connection so that two or more semiconductor elements of a plurality of said 1st semiconductor elements may be straddled is shown. It is sectional drawing. 金属部材をさらに搭載した状態を模式的に示す断面図である。It is sectional drawing which shows typically the state which mounted the metal member further. キャリアを剥離して基板に半導体装置を搭載し、アンダーフィルを充填した状態を模式的に示す断面図である。It is sectional drawing which shows typically the state which peeled the carrier, mounted the semiconductor device on the board | substrate, and was filled with the underfill. キャリアを剥離した半導体装置の上面図である。It is a top view of the semiconductor device which peeled the carrier. シリコン貫通電極（ＴＳＶ）を用いた積層体を含む半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor device containing the laminated body using a silicon penetration electrode (TSV). 第１の半導体素子及び第２の半導体素子を基板に搭載した半導体装置を模式的に示す上面図である。It is a top view which shows typically the semiconductor device which mounted the 1st semiconductor element and the 2nd semiconductor element on the board | substrate.

以下、図面を参照しながら本発明の好適な実施形態について詳細に説明する。以下の説明では、同一又は相当部分には同一符号を付し、重複する説明は省略する。また、上下左右等の位置関係は、特に断らない限り、図面に示す位置関係に基づくものとする。さらに、図面の寸法比率は図示の比率に限られるものではない。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same or corresponding parts are denoted by the same reference numerals, and redundant description is omitted. Further, the positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

なお、「左」、「右」、「正面」、「裏面」、「上」、「下」、「上方」、「下方」等の用語が利用されている場合、これらは、説明を意図したものであり、必ずしも永久にこの相対位置である、という意味ではない。   In addition, when terms such as “left”, “right”, “front”, “back”, “top”, “bottom”, “upward”, “downward” are used, these are intended for explanation. It does not necessarily mean that this relative position is permanent.

本発明の半導体装置の製造方法は、下記工程を備える：
（Ｉ）キャリア上に複数の第１の半導体素子を固定する工程
（II）前記第１の半導体素子を感光性樹脂材料で一括封止して感光性樹脂膜を形成する工程
（III）前記感光性樹脂膜を露光及び現像して、第１の半導体素子の電極部分を開口する開口部を形成する工程
（IV）前記開口部において、前記複数の第１の半導体素子の２以上に跨るように、第１の半導体素子の電極と第２の半導体素子を接続用電極を介して電気的に接続する工程 The method for manufacturing a semiconductor device of the present invention includes the following steps:
(I) Step of fixing a plurality of first semiconductor elements on a carrier (II) Step of forming a photosensitive resin film by collectively sealing the first semiconductor elements with a photosensitive resin material (III) The photosensitive A step of exposing and developing the conductive resin film to form an opening for opening the electrode portion of the first semiconductor element (IV) so that the opening extends over two or more of the plurality of first semiconductor elements. Electrically connecting the electrode of the first semiconductor element and the second semiconductor element via the connection electrode

本発明の半導体装置の製造方法では、感光性樹脂材料で複数の半導体素子を一括封止するため、取り扱い性が高い。また、封止材料として用いた感光性樹脂材料を露光及び現像によってパターン硬化膜とすることで、金属接続部（開口部に覆われていない部分）の噛みこみを抑制できる方法でアンダーフィルとして用いることができる。
このように、本発明の半導体装置の製造方法は、感光性樹脂材料を用いたパターン硬化膜が複数の半導体素子の封止部として機能するだけでなく、アンダーフィルとしても機能するため、低コスト化が可能な半導体素子の製造方法である。 In the method for manufacturing a semiconductor device of the present invention, since a plurality of semiconductor elements are collectively sealed with a photosensitive resin material, the handling property is high. Further, by using a photosensitive resin material used as a sealing material as a pattern cured film by exposure and development, it is used as an underfill by a method that can suppress the biting of the metal connection part (part not covered by the opening). be able to.
As described above, the method for manufacturing a semiconductor device of the present invention is low in cost because the pattern cured film using the photosensitive resin material functions not only as a sealing portion for a plurality of semiconductor elements but also as an underfill. This is a method for manufacturing a semiconductor device that can be manufactured.

本発明の一実施形態に係る図５に示す半導体装置１０１を製造する方法について説明する。尚、本発明の半導体装置の製造方法は、微細化及び多ピン化が必要とされる形態において特に好適である。特に、本発明の製造方法は、異種半導体素子を混載するためのインターポーザが必要なパッケージ形態において好適である。   A method for manufacturing the semiconductor device 101 shown in FIG. 5 according to an embodiment of the present invention will be described. The method for manufacturing a semiconductor device according to the present invention is particularly suitable in a form in which miniaturization and increase in the number of pins are required. In particular, the manufacturing method of the present invention is suitable for a package form that requires an interposer for mixing different types of semiconductor elements.

図１から図５を参照しながら、半導体装置１０１の製造方法について説明する。
まず、複数の第１の半導体素子２を第１の半導体素子２の電極７が表面に露出するようにキャリア１上に固定する（図１参照）。電極７は第１の半導体素子の金属接続部である。 A method for manufacturing the semiconductor device 101 will be described with reference to FIGS.
First, a plurality of first semiconductor elements 2 are fixed on the carrier 1 so that the electrodes 7 of the first semiconductor elements 2 are exposed on the surface (see FIG. 1). The electrode 7 is a metal connection part of the first semiconductor element.

キャリア１は特に限定されるものではないが、シリコン板、ガラス板、ＳＵＳ板、ガラスクロス入り基板等であり、高剛性材料からなる基板が好適である。また、キャリア上に第１の半導体素子２を固定させるための樹脂層や樹脂層付の金属薄膜を形成することもできる。また、キャリアには、シリコン板を埋め込むと低反りとなり好ましい。
樹脂層には、例えば、シリコーンやフッ素等の非極性成分を含有した樹脂や、加熱によって体積膨張又は発泡する成分を含有した樹脂を用いることができる。 The carrier 1 is not particularly limited, and is a silicon plate, a glass plate, a SUS plate, a glass cloth-containing substrate, or the like, and a substrate made of a highly rigid material is preferable. Also, a resin layer for fixing the first semiconductor element 2 on the carrier or a metal thin film with a resin layer can be formed. Moreover, it is preferable to embed a silicon plate in the carrier because of low warpage.
For the resin layer, for example, a resin containing a nonpolar component such as silicone or fluorine, or a resin containing a component that expands or foams when heated can be used.

キャリア１はウェハ状及びパネル状のいずれでもよい。また、キャリア１のサイズは特に限定されず、直径２００ｍｍ、直径３００ｍｍ又は直径４５０ｍｍのウェハや３００〜７００ｍｍ□のパネルが好ましく用いられる。   The carrier 1 may be either a wafer shape or a panel shape. The size of the carrier 1 is not particularly limited, and a wafer having a diameter of 200 mm, a diameter of 300 mm, or a diameter of 450 mm or a panel of 300 to 700 mm □ is preferably used.

キャリア１の厚みは０．２ｍｍから２．０ｍｍの範囲であることが好ましい。キャリア１の厚みが０．２ｍｍ未満の場合は工程中における取り扱い性が低下する傾向がある。一方、キャリア１の厚みが２．０ｍｍ超の場合は材料費が高くなる傾向がある。   The thickness of the carrier 1 is preferably in the range of 0.2 mm to 2.0 mm. When the thickness of the carrier 1 is less than 0.2 mm, the handleability during the process tends to decrease. On the other hand, when the thickness of the carrier 1 exceeds 2.0 mm, the material cost tends to increase.

第１の半導体素子２としては、ＣＰＵ、グラフィック処理ユニットＧＰＵ、ＤＲＡＭ、ＳＲＡＭ等の揮発性メモリ、フラッシュメモリ等の不揮発性メモリ、ＲＦチップやこれらを組合せた性能を有する半導体素子が好ましく用いられる。
また、第１の半導体素子２として、複数の半導体素子が積層された半導体素子積層体も用いることができる。具体的には、ＴＳＶを用いて積層した半導体素子積層体を使用することができる。図８は、半導体装置１０１に用いる半導体素子の一部が半導体素子積層体１２である例を示す。 As the first semiconductor element 2, a CPU, a graphic processing unit GPU, a volatile memory such as a DRAM or SRAM, a nonvolatile memory such as a flash memory, an RF chip, or a semiconductor element having a combination of these is preferably used.
Further, as the first semiconductor element 2, a semiconductor element stacked body in which a plurality of semiconductor elements are stacked can also be used. Specifically, a semiconductor element stacked body stacked using TSV can be used. FIG. 8 shows an example in which a part of the semiconductor elements used in the semiconductor device 101 is the semiconductor element stacked body 12.

第１の半導体素子２の厚みは、絶縁材料を薄くすることで反りを小さくできる観点から、４００μｍ以下であることが好ましく、パッケージをさらに薄型化できる観点から、２００μｍ以下であることがより好ましい。また、取り扱い性の観点から、第１の半導体素子２の厚みは３０μｍ以上であることが好ましい。   The thickness of the first semiconductor element 2 is preferably 400 μm or less from the viewpoint of reducing warpage by reducing the insulating material, and more preferably 200 μm or less from the viewpoint of further reducing the thickness of the package. Further, from the viewpoint of handleability, the thickness of the first semiconductor element 2 is preferably 30 μm or more.

第１の半導体素子２をキャリア１の正確な位置に配置するために、第１の半導体素子２及びキャリア１は、アライメントマークを有していることが好ましい。   In order to arrange the first semiconductor element 2 at an accurate position of the carrier 1, it is preferable that the first semiconductor element 2 and the carrier 1 have an alignment mark.

次いで、感光性樹脂材料を用いて第１の半導体素子２を覆うように感光性樹脂膜３を形成する（図２）。使用する感光性樹脂材料は特に限定されないが、液状、固形、フィルム状又はシート状の感光性樹脂材料を用いることができる。これらのうち、低反りかつ低コストで封止可能な点、さらにクリーンルーム環境下での汚染を回避する点で、フィルム状又はシート状の感光性樹脂材料が好適である。
フィルム状感光性樹脂材料による封止はラミネート方式でもコンプレッション方式のいずれでもよい。 Next, a photosensitive resin film 3 is formed so as to cover the first semiconductor element 2 using a photosensitive resin material (FIG. 2). The photosensitive resin material to be used is not particularly limited, but a liquid, solid, film-like or sheet-like photosensitive resin material can be used. Among these, a film-like or sheet-like photosensitive resin material is preferable in that it can be sealed at a low warpage and at a low cost, and further avoids contamination in a clean room environment.
Sealing with the film-like photosensitive resin material may be either a laminate method or a compression method.

感光性樹脂材料としては、熱硬化時のアウトガスが少なく、かつパターンの変形が少ない観点からネガ型の感光性樹脂材料が好ましい。ネガ型の感光性樹脂材料としては、特に限定はされないが、従来公知の感光性接着材、ソルダーレジスト、感光性アンダーフィル等の感光性絶縁材料が例示できる。   As the photosensitive resin material, a negative photosensitive resin material is preferable from the viewpoint of less outgas during thermosetting and less deformation of the pattern. Although it does not specifically limit as a negative photosensitive resin material, Photosensitive insulating materials, such as a conventionally well-known photosensitive adhesive, solder resist, and a photosensitive underfill, can be illustrated.

感光性樹脂材料は熱硬化成分を含有することが好ましく、封止後のさらなる加熱によって硬化させてもよい。加熱条件は例えば加熱温度は１２０〜１８０℃、３０分〜３時間である。
また、熱硬化成分を含む感光性樹脂材料を加熱硬化して得られるパターン硬化膜（封止部）の室温から１２０℃までの平均熱膨張係数は２５×１０−６／℃から１００×１０−６／℃の範囲であることが好ましい。平均熱膨張係数が２５×１０−６／℃未満の場合は感光性樹脂材料から得られる膜が脆くなるおそれがある。一方、１００×１０−６／℃超の場合は得られるパッケージに反りが生じ易くなり、取り扱い性が低下するおそれがある。 The photosensitive resin material preferably contains a thermosetting component, and may be cured by further heating after sealing. The heating conditions are, for example, a heating temperature of 120 to 180 ° C. and 30 minutes to 3 hours.
Moreover, the average thermal expansion coefficient from room temperature to 120 degreeC of the pattern cured film (sealing part) obtained by heat-curing the photosensitive resin material containing a thermosetting component is 25 * 10 < -6 > / degreeC to 100 * 10 < - >. It is preferably in the range of 6 / ° C. When the average coefficient of thermal expansion is less than 25 × 10 −6 / ° C., the film obtained from the photosensitive resin material may become brittle. On the other hand, if it exceeds 100 × 10 −6 / ° C., the resulting package is likely to warp, and the handleability may be reduced.

パターン硬化膜形成後の半導体素子封止パッケージの取り扱い性の観点から、感光性封止材料を熱硬化した後の封止部（パターン硬化膜）の室温弾性率は１ＧＰａ〜１０ＧＰａの範囲であることが好ましい。室温弾性率が１ＧＰａ未満であると封止部の自己保持性が乏しくなり、取り扱いが困難となる傾向がある。また、室温弾性率が１０ＧＰａ超であると封止部が脆くなり、割れ易くなる傾向がある。   From the viewpoint of handleability of the semiconductor element encapsulated package after the pattern cured film is formed, the room temperature elastic modulus of the encapsulated portion (pattern cured film) after thermally curing the photosensitive sealing material is in the range of 1 GPa to 10 GPa. Is preferred. When the room temperature elastic modulus is less than 1 GPa, the self-holding property of the sealing portion becomes poor and handling tends to be difficult. Further, if the room temperature elastic modulus is more than 10 GPa, the sealing portion becomes brittle and tends to break easily.

感光性樹脂材料を用いて一括封止して感光性樹脂膜を形成する工程は、液状又は固形材を用いたコンプレッションモールドよりも低コストで製造でき、かつ半導体素子へのダメージも少ない点で、ラミネート工程であることが好ましい。上記工程がラミネート工程である場合、使用できる感光性樹脂材料としては、例えばフィルム状感光性樹脂を用いることができる。   The process of forming a photosensitive resin film by encapsulating with a photosensitive resin material can be manufactured at a lower cost than a compression mold using a liquid or solid material, and there is less damage to the semiconductor element. A laminating process is preferred. When the said process is a lamination process, as a photosensitive resin material which can be used, a film-form photosensitive resin can be used, for example.

上記工程は、低温工程であることが好ましく、感光性材料は、４０〜１２０℃で封止可能なフィルム状感光性樹脂であることが好ましい。封止可能な温度が４０℃未満の感光性樹脂材料は常温でのタックが強く、取り扱い性が悪化するおそれがあり、封止可能温度が１２０℃超の感光性樹脂材料は、封止後に反りが大きくなるおそれがある。   The step is preferably a low-temperature step, and the photosensitive material is preferably a film-like photosensitive resin that can be sealed at 40 to 120 ° C. A photosensitive resin material having a sealable temperature of less than 40 ° C. has a strong tack at normal temperature and there is a possibility that the handleability may be deteriorated. A photosensitive resin material having a sealable temperature exceeding 120 ° C. warps after sealing. May increase.

次いで、感光性樹脂膜３を露光及び現像することによって感光性樹脂膜３の一部を開口したパターン硬化膜３’とし、第１の半導体素子２の電極７を露出して半導体素子封止パッケージ１００を得る（図３）。なお、図３の第１の半導体素子上の開口部について、電極７に対応しない部分も開口しているが、これは断面図であるからであり、これらも電極を露出している開口部である。
感光性樹脂膜３の露光方法としては、通常の投影露光方式、コンタクト露光方式、直描露光方式等を用いることができる。現像方法としては炭酸ナトリウムやＴＭＡＨ等のアルカリ水溶液を用いることが好ましい。また、パターン硬化膜を更に加熱することで硬化を進行させることもできる。 Next, the photosensitive resin film 3 is exposed and developed to form a patterned cured film 3 ′ in which a part of the photosensitive resin film 3 is opened, and the electrode 7 of the first semiconductor element 2 is exposed to expose the semiconductor element sealing package. 100 is obtained (FIG. 3). In addition, although the part which does not correspond to the electrode 7 is also opening about the opening part on the 1st semiconductor element of FIG. 3, this is because it is sectional drawing, These are also the opening parts which have exposed the electrode. is there.
As an exposure method for the photosensitive resin film 3, a normal projection exposure method, a contact exposure method, a direct drawing exposure method, or the like can be used. As a developing method, it is preferable to use an alkaline aqueous solution such as sodium carbonate or TMAH. Moreover, hardening can also be advanced by heating a pattern cured film further.

露光の位置合わせは、第１の半導体素子２又はキャリア１に形成されたアライメントマークを使用することができる。この際、アライメントマークの認識性を確保するために、感光性樹脂膜は、膜厚５０μｍ時において、４００〜８００ｎｍでの最大透過率が５０％以上であることが好ましく、７０％以上であることがより好ましい。
なお、感光性樹脂膜（封止部）の最大透過率が５０％未満の場合はアライメントマーク認識が困難となるおそれがある。最大透過率が７０％以上であれば、高い位置精度が得られ、高い歩留まりを得ることができる。
上記最大透過率は分光光度計（日立ハイテクノロジーズ（株）製、商品名「Ｕ−３３１０」）を用いて、４００〜８００ｎｍでの透過率を読み取ることで測定することができる。 For alignment of the exposure, alignment marks formed on the first semiconductor element 2 or the carrier 1 can be used. At this time, in order to ensure the alignment mark recognizability, the photosensitive resin film preferably has a maximum transmittance at 400 to 800 nm of 50% or more, and 70% or more when the film thickness is 50 μm. Is more preferable.
Note that when the maximum transmittance of the photosensitive resin film (sealing portion) is less than 50%, the alignment mark recognition may be difficult. If the maximum transmittance is 70% or more, high positional accuracy can be obtained, and a high yield can be obtained.
The maximum transmittance can be measured by reading the transmittance at 400 to 800 nm using a spectrophotometer (manufactured by Hitachi High-Technologies Corporation, trade name “U-3310”).

露光及び現像工程において、電極７を露出する開口部だけでなく、キャリア１を露出する開口部１１を設けることが好ましい。例えば、第１の半導体素子２周辺部に開口部を設けることによってダイシングせずに半導体素子を個片化することができる（図３及び図７）。本工程によって、ダイシング工程による樹脂割れや剥離による歩留まり低下を考慮する必要がなくなり、効率よく、低コストでパッケージを製造することができる。   In the exposure and development process, it is preferable to provide not only the opening for exposing the electrode 7 but also the opening 11 for exposing the carrier 1. For example, by providing an opening in the periphery of the first semiconductor element 2, the semiconductor element can be singulated without dicing (FIGS. 3 and 7). This process eliminates the need to consider the yield reduction due to resin cracking and peeling due to the dicing process, and allows the package to be manufactured efficiently and at low cost.

感光性樹脂膜を開口する際に、第１の半導体素子周辺部の樹脂膜をパターニングしてビア形状の開口部を設けた後に、シード形成とめっき工程によって開口したビアに銅等の導体を充填して、Ｔｈｒｏｕｇｈ Ｍｏｌｄ Ｖｉａ（ＴＭＶ）構造にすることもできる。   When opening the photosensitive resin film, after patterning the resin film in the periphery of the first semiconductor element to provide a via-shaped opening, the via formed by seed formation and plating is filled with a conductor such as copper. Then, a Through Mold Via (TMV) structure may be used.

次いで、隣接する２つの第１の半導体素子２に跨るように、第２の半導体素子４をパターン硬化膜３’の開口部上に搭載する（図４）。このとき第２の半導体素子４は接続用電極部６を介してそれぞれの第１の半導体素子の電極７と電気的に接続される。
複数の第１の半導体素子２を封止した半導体素子封止パッケージ１００をあらかじめ作製することで、第１の半導体素子を個別化した状態で第２の半導体素子を搭載する場合と比較して、第２の半導体素子の搭載時の位置ずれやたわみ等の変形を防ぐことができる。また、第２の半導体素子搭載後も取り扱い性が良好となる。また、露光と現像によって接続用電極部の不要な樹脂が除去されているため、感光性樹脂材料の噛み込みが少ない良好な接続体を得ることができる。 Next, the second semiconductor element 4 is mounted on the opening of the pattern cured film 3 ′ so as to straddle the two adjacent first semiconductor elements 2 (FIG. 4). At this time, the second semiconductor element 4 is electrically connected to the electrode 7 of each first semiconductor element via the connection electrode portion 6.
Compared to the case where the second semiconductor element is mounted in a state where the first semiconductor element is individualized by preparing the semiconductor element sealing package 100 in which the plurality of first semiconductor elements 2 are sealed in advance. It is possible to prevent deformation such as misalignment and deflection when the second semiconductor element is mounted. In addition, the handleability is improved even after mounting the second semiconductor element. In addition, since unnecessary resin in the connection electrode portion is removed by exposure and development, a good connection body with less biting of the photosensitive resin material can be obtained.

第２の半導体素子としては、システムオンパッケージ、シリコンフォトニクスチップ、ＭＥＭＳ、センサーチップ等を用いることができる。
第２の半導体素子は既存のシリコンプロセス技術で得られるため、インターコネクトピッチと幅が、有機基板内に作成される場合と比較して高密度である。そのため、本構造にすることで優れた半導体素子同士のインターコネクト密度を得ることができる。 As the second semiconductor element, a system-on-package, a silicon photonics chip, a MEMS, a sensor chip, or the like can be used.
Since the second semiconductor element is obtained by the existing silicon process technology, the interconnect pitch and width are higher than those formed in the organic substrate. Therefore, by using this structure, an excellent interconnect density between semiconductor elements can be obtained.

接続用電極部６及び電極７としては、例えば、めっきにより形成された金バンプや銅バンプ、さらに銅の上にはんだが形成されたバンプ、研磨処理によって露出された銅等が挙げられる。
接続用電極部６及び電極７は、金ワイヤーを用いて形成される金スタッドバンプ、必要に応じて超音波を併用した熱圧着により電極パッドに固定された金属ボール、めっきや蒸着により形成されたバンプ等でもよい。
接続用電極部６及び電極７は、単一の金属から構成されている必要はなく、複数の金属を含んでもよい。接続用電極部６及び電極７は、それぞれ金、銀、銅、ニッケル、インジウム、パラジウム、スズ、ビスマス等を含んでもよい。また、接続用電極部６及び電極７は、それぞれ複数の金属層を含む積層体であってもよい。 Examples of the connecting electrode portion 6 and the electrode 7 include gold bumps and copper bumps formed by plating, bumps formed by soldering on copper, and copper exposed by polishing.
The electrode part 6 and the electrode 7 for connection were formed by the gold stud bump formed using a gold wire, the metal ball fixed to the electrode pad by thermocompression using ultrasonic waves as necessary, and plating or vapor deposition. A bump or the like may be used.
The connecting electrode portion 6 and the electrode 7 do not need to be made of a single metal, and may include a plurality of metals. The connection electrode portion 6 and the electrode 7 may each contain gold, silver, copper, nickel, indium, palladium, tin, bismuth, or the like. Moreover, the connection electrode part 6 and the electrode 7 may each be a laminate including a plurality of metal layers.

第２の半導体素子４を搭載する際において、開口部を充填するためにパターン硬化膜３’を形成する感光性樹脂材料は熱流動性を有すると好ましい。低荷重で良好な金属接続とボイドを達成できる点で、感光性樹脂材料の露光後の最低溶融粘度が１００００Ｐａ・ｓ以下であることが好ましく、金属接続部に良好な合金形成できる点で５０００Ｐａ・ｓ以下であることがより好ましい。また、電極部の変形を抑制できる点で、感光性樹脂材料の露光後の最低溶融粘度が１０Ｐａ・ｓ以上であることが好ましい。   When mounting the second semiconductor element 4, it is preferable that the photosensitive resin material for forming the pattern cured film 3 ′ to fill the opening has thermal fluidity. It is preferable that the minimum melt viscosity after exposure of the photosensitive resin material is 10,000 Pa · s or less in that a good metal connection and void can be achieved with a low load, and 5000 Pa · in that a good alloy can be formed in the metal connection portion. More preferably, it is s or less. Moreover, it is preferable that the minimum melt viscosity after exposure of the photosensitive resin material is 10 Pa · s or more in that the deformation of the electrode portion can be suppressed.

感光性樹脂材料の最低溶融粘度は、フィルム上に感光性樹脂材料を積層後、露光した硬化膜付きフィルムを用意し、当該フィルムについて、粘弾性測定装置（レオメトリックス・サイエンティフィック・エフ・イー（株）製、商品名「ＡＲＥＳ」）を用いて測定された８０℃〜２００℃における溶融粘度の最低値で読み取ることができる。測定の際、測定プレートは、直径８ｍｍの平行プレートを用い、測定条件は、昇温速度５℃／ｍｉｎ、測定温度−５０℃〜３００℃、周波数１Ｈｚとするとよい。   The minimum melt viscosity of the photosensitive resin material is obtained by laminating the photosensitive resin material on the film, and then preparing an exposed film with a cured film. The viscoelasticity measuring device (Rheometrics Scientific F.E. It can be read by the minimum value of the melt viscosity at 80 ° C. to 200 ° C. measured using a product name “ARES” manufactured by Co., Ltd. At the time of measurement, a parallel plate having a diameter of 8 mm is used as a measurement plate, and measurement conditions are preferably a heating rate of 5 ° C./min, a measurement temperature of −50 ° C. to 300 ° C., and a frequency of 1 Hz.

第２の半導体素子搭載後の第２の半導体素子４と半導体素子封止パッケージ１００の圧着方法としては、個片化した第２の半導体素子４と個片化した半導体素子封止パッケージ１００を接続させる方式、個片化した第２の半導体素子４と、パネル又はウェハに固定された状態の半導体素子封止パッケージ１００を接続させる方式が挙げられ、製造コストと取り扱い性の観点から、後者の方が好ましい。
圧着は通常８０〜３５０℃で３〜３０秒の条件で実施できる。圧着温度が２２０℃よりも低い場合は、リフロー工程によって良好な金属接続状態にすることができる。より効率的にパッケージを製造する観点から、個片化した第２の半導体素子４と、パネル又はウェハ状態の半導体装置１００を１５０℃以下で仮圧着した後、リフロー工程によって金属接続させることが最も好ましい。 As a method of pressing the second semiconductor element 4 and the semiconductor element sealing package 100 after mounting the second semiconductor element, the separated second semiconductor element 4 and the individual semiconductor element sealing package 100 are connected. And a method of connecting the separated second semiconductor element 4 and the semiconductor element sealing package 100 fixed to a panel or a wafer. From the viewpoint of manufacturing cost and handleability, the latter is preferred. Is preferred.
The pressure bonding can usually be performed at 80 to 350 ° C. for 3 to 30 seconds. When the pressure bonding temperature is lower than 220 ° C., a good metal connection state can be achieved by the reflow process. From the viewpoint of more efficiently manufacturing a package, it is most preferable to make a metal connection by a reflow process after temporarily bonding the second semiconductor element 4 that has been singulated and the semiconductor device 100 in a panel or wafer state at 150 ° C. or lower. preferable.

次いで、電極７上にはんだボール等の電気接続のための金属部材９を搭載する（図５）。金属部材９は後述する基板８との接続用部材としての機能を有する。
電気接続のための金属部材９の搭載は市販のＮ２リフロー装置等を用いて容易に行うことができる。 Next, a metal member 9 for electrical connection such as a solder ball is mounted on the electrode 7 (FIG. 5). The metal member 9 functions as a member for connecting to the substrate 8 described later.
Mounting of the metal member 9 for electrical connection can be easily performed using a commercially available N 2 reflow apparatus or the like.

本発明の半導体装置の製造方法は、キャリア１を剥離する工程を含むことが好ましい。
キャリアを剥離する工程のタイミングは、封止された半導体素子の取り扱い性に問題がなければ特に限定はしないが、電気接続のための金属部材９を搭載（図５）した後（工程（IV）の後）にキャリア１を剥離することが好ましい。一方で、反りや取り扱い性、キャリア１上に形成される封止部の耐熱性に問題があり、第２の半導体素子を搭載する工程（図４）で良好な接続が困難である場合、感光性樹脂材料をパターニング（図３）した後（工程（III）の後）にキャリア１を剥離することができる。
キャリアの剥離方法としては特に制限しないがピール剥離、スライド剥離、加熱剥離等が挙げられる。また、剥離した後に溶剤やプラズマ等で洗浄することもできる。 The method for manufacturing a semiconductor device of the present invention preferably includes a step of peeling the carrier 1.
The timing of the carrier peeling process is not particularly limited as long as there is no problem in the handling of the sealed semiconductor element, but after mounting the metal member 9 for electrical connection (FIG. 5) (process (IV) The carrier 1 is preferably peeled off after). On the other hand, if there is a problem in warpage, handling property, and heat resistance of the sealing portion formed on the carrier 1, and it is difficult to make a good connection in the process of mounting the second semiconductor element (FIG. 4), After patterning the conductive resin material (FIG. 3) (after step (III)), the carrier 1 can be peeled off.
Although it does not restrict | limit especially as a peeling method of a carrier, Peel peeling, slide peeling, heat peeling, etc. are mentioned. Moreover, it can also wash | clean with a solvent, plasma, etc. after peeling.

上記方法によって作製した半導体装置１０１の上面図を図９に示す。
本発明の半導体装置は、半導体素子同士（第１の半導体素子）の伝送に半導体素子（第２の半導体素子）を使用するため高速通信が可能となる。 A top view of the semiconductor device 101 manufactured by the above method is shown in FIG.
Since the semiconductor device of the present invention uses a semiconductor element (second semiconductor element) for transmission between semiconductor elements (first semiconductor element), high-speed communication is possible.

図６は、キャリア１を剥離した半導体装置１０１と基板８を金属部材９を介して搭載し、半導体装置１０１及び基板８の間隙をアンダーフィル１０で充填した状態を示す断面図である。
基板８としては特に限定しないが、シリコン、ガラスインターポーザ、微細配線を有する有機インターポーザ、半導体素子、ガラスが埋め込まれた有機基板、微細配線基板等が挙げられる。
アンダーフィル１０の充填方法は特に限定しないが、半導体装置１０１もしくは基板８にアンダーフィルを塗布した後に、半導体装置１０１と基板８とを接続する方法や、半導体装置１０１と基板８とを圧着した後にモールド又はキャピラリー方式でアンダーフィルを注入する方法が挙げられる。 FIG. 6 is a cross-sectional view showing a state where the semiconductor device 101 from which the carrier 1 has been peeled off and the substrate 8 are mounted via the metal member 9 and the gap between the semiconductor device 101 and the substrate 8 is filled with the underfill 10.
Although it does not specifically limit as the board | substrate 8, Silicon, a glass interposer, the organic interposer which has fine wiring, a semiconductor element, the organic board | substrate with which glass was embedded, a fine wiring board, etc. are mentioned.
A method for filling the underfill 10 is not particularly limited. After the underfill is applied to the semiconductor device 101 or the substrate 8, a method for connecting the semiconductor device 101 and the substrate 8, or after the semiconductor device 101 and the substrate 8 are pressure-bonded. There is a method of injecting underfill by a mold or capillary method.

以上、本発明の一実施形態に係る半導体装置の製造方法について説明したが、本発明は上述した実施形態に限定されるものではなく、その趣旨を逸脱しない範囲で適宜変更を行ってもよい。   The method for manufacturing a semiconductor device according to an embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and modifications may be made as appropriate without departing from the spirit of the present invention.

１ キャリア
２ 第１の半導体素子
３ 感光性樹脂膜
３’ パターン硬化膜（封止部）
４ 第２の半導体素子
６ 接続用電極部
７ 電極（金属接続部）
８ 基板
９ 電気接続のための金属部材
１０ アンダーフィル
１１ キャリアを露出する開口部
１２ 半導体素子積層体
１００ 半導体素子封止パッケージ
１０１ 半導体装置 DESCRIPTION OF SYMBOLS 1 Carrier 2 1st semiconductor element 3 Photosensitive resin film 3 'Pattern cured film (sealing part)
4 Second semiconductor element 6 Electrode portion for connection 7 Electrode (metal connection portion)
DESCRIPTION OF SYMBOLS 8 Board | substrate 9 Metal member for electrical connection 10 Underfill 11 Opening part which exposes carrier 12 Semiconductor element laminated body 100 Semiconductor element sealing package 101 Semiconductor device

Claims (6)

（Ｉ）キャリア上に複数の第１の半導体素子を固定する工程と、
（II）前記第１の半導体素子を感光性樹脂材料で一括封止して感光性樹脂膜を形成する工程と、
（III）前記感光性樹脂膜を露光及び現像して、前記第１の半導体素子の電極部分を開口する開口部を形成する工程と、
（IV）前記開口部において、前記複数の第１の半導体素子の２以上の半導体素子に跨るように、第１の半導体素子の電極と第２の半導体素子を接続用電極を介して電気的に接続する工程とを備える半導体装置の製造方法。 (I) fixing a plurality of first semiconductor elements on a carrier;
(II) forming a photosensitive resin film by collectively sealing the first semiconductor element with a photosensitive resin material;
(III) exposing and developing the photosensitive resin film to form an opening for opening the electrode portion of the first semiconductor element;
(IV) In the opening, the electrode of the first semiconductor element and the second semiconductor element are electrically connected via the connection electrode so as to straddle two or more semiconductor elements of the plurality of first semiconductor elements. A method for manufacturing a semiconductor device comprising the step of connecting. さらに、前記キャリアを剥離する工程を備える請求項１に記載の半導体装置の製造方法。   Furthermore, the manufacturing method of the semiconductor device of Claim 1 provided with the process of peeling the said carrier. 前記感光性樹脂材料が、フィルム状材料又はシート状材料である請求項１又は２のいずれか一項に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the photosensitive resin material is a film-like material or a sheet-like material. 前記（III）の工程で形成するパターン硬化膜の膜厚が５０〜４００μｍである請求項１〜３のいずれか一項に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein a thickness of the pattern cured film formed in the step (III) is 50 to 400 µm. 前記感光性樹脂材料がネガ型である請求項１〜４のいずれか一項に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the photosensitive resin material is a negative type. 請求項１〜５のいずれか一項に記載の製造方法を用いて製造された半導体装置。   The semiconductor device manufactured using the manufacturing method as described in any one of Claims 1-5.
JP2015097217A 2015-05-12 2015-05-12 Semiconductor device and manufacturing method of semiconductor device Active JP6569288B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015097217A JP6569288B2 (en) 2015-05-12 2015-05-12 Semiconductor device and manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015097217A JP6569288B2 (en) 2015-05-12 2015-05-12 Semiconductor device and manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2016213371A true JP2016213371A (en) 2016-12-15
JP6569288B2 JP6569288B2 (en) 2019-09-04

Family

ID=57551783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015097217A Active JP6569288B2 (en) 2015-05-12 2015-05-12 Semiconductor device and manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP6569288B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243604A (en) * 2002-02-13 2003-08-29 Sony Corp Electronic component and manufacturing method of electronic component
JP2007103716A (en) * 2005-10-05 2007-04-19 Sony Corp Semiconductor device and manufacturing method thereof
JP2012169440A (en) * 2011-02-14 2012-09-06 Fujitsu Semiconductor Ltd Semiconductor device and manufacturing method of the same
JP2014086598A (en) * 2012-10-24 2014-05-12 Hitachi Chemical Co Ltd Method of manufacturing semiconductor device, semiconductor device, and photosensitive resin composition
JP2015510686A (en) * 2012-01-20 2015-04-09 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． Method and apparatus for substrate core layer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243604A (en) * 2002-02-13 2003-08-29 Sony Corp Electronic component and manufacturing method of electronic component
JP2007103716A (en) * 2005-10-05 2007-04-19 Sony Corp Semiconductor device and manufacturing method thereof
JP2012169440A (en) * 2011-02-14 2012-09-06 Fujitsu Semiconductor Ltd Semiconductor device and manufacturing method of the same
JP2015510686A (en) * 2012-01-20 2015-04-09 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． Method and apparatus for substrate core layer
JP2014086598A (en) * 2012-10-24 2014-05-12 Hitachi Chemical Co Ltd Method of manufacturing semiconductor device, semiconductor device, and photosensitive resin composition

Also Published As

Publication number Publication date
JP6569288B2 (en) 2019-09-04

Similar Documents

Publication Publication Date Title
US10867897B2 (en) PoP device
TWI651828B (en) Chip package structure and method of manufacturing same
US8410614B2 (en) Semiconductor device having a semiconductor element buried in an insulating layer and method of manufacturing the same
US8379400B2 (en) Interposer mounted wiring board and electronic component device
US9040361B2 (en) Chip scale package with electronic component received in encapsulant, and fabrication method thereof
TWI476888B (en) Package substrate having embedded via hole medium layer and fabrication method thereof
TWI517351B (en) Interposer package apparatus and method for constructing interposer assembly
TWI600129B (en) Chip on glass structure
JP2019512168A (en) Fan-out 3D package structure embedded in silicon substrate
JP2008218926A (en) Semiconductor and method of manufacturing the same
KR102647008B1 (en) Fan-out packages and methods of forming the same
TW200901435A (en) Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
TW200847418A (en) CMOS image sensor chip scale package with die receiving opening and method of the same
JP2007110117A (en) Wafer level chip scale package of image sensor, and method of manufacturing same
TW201436161A (en) Semiconductor package and method of manufacture
JP2009302505A (en) Semiconductor device and method of manufacturing semiconductor device
JP2010087229A (en) Semiconductor module, method of manufacturing semiconductor module, and portable device
TWI688067B (en) Semiconductor device and its manufacturing method
JP6792322B2 (en) Semiconductor devices and methods for manufacturing semiconductor devices
JP6569288B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2008218521A (en) Circuit device and method for manufacturing the same
JP2018088505A (en) Semiconductor device and manufacturing method for the same
JP2016213372A (en) Semiconductor device and method of manufacturing the same
JP2011049606A (en) Method of manufacturing semiconductor module
US10157839B1 (en) Interconnect structure and manufacturing method thereof

Legal Events

Date Code Title Description
RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20171204

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180402

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20181130

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20181225

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190222

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190709

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190722

R151 Written notification of patent or utility model registration

Ref document number: 6569288

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350