JP2005019938A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005019938A
JP2005019938A JP2003369008A JP2003369008A JP2005019938A JP 2005019938 A JP2005019938 A JP 2005019938A JP 2003369008 A JP2003369008 A JP 2003369008A JP 2003369008 A JP2003369008 A JP 2003369008A JP 2005019938 A JP2005019938 A JP 2005019938A
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layer
semiconductor device
rewiring
semiconductor
connection pad
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Hiroyasu Sadabetto
裕康 定別当
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Casio Computer Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To downsize a semiconductor device having upper-layer wiring on the whole including a circuit board mounted with it. <P>SOLUTION: A semiconductor constitution body 2, referred to CSP, is provided at the center part of the top surface of a base plate 1 and a rectangular frame type insulating layer 14 is provided around it; and an upper-layer insulating film 15 is provided on their top surfaces and upper-layer rewiring 17 is provided on its top surface while connected to a columnar electrode 12 of the semiconductor constitution body 2. A lower-layer insulating film 22 is provided on the reverse surface of the base plate 1 and lower-layer rewiring 24 is provided on its reverse surface while connected to the upper-layer rewiring 17 through a vertical conduction part 28. Then, an electronic component is connected to the lower-layer rewiring 24 and mounted to make electronic equipment smaller in size, and the wiring length is made shortest to suppress circuit characteristic deterioration. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

近年、携帯電話に代表されるような携帯型電子機器の小型化に相俟ってＣＳＰ(chip size package)と呼ばれる半導体装置が開発されている。このＣＳＰは、複数の外部接続用の接続パッドが形成されたベアーの半導体装置の上面にパッシベーション膜（中間絶縁膜）を設け、このパッシベーション膜の各接続パッドの対応部に開口部を形成し、該開口部を介して各接続パッドに接続される再配線を形成し、各再配線の他端部側に柱状の外部接続用電極を形成するとともに、各外部接続用電極間に封止材を充填したものである。このような、ＣＳＰによれば、各柱状の外部接続用電極上に半田ボールを形成しておくことにより、接続端子を有する回路基板にフェースダウン方式でボンディングすることができ、実装面積をほぼベアーの半導体装置と同一のサイズとすることが可能となるので、従来のワイヤーボンディング等を用いたフェースアップ方式のボンディング方法に比し、電子機器を大幅に小型化することが可能である。このような、ＣＳＰにおいて、生産性を高めるために、ウエハ状態の半導体基板にパッシベーション膜、再配線、外部接続用電極、および封止材を形成し、さらに、封止材で覆われずに露出された外部接続用電極の上面に半田ボールを設けた後、ダイシングラインで切断するようにしたものがある（例えば、特許文献１参照）。   In recent years, a semiconductor device called a CSP (chip size package) has been developed in conjunction with downsizing of a portable electronic device represented by a mobile phone. This CSP is provided with a passivation film (intermediate insulating film) on the upper surface of a bare semiconductor device in which a plurality of connection pads for external connection are formed, and an opening is formed in a corresponding portion of each connection pad of the passivation film. A rewiring connected to each connection pad is formed through the opening, a columnar external connection electrode is formed on the other end of each rewiring, and a sealing material is provided between the external connection electrodes. Filled. According to such CSP, by forming solder balls on each columnar external connection electrode, it is possible to bond to a circuit board having connection terminals by a face-down method, and the mounting area is almost bare. Therefore, the electronic device can be significantly reduced in size as compared with a conventional face-up bonding method using wire bonding or the like. In such a CSP, in order to increase productivity, a passivation film, a rewiring, an external connection electrode, and a sealing material are formed on a semiconductor substrate in a wafer state, and further exposed without being covered with the sealing material. There is one in which a solder ball is provided on the upper surface of the external connection electrode and then cut by a dicing line (see, for example, Patent Document 1).

特開２００１−１６８１２８号公報JP 2001-168128 A

ところで、上記従来の半導体装置では、集積化が進むに従って、外部接続用電極の数が増加すると、次のような問題があった。すなわち、上述した如く、ＣＳＰは、ベアーの半導体装置の上面に外部接続用電極を配列するので、通常は、マトリクス状に配列するのであるが、そのために、外部接続用電極数の多い半導体装置の場合には、外部接続用電極のサイズおよびピッチが極端に小さくなってしまう欠点を有しており、このため、ベアーの半導体装置のサイズの割に外部接続用電極が多いものには適用できないものであった。すなわち、外部接続用電極のサイズおよびピッチが極端に小さくなれば、回路基板との位置合わせが困難であるばかりでなく、接合強度が不足する、ボンディング時に電極間の短絡が発生する、通常はシリコン基板からなる半導体基板と回路基板の線膨張係数の差に起因して発生する応力により外部接続用電極が破壊される等の致命的な問題が発生するのである。   By the way, the conventional semiconductor device has the following problems when the number of external connection electrodes increases as integration increases. That is, as described above, the CSP arranges the external connection electrodes on the upper surface of the bare semiconductor device. Therefore, the CSP is usually arranged in a matrix. For this reason, the CSP has a large number of external connection electrodes. In some cases, the size and pitch of the external connection electrodes become extremely small, and therefore, this is not applicable to the case where the number of external connection electrodes is large for the size of the bare semiconductor device. Met. That is, if the size and pitch of the electrodes for external connection become extremely small, not only alignment with the circuit board is difficult, but also the bonding strength is insufficient, and a short circuit between the electrodes occurs during bonding, usually silicon A fatal problem such as destruction of the external connection electrode occurs due to the stress generated due to the difference between the linear expansion coefficients of the semiconductor substrate and the circuit board.

また、上記従来の半導体装置では、上述の如く、回路基板にフェースダウン方式でボンディングすることができ、実装面積をほぼベアーの半導体装置と同一のサイズとすることが可能となるので、従来のワイヤーボンディング等を用いたフェースアップ方式のボンディング方法に比し、電子機器を大幅に小型化することが可能であるが、それでも小型化に限界があった。すなわち、回路基板に他の必要な回路、例えば、インダクタ回路やアンテナ回路を形成し、これらの回路に上記従来の半導体装置を接続すると、これらが平面的に配置されるため、小型化に限界があった。また、平面的に配置される関係から、配線長が増大し、インピーダンス（浮遊容量等）の増加等の問題が生じ、回路特性が劣化することがあった。   Further, in the conventional semiconductor device, as described above, it can be bonded to the circuit board in a face-down manner, and the mounting area can be made almost the same size as the bare semiconductor device. Compared to the face-up type bonding method using bonding or the like, the electronic device can be greatly downsized, but there is still a limit to downsizing. That is, when other necessary circuits such as an inductor circuit and an antenna circuit are formed on the circuit board, and the conventional semiconductor device is connected to these circuits, these are arranged in a plane, so there is a limit to miniaturization. there were. In addition, due to the planar arrangement, the wiring length increases, causing problems such as an increase in impedance (such as stray capacitance), and circuit characteristics may deteriorate.

そこで、この発明は、外部接続用電極の数が増加しても、そのサイズおよびピッチを必要な大きさにすることが可能となり、且つ、電子機器のより一層の小型化が可能で、配線長を最短として回路特性劣化を抑制することが可能となる新規な半導体装置およびその製造方法を提供することを目的とする。   Therefore, even if the number of external connection electrodes increases, the present invention makes it possible to make the size and pitch necessary, and to further reduce the size of the electronic device, and to increase the wiring length. It is an object of the present invention to provide a novel semiconductor device and a method of manufacturing the same that can suppress deterioration of circuit characteristics.

請求項１に記載の発明は、ベース板と、該ベース板上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する少なくとも１つの半導体構成体と、該半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、該絶縁層上に、少なくとも一部が前記半導体構成体の外部接続用電極に接続されて設けられ、且つ、接続パッド部を有する少なくとも１層の上層再配線と、前記ベース板下に設けられた少なくとも１層の下層再配線と、前記絶縁層および前記ベース板に設けられた貫通孔内に前記上層再配線のうちのいずれかの層の上層再配線と前記下層再配線のうちのいずれかの層の下層再配線とを接続するように設けられた上下導通部と、を備えていることを特徴とするものである。
請求項２に記載の発明は、請求項１に記載の発明において、前記ベース板上に前記半導体構成体が複数個相互に離間して設けられていることを特徴とするものである。
請求項３に記載の発明は、請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とするものである。
請求項４に記載の発明は、請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッド部を有する再配線を有するものであることを特徴とするものである。
請求項５に記載の発明は、請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッドを有するものであることを特徴とするものである。
請求項６に記載の発明は、請求項１に記載の発明において、前記最上層の上層再配線の接続パッド部を除く部分を覆う上層絶縁膜を有することを特徴とするものである。
請求項７に記載の発明は、請求項６に記載の発明において、前記最上層の上層再配線の接続パッド部上に半田ボールが設けられていることを特徴とするものである。
請求項８に記載の発明は、請求項６に記載の発明において、前記上層絶縁膜上に電子部品が前記最上層の上層再配線の接続パッド部に接続されて搭載されていることを特徴とするものである。
請求項９に記載の発明は、請求項１に記載の発明において、前記最下層の下層再配線の接続パッド部を除く部分を覆う下層絶縁膜を有することを特徴とするものである。
請求項１０に記載の発明は、請求項９に記載の発明において、前記最下層の下層再配線の接続パッド部下に半田ボールが設けられていることを特徴とするものである。
請求項１１に記載の発明は、請求項９に記載の発明において、前記下層絶縁膜下に電子部品が前記最下層の下層再配線の接続パッド部に接続されて搭載されていることを特徴とするものである。
請求項１２に記載の発明は、請求項１１に記載の発明において、前記下層絶縁膜下の少なくとも一部に平坦な吸着ヘッド吸着用領域が設けられていることを特徴とするものである。
請求項１３に記載の発明は、請求項１２に記載の発明において、前記電子部品は前記下層絶縁膜下の周辺部に搭載され、前記下層絶縁膜の下面ほぼ中央部が前記吸着ヘッド吸着用領域とされていることを特徴とするものである。
請求項１４に記載の発明は、請求項１２に記載の発明において、前記電子部品は複数個で前記下層絶縁膜の下面ほぼ中央部を含む領域に搭載され、前記複数個の電子部品は封止膜で覆われ、該封止膜の下面が前記吸着ヘッド吸着用領域とされていることを特徴とするものである。
請求項１５に記載の発明は、請求項１２に記載の発明において、前記電子部品は複数個で前記下層絶縁膜の下面全体に搭載され、前記下層絶縁膜の下面ほぼ中央部に搭載された前記電子部品は封止膜で覆われ、該封止膜の下面に平板が設けられ、該平板の下面は前記吸着ヘッド吸着用領域とされていることを特徴とするものである。
請求項１６に記載の発明は、請求項１に記載の発明において、前記下層再配線の少なくとも一部または前記上層再配線の一部により薄膜回路素子が形成されていることを特徴とするものである。
請求項１７に記載の発明は、請求項１６に記載の発明において、前記薄膜回路素子は、インダクタ回路、またはアンテナ回路、のいずれかを含むことを特徴とするものである。
請求項１８に記載の発明は、請求項１に記載の発明において、前記ベース板の上面にグラウンド層が設けられていることを特徴とするものである。
請求項１９に記載の発明は、請求項１８に記載の発明において、前記グラウンド層は前記上下導通部または前記下層再配線に接続されていることを特徴とするものである。
請求項２０に記載の発明は、少なくとも、ベース板と、該ベース板上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する、少なくとも１つの半導体構成体と、該半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、該絶縁層上に少なくとも一部が前記半導体構成体の外部接続用電極に接続されて設けられ、且つ、接続パッド部を有する、少なくとも１層の上層再配線と、を備えた第１の半導体装置と、ベース板と、該ベース板上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する、少なくとも１つの半導体構成体と、該半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、該絶縁層上に少なくとも一部が前記半導体構成体の外部接続用電極に接続されて設けられ、且つ、接続パッド部を有する、少なくとも１層の上層再配線と、前記ベース板下に設けられた少なくとも１層の下層再配線と、前記絶縁層および前記ベース板に設けられた貫通孔内に前記上層再配線のうちのいずれかの層の上層再配線と前記下層再配線のうちのいずれかの層の下層再配線とを接続するように設けられた上下導通部と、を備えた第２の半導体装置と、を備え、前記第１の半導体装置上に、一乃至複数個の前記第２の半導体装置が互いに接続されて積層され、前記積層された第１の半導体装置と第２の半導体装置の間、または、複数の前記第２の半導体装置の間、の接続部において、上側の半導体装置の前記最下層の下層再配線の接続パッド部と、下側の半導体装置の前記最上層の上層再配線の接続パッド部と、が接続されていることを特徴とするものである。
請求項２１に記載の発明は、請求項２０に記載の発明において、前記上側の半導体装置と、前記下側の半導体装置とが、その間に介在された接着層を介して接着されていることを特徴とするものである。
請求項２２に記載の発明は、請求項２１に記載の発明において、前記上側の半導体装置の最下層の下層再配線の接続パッド部と、前記下側の半導体装置の最上層の上層再配線の接続パッド部とは、前記接着層に設けられた貫通孔内に設けられた導電材を介して接続されていることを特徴とするものである。
請求項２３に記載の発明は、請求項２０に記載の発明において、前記第１および第２の半導体装置は、前記最上層の上層再配線の接続パッド部を除く部分を覆う上層絶縁膜を有することを特徴とするものである。
請求項２４に記載の発明は、請求項２３に記載の発明において、前記積層された第２の半導体装置の最上層の半導体装置の、前記最上層の上層再配線の接続パッド部上に半田ボールが設けられていることを特徴とするものである。
請求項２５に記載の発明は、ベース板上に、各々が半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する複数の半導体構成体を相互に離間させて配置する工程と、前記半導体構成体の周囲における前記ベース板上に絶縁層を形成する工程と、接続パッド部を有し、且つ、少なくとも一部がいずれかの前記半導体構成体の前記外部接続用電極に接続される少なくとも１層の上層再配線を、該上層再配線のうち、最上層の上層再配線の接続パッド部が前記絶縁層上に配置されるように形成する工程と、前記ベース板下に少なくとも１層の下層再配線を形成する工程と、前記絶縁層および前記ベース板に形成された貫通孔内に前記上層再配線のうちのいずれかの層の上層再配線と前記下層再配線のうちのいずれかの層の下層再配線とを接続する上下導通部を形成する工程と、前記半導体構成体間における前記絶縁層および前記ベース板を切断して前記最上層の上層再配線の接続パッド部が前記絶縁層上に配置された半導体装置を複数個得る工程と、を有することを特徴とするものである。
請求項２６に記載の発明は、請求項２５に記載の発明において、前記最下層の上層再配線と、前記最上層の下層再配線と、前記上下導通部と、を同時に形成することを特徴とするものである。
請求項２７に記載の発明は、請求項２５に記載の発明において、前記最下層の上層再配線と、前記最上層の下層再配線と、を同時に形成することを特徴とするものである。
請求項２８に記載の発明は、請求項２５に記載の発明において、前記最下層の上層再配線と、前記最上層の下層再配線と、を別々に形成することを特徴とするものである。
請求項２９に記載の発明は、請求項２７または２８に記載の発明において、前記最下層の上層再配線および前記最上層の下層再配線を形成した後に、前記絶縁層および前記ベース板に前記貫通孔を形成し、該貫通孔内に導電性ペーストからなる前記上下導通部を形成することを特徴とするものである。
請求項３０に記載の発明は、請求項２５に記載の発明において、前記切断は、前記半導体構成体が複数個含まれるように切断することを特徴とするものである。
請求項３１に記載の発明は、請求項２５に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とするものである。
請求項３２に記載の発明は、請求項２５に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッド部を有する再配線を有するものであることを特徴とするものである。
請求項３３に記載の発明は、請求項２５に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッドを有するものであることを特徴とするものである。
請求項３４に記載の発明は、請求項２５に記載の発明において、前記最上層の上層再配線の接続パッド部を除く部分を覆う上層絶縁膜を形成する工程を有することを特徴とするものである。
請求項３５に記載の発明は、請求項３４に記載の発明において、前記最上層の上層再配線の接続パッド部上に半田ボールを形成する工程を有することを特徴とするものである。
請求項３６に記載の発明は、請求項３４に記載の発明において、前記上層絶縁膜上に電子部品を前記上層再配線の接続パッド部に接続させて搭載する工程を有することを特徴とするものである。
請求項３７に記載の発明は、請求項２５に記載の発明において、前記最下層の下層再配線の接続パッド部を除く部分を覆う下層絶縁膜を形成する工程を有することを特徴とするものである。
請求項３８に記載の発明は、請求項３７に記載の発明において、前記最下層の下層再配線の接続パッド部下に半田ボールを形成する工程を有することを特徴とするものである。
請求項３９に記載の発明は、請求項３７に記載の発明において、前記下層絶縁膜下に電子部品を前記最下層の下層再配線の接続パッド部に接続させて搭載する工程を有することを特徴とするものである。
請求項４０に記載の発明は、請求項３８に記載の発明において、前記下層絶縁膜下の少なくとも一部に平坦な吸着ヘッド吸着用領域を形成する工程を有することを特徴とするものである。
請求項４１に記載の発明は、請求項２５に記載の発明において、前記下層再配線の少なくとも一部または前記上層再配線の一部により薄膜回路素子を形成することを特徴とするものである。
請求項４２に記載の発明は、請求項４１に記載の発明において、前記薄膜回路素子は、インダクタ回路、またはアンテナ回路、のいずれかを含むことを特徴とするものである。
請求項４３に記載の発明は、請求項２５に記載の発明において、前記ベース板の上面にグラウンド層を形成する工程を有することを特徴とするものである。
請求項４４に記載の発明は、請求項４３に記載の発明において、前記上下導通部または前記最上層の下層再配線を形成するとき、前記上下導通部または前記最上層の下層再配線を前記グラウンド層に接続することを特徴とするものである。
請求項４５に記載の発明は、少なくとも、ベース板と、該ベース板上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する、少なくとも１つの半導体構成体と、該半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、該絶縁層上に少なくとも一部が前記半導体構成体の外部接続用電極に接続されて設けられ、且つ、接続パッド部を有する、少なくとも１層の上層再配線と、を備えた第１の半導体装置と、ベース板と、該ベース板上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する、少なくとも１つの半導体構成体と、該半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、該絶縁層上に少なくとも一部が前記半導体構成体の外部接続用電極に接続されて設けられ、且つ、接続パッド部を有する、少なくとも１層の上層再配線と、前記ベース板下に設けられた少なくとも１層の下層再配線と、前記絶縁層および前記ベース板に設けられた貫通孔内に前記上層再配線のうちのいずれかの層の上層再配線と前記下層再配線のうちのいずれかの層の下層再配線とを接続するように設けられた上下導通部と、を備えた第２の半導体装置と、を備え、前記第１の半導体装置上に、一乃至複数個の前記第２の半導体装置を積層し、積層する前記第１の半導体装置と第２の半導体装置の間、または、複数の前記第２の半導体装置の間において、上側の半導体装置の最下層の下層再配線の接続パッド部と下側の半導体装置の最上層の上層再配線の接続パッド部とを接続する工程を有することを特徴とするものである。
請求項４６に記載の発明は、請求項４５に記載の発明において、前記第１の半導体装置および第２の半導体装置を、その各間に介在された接着層を介して一度に接着する工程を有することを特徴とするものである。
請求項４７に記載の発明は、請求項４６に記載の発明において、前記接着工程において、前記上側の半導体装置の最下層の下層再配線の接続パッド部と、前記下側の半導体装置の最上層の上層再配線の接続パッド部とを、前記接着層に設けられた貫通孔内に設けられた導電材を介して接続することを特徴とするものである。
請求項４８に記載の発明は、請求項４５に記載の発明において、前記第１および第２の半導体装置は、前記最上層の上層再配線の接続パッド部を除く部分を覆う上層絶縁膜を有することを特徴とするものである。
請求項４９に記載の発明は、請求項４５に記載の発明において、前記第１および第２の半導体装置を積層した後に、前記積層された第２の半導体装置の最上層の半導体装置の、前記最上層の上層再配線の接続パッド部上に半田ボールを形成する工程を有することを特徴とするものである。 The invention according to claim 1 includes a base plate, at least one semiconductor structure provided on the base plate and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, An insulating layer provided on the base plate around the semiconductor structure; and at least a part of the insulating layer provided on the insulating layer connected to an external connection electrode of the semiconductor structure; and a connection pad portion An upper layer rewiring having at least one layer, at least one lower layer rewiring provided under the base plate, and in the through hole provided in the insulating layer and the base plate, A vertical conduction part provided to connect an upper layer rewiring of any layer and a lower layer rewiring of any one of the lower layer rewirings, .
According to a second aspect of the present invention, in the first aspect of the present invention, a plurality of the semiconductor structural bodies are provided on the base plate so as to be separated from each other.
According to a third aspect of the present invention, in the first aspect of the present invention, the semiconductor structure has a columnar electrode as the external connection electrode.
The invention according to claim 4 is the invention according to claim 1, wherein the semiconductor structure has a rewiring having a connection pad portion as the external connection electrode. is there.
According to a fifth aspect of the invention, in the first aspect of the invention, the semiconductor structure has a connection pad as the external connection electrode.
According to a sixth aspect of the present invention, in the first aspect of the present invention, an upper layer insulating film that covers a portion of the uppermost upper layer rewiring other than the connection pad portion is provided.
According to a seventh aspect of the invention, in the sixth aspect of the invention, a solder ball is provided on a connection pad portion of the uppermost upper layer rewiring.
The invention according to claim 8 is characterized in that, in the invention according to claim 6, an electronic component is mounted on the upper insulating film while being connected to a connection pad portion of the uppermost upper layer rewiring. To do.
The invention according to claim 9 is the invention according to claim 1, further comprising a lower insulating film that covers a portion of the lowermost lower layer rewiring except a connection pad portion.
According to a tenth aspect of the present invention, in the ninth aspect of the invention, a solder ball is provided below a connection pad portion of the lower layer lower layer rewiring.
The invention according to claim 11 is the invention according to claim 9, wherein an electronic component is mounted under the lower insulating film connected to a connection pad portion of the lowermost lower layer rewiring. To do.
A twelfth aspect of the invention is characterized in that, in the invention of the eleventh aspect, a flat suction head suction region is provided at least partially under the lower insulating film.
According to a thirteenth aspect of the present invention, in the twelfth aspect of the present invention, the electronic component is mounted on a peripheral portion below the lower insulating film, and a substantially central portion of the lower surface of the lower insulating film is in the suction head suction region. It is characterized by being said.
According to a fourteenth aspect of the present invention, in the twelfth aspect of the present invention, a plurality of the electronic components are mounted in a region including a substantially central portion of the lower surface of the lower insulating film, and the plurality of electronic components are sealed. It is covered with a film, and the lower surface of the sealing film is the suction head suction region.
According to a fifteenth aspect of the present invention, in the invention according to the twelfth aspect, a plurality of the electronic components are mounted on the entire lower surface of the lower insulating film, and are mounted substantially at the center of the lower surface of the lower insulating film. The electronic component is covered with a sealing film, a flat plate is provided on the lower surface of the sealing film, and the lower surface of the flat plate is used as the suction head suction region.
The invention according to claim 16 is the invention according to claim 1, wherein a thin film circuit element is formed by at least a part of the lower layer rewiring or a part of the upper layer rewiring. is there.
The invention according to claim 17 is the invention according to claim 16, wherein the thin film circuit element includes either an inductor circuit or an antenna circuit.
The invention described in claim 18 is the invention described in claim 1, characterized in that a ground layer is provided on the upper surface of the base plate.
The invention according to claim 19 is the invention according to claim 18, wherein the ground layer is connected to the vertical conduction part or the lower layer rewiring.
The invention according to claim 20 includes at least one semiconductor structure having at least a base plate, a semiconductor substrate, and a plurality of external connection electrodes provided on the semiconductor substrate. A body, an insulating layer provided on the base plate around the semiconductor structure, and at least a part of the insulating layer connected to an external connection electrode of the semiconductor structure, and connected A first semiconductor device having at least one upper layer rewiring having a pad portion; a base plate; and a semiconductor substrate and a plurality of semiconductor substrates provided on the semiconductor substrate. At least one semiconductor structure having a plurality of external connection electrodes, an insulating layer provided on the base plate around the semiconductor structure, and at least a part of the semiconductor structure on the insulating layer. At least one upper layer redistribution provided to be connected to an external connection electrode of the body and having a connection pad portion; at least one lower layer redistribution provided under the base plate; and the insulating layer And an upper layer rewiring of any layer of the upper layer rewiring and a lower layer rewiring of any layer of the lower layer rewiring are provided in a through hole provided in the base plate. And a second semiconductor device having a vertical conduction portion, wherein one or a plurality of the second semiconductor devices are connected to each other and stacked on the first semiconductor device, Connection pad portion of the lower layer lower layer rewiring of the upper semiconductor device in a connection portion between the first semiconductor device and the second semiconductor device, or between the plurality of second semiconductor devices And the uppermost layer of the lower semiconductor device A connection pad portions of the layer rewiring, is characterized in that is connected.
The invention according to claim 21 is the invention according to claim 20, wherein the upper semiconductor device and the lower semiconductor device are bonded via an adhesive layer interposed therebetween. It is a feature.
According to a twenty-second aspect of the invention, in the invention of the twenty-first aspect, the connection pad portion of the lowermost layer rewiring of the upper semiconductor device and the upper layer rewiring of the uppermost layer of the lower semiconductor device. The connection pad portion is connected through a conductive material provided in a through hole provided in the adhesive layer.
According to a twenty-third aspect of the present invention, in the twentieth aspect, the first and second semiconductor devices have an upper insulating film that covers a portion excluding the connection pad portion of the uppermost upper layer rewiring. It is characterized by this.
According to a twenty-fourth aspect of the present invention, in the invention of the twenty-third aspect, the solder ball is placed on the connection pad portion of the uppermost upper layer rewiring of the uppermost semiconductor device of the stacked second semiconductor device. Is provided.
According to a twenty-fifth aspect of the present invention, there is provided a step of disposing a plurality of semiconductor structures each having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate on the base plate so as to be separated from each other. A step of forming an insulating layer on the base plate around the semiconductor structure, and a connection pad portion, and at least a part of which is connected to the external connection electrode of the semiconductor structure Forming at least one upper redistribution layer so that a connection pad portion of the uppermost upper layer redistribution of the upper redistribution layers is disposed on the insulating layer; and Forming a lower layer rewiring of a layer, and any one of the upper layer rewiring and the lower layer rewiring of any one of the upper layer rewirings in the through holes formed in the insulating layer and the base plate Some layers below A step of forming a vertical conduction part for connecting the wiring, and the insulating layer and the base plate between the semiconductor constructs are cut, and a connection pad part of the uppermost upper layer rewiring is disposed on the insulating layer. And a step of obtaining a plurality of semiconductor devices.
The invention of claim 26 is characterized in that, in the invention of claim 25, the lowermost layer upper layer rewiring, the uppermost layer lower layer rewiring, and the vertical conduction portion are formed simultaneously. To do.
According to a twenty-seventh aspect of the present invention, in the invention of the twenty-fifth aspect, the lowermost layer upper layer rewiring and the uppermost layer lower layer rewiring are formed simultaneously.
The invention described in claim 28 is characterized in that, in the invention described in claim 25, the lower layer upper layer rewiring and the uppermost layer lower layer rewiring are separately formed.
The invention according to claim 29 is the invention according to claim 27 or 28, wherein after the lowermost layer upper layer rewiring and the uppermost layer lower layer rewiring are formed, the insulating layer and the base plate are penetrated by the penetration. A hole is formed, and the vertical conduction part made of a conductive paste is formed in the through hole.
According to a thirty-third aspect, in the invention according to the twenty-fifth aspect, the cutting is performed so that a plurality of the semiconductor structural bodies are included.
The invention according to claim 31 is the invention according to claim 25, wherein the semiconductor structure has a columnar electrode as the external connection electrode.
The invention described in claim 32 is the invention described in claim 25, wherein the semiconductor structure has a rewiring having a connection pad portion as the external connection electrode. is there.
A thirty-third aspect of the invention is characterized in that in the invention of the twenty-fifth aspect, the semiconductor structure has a connection pad as the external connection electrode.
The invention according to claim 34 is characterized in that, in the invention according to claim 25, the method further comprises a step of forming an upper insulating film covering a portion of the uppermost upper layer rewiring except for the connection pad portion. is there.
A thirty-fifth aspect of the invention is characterized in that in the thirty-fourth aspect of the invention, a solder ball is formed on the connection pad portion of the uppermost upper layer rewiring.
A thirty-sixth aspect of the invention is characterized in that, in the thirty-fourth aspect of the invention, the electronic component is mounted on the upper insulating film while being connected to the connection pad portion of the upper rewiring. It is.
The invention of claim 37 is characterized in that, in the invention of claim 25, the method further comprises a step of forming a lower insulating film covering a portion excluding the connection pad portion of the lowermost lower layer rewiring. is there.
A thirty-eighth aspect of the invention is characterized in that, in the thirty-seventh aspect of the invention, a solder ball is formed under the connection pad portion of the lowermost lower layer rewiring.
The invention according to claim 39 is the invention according to claim 37, further comprising a step of mounting an electronic component under the lower insulating film while being connected to a connection pad portion of the lowermost lower layer rewiring. It is what.
A fortieth aspect of the invention is characterized in that, in the invention of the thirty-eighth aspect, the method further comprises a step of forming a flat suction head suction region at least partially under the lower insulating film.
The invention of claim 41 is characterized in that, in the invention of claim 25, a thin film circuit element is formed by at least a part of the lower layer rewiring or a part of the upper layer rewiring.
The invention of claim 42 is characterized in that, in the invention of claim 41, the thin film circuit element includes either an inductor circuit or an antenna circuit.
The invention according to claim 43 is the invention according to claim 25, further comprising a step of forming a ground layer on the upper surface of the base plate.
The invention according to claim 44 is the invention according to claim 43, wherein when forming the upper and lower conductive portion or the uppermost lower layer rewiring, the upper and lower conductive portion or the uppermost lower layer rewiring is connected to the ground. It is characterized by connecting to the layers.
According to a 45th aspect of the present invention, there is provided at least one semiconductor configuration including at least a base plate, a semiconductor substrate, and a plurality of external connection electrodes provided on the semiconductor substrate. A body, an insulating layer provided on the base plate around the semiconductor structure, and at least a part of the insulating layer connected to an external connection electrode of the semiconductor structure, and connected A first semiconductor device having at least one upper layer rewiring having a pad portion; a base plate; and a semiconductor substrate and a plurality of semiconductor substrates provided on the semiconductor substrate. At least one semiconductor structure having a plurality of external connection electrodes, an insulating layer provided on the base plate around the semiconductor structure, and at least a part of the semiconductor structure on the insulating layer. At least one upper layer redistribution provided to be connected to an external connection electrode of the body and having a connection pad portion; at least one lower layer redistribution provided under the base plate; and the insulating layer And an upper layer rewiring of any layer of the upper layer rewiring and a lower layer rewiring of any layer of the lower layer rewiring are provided in a through hole provided in the base plate. A first semiconductor device comprising: a first semiconductor device comprising: a first semiconductor device comprising: a first semiconductor device comprising: a first semiconductor device comprising: a first semiconductor device comprising: a first semiconductor device comprising: Between the semiconductor device and the second semiconductor device, or between the plurality of second semiconductor devices, the connection pad portion of the lower layer rewiring of the lowermost layer of the upper semiconductor device and the uppermost layer of the lower semiconductor device The process of connecting the connection pad of the upper layer rewiring It is characterized in that it has.
The invention according to a 46th aspect is the invention according to the 45th aspect, wherein the first semiconductor device and the second semiconductor device are bonded at once through an adhesive layer interposed therebetween. It is characterized by having.
According to a 47th aspect of the present invention, in the invention according to the 46th aspect, in the bonding step, a connection pad portion of a lower layer lower layer rewiring of the upper semiconductor device and an uppermost layer of the lower semiconductor device are provided. The connection pad portion of the upper layer rewiring is connected via a conductive material provided in a through hole provided in the adhesive layer.
According to a 48th aspect of the invention, in the invention according to the 45th aspect, the first and second semiconductor devices have an upper insulating film that covers a portion excluding the connection pad portion of the uppermost upper layer rewiring. It is characterized by this.
According to a 49th aspect of the present invention, in the invention according to the 45th aspect, after the first and second semiconductor devices are stacked, the uppermost semiconductor device of the stacked second semiconductor devices, It has a step of forming a solder ball on the connection pad portion of the upper layer upper layer rewiring.

この発明によれば、半導体構成体の周囲に設けられた絶縁層上に最上層の上層再配線の少なくとも一部の接続パッド部を配置しているので、最上層の上層再配線の接続パッド部（外部接続用電極）の数が増加しても、そのサイズおよびピッチを必要な大きさにすることが可能となる。また、ベース板下に少なくとも１層の下層再配線を設け、絶縁層およびベース板に設けられた貫通孔内に設けられた上下導通部を介して、上層再配線のうちのいずれかの層の上層再配線と下層再配線のうちのいずれかの層の下層再配線とを接続しているので、最上層の上層再配線または最下層の下層再配線に電子部品を接続させて搭載するようにして、電子機器のより一層の小型化が可能で、且つ、配線長を最短として回路特性を向上させることが可能となる。   According to the present invention, the connection pad portion of the uppermost upper layer rewiring is arranged on the insulating layer provided around the semiconductor structure, so that the uppermost upper layer rewiring connection pad portion is arranged. Even if the number of (external connection electrodes) increases, the size and pitch can be made as large as necessary. In addition, at least one lower layer rewiring is provided under the base plate, and any one of the upper layer rewirings is provided via the insulating layer and the vertical conduction portion provided in the through hole provided in the base plate. Since the upper layer rewiring and the lower layer rewiring of any one of the lower layer rewiring are connected, electronic components are connected to the uppermost upper layer rewiring or the lowermost lower layer rewiring. As a result, the electronic device can be further reduced in size, and the circuit characteristics can be improved with the wiring length as short as possible.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示す。この半導体装置は平面矩形形状のベース板１を備えている。ベース板１は、ガラス繊維、アラミド繊維、液晶繊維等にエポキシ系樹脂、ポリイミド系樹脂、ＢＴ（ビスマレイミド・トリアジン）樹脂、ＰＰＥ（ポリフェニレンエーテル）等を含浸させたもの、あるいは、シリコン、ガラス、セラミックス、樹脂単体等の絶縁材料からなっている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. The semiconductor device includes a base plate 1 having a planar rectangular shape. The base plate 1 is made by impregnating glass fiber, aramid fiber, liquid crystal fiber or the like with epoxy resin, polyimide resin, BT (bismaleimide / triazine) resin, PPE (polyphenylene ether) or the like, or silicon, glass, It is made of an insulating material such as ceramics or resin.

ベース板１の上面には、ベース板１のサイズよりもある程度小さいサイズの平面矩形形状の半導体構成体２の下面がダイボンド材からなる接着層３を介して接着されている。この場合、半導体構成体２は、後述する再配線、柱状電極、封止膜を有しており、一般的にはＣＳＰと呼ばれるものであり、特に、後述の如く、シリコンウエハ上に再配線、柱状電極、封止膜を形成した後、ダイシングにより個々の半導体構成体２を得る方法を採用しているため、特に、ウエハレベルＣＳＰ（Ｗ−ＣＳＰ）とも言われている。以下に、半導体構成体２の構成について説明する。   On the upper surface of the base plate 1, the lower surface of a planar rectangular semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is bonded via an adhesive layer 3 made of a die bond material. In this case, the semiconductor structure 2 has a rewiring, a columnar electrode, and a sealing film, which will be described later, and is generally called CSP. In particular, as described later, rewiring on a silicon wafer, Since a method of obtaining individual semiconductor structures 2 by dicing after forming the columnar electrode and the sealing film is adopted, it is particularly called wafer level CSP (W-CSP). Below, the structure of the semiconductor structure 2 is demonstrated.

半導体構成体２はシリコン基板（半導体基板）４を備えている。シリコン基板４は接着層３を介してベース板１に接着されている。シリコン基板４の上面には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド５が集積回路に接続されて設けられている。接続パッド５の中央部を除くシリコン基板４の上面には酸化シリコン等からなる絶縁膜６が設けられ、接続パッド５の中央部は絶縁膜６に設けられた開口部７を介して露出されている。   The semiconductor structure 2 includes a silicon substrate (semiconductor substrate) 4. The silicon substrate 4 is bonded to the base plate 1 via the adhesive layer 3. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 4, and a plurality of connection pads 5 made of aluminum-based metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit. An insulating film 6 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 4 excluding the central portion of the connection pad 5, and the central portion of the connection pad 5 is exposed through an opening 7 provided in the insulating film 6. Yes.

絶縁膜６の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる保護膜（絶縁膜）８が設けられている。この場合、絶縁膜６の開口部７に対応する部分における保護膜８には開口部９が設けられている。両開口部７、９を介して露出された接続パッド５の上面から保護膜８の上面の所定の箇所にかけて、銅等からなる下地金属層１０が設けられている。下地金属層１０の上面全体には銅からなる再配線１１が設けられている。   A protective film (insulating film) 8 made of an epoxy resin, a polyimide resin, or the like is provided on the upper surface of the insulating film 6. In this case, an opening 9 is provided in the protective film 8 at a portion corresponding to the opening 7 of the insulating film 6. A base metal layer 10 made of copper or the like is provided from the upper surface of the connection pad 5 exposed through the openings 7 and 9 to a predetermined portion of the upper surface of the protective film 8. A rewiring 11 made of copper is provided on the entire upper surface of the base metal layer 10.

再配線１１の接続パッド部上面には銅からなる柱状電極（外部接続用電極）１２が設けられている。再配線１１を含む保護膜８の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる封止膜（絶縁膜）１３がその上面が柱状電極１２の上面と面一となるように設けられている。このように、Ｗ−ＣＳＰと呼ばれる半導体構成体２は、シリコン基板４、接続パッド５、絶縁膜６を含み、さらに、保護膜８、再配線１１、柱状電極１２、封止膜１３を含んで構成されている。   A columnar electrode (external connection electrode) 12 made of copper is provided on the upper surface of the connection pad portion of the rewiring 11. A sealing film (insulating film) 13 made of an epoxy resin, a polyimide resin, or the like is provided on the upper surface of the protective film 8 including the rewiring 11 so that the upper surface is flush with the upper surface of the columnar electrode 12. . As described above, the semiconductor structure 2 called W-CSP includes the silicon substrate 4, the connection pad 5, and the insulating film 6, and further includes the protective film 8, the rewiring 11, the columnar electrode 12, and the sealing film 13. It is configured.

半導体構成体２の周囲におけるベース板１の上面には矩形枠状の絶縁層１４がその上面が半導体構成体２の上面とほぼ面一となるように設けられている。絶縁層１４は、例えば、熱硬化性樹脂、あるいは、熱硬化性樹脂中にガラス繊維やシリカフィラー等の補強材を分散させたものからなっている。   A rectangular frame-shaped insulating layer 14 is provided on the upper surface of the base plate 1 around the semiconductor structure 2 so that the upper surface is substantially flush with the upper surface of the semiconductor structure 2. The insulating layer 14 is made of, for example, a thermosetting resin or a material in which a reinforcing material such as glass fiber or silica filler is dispersed in a thermosetting resin.

半導体構成体２および絶縁層１４の上面には第１の上層絶縁膜１５がその上面を平坦とされて設けられている。第１の上層絶縁膜１５は、ビルドアップ基板に用いられる、通常、ビルドアップ材と言われるもので、例えば、エポキシ系樹脂やＢＴ樹脂等の熱硬化性樹脂中に繊維やフィラー等の補強材を分散させたものである。この場合、繊維は、ガラス繊維やアラミド繊維等である。フィラーは、シリカフィラーやセラミックス系フィラー等である。   A first upper insulating film 15 is provided on the upper surface of the semiconductor structure 2 and the insulating layer 14 with the upper surface being flat. The first upper-layer insulating film 15 is a so-called build-up material used for a build-up substrate. For example, a reinforcing material such as a fiber or a filler in a thermosetting resin such as an epoxy resin or a BT resin. Are dispersed. In this case, the fiber is glass fiber, aramid fiber, or the like. The filler is a silica filler or a ceramic filler.

第１の上層絶縁膜１５の上面の所定の箇所には銅からなる上層下地金属層１６が設けられている。上層下地金属層１６の上面全体には銅からなる上層再配線１７が設けられている。上層再配線１７を含む上層下地金属層１６の少なくとも一部は、柱状電極１２の上面中央部に対応する部分における第１の上層絶縁膜１５に設けられた開口部１８を介して柱状電極１２の上面に接続されている。   An upper base metal layer 16 made of copper is provided at a predetermined position on the upper surface of the first upper insulating film 15. An upper layer rewiring 17 made of copper is provided on the entire upper surface of the upper base metal layer 16. At least a part of the upper base metal layer 16 including the upper layer redistribution 17 is connected to the columnar electrode 12 through an opening 18 provided in the first upper layer insulating film 15 in a portion corresponding to the center of the upper surface of the columnar electrode 12. Connected to the top surface.

上層再配線１７を含む第１の上層絶縁膜１５の上面にはソルダーレジスト等からなる第２の上層絶縁膜１９が設けられている。上層再配線１７の接続パッド部に対応する部分における第２の上層絶縁膜１９には開口部２０が設けられている。開口部２０内およびその上方には半田ボール２１が上層再配線１７の接続パッド部に接続されて設けられている。複数の半田ボール２１は、第２の上層絶縁膜１９上にマトリクス状に配置されている。   A second upper layer insulating film 19 made of a solder resist or the like is provided on the upper surface of the first upper layer insulating film 15 including the upper layer rewiring 17. An opening 20 is provided in the second upper insulating film 19 in a portion corresponding to the connection pad portion of the upper layer rewiring 17. Solder balls 21 are provided in the opening 20 and above it so as to be connected to the connection pads of the upper layer rewiring 17. The plurality of solder balls 21 are arranged in a matrix on the second upper layer insulating film 19.

ベース板１の下面には第１の下層絶縁膜２２がその下面を平坦とされて設けられている。第１の下層絶縁膜２２は、例えば、第１の上層絶縁膜１５と同一の材料からなっている。第１の下層絶縁膜２２の下面の所定の箇所には銅からなる下層下地金属層２３が設けられている。下層下地金属層２３の下面全体には銅からなる下層再配線２４が設けられている。   A first lower insulating film 22 is provided on the lower surface of the base plate 1 with the lower surface being flat. The first lower insulating film 22 is made of the same material as that of the first upper insulating film 15, for example. A lower base metal layer 23 made of copper is provided at a predetermined position on the lower surface of the first lower insulating film 22. An entire lower surface of the lower base metal layer 23 is provided with a lower layer rewiring 24 made of copper.

下層再配線２４を含む第１の下層絶縁膜２２の下面にはソルダーレジスト等からなる第２の下層絶縁膜２５が設けられている。下層再配線２４の接続パッド部に対応する部分における第２の下層絶縁膜２５には開口部２６が設けられている。そして、下層再配線２４の接続パッド部は開口部２６を介して露出されている。   A second lower insulating film 25 made of a solder resist or the like is provided on the lower surface of the first lower insulating film 22 including the lower layer rewiring 24. An opening 26 is provided in the second lower insulating film 25 in a portion corresponding to the connection pad portion of the lower layer rewiring 24. The connection pad portion of the lower layer rewiring 24 is exposed through the opening 26.

上層再配線１７を含む上層下地金属層１６の少なくとも一部と下層再配線２４を含む下層下地金属層２３とは、第１の上層絶縁膜１５、絶縁層１４、ベース板１および第１の下層絶縁膜２２の所定の箇所に設けられた貫通孔２７の内壁面に設けられた銅からなる下地金属層２８ａと銅層２８ｂとからなる上下導通部２８を介して接続されている。この場合、上下導通部２８内には、上下配線の電気的な導通を良くするために、銅ペースト、銀ペースト、導電性樹脂等からなる導電材２９が充填されているが、絶縁性樹脂が充填されていてもよく、また、空洞であってもよい。   At least a part of the upper base metal layer 16 including the upper layer rewiring 17 and the lower base metal layer 23 including the lower layer rewiring 24 include the first upper layer insulating film 15, the insulating layer 14, the base plate 1, and the first lower layer. The insulating film 22 is connected via a vertical conductive portion 28 made of a base metal layer 28a made of copper and a copper layer 28b provided on the inner wall surface of a through hole 27 provided in a predetermined location of the insulating film 22. In this case, the upper and lower conductive portion 28 is filled with a conductive material 29 made of copper paste, silver paste, conductive resin, or the like in order to improve the electrical continuity of the upper and lower wirings. It may be filled or may be a cavity.

ところで、ベース板１のサイズを半導体構成体２のサイズよりもある程度大きくしているのは、シリコン基板４上の接続パッド５の数の増加に応じて、半田ボール２１の配置領域を半導体構成体２のサイズよりもある程度大きくし、これにより、上層再配線１７の接続パッド部（第２の上層絶縁膜１９の開口部２０内の部分）のサイズおよびピッチを柱状電極１２のサイズおよびピッチよりも大きくするためである。   By the way, the size of the base plate 1 is made somewhat larger than the size of the semiconductor structure 2 because the area where the solder balls 21 are arranged is increased as the number of connection pads 5 on the silicon substrate 4 increases. Thus, the size and pitch of the connection pad portion of the upper layer rewiring 17 (portion in the opening 20 of the second upper layer insulating film 19) is made larger than the size and pitch of the columnar electrode 12. This is to make it larger.

このため、マトリクス状に配置された上層再配線１７の接続パッド部は、半導体構成体２に対応する領域のみでなく、半導体構成体２の周側面の外側に設けられた絶縁層１４に対応する領域上にも配置されている。つまり、マトリクス状に配置された半田ボール２１のうち、少なくとも最外周の半田ボール２１は半導体構成体２よりも外側に位置する周囲に配置されている。   For this reason, the connection pad portion of the upper layer rewiring 17 arranged in a matrix shape corresponds not only to the region corresponding to the semiconductor structure 2 but also to the insulating layer 14 provided outside the peripheral side surface of the semiconductor structure 2. It is also arranged on the area. That is, among the solder balls 21 arranged in a matrix, at least the outermost solder balls 21 are arranged around the semiconductor structure 2.

また、この半導体装置では、ベース板１下に設けられた第１の下層絶縁膜２２下に下層再配線２４を設け、第１の上層絶縁膜１５、絶縁層１４、ベース板１および第１の下層絶縁膜２２に設けられた貫通孔２７内に設けられた上下導通部２８を介して、上層再配線１７の少なくとも一部と下層再配線２４とを接続しているので、例えば、下層再配線２４の少なくとも一部によりインダクタ回路やアンテナ回路等の薄膜回路素子を形成するようにしてもよい。また、後で説明するが、第２の下層絶縁膜２５の下面に電子部品を搭載するようにすることもでき、これらにより、電子機器のより一層の小型化が可能となるとともに、配線長を最短として回路特性を向上させることができる。   Further, in this semiconductor device, the lower layer rewiring 24 is provided under the first lower layer insulating film 22 provided under the base plate 1, and the first upper layer insulating film 15, the insulating layer 14, the base plate 1 and the first plate 1 Since at least a part of the upper layer rewiring 17 and the lower layer rewiring 24 are connected via the vertical conduction portion 28 provided in the through hole 27 provided in the lower insulating film 22, for example, the lower layer rewiring A thin film circuit element such as an inductor circuit or an antenna circuit may be formed by at least a part of 24. Further, as will be described later, an electronic component can be mounted on the lower surface of the second lower insulating film 25, thereby enabling further downsizing of the electronic device and reducing the wiring length. Circuit characteristics can be improved as shortest.

次に、この半導体装置の製造方法の一例について説明するに、まず、半導体構成体２の製造方法の一例について説明する。この場合、まず、図２に示すように、ウエハ状態のシリコン基板（半導体基板）４上にアルミニウム系金属等からなる接続パッド５、酸化シリコン等からなる絶縁膜６およびエポキシ系樹脂やポリイミド系樹脂等からなる保護膜８が設けられ、接続パッド５の中央部が絶縁膜６および保護膜８に形成された開口部７、９を介して露出されたものを用意する。上記において、ウエハ状態のシリコン基板４には、各半導体構成体が形成される領域に所定の機能の集積回路が形成され、接続パッド５は、それぞれ、対応する領域に形成された集積回路に電気的に接続されている。   Next, an example of a method for manufacturing the semiconductor device 2 will be described. In this case, first, as shown in FIG. 2, on a silicon substrate (semiconductor substrate) 4 in a wafer state, a connection pad 5 made of an aluminum-based metal, an insulating film 6 made of silicon oxide or the like, and an epoxy-based resin or a polyimide-based resin. A protective film 8 made of the like is provided, and the connection pad 5 is exposed through the openings 7 and 9 formed in the insulating film 6 and the protective film 8. In the above, on the silicon substrate 4 in the wafer state, an integrated circuit having a predetermined function is formed in a region where each semiconductor structure is formed, and the connection pad 5 is electrically connected to the integrated circuit formed in the corresponding region. Connected.

次に、図３に示すように、両開口部７、９を介して露出された接続パッド５の上面を含む保護膜８の上面全体に下地金属層１０を形成する。この場合、下地金属層１０は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 3, a base metal layer 10 is formed on the entire upper surface of the protective film 8 including the upper surface of the connection pad 5 exposed through the openings 7 and 9. In this case, the base metal layer 10 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

次に、下地金属層１０の上面にメッキレジスト膜３１をパターン形成する。この場合、再配線１１形成領域に対応する部分におけるメッキレジスト膜３１には開口部３２が形成されている。次に、下地金属層１０をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜３１の開口部３２内の下地金属層１０の上面に再配線１１を形成する。次に、メッキレジスト膜３１を剥離する。   Next, a plating resist film 31 is pattern-formed on the upper surface of the base metal layer 10. In this case, an opening 32 is formed in the plating resist film 31 in a portion corresponding to the rewiring 11 formation region. Next, by performing electrolytic plating of copper using the base metal layer 10 as a plating current path, the rewiring 11 is formed on the upper surface of the base metal layer 10 in the opening 32 of the plating resist film 31. Next, the plating resist film 31 is peeled off.

次に、図４に示すように、再配線１１を含む下地金属層１０の上面にメッキレジスト膜３３をパターン形成する。この場合、柱状電極１２形成領域に対応する部分におけるメッキレジスト膜３３には開口部３４が形成されている。次に、下地金属層１０をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜３３の開口部３４内の再配線１１の接続パッド部上面に柱状電極１２を形成する。次に、メッキレジスト膜３３を剥離し、次いで、再配線１１をマスクとして下地金属層１０の不要な部分をエッチングして除去すると、図５に示すように、再配線１１下にのみ下地金属層１０が残存される。   Next, as shown in FIG. 4, a plating resist film 33 is formed on the upper surface of the base metal layer 10 including the rewiring 11. In this case, an opening 34 is formed in the plating resist film 33 in a portion corresponding to the columnar electrode 12 formation region. Next, the columnar electrode 12 is formed on the connection pad portion upper surface of the rewiring 11 in the opening 34 of the plating resist film 33 by performing electrolytic plating of copper using the base metal layer 10 as a plating current path. Next, when the plating resist film 33 is peeled off, and then unnecessary portions of the base metal layer 10 are removed by etching using the rewiring 11 as a mask, the base metal layer is formed only under the rewiring 11 as shown in FIG. 10 remains.

次に、図６に示すように、スクリーン印刷法、スピンコーティング法、ダイコート法等により、柱状電極１２および再配線１１を含む保護膜８の上面全体にエポキシ系樹脂やポリイミド系樹脂等からなる封止膜１３をその厚さが柱状電極１２の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極１２の上面は封止膜１３によって覆われている。   Next, as shown in FIG. 6, the entire upper surface of the protective film 8 including the columnar electrode 12 and the rewiring 11 is sealed with an epoxy resin, a polyimide resin, or the like by screen printing, spin coating, die coating, or the like. The stop film 13 is formed so that its thickness is greater than the height of the columnar electrode 12. Therefore, in this state, the upper surface of the columnar electrode 12 is covered with the sealing film 13.

次に、封止膜１３および柱状電極１２の上面側を適宜に研磨し、図７に示すように、柱状電極１２の上面を露出させ、且つ、この露出された柱状電極１２の上面を含む封止膜１３の上面を平坦化する。ここで、柱状電極１２の上面側を適宜に研磨するのは、電解メッキにより形成される柱状電極１２の高さにばらつきがあるため、このばらつきを解消して、柱状電極１２の高さを均一にするためである。   Next, the upper surface side of the sealing film 13 and the columnar electrode 12 is appropriately polished to expose the upper surface of the columnar electrode 12 and to include the exposed upper surface of the columnar electrode 12 as shown in FIG. The upper surface of the stop film 13 is flattened. Here, the reason why the upper surface side of the columnar electrode 12 is appropriately polished is that there is a variation in the height of the columnar electrode 12 formed by electrolytic plating, so this variation is eliminated and the height of the columnar electrode 12 is made uniform. It is to make it.

次に、図８に示すように、シリコン基板４の下面全体に接着層３を接着する。接着層３は、エポキシ系樹脂、ポリイミド系樹脂等のダイボンド材からなるものであり、加熱加圧により、半硬化した状態でシリコン基板４に固着する。次に、シリコン基板４に固着された接着層３をダイシングテープ（図示せず）に貼り付け、図９に示すダイシング工程を経た後に、ダイシングテープから剥がすと、図１に示すように、シリコン基板４の下面に接着層３を有する半導体構成体２が複数個得られる。   Next, as shown in FIG. 8, the adhesive layer 3 is bonded to the entire lower surface of the silicon substrate 4. The adhesive layer 3 is made of a die bond material such as an epoxy resin or a polyimide resin, and is fixed to the silicon substrate 4 in a semi-cured state by heating and pressing. Next, the adhesive layer 3 fixed to the silicon substrate 4 is affixed to a dicing tape (not shown), passed through the dicing step shown in FIG. 9, and then peeled off from the dicing tape, as shown in FIG. A plurality of semiconductor structures 2 having the adhesive layer 3 on the lower surface of 4 are obtained.

このようにして得られた半導体構成体２では、シリコン基板４の下面に接着層３を有するため、ダイシング工程後に各半導体構成体２のシリコン基板４の下面にそれぞれ接着層を設けるといった極めて面倒な作業が不要となる。なお、ダイシング工程後にダイシングテープから剥がす作業は、ダイシング工程後に各半導体構成体２のシリコン基板４の下面にそれぞれ接着層を設ける作業に比べれば、極めて簡単である。   Since the semiconductor structure 2 obtained in this way has the adhesive layer 3 on the lower surface of the silicon substrate 4, it is extremely troublesome to provide an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after the dicing process. Work becomes unnecessary. In addition, the operation | work which peels from a dicing tape after a dicing process is very simple compared with the operation | work which each provides an adhesive layer on the lower surface of the silicon substrate 4 of each semiconductor structure 2 after a dicing process.

次に、このようにして得られた半導体構成体２を用いて、図１に示す半導体装置を製造する場合の一例について説明する。まず、図１０に示すように、図１に示すベース板１を複数枚採取することができる大きさで、限定する意味ではないが、平面形状が矩形形状のベース板１を用意する。次に、ベース板１の上面の所定の複数箇所にそれぞれ半導体構成体２のシリコン基板４の下面に接着された接着層３を接着する。ここでの接着は、加熱加圧により、接着層３を本硬化させる。   Next, an example of manufacturing the semiconductor device shown in FIG. 1 using the semiconductor structure 2 obtained in this way will be described. First, as shown in FIG. 10, the base plate 1 is prepared in such a size that a plurality of the base plates 1 shown in FIG. Next, the adhesive layer 3 bonded to the lower surface of the silicon substrate 4 of the semiconductor structure 2 is bonded to a plurality of predetermined locations on the upper surface of the base plate 1. In this bonding, the adhesive layer 3 is fully cured by heating and pressing.

次に、半導体構成体２間および最外周に配置された半導体構成体２の外側におけるベース板１の上面に、例えばスクリーン印刷法やスピンコーティング法等により、第１の絶縁材料１４ａを形成し、さらにその上面にシート状の第２の絶縁材料１５ａを配置する。また、ベース板１の下面にシート状の第３の絶縁材料２２ａを配置する。第１の絶縁材料１４ａは、例えば、熱硬化性樹脂、あるいは、熱硬化性樹脂中にガラス繊維やシリカフィラー等の補強材を分散させたものである。   Next, the first insulating material 14a is formed on the upper surface of the base plate 1 between the semiconductor structural bodies 2 and outside the semiconductor structural bodies 2 arranged on the outermost periphery by, for example, a screen printing method or a spin coating method. Further, a sheet-like second insulating material 15a is disposed on the upper surface. A sheet-like third insulating material 22 a is disposed on the lower surface of the base plate 1. The first insulating material 14a is, for example, a thermosetting resin or a material in which a reinforcing material such as glass fiber or silica filler is dispersed in a thermosetting resin.

シート状の第２、第３の絶縁材料１５ａ、２２ａは、限定する意味ではないが、ビルドアップ材が好ましく、このビルドアップ材としては、エポキシ系樹脂やＢＴ樹脂等の熱硬化性樹脂中にシリカフィラーを混入させ、熱硬化性樹脂を半硬化状態にしたものがある。しかしながら、第２、第３の絶縁材料１５ａ、２２ａとして、ガラス繊維にエポキシ系樹脂等の熱硬化性樹脂を含浸させ、熱硬化性樹脂を半硬化状態にしてシート状となしたプリプレグ材、またはフィラーが混入されない、熱硬化性樹脂のみからなる材料を用いることもできる。   The sheet-like second and third insulating materials 15a and 22a are not limited, but a build-up material is preferable. As the build-up material, a thermosetting resin such as an epoxy resin or a BT resin is used. There is one in which a silica filler is mixed to make a thermosetting resin in a semi-cured state. However, as the second and third insulating materials 15a and 22a, a prepreg material in which a glass fiber is impregnated with a thermosetting resin such as an epoxy resin and the thermosetting resin is semi-cured into a sheet shape, or It is also possible to use a material made of only a thermosetting resin in which no filler is mixed.

次に、図１１に示す一対の加熱加圧板３７、３８を用いて、第１〜第３の絶縁材料１４ａ、１５ａ、２２ａを加熱加圧する。すると、半導体構成体２間および最外周に配置された半導体構成体２の外側におけるベース板１の上面に絶縁層１４が形成され、半導体構成体２および絶縁層１４の上面に第１の上層絶縁膜１５が形成され、ベース板１の下面に第１の下層絶縁膜２２が形成される。   Next, the first to third insulating materials 14a, 15a, and 22a are heated and pressurized using a pair of heating and pressing plates 37 and 38 shown in FIG. Then, an insulating layer 14 is formed on the upper surface of the base plate 1 between the semiconductor structural members 2 and outside the semiconductor structural members 2 arranged on the outermost periphery, and the first upper layer insulation is formed on the upper surfaces of the semiconductor structural members 2 and the insulating layer 14. A film 15 is formed, and a first lower insulating film 22 is formed on the lower surface of the base plate 1.

この場合、第１の上層絶縁膜１５の上面は、上側の加熱加圧板３６の下面によって押さえ付けられるため、平坦面となる。また、第１の下層絶縁膜２２の下面は、下側の加熱加圧板３８の上面によって押さえ付けられるため、平坦面となる。したがって、第１の上層絶縁膜１５の上面および第１の下層絶縁膜２２の下面を平坦化するための研磨工程は不要である。このため、ベース板１のサイズが例えば５００×５００ｍｍ程度と比較的大きくても、その上に配置された複数の半導体構成体２に対して第１の上層絶縁膜１５の上面および第１の下層絶縁膜２２の下面の平坦化を一括して簡単に行なうことができる。   In this case, the upper surface of the first upper-layer insulating film 15 is pressed by the lower surface of the upper heating / pressurizing plate 36 and thus becomes a flat surface. In addition, the lower surface of the first lower insulating film 22 is pressed by the upper surface of the lower heating / pressurizing plate 38 and thus becomes a flat surface. Therefore, a polishing step for flattening the upper surface of the first upper insulating film 15 and the lower surface of the first lower insulating film 22 is unnecessary. For this reason, even if the size of the base plate 1 is relatively large, for example, about 500 × 500 mm, the upper surface and the first lower layer of the first upper insulating film 15 with respect to the plurality of semiconductor structures 2 arranged thereon. Flattening of the lower surface of the insulating film 22 can be easily performed collectively.

次に、図１２に示すように、レーザビームを照射するレーザ加工により、柱状電極１２の上面中央部に対応する部分における第１の上層絶縁膜１５に開口部１８を形成する。また、メカニカルドリルを用いて、またはＣＯ２レーザビームを照射するレーザ加工により、第１の上層絶縁膜１５、絶縁層１４、ベース板１および第１の下層絶縁膜２２の所定の箇所に貫通孔２７を形成する。次に、必要に応じて、開口部１８内および貫通孔２７内等に発生したエポキシスミア等をデスミア処理により除去する。   Next, as shown in FIG. 12, an opening 18 is formed in the first upper insulating film 15 at a portion corresponding to the central portion of the upper surface of the columnar electrode 12 by laser processing with laser beam irradiation. Further, through holes 27 are formed at predetermined positions of the first upper insulating film 15, the insulating layer 14, the base plate 1, and the first lower insulating film 22 by using a mechanical drill or laser processing with irradiation of a CO 2 laser beam. Form. Next, the epoxy smear etc. which generate | occur | produced in the opening part 18 and the through-hole 27 grade | etc., Are removed by a desmear process as needed.

次に、図１３に示すように、開口部１８を介して露出された柱状電極１２の上面を含む第１の上層絶縁膜１５の上面全体、第１の下層絶縁膜２２の下面全体および貫通孔２７の内壁面に、銅の無電解メッキにより、上層下地金属層１６、下層下地金属層２３、下地金属層２８ａを形成する。次に、上層下地金属層１６の上面に上層メッキレジスト膜４１をパターン形成し、また、下層下地金属層２３の下面に下層メッキレジスト膜４２をパターン形成する。この場合、貫通孔２７を含む上層再配線１７形成領域に対応する部分における上層メッキレジスト膜４１には開口部４３が形成されている。また、貫通孔２７を含む下層再配線２４形成領域に対応する部分における下層メッキレジスト膜４２には開口部４４が形成されている。   Next, as shown in FIG. 13, the entire upper surface of the first upper insulating film 15 including the upper surface of the columnar electrode 12 exposed through the opening 18, the entire lower surface of the first lower insulating film 22, and the through hole The upper base metal layer 16, the lower base metal layer 23, and the base metal layer 28a are formed on the inner wall surface 27 by electroless plating of copper. Next, the upper plating resist film 41 is patterned on the upper surface of the upper lower metal layer 16, and the lower plating resist film 42 is patterned on the lower surface of the lower base metal layer 23. In this case, an opening 43 is formed in the upper layer plating resist film 41 in the portion corresponding to the upper layer rewiring 17 formation region including the through hole 27. In addition, an opening 44 is formed in the lower plating resist film 42 in a portion corresponding to the lower layer rewiring 24 formation region including the through hole 27.

次に、下地金属層１６、２３、２８ａをメッキ電流路として銅の電解メッキを行なうことにより、上層メッキレジスト膜４１の開口部４３内の下地金属層１６の上面に上層再配線１７を形成し、また、下層メッキレジスト膜４２の開口部４４内の下地金属層２３の下面に下層再配線２４を形成し、さらに、貫通孔２７内の下地金属層２８ａの表面に銅層２８ｂを形成する。   Next, the upper layer rewiring 17 is formed on the upper surface of the lower metal layer 16 in the opening 43 of the upper plating resist film 41 by performing copper electroplating using the lower metal layer 16, 23, 28a as a plating current path. Further, the lower layer rewiring 24 is formed on the lower surface of the base metal layer 23 in the opening 44 of the lower layer plating resist film 42, and the copper layer 28 b is formed on the surface of the base metal layer 28 a in the through hole 27.

次に、両メッキレジスト膜４１、４２を剥離し、次いで、上層再配線１７および下層再配線２４をマスクとして下地金属層１６、２３の不要な部分をエッチングして除去すると、図１４に示すように、上層再配線１７下にのみ上層下地金属層１６が残存され、また、下層再配線２４上にのみ下層下地金属層２３が残存される。この状態では、上層再配線１７を含む上層下地金属層１６の少なくとも一部は第１の上層絶縁膜１５の開口部１８を介して柱状電極１２の上面に接続されている。また、上層再配線１７を含む上層下地金属層１６の少なくとも一部と下層再配線２４を含む下層下地金属層２３とは、貫通孔２７の内壁面に設けられた下地金属層２８ａと銅層２８ｂとからなる上下導通部２８を介して接続されている。   Next, both plating resist films 41 and 42 are peeled off, and then unnecessary portions of the underlying metal layers 16 and 23 are removed by etching using the upper layer rewiring 17 and the lower layer rewiring 24 as a mask, as shown in FIG. In addition, the upper base metal layer 16 remains only under the upper layer rewiring 17, and the lower base metal layer 23 remains only on the lower layer rewiring 24. In this state, at least a part of the upper base metal layer 16 including the upper layer rewiring 17 is connected to the upper surface of the columnar electrode 12 through the opening 18 of the first upper layer insulating film 15. In addition, at least a part of the upper base metal layer 16 including the upper layer rewiring 17 and the lower base metal layer 23 including the lower layer rewiring 24 include a base metal layer 28 a and a copper layer 28 b provided on the inner wall surface of the through hole 27. Are connected through a vertical conduction portion 28.

次に、図１５に示すように、スクリーン印刷法等により、上下導通部２８内に銅ペースト、銀ペースト、導電性樹脂等からなる導電材２９を充填する。次に、必要に応じて、貫通孔２７から突出された余分の導電材２９をバフ研磨等により除去する。次に、スクリーン印刷法やスピンコーティング法等により、上層再配線１７を含む第１の上層絶縁膜１５の上面にソルダーレジスト等からなる第２の上層絶縁膜１９を形成する。この場合、上層再配線１７の接続パッド部に対応する部分における第２の上層絶縁膜１９には開口部２０が形成されている。また、スクリーン印刷法やスピンコーティング法等により、下層再配線２４を含む第１の下層絶縁膜２２の下面にソルダーレジスト等からなる第２の下層絶縁膜２５を形成する。この場合、下層再配線２４の接続パッド部に対応する部分における第２の下層絶縁膜２５には開口部２６が形成されている。   Next, as shown in FIG. 15, a conductive material 29 made of copper paste, silver paste, conductive resin, or the like is filled in the vertical conduction portion 28 by screen printing or the like. Next, if necessary, excess conductive material 29 protruding from the through hole 27 is removed by buffing or the like. Next, a second upper layer insulating film 19 made of a solder resist or the like is formed on the upper surface of the first upper layer insulating film 15 including the upper layer rewiring 17 by a screen printing method, a spin coating method, or the like. In this case, an opening 20 is formed in the second upper layer insulating film 19 in a portion corresponding to the connection pad portion of the upper layer rewiring 17. Further, a second lower insulating film 25 made of a solder resist or the like is formed on the lower surface of the first lower insulating film 22 including the lower rewiring 24 by a screen printing method, a spin coating method, or the like. In this case, an opening 26 is formed in the second lower insulating film 25 in a portion corresponding to the connection pad portion of the lower layer rewiring 24.

次に、開口部２０内およびその上方に半田ボール２１を上層再配線１７の接続パッド部に接続させて形成する。次に、互いに隣接する半導体構成体２間において、第２の上層絶縁膜１９、第１の上層絶縁膜１５、絶縁層１４、ベース板１、第１の下層絶縁膜２２および第２の下層絶縁膜２５を切断すると、図１に示す半導体装置が複数個得られる。   Next, a solder ball 21 is formed in the opening 20 and above it by connecting to the connection pad portion of the upper layer rewiring 17. Next, between the semiconductor structures 2 adjacent to each other, the second upper insulating film 19, the first upper insulating film 15, the insulating layer 14, the base plate 1, the first lower insulating film 22, and the second lower insulating film. When the film 25 is cut, a plurality of semiconductor devices shown in FIG. 1 are obtained.

以上のように、上記製造方法では、ベース板１上に複数の半導体構成体２を接着層３を介して配置し、複数の半導体構成体２に対して、特に、上層再配線１７、下層再配線２４、上下導通部２８および半田ボール２１の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。また、図１２に示す製造工程以降では、ベース板１と共に複数の半導体構成体２を搬送することができるので、これによっても製造工程を簡略化することができる。   As described above, in the manufacturing method described above, a plurality of semiconductor structures 2 are arranged on the base plate 1 via the adhesive layer 3, and the upper layer rewiring 17, the lower layer rewiring 17, etc. Since the wiring 24, the vertical conduction portion 28, and the solder ball 21 are formed in a lump and then divided to obtain a plurality of semiconductor devices, the manufacturing process can be simplified. In addition, after the manufacturing process shown in FIG. 12, a plurality of semiconductor structures 2 can be transported together with the base plate 1, so that the manufacturing process can be simplified.

（変形例１）
上記実施形態では、半田ボール２１を、半導体構成体２上およびその周囲の絶縁層１４上の全面に対応してマトリクス状に配列されるように設けているが、これに限定されるものではない。例えば、半田ボール２１を半導体構成体２の周囲の絶縁層１４上に対応する領域上にのみ設けるようにしてもよい。その場合、半田ボール２１を半導体構成体２の全周囲ではなく、半導体構成体２の４辺のうち、１〜３辺の側方のみに設けてもよい。また、このような場合には、絶縁層１４を矩形枠状のものとする必要はなく、半田ボール２１を設ける辺の側方のみに配置されるようにしてもよい。 (Modification 1)
In the above embodiment, the solder balls 21 are provided so as to be arranged in a matrix corresponding to the entire surface of the semiconductor structure 2 and the surrounding insulating layer 14, but the present invention is not limited to this. . For example, the solder ball 21 may be provided only on a region corresponding to the insulating layer 14 around the semiconductor structure 2. In that case, the solder balls 21 may be provided not on the entire periphery of the semiconductor structure 2 but only on the sides of the 1 to 3 sides of the 4 sides of the semiconductor structure 2. In such a case, the insulating layer 14 does not need to have a rectangular frame shape, and may be disposed only on the side of the side where the solder ball 21 is provided.

（変形例２）
上記実施形態では、図１３に示すように、電解メッキにより上層再配線１７および下層再配線２４を形成している（以下、パターニングメッキ法という）が、これに限定されるものではない。例えば、無電解メッキにより形成した下地金属層１６、２３、２８ａの表面全体に電解メッキにより銅層を形成し、この銅層および下地金属層１６、２３、２８ａをフォトリソグラフィ法により連続してパターニングして、図１４に示すように、上層下地金属層１６を含む上層再配線１７を形成するとともに、下層下地金属層２３を含む下層再配線２４を形成するようにしてもよい（以下、パターニングエッチング法という）。また、いずれの方法においても、無電解メッキを行なう前に、貫通孔２７内にカーボン等からなる薄い導電膜を形成するようにしてもよい。 (Modification 2)
In the above embodiment, as shown in FIG. 13, the upper layer rewiring 17 and the lower layer rewiring 24 are formed by electrolytic plating (hereinafter referred to as patterning plating method), but the present invention is not limited to this. For example, a copper layer is formed by electrolytic plating on the entire surface of the base metal layers 16, 23, and 28a formed by electroless plating, and the copper layer and the base metal layers 16, 23, and 28a are successively patterned by photolithography. Then, as shown in FIG. 14, the upper layer rewiring 17 including the upper base metal layer 16 and the lower layer rewiring 24 including the lower base metal layer 23 may be formed (hereinafter referred to as patterning etching). The law). In any method, a thin conductive film made of carbon or the like may be formed in the through hole 27 before electroless plating.

（変形例３）
ここで、上層再配線１７は、集積化が進むに従って、比較的微細なパターン形成が要求される傾向にある。一方、下層再配線２４は、これによりインダクタ回路やアンテナ回路等の薄膜回路素子を形成したり、あるいは比較的粗い配線を形成する程度であるため、要求されるパターン精度は比較的緩い。 (Modification 3)
Here, the upper layer rewiring 17 tends to be required to form a relatively fine pattern as the integration proceeds. On the other hand, since the lower layer rewiring 24 is formed to form a thin film circuit element such as an inductor circuit or an antenna circuit, or to form a relatively rough wiring, the required pattern accuracy is relatively loose.

ところで、一般に、パターニングメッキ法によって形成される配線層のパターニング精度はメッキレジスト膜によって形成されるパターンの精度に依存するが、メッキレジスト膜は厚さが比較的厚く、サイドエッチングが大きいため、パターンニングの精度は比較的低く、そのため、パターニングメッキ法によって形成される配線層のパターニング精度も低い。したがって、パターニングメッキ法は微細化には適していない。一方、パターニングエッチング法によって形成される配線層のパターニング精度は、電解メッキによって形成される配線層のエッチングによるパターンニング精度に依って決まり、この配線層の厚さは比較的薄いものであるため、サイドエッチングは少なく、比較的高い精度のパターンニングを行うことができる。したがって、パターニングエッチング法は微細化に適している。   By the way, in general, the patterning accuracy of the wiring layer formed by the patterning plating method depends on the accuracy of the pattern formed by the plating resist film. However, since the plating resist film is relatively thick and side etching is large, Therefore, the patterning accuracy of the wiring layer formed by the patterning plating method is also low. Therefore, the patterning plating method is not suitable for miniaturization. On the other hand, the patterning accuracy of the wiring layer formed by the patterning etching method is determined by the patterning accuracy by etching of the wiring layer formed by electrolytic plating, and the thickness of this wiring layer is relatively thin. Side etching is small and patterning with relatively high accuracy can be performed. Therefore, the patterning etching method is suitable for miniaturization.

そこで、比較的微細なパターニングが要求される上層再配線１７をパターニングエッチング法により形成し、微細なパターニングが要求されない下層再配線２４をパターニングメッキ法により形成するようにしてもよい。この場合、両面を同時に処理するようにしてもよく、また、片面ずつ別々に処理するようにしてもよい。片面ずつ別々に処理する場合には、一方の面を処理するとき、他方の面をレジストや保護フィルム等で覆っておくようにすればよい。また、いずれの処理方法においても、次に説明する上下導通部の形成方法を採用するようにしてもよい。   Therefore, the upper layer rewiring 17 requiring relatively fine patterning may be formed by a patterning etching method, and the lower layer rewiring 24 not requiring fine patterning may be formed by a patterning plating method. In this case, both sides may be processed simultaneously, or each side may be processed separately. When processing one surface separately, when processing one surface, the other surface may be covered with a resist or a protective film. In any of the processing methods, a method for forming the vertical conduction portion described below may be adopted.

（変形例４）
上記実施形態では、貫通孔２７内に下地金属層２８ａと銅層２８ｂとからなる上下導通部２８を形成しているが、これに限定されるものではない。例えば、貫通孔２７内全部に銅ペースト、銀ペースト、導電性樹脂等からなる導電性材料を充填して、上下導通部を形成するようにしてもよい。この場合、まず、貫通孔２７を形成せずに、無電解メッキおよび電解メッキ等により、図１３に示すように、上層下地金属層１６、上層再配線１７、下層下地金属層２３および下層再配線２４を形成する。 (Modification 4)
In the above embodiment, the vertical conduction portion 28 including the base metal layer 28a and the copper layer 28b is formed in the through hole 27. However, the present invention is not limited to this. For example, the conductive material made of copper paste, silver paste, conductive resin, or the like may be filled in the entire through hole 27 to form the vertical conduction portion. In this case, first, the upper base metal layer 16, the upper layer rewiring 17, the lower base metal layer 23, and the lower layer rewiring are formed by electroless plating, electrolytic plating, or the like without forming the through hole 27, as shown in FIG. 24 is formed.

次に、全体の両面に保護フィルムを貼り付け、これらの保護フィルムと上層下地金属層１６、上層再配線１７、下層下地金属層２３および下層再配線２４とを含むものに、メカニカルドリルを用いて、またはＣＯ２レーザビームを照射するレーザ加工により、貫通孔２７を形成する。次に、スクリーン印刷法等により、貫通孔２７内に銅ペースト、銀ペースト、導電性樹脂等からなる導電性材料を充填する。次に、両保護フィルムを剥離する。次に、貫通孔２７から突出された余分の導電性材料をバフ研磨等により除去する。次に、導電性材料をベークして硬化させると、上下導通部が形成される。   Next, a protective film is pasted on both surfaces, and a mechanical drill is used to include these protective films and the upper base metal layer 16, the upper layer rewiring 17, the lower layer base metal layer 23, and the lower layer rewiring 24. Alternatively, the through hole 27 is formed by laser processing that irradiates a CO2 laser beam. Next, a conductive material made of copper paste, silver paste, conductive resin, or the like is filled into the through holes 27 by screen printing or the like. Next, both protective films are peeled off. Next, excess conductive material protruding from the through hole 27 is removed by buffing or the like. Next, when the conductive material is baked and cured, the vertical conduction portion is formed.

（第２実施形態）
図１６はこの発明の第２実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す場合と異なる点は、ベース板１の上面の所定の箇所に銅箔からなるグラウンド層５１を設け、このグラウンド層５１の上面に半導体構成体２のシリコン基板４の下面を接着層３を介して接着し、グラウンド層５１の所定の箇所に形成された円孔５２の内壁面を上下導通部２８の下地金属層２８ａに接続させた点である。この場合、貫通孔２７を形成するとき、同時に、グラウンド層５１に円孔５２を形成する。そして、貫通孔２７内に下地金属層２８ａを形成すると、この下地金属層２８ａはグラウンド層５１の円孔５２の内壁面に接続される。 (Second Embodiment)
FIG. 16 is a sectional view of a semiconductor device as a second embodiment of the present invention. In this semiconductor device, the difference from the case shown in FIG. 1 is that a ground layer 51 made of copper foil is provided at a predetermined location on the upper surface of the base plate 1, and the silicon substrate 4 of the semiconductor structure 2 is formed on the upper surface of the ground layer 51. The lower surface of the circular hole 52 is bonded through the adhesive layer 3, and the inner wall surface of the circular hole 52 formed at a predetermined position of the ground layer 51 is connected to the base metal layer 28 a of the vertical conduction portion 28. In this case, when the through hole 27 is formed, the circular hole 52 is formed in the ground layer 51 at the same time. When the base metal layer 28 a is formed in the through hole 27, the base metal layer 28 a is connected to the inner wall surface of the circular hole 52 of the ground layer 51.

（第３実施形態）
図１６では、グラウンド層５１に上下導通部２８を接続させているが、これに限定されるものではない。例えば、図１７に示すこの発明の第３実施形態のように、グラウンド層５１に下層下地金属層２３を含む下層再配線２４を第１の下層絶縁膜２２およびベース板１に形成された開口部５３を介して接続するようにしてもよい。 (Third embodiment)
In FIG. 16, the vertical conduction part 28 is connected to the ground layer 51, but the present invention is not limited to this. For example, as in the third embodiment of the present invention shown in FIG. 17, the lower layer rewiring 24 including the lower layer underlying metal layer 23 in the ground layer 51 is formed in the first lower insulating film 22 and the base plate 1. You may make it connect via 53.

（第４実施形態）
上記第１実施形態では、図１に示すように、第１の上層絶縁膜１５上に上層再配線１６を１層だけ形成した場合について説明したが、これに限らず、２層以上としてもよく、例えば、図１８に示すこの発明の第４実施形態のように、２層としてもよい。すなわち、半導体構成体２および絶縁層１４の上面にはビルドアップ材等からなる第１の上層絶縁膜６１が設けられている。第１の上層絶縁膜６１の上面には第１の上層下地金属層６２を含む第１の上層再配線６３が第１の上層絶縁膜６１に形成された開口部６４を介して柱状電極１２の上面に接続されて設けられている。 (Fourth embodiment)
In the first embodiment, as shown in FIG. 1, the case where only one upper layer rewiring 16 is formed on the first upper insulating film 15 has been described. However, the present invention is not limited to this, and two or more layers may be used. For example, two layers may be used as in the fourth embodiment of the present invention shown in FIG. That is, the first upper insulating film 61 made of a build-up material or the like is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 14. A first upper layer rewiring 63 including a first upper layer underlying metal layer 62 is formed on the upper surface of the first upper layer insulating film 61 through the opening 64 formed in the first upper layer insulating film 61. It is connected to the upper surface.

第１の上層再配線６３を含む第１の上層絶縁膜６１の上面にはビルドアップ材等からなる第２の上層絶縁膜６５が設けられている。第２の上層絶縁膜６５の上面には第２の下地金属層６６を含む第２の上層再配線６７が第２の上層絶縁膜６５に形成された開口部６８を介して第１の上層再配線６３の接続パッド部に接続されて設けられている。   A second upper layer insulating film 65 made of a buildup material or the like is provided on the upper surface of the first upper layer insulating film 61 including the first upper layer rewiring 63. A second upper layer rewiring 67 including a second base metal layer 66 is formed on the upper surface of the second upper layer insulating film 65 through an opening 68 formed in the second upper layer insulating film 65. The wiring 63 is connected to the connection pad portion.

第２の上層再配線６７を含む第２の上層絶縁膜６５の上面にはソルダーレジスト等からなる第３の上層絶縁膜６９が設けられている。第２の上層再配線６７の接続パッド部に対応する部分における第３の上層絶縁膜６９には開口部７０が形成されている。開口部７０内およびその上方には半田ボール７１が第２の上層再配線６７の接続パッド部に接続されて設けられている。   A third upper layer insulating film 69 made of a solder resist or the like is provided on the upper surface of the second upper layer insulating film 65 including the second upper layer rewiring 67. An opening 70 is formed in the third upper-layer insulating film 69 in a portion corresponding to the connection pad portion of the second upper-layer rewiring 67. Solder balls 71 are provided in and above the opening 70 so as to be connected to the connection pad portion of the second upper layer rewiring 67.

ところで、この第４実施形態では、第１の上層下地金属層６２を含む第１の上層再配線６３と下層下地金属層２３を含む下層再配線２４とを上下導通部２８を介して接続しているが、これに限らず、第２の上層下地金属層６６を含む第２の上層再配線６７と下層下地金属層２３を含む下層再配線２４とを上下導通部を介して接続するようにしてもよい。   By the way, in the fourth embodiment, the first upper layer rewiring 63 including the first upper layer base metal layer 62 and the lower layer rewiring 24 including the lower layer base metal layer 23 are connected via the vertical conduction part 28. However, the present invention is not limited to this, and the second upper layer redistribution 67 including the second upper layer underlying metal layer 66 and the lower layer redistribution 24 including the lower layer underlying metal layer 23 are connected via the vertical conduction portion. Also good.

また、この第４実施形態では、半田ボール７１は、半導体構成体２の周囲の矩形枠状の絶縁層１４上に対応する領域上のみに設けられている。この結果、半導体構成体２上に対応する領域における第２の上層絶縁膜６５の上面の大部分は、半田ボール７１に接続される第２の上層再配線６７を形成しないようにすることができるため、余剰領域となっている。そこで、この余剰領域に、第２の上層再配線からなる、例えばインダクタ回路等の薄膜受動素子７２を形成するようにして、電子機器の小型化を図るようにしてもよい。   In the fourth embodiment, the solder balls 71 are provided only on regions corresponding to the rectangular frame-shaped insulating layer 14 around the semiconductor structure 2. As a result, most of the upper surface of the second upper layer insulating film 65 in the region corresponding to the semiconductor structure 2 can be prevented from forming the second upper layer rewiring 67 connected to the solder ball 71. Therefore, it is a surplus area. Therefore, the electronic device may be miniaturized by forming a thin film passive element 72 such as an inductor circuit made of the second upper layer rewiring in the surplus region.

また、第２の下層絶縁膜２５の下面周辺部の所定の一部に、より一層の小型化および配線長の最短化を図るため、コンデンサや抵抗等からなるチップ部品７３を搭載するようにしてもよい。この場合、チップ部品７３の両側の電極は、開口部２６内にスクリーン印刷等により充填された半田７４を介して下層再配線２４に接続されている。   In addition, a chip component 73 made of a capacitor, a resistor, or the like is mounted on a predetermined part of the lower peripheral portion of the second lower insulating film 25 in order to further reduce the size and shorten the wiring length. Also good. In this case, the electrodes on both sides of the chip component 73 are connected to the lower layer rewiring 24 via the solder 74 filled in the opening 26 by screen printing or the like.

さらに、チップ部品７３搭載領域を除く領域における第１の下層絶縁膜２２の下面に、下層再配線からなる、例えばアンテナ回路等の薄膜受動素子７４を形成するようにしてもよい。この場合、薄膜受動素子７４の形成領域として比較的大きな面積を確保することができて、薄膜受動素子７４としてアンテナ回路を良好に適用することができる。また、この場合、第２の下層絶縁膜２５の下面周辺部にチップ部品７３を搭載し、第２の下層絶縁膜２５の下面ほぼ中央部を平坦な領域としているため、この中央部の平坦領域を、この半導体装置をハンドリングするための吸着ヘッドを吸着させる、吸着ヘッド吸着用領域（マウント用ピックアップ領域）とすることができる。   Furthermore, a thin-film passive element 74 such as an antenna circuit may be formed on the lower surface of the first lower insulating film 22 in the region excluding the chip component 73 mounting region, such as an antenna circuit. In this case, a relatively large area can be secured as a formation region of the thin film passive element 74, and the antenna circuit can be favorably applied as the thin film passive element 74. Further, in this case, since the chip component 73 is mounted on the lower peripheral portion of the second lower insulating film 25 and the substantially lower central portion of the second lower insulating film 25 is a flat region, the flat region of this central portion Can be a suction head suction region (mounting pickup region) in which a suction head for handling the semiconductor device is sucked.

ところで、第２の下層絶縁膜２５の下面の中央部付近を含む、下面のほぼ全体領域に複数個のチップ部品７３を搭載するようにすることもできる。その場合には、より一層の小型化および配線長の最短化を図ることができるが、その反面、平坦な吸着ヘッド吸着用領域を確保することが困難となる。そこで、次に、このような場合でも、平坦な吸着ヘッド吸着用領域を確保することができる第５、第６実施形態について説明する。   By the way, a plurality of chip parts 73 can be mounted in almost the entire area of the lower surface including the vicinity of the center of the lower surface of the second lower insulating film 25. In this case, the size can be further reduced and the wiring length can be shortened. However, on the other hand, it is difficult to secure a flat suction head suction area. Thus, next, fifth and sixth embodiments that can secure a flat suction head suction region even in such a case will be described.

（第５実施形態）
図１９はこの発明の第５実施形態としての半導体装置の断面図を示す。この半導体装置では、第２の下層絶縁膜２５の下面のほぼ中央部を含む全体領域に複数個のチップ部品７３が搭載され、これらのチップ部品７３がエポキシ系樹脂やポリイミド系樹脂等からなる封止膜７５で覆われ、封止膜７５の下面が研磨により平坦とされ、この平坦な下面が吸着ヘッド吸着用領域とされている。 (Fifth embodiment)
FIG. 19 is a sectional view of a semiconductor device as a fifth embodiment of the present invention. In this semiconductor device, a plurality of chip components 73 are mounted on the entire area including the substantially central portion of the lower surface of the second lower insulating film 25, and these chip components 73 are sealed with epoxy resin, polyimide resin or the like. The bottom surface of the sealing film 75 is covered with a stop film 75 and is flattened by polishing, and the flat bottom surface is a suction head suction region.

（第６実施形態）
図２０はこの発明の第５実施形態としての半導体装置の断面図を示す。この半導体装置では、第２の下層絶縁膜２５の下面のほぼ中央部を含む全体領域に複数個のチップ部品７３が搭載され、第２の下層絶縁膜２５の下面ほぼ中央部に搭載されたチップ部品７３がエポキシ系樹脂やポリイミド系樹脂等からなる封止膜７５で覆われ、この封止膜７５の下面に金属板等からなる平板７６が貼り付けられ、この平板７６の下面が平坦な吸着ヘッド吸着用領域とされている。なお、チップ部品７３の代わりに、あるいは、チップ部品７３と共に、ＬＳＩ等の集積回路からなる半導体ＩＣチップ（図示せず）や、図１に示す半導体構成体２と同等のもの、等を搭載するようにしてもよい。 (Sixth embodiment)
FIG. 20 is a sectional view of a semiconductor device as a fifth embodiment of the present invention. In this semiconductor device, a plurality of chip components 73 are mounted in the entire region including the substantially central portion of the lower surface of the second lower insulating film 25, and the chip is mounted on the lower surface of the second lower insulating film 25. The component 73 is covered with a sealing film 75 made of epoxy resin, polyimide resin, or the like, and a flat plate 76 made of a metal plate or the like is attached to the lower surface of the sealing film 75, and the lower surface of the flat plate 76 is flatly adsorbed. It is a head suction area. Instead of or together with the chip component 73, a semiconductor IC chip (not shown) made of an integrated circuit such as an LSI, or the equivalent of the semiconductor structure 2 shown in FIG. You may do it.

（第７実施形態）
上記第１実施形態では、図１に示すように、第１の下層絶縁膜２２下に下層再配線２４を１層だけ形成した場合について説明したが、これに限らず、２層以上としてもよく、例えば、図２１に示すこの発明の第７実施形態のように、２層としてもよい。すなわち、ベース板１の下面にはビルドアップ材等からなる第１の下層絶縁膜１０１が設けられている。第１の下層絶縁膜１０１の下面には第１の下層下地金属層１０２を含む第１の下層再配線１０３が上下導通部２８に接続されて設けられている。 (Seventh embodiment)
In the first embodiment, as shown in FIG. 1, the case where only one lower layer rewiring 24 is formed under the first lower insulating film 22 has been described. However, the present invention is not limited to this, and two or more layers may be used. For example, it is good also as two layers like 7th Embodiment of this invention shown in FIG. That is, a first lower insulating film 101 made of a buildup material or the like is provided on the lower surface of the base plate 1. A first lower layer rewiring 103 including a first lower layer base metal layer 102 is provided on the lower surface of the first lower layer insulating film 101 so as to be connected to the vertical conduction part 28.

第１の下層再配線１０２を含む第１の下層絶縁膜１０１の下面にはビルドアップ材等からなる第２の下層絶縁膜１０４が設けられている。第２の下層絶縁膜１０４の下面には第２の下層下地金属層１０５を含む第２の下層再配線１０６が第２の下層絶縁膜１０４に形成された開口部１０７を介して第１の下層再配線１０３の接続パッド部に接続されて設けられている。第２の下層再配線１０６を含む第２の下層絶縁膜１０４の下面にはソルダーレジスト等からなる第３の下層絶縁膜１０８が設けられている。第２の下層再配線１０６の接続パッド部に対応する部分における第３の下層絶縁膜１０８には開口部１０９が形成されている。   A second lower insulating film 104 made of a build-up material or the like is provided on the lower surface of the first lower insulating film 101 including the first lower rewiring 102. A second lower layer rewiring 106 including a second lower layer underlying metal layer 105 is formed on the lower surface of the second lower layer insulating film 104 through an opening 107 formed in the second lower layer insulating film 104. It is connected to the connection pad portion of the rewiring 103. A third lower insulating film 108 made of solder resist or the like is provided on the lower surface of the second lower insulating film 104 including the second lower rewiring 106. An opening 109 is formed in the third lower layer insulating film 108 in the portion corresponding to the connection pad portion of the second lower layer rewiring 106.

ところで、この第７実施形態では、上層下地金属層１６を含む上層再配線１７と第１の下層下地金属層１０２を含む第１の下層再配線１０３とを上下導通部２８を介して接続しているが、これに限らず、上層下地金属層１６を含む上層再配線１７と第２の下層下地金属層１０５を含む第２の下層再配線１０６とを上下導通部を介して接続するようにしてもよい。   By the way, in the seventh embodiment, the upper layer rewiring 17 including the upper base metal layer 16 and the first lower layer rewiring 103 including the first lower base metal layer 102 are connected via the vertical conduction part 28. However, the present invention is not limited to this, and the upper layer rewiring 17 including the upper layer base metal layer 16 and the second lower layer rewiring 106 including the second lower layer base metal layer 105 are connected via the vertical conduction portion. Also good.

ここで、図示していないが、上層再配線を２層以上とし、且つ、下層再配線を２層以上とする場合には、図１８および図２１に示す場合も含めて、上層再配線のうちのいずれかの層の上層再配線と下層再配線のうちのいずれかの層の下層再配線とを上下導通部を介して接続するようにしてもよい。   Here, although not shown, when the upper layer rewiring has two or more layers and the lower layer rewiring has two or more layers, including the cases shown in FIGS. The upper layer rewiring and the lower layer rewiring of any one of the lower layer rewirings may be connected via the vertical conduction part.

（第８実施形態）
上記第１実施形態には、互いに隣接する半導体構成体２間において切断したが、これに限らず、２個またはそれ以上の半導体構成体２を１組として切断し、例えば、図２２に示すこの発明の第８実施形態のように、２個の半導体構成体２を１組として切断し、マルチチップモジュール型の半導体装置を得るようにしてもよい。この場合、２個で１組の半導体構成体２は同種、異種のいずれであってもよい。 (Eighth embodiment)
In the first embodiment, the semiconductor structures 2 adjacent to each other are cut. However, the present invention is not limited to this, and two or more semiconductor structures 2 are cut as one set, for example, as shown in FIG. As in the eighth embodiment of the invention, two semiconductor structures 2 may be cut as a set to obtain a multichip module type semiconductor device. In this case, the two sets of semiconductor structures 2 may be of the same type or different types.

（第９実施形態）
図２３はこの発明の第９実施形態としての半導体装置の断面図を示す。この半導体装置では、例えば図１に示すものと同じものからなる第１の半導体ブロック８１下に第２、第３の半導体ブロック８２、８３が搭載されている。この場合、第２の半導体ブロック８２は、例えば図１に示すものと比較して、半田ボール２１を備えていないものからなっている。第３の半導体ブロック８３は、例えば図１に示すものと比較して、貫通孔２７、上下導通部２８、導電材２９、第１の下層絶縁膜２２、第２の下層絶縁膜２５、下層下地金属層２３、下層再配線２４および半田ボール２１を備えていないものからなっている。 (Ninth embodiment)
FIG. 23 is a sectional view of a semiconductor device as a ninth embodiment of the invention. In this semiconductor device, for example, second and third semiconductor blocks 82 and 83 are mounted under a first semiconductor block 81 made of the same one as shown in FIG. In this case, the second semiconductor block 82 is not provided with the solder ball 21 as compared with, for example, that shown in FIG. The third semiconductor block 83 includes, for example, a through hole 27, a vertical conduction portion 28, a conductive material 29, a first lower insulating film 22, a second lower insulating film 25, and a lower base as compared with the one shown in FIG. The metal layer 23, the lower layer rewiring 24, and the solder ball 21 are not provided.

また、第１の半導体ブロック８１と第２の半導体ブロック８２とは、その間に介在された接着層８４を介して接着されている。この場合、第１の半導体ブロック８１の下層再配線２４の接続パッド部と第２の半導体ブロック８２の上層再配線１７の接続パッド部とは、接着層８４に設けられた貫通孔８５の部分に設けられた導電材８６を介して接続されている。   Further, the first semiconductor block 81 and the second semiconductor block 82 are bonded through an adhesive layer 84 interposed therebetween. In this case, the connection pad portion of the lower layer rewiring 24 of the first semiconductor block 81 and the connection pad portion of the upper layer rewiring 17 of the second semiconductor block 82 are formed in the portion of the through hole 85 provided in the adhesive layer 84. They are connected via a conductive material 86 provided.

さらに、第２の半導体ブロック８２と第３の半導体ブロック８３とは、その間に介在された接着層８７を介して接着されている。この場合、第２の半導体ブロック８２の下層再配線２４の接続パッド部と第３の半導体ブロック８３の上層再配線１７の接続パッド部とは、接着層８７に設けられた貫通孔８８の部分に設けられた導電材８９を介して接続されている。   Further, the second semiconductor block 82 and the third semiconductor block 83 are bonded to each other through an adhesive layer 87 interposed therebetween. In this case, the connection pad portion of the lower layer rewiring 24 of the second semiconductor block 82 and the connection pad portion of the upper layer rewiring 17 of the third semiconductor block 83 are formed in the portion of the through hole 88 provided in the adhesive layer 87. They are connected via a conductive material 89 provided.

次に、この半導体装置の製造方法の一例について説明する。まず、図２４に示すように、例えば、第２の半導体ブロック８２の第２の上層絶縁膜１９の上面に、液晶ポリマー、熱可塑性ポリイミド、ＰＥＥＫ（ポリエーテルエーテルケトン）、ＰＰＳ（ポリフェニレンサルファイド）等の熱可塑性樹脂からなる薄いシート状の接着層８４を貼り付ける。この場合、接着層８４の上面には保護フィルム９０が貼り付けられている。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 24, for example, a liquid crystal polymer, thermoplastic polyimide, PEEK (polyether ether ketone), PPS (polyphenylene sulfide), etc. are formed on the upper surface of the second upper insulating film 19 of the second semiconductor block 82. A thin sheet-like adhesive layer 84 made of a thermoplastic resin is attached. In this case, a protective film 90 is attached to the upper surface of the adhesive layer 84.

次に、レーザビームを照射するレーザ加工により、第２の上層絶縁膜１９の開口部２０つまり上層再配線１７の接続パッド部に対応する部分における保護フィルム９０および接着層８４に貫通孔８５を形成する。次に、貫通孔８５および開口部２０内に、スクリーン印刷法等により、低温焼結可能な銅ペースト、銀ペースト、導電性樹脂等からなる導電材８６を充填する。次に、保護フィルム９０を剥離する。この状態では、導電材８６は接着層８４上に保護フィルム９０の厚さの分だけ突出されている。   Next, through holes 85 are formed in the protective film 90 and the adhesive layer 84 at the portions corresponding to the openings 20 of the second upper insulating film 19, that is, the connection pad portions of the upper layer rewiring 17, by laser processing with laser beam irradiation. To do. Next, the through hole 85 and the opening 20 are filled with a conductive material 86 made of copper paste, silver paste, conductive resin, or the like that can be sintered at low temperature by a screen printing method or the like. Next, the protective film 90 is peeled off. In this state, the conductive material 86 protrudes on the adhesive layer 84 by the thickness of the protective film 90.

次に、上記と同様にして、第３の半導体ブロック８３の第２の上層絶縁膜１９の上面に貼り付けられた接着層８７に形成された貫通孔８８内等に導電材８９が充填されたものを用意する。次に、図２５に示すように、第３の半導体ブロック８３上の接着層８７上に第２の半導体ブロック８２を配置し、第２の半導体ブロック８２上の接着層８４上に第１の半導体ブロック８１を配置する。この場合、第１の半導体ブロック８１には半田ボール２１は形成されていない。また、このように配置した状態では、導電材８６、８９の上部はその上の半導体ブロック８１、８２の第２の下層絶縁膜２５の開口部２６内に挿入されている。   Next, in the same manner as described above, the conductive material 89 is filled into the through-hole 88 formed in the adhesive layer 87 attached to the upper surface of the second upper insulating film 19 of the third semiconductor block 83. Prepare things. Next, as shown in FIG. 25, the second semiconductor block 82 is disposed on the adhesive layer 87 on the third semiconductor block 83, and the first semiconductor is formed on the adhesive layer 84 on the second semiconductor block 82. A block 81 is arranged. In this case, the solder ball 21 is not formed on the first semiconductor block 81. Further, in such a state, the upper portions of the conductive materials 86 and 89 are inserted into the openings 26 of the second lower insulating film 25 of the semiconductor blocks 81 and 82 thereon.

次に、一対の加熱加圧板９１、９２を用いて、第１〜第３の半導体ブロック８１〜８３および接着層８４、８７を加熱加圧する。すると、導電材８６、８９が焼結し、導電材８６を介して、第１の半導体ブロック８１の下層再配線２４の接続パッド部と第２の半導体ブロック８２の上層再配線１７の接続パッド部とが接続され、また、導電材８９を介して、第２の半導体ブロック８２の下層再配線２４の接続パッド部と第３の半導体ブロック８３の上層再配線１７の接続パッド部とが接続される。   Next, the first to third semiconductor blocks 81 to 83 and the adhesive layers 84 and 87 are heated and pressurized using a pair of heating and pressing plates 91 and 92. Then, the conductive materials 86 and 89 are sintered, and the connection pad portion of the lower layer rewiring 24 of the first semiconductor block 81 and the connection pad portion of the upper layer rewiring 17 of the second semiconductor block 82 are interposed via the conductive material 86. And the connection pad portion of the lower layer rewiring 24 of the second semiconductor block 82 and the connection pad portion of the upper layer rewiring 17 of the third semiconductor block 83 are connected via the conductive material 89. .

また、接着層８４、８７が硬化すると、接着層８４を介して、第１の半導体ブロック８１と第２の半導体ブロック８２とが接着され、また、接着層８７を介して、第２の半導体ブロック８２と第３の半導体ブロック８３とが接着される。次に、図２３に示すように、第１の半導体ブロック８１上に半田ボール２１を形成する。かくして、図２２に示す半導体装置が得られる。   When the adhesive layers 84 and 87 are cured, the first semiconductor block 81 and the second semiconductor block 82 are bonded via the adhesive layer 84, and the second semiconductor block is bonded via the adhesive layer 87. 82 and the third semiconductor block 83 are bonded together. Next, as shown in FIG. 23, solder balls 21 are formed on the first semiconductor block 81. Thus, the semiconductor device shown in FIG. 22 is obtained.

以上のように、上記製造方法では、第１〜第３の半導体ブロック８１〜８３をその各間に介在された接着層８４、８７を介して一度に接着しているので、製造工程を簡略化することができる。なお、第３の半導体ブロック８３は、第２の半導体ブロック８２と同様に、例えば図１に示すものと比較して、半田ボール２１を備えていないものとしてもよい。   As described above, in the manufacturing method described above, the first to third semiconductor blocks 81 to 83 are bonded at once via the adhesive layers 84 and 87 interposed therebetween, so that the manufacturing process is simplified. can do. Note that, like the second semiconductor block 82, the third semiconductor block 83 may not include the solder balls 21 as compared with, for example, the one shown in FIG.

（その他の実施形態）
上記各実施形態において、半導体構成体２は、外部接続用電極として、再配線１１の接続パッド部上に設けられた柱状電極１２を有するものとしたが、これに限定されるものではない。例えば、半導体構成体２は、外部接続用電極としての接続パッド部を有する再配線１１を有するものであってもよく、また、外部接続用電極としての接続パッド５を有するものであってもよく、さらに、外部接続用電極として、接続パッド５上に設けられた柱状電極を有するものであってもよい。 (Other embodiments)
In each said embodiment, although the semiconductor structure 2 shall have the columnar electrode 12 provided on the connection pad part of the rewiring 11 as an external connection electrode, it is not limited to this. For example, the semiconductor structure 2 may have a rewiring 11 having a connection pad portion as an external connection electrode, or may have a connection pad 5 as an external connection electrode. Furthermore, the electrode for external connection may have a columnar electrode provided on the connection pad 5.

また、例えば、図１に示す第１実施形態においては、半田ボール２１は第２の上層絶縁膜１９に設けられた開口部２０から露出された上層再配線１７の接続パッド部に接続されて設けられるとしたが、これに限るものではなく、例えば、半田ボール２１を第２の下層絶縁膜２５に設けられた開口部２６から露出された下層再配線２４に接続させて設けるようにしてもよい。また、例えば、図１８に示す第４実施形態においては、チップ部品７３や半導体チップ等は下層絶縁膜２５の下面に、下層再配線２４に接続させて搭載するとしたが、これに限るものではなく、例えば、チップ部品７３や半導体チップ等を上層絶縁膜１９の上面に、上層再配線１７の接続パッド部に接続させて搭載するようにしてもよい。   Further, for example, in the first embodiment shown in FIG. 1, the solder ball 21 is provided connected to the connection pad portion of the upper layer rewiring 17 exposed from the opening 20 provided in the second upper layer insulating film 19. However, the present invention is not limited to this. For example, the solder ball 21 may be connected to the lower layer rewiring 24 exposed from the opening 26 provided in the second lower layer insulating film 25. . For example, in the fourth embodiment shown in FIG. 18, the chip component 73, the semiconductor chip, and the like are mounted on the lower surface of the lower insulating film 25 while being connected to the lower layer rewiring 24. However, the present invention is not limited to this. For example, the chip component 73, the semiconductor chip, or the like may be mounted on the upper surface of the upper insulating film 19 while being connected to the connection pad portion of the upper layer rewiring 17.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初用意したものの断面図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図３に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図４に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図５に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図６に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図７に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図８に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図９に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１０に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１１に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１２に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１３に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１４に続く製造工程の断面図。FIG. 15 is a cross-sectional view of the manufacturing process following FIG. 14. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention. この発明の第３実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 3rd Embodiment of this invention. この発明の第４実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 4th Embodiment of this invention. この発明の第５実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 5th Embodiment of this invention. この発明の第６実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 6th Embodiment of this invention. この発明の第７実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 7th Embodiment of this invention. この発明の第８実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 8th Embodiment of this invention. この発明の第９実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 9th Embodiment of this invention. 図２３に示す半導体装置の製造方法の一例において、所定の製造工程の断面図。FIG. 24 is a cross-sectional view of a predetermined manufacturing process in the example of the method for manufacturing the semiconductor device shown in FIG. 23. 図２４に続く製造工程の断面図。FIG. 25 is a cross-sectional view of the manufacturing process following FIG. 24.

符号の説明Explanation of symbols

１ ベース板
２ 半導体構成体
３ 接着層
４ シリコン基板
５ 接続パッド
１１ 再配線
１２ 柱状電極
１３ 封止膜
１４ 絶縁層
１５ 第１の上層絶縁膜
１７ 上層再配線
１９ 第２の上層絶縁膜
２１ 半田ボール
２２ 第１の下層絶縁膜
２４ 下層再配線
２５ 第２の下層絶縁膜
２７ 貫通孔
２８ 上下導通部 DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Adhesion layer 4 Silicon substrate 5 Connection pad 11 Rewiring 12 Columnar electrode 13 Sealing film 14 Insulating layer 15 1st upper layer insulating film 17 Upper layer rewiring 19 2nd upper layer insulating film 21 Solder ball 22 1st lower layer insulating film 24 Lower layer rewiring 25 2nd lower layer insulating film 27 Through-hole 28 Vertical conduction part

Claims (49)

ベース板と、
該ベース板上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する少なくとも１つの半導体構成体と、
該半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、
該絶縁層上に、少なくとも一部が前記半導体構成体の外部接続用電極に接続されて設けられ、且つ、接続パッド部を有する少なくとも１層の上層再配線と、
前記ベース板下に設けられた少なくとも１層の下層再配線と、
前記絶縁層および前記ベース板に設けられた貫通孔内に前記上層再配線のうちのいずれかの層の上層再配線と前記下層再配線のうちのいずれかの層の下層再配線とを接続するように設けられた上下導通部と、
を備えていることを特徴とする半導体装置。 A base plate,
At least one semiconductor structure provided on the base plate and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate;
An insulating layer provided on the base plate around the semiconductor structure;
On the insulating layer, at least a part of the upper redistribution layer provided to be connected to the external connection electrode of the semiconductor structure and having a connection pad portion;
At least one lower layer rewiring provided under the base plate;
An upper layer rewiring of any one of the upper layer rewirings and a lower layer rewiring of any one of the lower layer rewirings are connected in through holes provided in the insulating layer and the base plate. The vertical conduction part provided as follows:
A semiconductor device comprising: 請求項１に記載の発明において、前記ベース板上に前記半導体構成体が複数個相互に離間して設けられていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein a plurality of the semiconductor structural bodies are provided on the base plate so as to be separated from each other. 請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とする半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor structure includes a columnar electrode as the external connection electrode. 請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッド部を有する再配線を有するものであることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the semiconductor structure has a rewiring having a connection pad portion as the external connection electrode. 請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッドを有するものであることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the semiconductor structure has a connection pad as the external connection electrode. 請求項１に記載の発明において、前記最上層の上層再配線の接続パッド部を除く部分を覆う上層絶縁膜を有することを特徴とする半導体装置。 2. The semiconductor device according to claim 1, further comprising an upper insulating film that covers a portion excluding the connection pad portion of the uppermost upper layer rewiring. 請求項６に記載の発明において、前記最上層の上層再配線の接続パッド部上に半田ボールが設けられていることを特徴とする半導体装置。 7. The semiconductor device according to claim 6, wherein a solder ball is provided on a connection pad portion of the uppermost layer rewiring. 請求項６に記載の発明において、前記上層絶縁膜上に電子部品が前記最上層の上層再配線の接続パッド部に接続されて搭載されていることを特徴とする半導体装置。 7. The semiconductor device according to claim 6, wherein an electronic component is mounted on the upper insulating film so as to be connected to a connection pad portion of the uppermost upper layer rewiring. 請求項１に記載の発明において、前記最下層の下層再配線の接続パッド部を除く部分を覆う下層絶縁膜を有することを特徴とする半導体装置。 2. The semiconductor device according to claim 1, further comprising a lower insulating film that covers a portion excluding the connection pad portion of the lowermost lower layer rewiring. 請求項９に記載の発明において、前記下層再配線の接続パッド部下に半田ボールが設けられていることを特徴とする半導体装置。 10. The semiconductor device according to claim 9, wherein a solder ball is provided under a connection pad portion of the lower layer rewiring. 請求項９に記載の発明において、前記最下層の下層絶縁膜下に電子部品が前記最下層の下層再配線の接続パッド部に接続されて搭載されていることを特徴とする半導体装置。 10. The semiconductor device according to claim 9, wherein an electronic component is connected to and mounted on a connection pad portion of the lowermost lower layer rewiring under the lowermost lower layer insulating film. 請求項１１に記載の発明において、前記下層絶縁膜下の少なくとも一部に平坦な吸着ヘッド吸着用領域が設けられていることを特徴とする半導体装置。 12. The semiconductor device according to claim 11, wherein a flat suction head suction region is provided at least partly below the lower insulating film. 請求項１２に記載の発明において、前記電子部品は前記下層絶縁膜下の周辺部に搭載され、前記下層絶縁膜の下面ほぼ中央部が前記吸着ヘッド吸着用領域とされていることを特徴とする半導体装置。 The invention according to claim 12 is characterized in that the electronic component is mounted in a peripheral portion below the lower insulating film, and a substantially central portion of the lower surface of the lower insulating film is used as the suction head suction region. Semiconductor device. 請求項１２に記載の発明において、前記電子部品は複数個で前記下層絶縁膜の下面ほぼ中央部を含む領域に搭載され、前記複数個の電子部品は封止膜で覆われ、該封止膜の下面が前記吸着ヘッド吸着用領域とされていることを特徴とする半導体装置。 The invention according to claim 12, wherein a plurality of the electronic components are mounted in a region including a substantially central portion of the lower surface of the lower insulating film, and the plurality of electronic components are covered with a sealing film, A lower surface of the semiconductor device is the suction head suction region. 請求項１２に記載の発明において、前記電子部品は複数個で前記下層絶縁膜の下面全体に搭載され、前記下層絶縁膜の下面ほぼ中央部に搭載された前記電子部品は封止膜で覆われ、該封止膜の下面に平板が設けられ、該平板の下面は前記吸着ヘッド吸着用領域とされていることを特徴とする半導体装置。 The invention according to claim 12, wherein a plurality of the electronic components are mounted on the entire lower surface of the lower insulating film, and the electronic components mounted substantially at the center of the lower surface of the lower insulating film are covered with a sealing film. A semiconductor device, wherein a flat plate is provided on the lower surface of the sealing film, and the lower surface of the flat plate serves as the suction head suction region. 請求項１に記載の発明において、前記下層再配線の少なくとも一部または前記上層再配線の一部により薄膜回路素子が形成されていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein a thin film circuit element is formed by at least a part of the lower layer rewiring or a part of the upper layer rewiring. 請求項１６に記載の発明において、前記薄膜回路素子は、インダクタ回路、またはアンテナ回路、のいずれかを含むことを特徴とする半導体装置。 17. The semiconductor device according to claim 16, wherein the thin film circuit element includes either an inductor circuit or an antenna circuit. 請求項１に記載の発明において、前記ベース板の上面にグラウンド層が設けられていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein a ground layer is provided on an upper surface of the base plate. 請求項１８に記載の発明において、前記グラウンド層は前記上下導通部または前記下層再配線に接続されていることを特徴とする半導体装置。 The semiconductor device according to claim 18, wherein the ground layer is connected to the vertical conduction portion or the lower layer rewiring. 少なくとも、ベース板と、該ベース板上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する、少なくとも１つの半導体構成体と、該半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、該絶縁層上に少なくとも一部が前記半導体構成体の外部接続用電極に接続されて設けられ、且つ、接続パッド部を有する、少なくとも１層の上層再配線と、を備えた第１の半導体装置と、
ベース板と、該ベース板上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する、少なくとも１つの半導体構成体と、該半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、該絶縁層上に少なくとも一部が前記半導体構成体の外部接続用電極に接続されて設けられ、且つ、接続パッド部を有する、少なくとも１層の上層再配線と、前記ベース板下に設けられた少なくとも１層の下層再配線と、前記絶縁層および前記ベース板に設けられた貫通孔内に前記上層再配線のうちのいずれかの層の上層再配線と前記下層再配線のうちのいずれかの層の下層再配線とを接続するように設けられた上下導通部と、を備えた第２の半導体装置と、を備え、
前記第１の半導体装置上に、一乃至複数個の前記第２の半導体装置が互いに接続されて積層され、
前記積層された第１の半導体装置と第２の半導体装置の間、または、複数の前記第２の半導体装置の間、の接続部において、上側の半導体装置の前記最下層の下層再配線の接続パッド部と、下側の半導体装置の前記最上層の上層再配線の接続パッド部と、が接続されていることを特徴とする半導体装置。 At least one semiconductor structure having at least a base plate, a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and a periphery of the semiconductor structure An insulating layer provided on the base plate, and at least a part of the insulating layer provided on the insulating layer connected to the external connection electrode of the semiconductor structure and having a connection pad portion A first semiconductor device comprising an upper layer rewiring;
A base plate, at least one semiconductor structure having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and the periphery of the semiconductor structure. An insulating layer provided on the base plate; and at least a part of the upper layer formed on the insulating layer and connected to the external connection electrode of the semiconductor structure and having a connection pad portion. An upper layer rewiring of any layer of the wiring, at least one lower layer rewiring provided under the base plate, and the upper layer rewiring in the through hole provided in the insulating layer and the base plate And a vertical conduction part provided to connect the lower layer rewiring of any one of the lower layer rewirings, and a second semiconductor device comprising:
On the first semiconductor device, one or a plurality of the second semiconductor devices are connected to each other and stacked,
Connection of the lower layer lower layer rewiring of the upper semiconductor device at a connection portion between the stacked first semiconductor devices and the second semiconductor devices or between the plurality of second semiconductor devices. A semiconductor device characterized in that a pad portion and a connection pad portion of the uppermost layer rewiring of the lower semiconductor device are connected. 請求項２０に記載の発明において、前記上側の半導体装置と、前記下側の半導体装置とが、その間に介在された接着層を介して接着されていることを特徴とする半導体装置。 21. The semiconductor device according to claim 20, wherein the upper semiconductor device and the lower semiconductor device are bonded through an adhesive layer interposed therebetween. 請求項２１に記載の発明において、前記上側の半導体装置の最下層の下層再配線の接続パッド部と、前記下側の半導体装置の最上層の上層再配線の接続パッド部とは、前記接着層に設けられた貫通孔内に設けられた導電材を介して接続されていることを特徴とする半導体装置。 23. The connection pad portion of the lower layer rewiring of the lowermost layer of the upper semiconductor device and the connection pad portion of the upper layer rewiring of the uppermost layer of the lower semiconductor device according to the invention of claim 21, A semiconductor device, wherein the semiconductor device is connected via a conductive material provided in a through hole provided in the semiconductor device. 請求項２０に記載の発明において、前記第１および第２の半導体装置は、前記最上層の上層再配線の接続パッド部を除く部分を覆う上層絶縁膜を有することを特徴とする半導体装置。 21. The semiconductor device according to claim 20, wherein the first and second semiconductor devices have an upper insulating film that covers a portion of the uppermost upper layer rewiring except for connection pad portions. 請求項２３に記載の発明において、前記積層された第２の半導体装置の最上層の半導体装置の、前記最上層の上層再配線の接続パッド部上に半田ボールが設けられていることを特徴とする半導体装置。 25. The invention according to claim 23, wherein a solder ball is provided on a connection pad portion of the uppermost upper layer rewiring of the uppermost semiconductor device of the stacked second semiconductor devices. Semiconductor device. ベース板上に、各々が半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する複数の半導体構成体を相互に離間させて配置する工程と、
前記半導体構成体の周囲における前記ベース板上に絶縁層を形成する工程と、
接続パッド部を有し、且つ、少なくとも一部がいずれかの前記半導体構成体の前記外部接続用電極に接続される少なくとも１層の上層再配線を、該上層再配線のうち、最上層の上層再配線の接続パッド部が前記絶縁層上に配置されるように形成する工程と、
前記ベース板下に少なくとも１層の下層再配線を形成する工程と、
前記絶縁層および前記ベース板に形成された貫通孔内に前記上層再配線のうちのいずれかの層の上層再配線と前記下層再配線のうちのいずれかの層の下層再配線とを接続する上下導通部を形成する工程と、
前記半導体構成体間における前記絶縁層および前記ベース板を切断して前記最上層の上層再配線の接続パッド部が前記絶縁層上に配置された半導体装置を複数個得る工程と、
を有することを特徴とする半導体装置の製造方法。 A step of disposing, on the base plate, a plurality of semiconductor structures each having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate;
Forming an insulating layer on the base plate around the semiconductor structure;
At least one upper layer redistribution having a connection pad portion and at least a part of which is connected to the external connection electrode of any one of the semiconductor structures, the uppermost upper layer among the upper layer redistributions Forming a connection pad portion of rewiring so as to be disposed on the insulating layer;
Forming at least one lower layer rewiring under the base plate;
An upper layer rewiring of any one of the upper layer rewirings and a lower layer rewiring of any one of the lower layer rewirings are connected in through holes formed in the insulating layer and the base plate. Forming a vertical conduction part;
Cutting the insulating layer and the base plate between the semiconductor structures to obtain a plurality of semiconductor devices in which connection pads of the uppermost upper layer rewiring are arranged on the insulating layer;
A method for manufacturing a semiconductor device, comprising: 請求項２５に記載の発明において、前記最下層の上層再配線と、前記最上層の下層再配線と、前記上下導通部と、を同時に形成することを特徴とする半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, wherein the uppermost lower layer rewiring, the uppermost lower layer rewiring, and the vertical conduction portion are formed simultaneously. 請求項２５に記載の発明において、前記最下層の上層再配線と、前記最上層の下層再配線と、を同時に形成することを特徴とする半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, wherein the uppermost lower layer rewiring and the uppermost lower layer rewiring are simultaneously formed. 請求項２５に記載の発明において、前記最下層の上層再配線と、前記最上層の下層再配線と、を別々に形成することを特徴とする半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, wherein the lowermost layer upper layer rewiring and the uppermost layer lower layer rewiring are formed separately. 請求項２７または２８に記載の発明において、前記最下層の上層再配線および前記最上層の下層再配線を形成した後に、前記絶縁層および前記ベース板に前記貫通孔を形成し、該貫通孔内に導電性ペーストからなる前記上下導通部を形成することを特徴とする半導体装置の製造方法。 29. The invention according to claim 27 or 28, wherein after forming the lowermost layer upper layer rewiring and the uppermost layer lower layer rewiring, the through hole is formed in the insulating layer and the base plate, A method for manufacturing a semiconductor device, comprising: forming the upper and lower conductive portions made of a conductive paste. 請求項２５に記載の発明において、前記切断は、前記半導体構成体が複数個含まれるように切断することを特徴とする半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, wherein the cutting is performed so that a plurality of the semiconductor structural bodies are included. 請求項２５に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とする半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, wherein the semiconductor structure has a columnar electrode as the external connection electrode. 請求項２５に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッド部を有する再配線を有するものであることを特徴とする半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, wherein the semiconductor structure includes a rewiring having a connection pad portion as the external connection electrode. 請求項２５に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッドを有するものであることを特徴とする半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, wherein the semiconductor structure has a connection pad as the external connection electrode. 請求項２５に記載の発明において、前記最上層の上層再配線の接続パッド部を除く部分を覆う上層絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, further comprising a step of forming an upper insulating film that covers a portion of the uppermost upper layer rewiring except a connection pad portion. 請求項３４に記載の発明において、前記最上層の上層再配線の接続パッド部上に半田ボールを形成する工程を有することを特徴とする半導体装置の製造方法。 35. The method of manufacturing a semiconductor device according to claim 34, further comprising a step of forming a solder ball on a connection pad portion of the upper-layer upper layer rewiring. 請求項３４に記載の発明において、前記上層絶縁膜上に電子部品を前記上層再配線の接続パッド部に接続させて搭載する工程を有することを特徴とする半導体装置の製造方法。 35. The method of manufacturing a semiconductor device according to claim 34, further comprising a step of mounting an electronic component on the upper insulating film while being connected to a connection pad portion of the upper rewiring. 請求項２５に記載の発明において、前記最下層の下層再配線の接続パッド部を除く部分を覆う下層絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, further comprising a step of forming a lower insulating film that covers a portion excluding the connection pad portion of the lowermost lower layer rewiring. 請求項３７に記載の発明において、前記最下層の下層再配線の接続パッド部下に半田ボールを形成する工程を有することを特徴とする半導体装置の製造方法。 38. The method of manufacturing a semiconductor device according to claim 37, further comprising a step of forming a solder ball under a connection pad portion of the lowermost lower layer rewiring. 請求項３７に記載の発明において、前記下層絶縁膜下に電子部品を前記最下層の下層再配線の接続パッド部に接続させて搭載する工程を有することを特徴とする半導体装置の製造方法。 38. The method of manufacturing a semiconductor device according to claim 37, further comprising a step of connecting and mounting an electronic component under the lower insulating film to a connection pad portion of the lowermost lower layer rewiring. 請求項３８に記載の発明において、前記下層絶縁膜下の少なくとも一部に平坦な吸着ヘッド吸着用領域を形成する工程を有することを特徴とする半導体装置の製造方法。 39. The method of manufacturing a semiconductor device according to claim 38, further comprising a step of forming a flat suction head suction region at least partly below the lower insulating film. 請求項２５に記載の発明において、前記下層再配線の少なくとも一部または前記上層再配線の一部により薄膜回路素子を形成することを特徴とする半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, wherein a thin film circuit element is formed by at least a part of the lower layer rewiring or a part of the upper layer rewiring. 請求項４１に記載の発明において、前記薄膜回路素子は、インダクタ回路、またはアンテナ回路、のいずれかを含むことを特徴とする半導体装置の製造方法。 42. The method of manufacturing a semiconductor device according to claim 41, wherein the thin film circuit element includes either an inductor circuit or an antenna circuit. 請求項２５に記載の発明において、前記ベース板の上面にグラウンド層を形成する工程を有することを特徴とする半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, further comprising a step of forming a ground layer on an upper surface of the base plate. 請求項４３に記載の発明において、前記上下導通部または前記最上層の下層再配線を形成するとき、前記上下導通部または前記最上層の下層再配線を前記グラウンド層に接続することを特徴とする半導体装置の製造方法。 45. The invention according to claim 43, wherein when forming the vertical conduction part or the uppermost lower layer rewiring, the vertical conduction part or the uppermost lower layer rewiring is connected to the ground layer. A method for manufacturing a semiconductor device. 少なくとも、ベース板と、該ベース板上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する、少なくとも１つの半導体構成体と、該半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、該絶縁層上に少なくとも一部が前記半導体構成体の外部接続用電極に接続されて設けられ、且つ、接続パッド部を有する、少なくとも１層の上層再配線と、を備えた第１の半導体装置と、
ベース板と、該ベース板上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する、少なくとも１つの半導体構成体と、該半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、該絶縁層上に少なくとも一部が前記半導体構成体の外部接続用電極に接続されて設けられ、且つ、接続パッド部を有する、少なくとも１層の上層再配線と、前記ベース板下に設けられた少なくとも１層の下層再配線と、前記絶縁層および前記ベース板に設けられた貫通孔内に前記上層再配線のうちのいずれかの層の上層再配線と前記下層再配線のうちのいずれかの層の下層再配線とを接続するように設けられた上下導通部と、を備えた第２の半導体装置と、を備え、
前記第１の半導体装置上に、一乃至複数個の前記第２の半導体装置を積層し、積層する前記第１の半導体装置と第２の半導体装置の間、または、複数の前記第２の半導体装置の間において、上側の半導体装置の最下層の下層再配線の接続パッド部と下側の半導体装置の最上層の上層再配線の接続パッド部とを接続する工程を有することを特徴とする半導体装置の製造方法。 At least one semiconductor structure having at least a base plate, a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and a periphery of the semiconductor structure An insulating layer provided on the base plate, and at least a part of the insulating layer provided on the insulating layer connected to the external connection electrode of the semiconductor structure and having a connection pad portion A first semiconductor device comprising an upper layer rewiring;
A base plate, at least one semiconductor structure having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and the periphery of the semiconductor structure. An insulating layer provided on the base plate; and at least a part of the upper layer formed on the insulating layer and connected to the external connection electrode of the semiconductor structure and having a connection pad portion. An upper layer rewiring of any layer of the wiring, at least one lower layer rewiring provided under the base plate, and the upper layer rewiring in the through hole provided in the insulating layer and the base plate And a vertical conduction part provided to connect the lower layer rewiring of any one of the lower layer rewirings, and a second semiconductor device comprising:
One to a plurality of second semiconductor devices are stacked on the first semiconductor device, and the first semiconductor device and the second semiconductor device to be stacked, or a plurality of the second semiconductor devices. A semiconductor comprising a step of connecting a connection pad portion of a lower layer rewiring in the lowermost layer of the upper semiconductor device and a connection pad portion of an upper layer rewiring of the uppermost semiconductor device between the devices. Device manufacturing method. 請求項４５に記載の発明において、前記第１の半導体装置および第２の半導体装置を、その各間に介在された接着層を介して一度に接着する工程を有することを特徴とする半導体装置の製造方法。 45. The semiconductor device according to claim 45, further comprising a step of bonding the first semiconductor device and the second semiconductor device at a time through an adhesive layer interposed therebetween. Production method. 請求項４６に記載の発明において、前記接着工程において、前記上側の半導体装置の最下層の下層再配線の接続パッド部と、前記下側の半導体装置の最上層の上層再配線の接続パッド部とを、前記接着層に設けられた貫通孔内に設けられた導電材を介して接続することを特徴とする半導体装置の製造方法。 47. In the invention according to claim 46, in the bonding step, a connection pad portion of a lower layer rewiring of the lowermost layer of the upper semiconductor device, and a connection pad portion of an upper layer rewiring of the uppermost layer of the lower semiconductor device, Are connected through a conductive material provided in a through-hole provided in the adhesive layer. 請求項４５に記載の発明において、前記第１および第２の半導体装置は、前記最上層の上層再配線の接続パッド部を除く部分を覆う上層絶縁膜を有することを特徴とする半導体装置の製造方法。 46. The semiconductor device according to claim 45, wherein the first and second semiconductor devices have an upper insulating film that covers a portion of the uppermost upper layer rewiring except a connection pad portion. Method. 請求項４５に記載の発明において、前記第１および第２の半導体装置を積層した後に、前記積層された第２の半導体装置の最上層の半導体装置の、前記最上層の上層再配線の接続パッド部上に半田ボールを形成する工程を有することを特徴とする半導体装置の製造方法。
46. The connection pad of the uppermost upper layer rewiring of the uppermost semiconductor device of the stacked second semiconductor device after the first and second semiconductor devices are stacked after the first and second semiconductor devices are stacked. A method for manufacturing a semiconductor device, comprising: forming a solder ball on a portion.
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JP2008073818A (en) * 2006-09-22 2008-04-03 Murata Mfg Co Ltd Electronic component and composite electronic component
JP2008186941A (en) * 2007-01-29 2008-08-14 Cmk Corp Semiconductor device and its manufacturing method
JP4551468B2 (en) * 2007-09-05 2010-09-29 太陽誘電株式会社 Electronic component built-in multilayer board
JP2009081423A (en) * 2007-09-05 2009-04-16 Taiyo Yuden Co Ltd Multilayer board with built-in electronic component and its manufacturing method
US7843071B2 (en) 2008-01-31 2010-11-30 Casio Computer Co., Ltd. Semiconductor device including wiring and manufacturing method thereof
JP2009182202A (en) * 2008-01-31 2009-08-13 Casio Comput Co Ltd Method of manufacturing semiconductor device
JP2009289869A (en) * 2008-05-28 2009-12-10 Shinko Electric Ind Co Ltd Method of manufacturing semiconductor substrate and semiconductor substrate
JP2009289862A (en) * 2008-05-28 2009-12-10 Casio Comput Co Ltd Semiconductor device
JP2013105992A (en) * 2011-11-16 2013-05-30 Casio Comput Co Ltd Semiconductor device built-in substrate module and manufacturing method of the same
JP2017224900A (en) * 2016-06-13 2017-12-21 ラピスセミコンダクタ株式会社 Semiconductor device, communication system, and semiconductor device manufacturing method
KR20190111746A (en) * 2018-03-23 2019-10-02 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor packages and methods of forming same
KR102192020B1 (en) * 2018-03-23 2020-12-17 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor packages and methods of forming same
US11315891B2 (en) 2018-03-23 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming semiconductor packages having a die with an encapsulant

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