JP2007294832A - Integrated circuit chip component, and multi-chip module and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve integration comparable to a silicon process at a low cost by a process and structure other than a silicon process. <P>SOLUTION: An integrated circuit chip component has at least either an integrated circuit chip component of terminal section forming area expansion type in which the terminal section forming surface of the integrated circuit chip is covered by a protection layer and an extending wiring section and a terminal section are formed in the protection layer, or an integrated circuit chip component of terminal section forming area identical type. One or a plurality of integrated circuit chip components of the terminal section forming area expansion type and the terminal section forming area identical type are arranged two-dimensionally or three-dimensionally in a further protection layer and horizontal wiring or vertical wiring for arbitrarily connecting the plurality of integrated circuit chip components in the further protection layer is formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multilayer wiring technique in a silicon process technique, a planarization technique, a three-dimensional chip technique, and a three-dimensional package technique such as SIP (system in package), POP (package on package), or multichip package. .

Conventionally and at present, semiconductor integration has been performed by a silicon process, and the role classification has been clarified from the package technology. For example, integration of semiconductors, addition of functions, and value creation have been performed mainly by silicon processes. However, development costs and manufacturing costs for integrated circuit processes have been enormous. For example, development costs for 65nm nodes have reached 9 billion dollars worldwide, and only some manufacturers can bear them. The trend toward oligopoly is spurring.
As shown in Moore's Law, silicon process miniaturization is updated every two years for one silicon technology node (30% miniaturization, ie, cell size is halved and chip integration is doubled). While the package technology has been reduced to 1.7 / 10 over the past 10 years, the package technology is 100 μm pitch is 30 μm pitch for wire bond diameter, and 250 μm pitch is 150 μm pitch for flip chip connection. In the wiring board technology, the width of 75 μm is about 25 μm, which is about 3/10 at most and there is a difference in reduction speed, and it is estimated that the future trend will further open the difference in the degree of reduction.

  With regard to integration, even in the conventional packaging technology, even if there are small-scale integration technologies found in SIP and POP, it is extremely important to aim at higher density integration several times or more on the extension of the technology. Have difficulty. In addition, the integration of chips in the final product is currently limited by the packaging and mounting technology. Nowadays, it seems that we want a breakthrough of large-scale integration other than silicon process and miniaturization of wiring connection that can realize more advanced information technology, portability, miniaturization, and cost reduction. .

Technologies found in conventional SIP, POP, and 3D chip modules are characterized in the following documents.
As a first example of the prior art, a configuration is known in which thin wiring films and adhesive films to which chips are connected are alternately laminated and via holes formed in both films are connected. (See Patent Document 1 and FIG. 4)
As a second example of the prior art, a semiconductor chip is mounted on a PTP (Paper Thin Package) substrate provided with via connection electrodes, and this is joined to a core substrate provided with via connection electrodes by superposition hot pressing. A stacked configuration is disclosed. (See Patent Document 2 and FIG. 5)
As a third example of the prior art, there is disclosed a configuration in which a plurality of substrates having conductive circuits and interlayer conductive portions are prepared, IC chips are mounted in holes formed in the substrate, and these are stacked and pressure-bonded and laminated. Has been. (Patent Document 3: see FIGS. 6, 9, and 12)
As a fourth example of the prior art, a configuration is known in which through holes are formed in a plurality of chips, and conductive resins are buried and connected to form a stack. (See Patent Document 4: FIG. 1)
In addition, bumps are formed above and below the electrode through-holes formed in the chip, and a plurality of chips are laminated by bonding the bumps, or a plurality of WLPs (Wafer Level Packages) are provided in the wiring board. A configuration is known in which layer embedding and module mounting density are increased.
JP-A-9-232503 JP 2002-343934 A JP 2003-303938 A Japanese Patent No. 2871636

The features, limitations and problems of the prior art can be summarized as follows.
(1) Problems of using bare chips In the conventional laminated structure, a laminated structure in which bare chips probe-tested on a wafer are simply mounted on a substrate is the mainstream. In addition, due to recent demands for miniaturization and thinning, bare chips tend to be thinned, and terminal groups formed on bare chips tend to be narrowed. However, the recent development of wafer-level electrical property test and burn-in test technology is remarkable, but is still incomplete compared to the electrical property test and burn-in test technology applied to incomplete products (package products). For example, a prober of a semiconductor inspection apparatus has a problem that it is difficult to measure a high frequency of several hundred MHz or more in mass production due to restrictions on the length, small diameter, and small pitch of the inspection needle, and a thousand pins found in logic products. There is a problem that the prober corresponding to the above-mentioned multi-pin test is expensive, and there is a problem of inspection limit due to sorting performance and cost of products with good electrical characteristics of bare chips. Furthermore, there is a limit to the removal of initial defects by the burn-in test.
Large integration with imperfect components in such electrical characteristics and reliability would have a significant cost problem due to the yield of the integrated product and the burden of final testing, limiting the integration density. This is the biggest problem of current SIP and multichip modules.

  In addition, for high integration, the thickness of the integrated circuit chip must be made extremely thin (in recent years, the thickness has evolved from 100 μm or less to 10 μm or less). Due to the uneven stress on the surface and the stress on the front and back surfaces, problems such as warping, cracks, cracks and cracks occur on the bare chip itself, and there are also problems such as weak moisture resistance and weak chemical resistance of the bare bare die. There is a risk of chip quality degradation during manufacturing and handling.

(2) Problems when using a packaged product as a component When using a packaged product as a component, in order to solve the above problem, if a device that has been packaged, final tested and selected is used for integration Although the problems related to the bare chip test are solved, there are other problems such as the thickness of the interposer (rewiring board) itself (several tens of μm or more) and the wiring connection of the chip interposer. Refer to)) Obstacles to miniaturization, thinning, and high integration. Further, the bare chip to be packaged itself has a limit on the ultrathinning as described above, and there is a problem that the cost is doubled because the packaged product is further packaged. In addition, there is an example of a structure in which a packaged product is embedded in a wiring board. However, in a packaged product, basically only one layer can be embedded, and it is difficult to wire between embedded packaged products. Considering this, there is a problem that is more competitive than other existing technologies (SiP: System in Package).

(3) Limitations of wiring connection technology, wire bonds, and bumps Wire bonds cannot be made with a wire diameter of 15 μm or less due to capillary restrictions, and bonding pads with a pitch of 25 μm or less are difficult to realize. Since the wiring is basically only the connection between the upper and lower chips and between the chip and the interposer, there is a problem that large integration (10 layers or more) becomes difficult.
In addition, bump formation is expensive, and there is a problem that it is difficult to make the pitch 20 μm or less and 10 μm diameter or less.
In the case of the laminated structure, wiring is basically only the connection between the upper and lower chips, and the connection between the chip and the interposer. Therefore, it is necessary to process the bare chip to be wired, and the wiring becomes complicated. In addition, since direct wiring connection in the horizontal direction is difficult without a wiring substrate on the way, there is a problem that large-scale three-dimensional integration is limited.
(4) Limitations of technology for placing bare chips in or on the wiring board and laminating the wiring boards by bonding or thermocompression Bare chip integration has the basic problems described above, and the individual substrates on which the bare chips are mounted are stacked and bonded. There is a limit to fine patterns due to limitations such as overlay accuracy, substrate warpage, distortion, etc., and thermocompression is particularly unsatisfactory for small and thin integrated modules because stress damage occurs even on thin bare chips. Application fields are limited.

(5) When a through hole is made in a bare chip, filled with a conductive resin, etc., and chip stacking is performed by bonding the upper and lower chips, the shape can be reduced and high integration can be achieved, but there is a basic problem as a bare chip In addition, there are problems in yield reduction, quality reduction, and cost increase due to the provision of through holes in the bare chip, and there are also problems in alignment accuracy and adhesion reliability due to adhesion, and there is a limit to high integration. In addition, when bumps are formed above and below the through electrodes and chip stacking is performed by bump connection, the reliability and manufacturing cost of the multilayer bumps become a problem. Furthermore, when stacking basically through the through-holes in the chip, the wiring is limited and the selectivity of the chip cannot be secured, so the cost of separately creating an additional circuit for securing the selectivity becomes a problem, The limited wiring function limits the improvement of module integration. For this purpose, the production of dedicated chips also greatly increases costs.
(6) In the prior art, there are various structures and manufacturing methods from the viewpoint of satisfying the short-term requirements of application products incorporating integrated circuit chips, and there is a consistent and unified structure and manufacturing method including future miniaturization and integration. Not provided. For this reason, there is a lot of waste in the technical target setting, development mass production process, development of equipment, materials, jigs, standardization, improvement, etc., and the development speed is slow and the cost is high.

Based on the above background, the current state of electrical characteristics and reliability is comparable to that of a finished product without using an interposer for super-integration of integrated circuit chips. Basic element structure that can cope with thinning (from 200 μm to several μm) and its basic elements are arranged in three dimensions with high-density wiring, and for further ultra-thinning and miniaturization technology evolution in the future The fact is that no method has been provided that can basically maintain the same structure and manufacturing method.
The present invention is capable of realizing integration comparable to a silicon process with a process and structure other than the silicon process at a low cost, and at the same time, synthesizing with the integration of the silicon process to achieve a higher level of integration, It is a breakthrough that accelerates value creation in the high-density integration field.

The present invention is a completely new structure and a manufacturing method therefor, which has been constructed based on new knowledge in view of the conventional technology as described above, and the gist of the invention is as follows.
1). In the present invention, at least a terminal portion forming surface of an integrated circuit chip having a terminal portion is covered with a protective layer made of an insulating material having a larger area than the terminal portion forming surface, and the terminal portion is connected to the protective layer. An extension wiring portion and a rearranged terminal portion are formed, and the extension wiring portion extends from the terminal portion in the thickness direction of the protective layer, and the inner side upper and lower conductor portions A conductor portion extending in the surface direction of the protective layer, an outer upper and lower conductor portion for drawing the conductor portion to the outside of the protective layer, and the outer upper and lower conductor portion on the outer side of the protective layer And a repositioning terminal portion provided to be connected to the terminal portion forming area expansion type.
2). In the multichip module of the present invention, at least the terminal part forming surface of the integrated circuit chip provided with the terminal part is covered with a protective layer made of an insulating material having a larger area than the terminal part forming surface, An extended wiring portion for connecting the terminal portion and a rearranged terminal portion are formed, and the extended wiring portion is formed to extend from the terminal portion in the thickness direction of the protective layer; A conductor part formed to extend from the inner side upper and lower conductor part in the surface direction of the protective layer, an outer side upper and lower conductor part for pulling out the conductor part to the outside of the protective layer, and the outer side of the protective layer A terminal portion forming area expansion type integrated circuit chip component comprising a rearrangement terminal portion provided connected to the outer side upper and lower conductor portions;
A terminal portion forming surface of an integrated circuit chip having a terminal portion is covered with a protective layer made of an insulating material having the same area as the terminal portion forming surface, and the protective layer is covered with the protective layer from the terminal portion of the integrated circuit chip. Provided with at least one of integrated circuit chip parts of the same type of terminal part formation area provided with a wiring part connected to a terminal part provided on the outside side,
One or a plurality of integrated circuit chip components of the terminal part formation area expansion type and the terminal part formation area same type are arranged two-dimensionally or three-dimensionally in a further protective layer. A horizontal wiring or a vertical wiring for arbitrarily connecting the plurality of integrated circuit chip components arranged two-dimensionally or three-dimensionally in the protective layer is formed.

3). The multichip module of the present invention is externally connected to any one of the plurality of integrated circuit chip components arranged two-dimensionally or three-dimensionally in the further protective layer via the horizontal wiring or vertical wiring. It is configured to be connectable.
4). In the multichip module of the present invention, a single chip module in which a single integrated circuit chip component is arranged in the protective layer or the multichip module is formed on a wiring board, and the single chip module or the multichip module Electrode bonding of the wiring board is performed by electroplating, a protective layer of the single chip module or multichip module is in close contact with the wiring board, and the single chip module or multichip module is integrated with the wiring board. It is characterized by that.
5). In the multichip module of the present invention, the integrated circuit chip component is covered with a further protective layer arranged in parallel or stacked, and wiring for connecting the terminals of the integrated circuit chip components on the inner side to each other is provided. Provided in the protective layer, connected to and extended on the further protective layer, another terminal is disposed, the mutual protective layers are integrated, and the plurality of integrated circuit chip components are arranged in the further protective layer. It is characterized by being spaced apart.
6). In the multichip module of the present invention, the integrated circuit chip components are assembled in a state in which the integrated circuit chip components are mixed with the integrated circuit chip or the passive element, and a plurality of protective layers are integrated with each other and wired to the internal integrated circuit chip. It is characterized by.
7). The multi-chip module of the present invention satisfies the required requirements via the terminal part of the terminal part forming area expansion type integrated circuit chip part, and passes the electrical characteristics test and burn-in test of high frequency, function, AC, parameter, etc. of 100 MHz or higher. In other words, the protective layers of the integrated circuit chip components having the same quality and reliability are integrated with a further protective layer.
8). The multichip module of the present invention is the multichip module according to any one of 2) to 7), wherein the integrated circuit chip component, the integrated circuit chip, and the passive component inside the protective layer are selectively connected. A vertical wiring or a horizontal wiring to be connected is arranged in a protective layer outside any one of the integrated circuit chip component, the integrated circuit chip, and the passive component.

9). The multichip module of the present invention includes a test terminal for the multilayer circuit chip component in the multichip module on the lower layer side and an upper layer side by the upper and lower conductor portions that vertically conduct the protective layer on the outer side of the internal integrated circuit chip component. A test terminal for an integrated circuit chip of the multichip module is electrically connected.
10). The multichip module of the present invention is the multichip module according to any one of 2) to 9), wherein an external terminal of the multichip module and any integrated circuit chip component or integrated circuit chip or passive in the multichip module. Connection from any connection terminal of the component to any connection terminal of any integrated circuit chip component, integrated circuit chip, and passive component in the multichip module is other than the integrated circuit chip component, integrated circuit chip, and passive component. It is characterized by having a wiring capable of selecting whether or not to be connected via a connection terminal.
11). A method for manufacturing a multichip module according to the present invention includes an integrated circuit chip component according to claim 1, a protective layer covering the integrated circuit chip component, and a previous integration in the protective layer on a substrate or a wiring board. A one-layer chip module is formed by forming a wiring connected to the terminal of the circuit chip component and a horizontal wiring connecting the integrated circuit chip component in the same layer as the via wiring connecting the wiring terminal and the layer, and the one-layer chip module It is characterized by being laminated and manufactured by repeating the manufacturing process.
12). According to a method of manufacturing a multichip module of the present invention, the integrated circuit chip component according to claim 1 or 2 is placed on an insulating material lower protective layer on a base with the terminal portion facing upward, and then the lower portion. An upper protective layer made of an insulating material is formed on the protective layer so as to cover the integrated circuit chip component, and is connected to a terminal portion of the integrated circuit chip component on the upper protective layer and exposed on the upper protective layer. Upper and lower conductor portions are formed, and thereafter, an extended wiring portion connected to the inner upper and lower conductor portions is formed on the upper surface of the lower protective layer, and then the upper protective layer covering the extended wiring portion on the lower protective layer And forming an external upper and lower conductor portion that reaches the upper surface side of the upper protective layer by connecting to the extended wiring portion in the upper protective layer, and then the upper portion on the upper side of the outer upper and lower conductor portion Edge located on top of protective layer And forming a section.
13). The integrated circuit chip component according to claim 1 or 2 is placed on an insulating material lower protective layer formed on a wiring board with a terminal portion of the integrated circuit chip component facing upward, and then the lower protection Form via wiring and terminals to be connected to the wiring board terminals in the layer, and further form an upper protective layer of an insulating material so as to cover the integrated circuit chip component, and connect to the upper protective layer to the lower protective layer upper terminal Forming via wiring and a terminal exposed on the upper protective layer, and connecting the terminal portion of the integrated circuit chip component to the terminal, and an inner upper and lower conductor on the upper surface of the upper protective layer An extended wiring portion connected to the portion is formed.
14). In the method for manufacturing a multichip module of the present invention, a plurality of integrated circuit chip components arranged in a horizontal direction are arranged on the lower protective layer, and the extension wiring portions of the plurality of integrated circuit chip components are connected in a horizontal direction. The horizontal wiring to be formed is formed.
15). The manufacturing method of the multichip module of the present invention satisfies the required requirements via the terminal portion of the integrated circuit chip component of the terminal portion formation area extended type or the terminal portion extended area same type, high frequency of 100 MHz or more, function, AC The protective layers of the integrated circuit chip parts that have passed the electrical characteristics test such as parameters and the burn-in test are integrated.
16). According to the method of manufacturing a multichip module of the present invention, an integrated circuit chip having a terminal portion is placed on an insulating material lower protective layer on a base with the terminal portion facing upward, and then the integrated circuit is formed on the lower protective layer. An upper protective layer made of an insulating material is formed so as to cover the chip, and internal upper and lower conductor portions that are connected to terminal portions of the integrated circuit chip and exposed on the upper protective layer are formed on the upper protective layer, and then Forming an extension wiring part connected to the inner upper and lower conductors on the upper surface of the upper protection layer, and then forming an upper protection layer covering the extension wiring part on the lower protection layer, and the upper protection layer And forming an external upper and lower conductor portion that is connected to the extended wiring portion and reaches the upper surface side of the upper protective layer, and then a terminal portion located on the upper surface of the upper protective layer on the upper side of the outer upper and lower conductor portion It is characterized by forming .

17). The chip module manufacturing method of the present invention includes a stack of a plurality of chip modules obtained by the manufacturing method according to any one of 11) to 16), and wiring between an upper layer chip module wiring layer and a lower layer chip module wiring. The parts are connected by upper and lower conductor parts.

18). The chip module manufacturing method of the present invention is obtained by obtaining a plurality of chip modules by the manufacturing method described in any one of 11) to 17), and laminating these chip modules, and the wiring portion and lower layer of the upper layer side chip module. The connection with the wiring part of the chip module on the side is made by connecting any connection terminal of any chip module in the final chip module and any connection terminal of any chip module in the chip module or an external terminal of the chip module. Is selected and connected to an arbitrary connection terminal of another chip module in the chip module.
19). According to the chip module manufacturing method of the present invention, a plurality of integrated circuit chips are three-dimensionally arranged in an insulator together with wiring for arbitrarily connecting the plurality of integrated circuit chips, and integrated into the insulator. As a method of making a multichip module, an integrated circuit chip component or various chip modules are embedded in an insulator or covered with an insulator, and a wiring pattern is formed on the insulator before the integrated circuit chip component or chip module is formed. These are combined, integrated, and integrated by curing the insulating material covering them.
20). The chip module manufacturing method of the present invention is such that all elements constituting the chip module according to any one of 11) to 19) are guaranteed in electrical characteristics and reliability. As a method for guaranteeing the electrical function and characteristics, only the wiring function and characteristics in the chip module are tested.

According to the present invention, the effects described below can be obtained.
1). Devices for integrating integrated circuit chips are guaranteed to be very small, ultra-thin, and KGD (Known Good Die). The burn-in test that removes the initial reliability failure can be applied, the quality of the device can be determined, and it is much smaller than the conventional package product and can be made thin without an interposer. The test terminal pitch of the device can be selected from 80 μm to 150 μm, for example, in accordance with the socket technology with the conventional package product of 300 μm, and with the optimal diameter layout. In addition, according to future technological progress, the terminal pitch of 20-30 μm level for current bonding and bump bonding restrictions is further reduced, terminals are arranged outside the chip surface, and the mechanical pressure on the chip at the time of test contact Can also be avoided.
2). Since the element relaxes the stress applied to the front and back surfaces of the integrated circuit chip with an insulator and protects the integrated circuit chip, the integrated circuit chip can be made thinner to less than 100 μm to several μm, and the damage in the integrated manufacturing process is extremely small. . That is, an extremely thin element can be manufactured without damage.
3). In the three-dimensional integrated manufacturing process, the protective layer of the buried element and the buried insulator are stacked and closely integrated together with the wiring connecting the elements for each layer. Therefore, high density and high integration are possible. Even if the integrated circuit chip to be integrated is thin, it is covered and protected by a protective layer, so that chemical resistance and moisture resistance are increased in addition to mechanical strength, and quality deterioration during the manufacturing process can be prevented.

4). Patterning in the three-dimensional integration process is performed by lithography, and the wiring is basically plated, so there is no problem of alignment accuracy in the case of superposition, there is no metal bonding such as bonding or soldering in the wiring, and miniaturization of the wiring is a process of silicon process. It can easily be advanced with the development of technology.
Since the module can be connected to the wiring board by the plated wiring and the insulating layer can be tightly integrated, fine processing can be performed with high accuracy without applying thermal stress to the extremely thin integrated circuit chip component. Moreover, since it is integrated with the wiring board in the module manufacturing process, the mounting process can be omitted, which is advantageous in terms of cost quality.
5). Also, high-density wiring capability can be achieved by miniaturization of wiring, multiple power supply lines are possible, ground lines can be made freely, wiring pattern accuracy can be improved, capacitors, coils, etc. Passive elements can be easily incorporated. In addition, the wiring capacity in the module is the same level as the state in which the constituent elements are arranged in a single layer on the wiring board (flat placement), that is, it can be connected to the elements in the module from inside and outside the module without passing through other elements. , The module's ability will increase further. Since the module has a small shape and can respond to high frequency requirements, it can meet the required SI (signal integrity) of the module at high frequencies, and can improve the performance and functionality of the module.
6). Heat can be dissipated to some extent by forming heat dissipating lines.
7). The area of the insulator covering the integrated circuit chip constituting the three-dimensional integration process and the area of the connection terminal formed on the insulator are both larger than the area of the chip and the connection terminal on the chip, that is, the terminal on the chip Elements with extended wiring are also elements having the same area of the insulator and the area of the connection terminal on the insulator that do not require a test request such as a high-frequency test and multiple pins, that is, the terminals on the chip are of the same area type. Since the extended wiring elements can be incorporated in the same manner, various integrated circuit chips can be integrated, and the degree of freedom and versatility of the module increases.

8). The structure of the multi-chip module also allows the integrated circuit chips to be three-dimensionally aligned in the insulator together with the wiring that surrounds and connects the integrated circuit chips, so that the thinning of the chip, lithography, and flattening technology can be matched. , High density integration with the same shape and no waste of development and mass production. Therefore, standardization of specifications is facilitated, contributing to design, manufacturing, and product application.
9). Since the elements constituting the multichip module are completely guaranteed good quality, there is no problem of yield in the incorporated elements, and high integration can be achieved. Conventionally, the electrical characteristic test for guaranteeing the electrical characteristics of the multichip module has been one of the causes of high cost because it requires enormous man-hours for each increase in the elements including the test of the constituent elements, but according to the present invention, The electrical characteristic guarantee for mass production of multichip modules can be performed mainly after the system evaluation and then the wiring function and quality inspection, so the test burden cost can be greatly reduced.
10). Much higher density multi-chip module than the prior art, for example, stacking 16-32 or more in 1 mm thickness, if integrated three-dimensionally, the integration of the horizontal number of times can use the advanced integrated circuit chip as a component, This means integration of silicon technology more than several generations of nodes, and its development and manufacturing costs are much lower than silicon process development and manufacturing.

11). As application products, large scale integration of general memory chips such as DRAM and FLASH memory has a great use by itself. In addition, memory chips such as MRAM and FRAM, which have high performance but difficult to miniaturize cells, can be efficiently integrated by dividing the cell portion and peripheral circuits into separate chips and integrating them at high density. . Integration of integrated circuit chips is a very effective module because it is technically or economically difficult to make by the same silicon process. It will greatly contribute to the advancement of mobile PCs in the enhancement of functions of portable devices such as mobile phones, the increase of flash memory capacity and the replacement of HDDs. Basically, difficult to manufacture in the same silicon process, such as a mixture of analog ICs and digital ICs, satisfies product requirements that are expensive or difficult to manufacture. If a high performance CPU can separate a large cache memory in a module, the cost of the high performance CPU will be greatly reduced. In addition, because of the possibility of hierarchical large-scale integration, it can be integrated in a small size including integrated circuit chips and other passive components on a considerable portion of the current wiring board, and it can be used not only for portable products but also for devices that require all integrated circuit chips. High performance, high functionality, low cost.
12). An integrated module can be formed on a wiring board to form a multi-chip module or a connection terminal on the outermost part of the multi-chip module to make a highly integrated and highly functional device. Further, since a plurality of multichip modules can be further integrated to achieve higher integration, that is, the multichip modules can be hierarchized, and integrated circuit chips and passive elements having different thicknesses can be integrated into a module. Therefore, the degree of freedom and versatility are further increased.
13). The wiring function in the multi-chip module can be directly connected from any connection terminal of any chip in the module to any connection terminal of any chip without connecting to the connection terminals of other chips. Although it has a laminated structure, it has a flat wiring function and is flexible.

The best mode of the present invention will be described below.
In addition, since embodiment described below is described in detail in order to make the meaning of this invention understand better, unless otherwise specified, this invention is not limited.
FIGS. 1 to 9 are cross-sectional views for explaining a method of manufacturing an integrated circuit chip component of the terminal area forming area expansion type according to the present invention in the order of steps, and FIGS. 4 to 7 are steps for manufacturing a single integrated circuit chip component. The process is shown as an enlarged view. Reference numeral 10 in the drawing is a cross-sectional view of the integrated circuit chip component of the terminal portion formation area expansion type according to the first embodiment of the present invention manufactured through the steps shown in FIGS. Note that in these cross-sectional views or the cross-sectional views shown later, the scales, dimensional ratios, the number of wires, and the like of each part are appropriately adjusted so that the internal wires and the internal structure can be easily seen.
"Configuration of integrated circuit chip parts"
An integrated circuit chip component A of the terminal portion forming area expansion type integrated circuit chip component A according to the first embodiment of the present invention shown in FIG. 7 is formed by laminating a protective layer 2 made of an insulating material on a substrate 1. An integrated circuit chip module (Integrated Circuit Chip Module) 3 is embedded substantially in parallel with the substrate 1 on the inner upper side of the protective layer 2, and the integrated circuit chip 3 is expanded on the upper side of the integrated circuit chip 3 in the vertical or horizontal width. The extended wiring portion 5 is formed so as to be electrically connected to the terminal portion 3a of the integrated circuit chip 3, and is connected to the terminal portion 3a of the integrated circuit chip 3 via the extended wiring portion 5 on the upper surface of the protective layer 2. A surface expansion terminal portion (relocation terminal portion) 6 to be electrically connected is formed.

  The integrated circuit chip 3 shown in FIG. 7 includes an integrated circuit using various semiconductor elements inside, and each input / output terminal of the integrated circuit is connected to the terminal portion 3a by a bonding member such as wire bonding or bump. Is a bare chip such as an LSI or an IC having a structure in which is sealed with an insulating sealing resin. As an example of such an integrated circuit chip 3, a variety of devices can be employed, from those having a high-function integrated circuit called a CPU (central processing unit) to storage elements called a memory. Various CPUs can be used, ranging from a large-scale CPU having more terminals than the above to a memory having about 100 terminals or less in the memory. Accordingly, FIG. 7 shows an example in which six terminal portions 3a are described on the upper surface (terminal portion forming surface) side of the integrated circuit chip 3 for the sake of simplification. In the case of a small number, the number of terminals is several tens, and in the case of a large number, those having 1000 or more terminal portions 3a are applied. Of course, in the present invention, one having a number of terminals outside this range may be applied.

The substrate 1 may be either insulating or conductive, but has a strength and flatness that can be handled, and a protective layer 2 formed thereon is applied. Alternatively, it is necessary to attach, have a certain degree of adhesion and can be peeled off.
The protective layer 2 is made of an insulating material such as a photo-sensitive thermosetting resin such as PI (polyimide) resin, phenol resin, BCB, OXAZOLE, or a general photo-non-photosensitive organic type, curable resin such as heat or light, and SOG. (Spin-on-glass) and other inorganic materials, and organic and inorganic mixed materials or TEOS and other insulating materials for CVD in the CVD process or by mixing with curing of coating materials The thickness of the integrated circuit chip 3 can be embedded therein. Accordingly, the thickness of the protective layer 2 can be appropriately changed according to the thickness of the integrated circuit chip 3. The resin constituting the protective layer 2 is not limited to the above-described photothermographic resin, photofire photosensitive thermosetting resin, etc., but the thermosetting resin has a large thermal shrinkage and is about 100 μm or thinner. When the integrated circuit chip 3 is applied, thermal stress acts on the integrated circuit chip 3 due to thermal shrinkage of the thermosetting resin, which may cause chip cracking or chipping. When used, it is preferable to use a resin having a small shrinkage rate. In this respect, in the integrated circuit chip component A, the upper and lower surfaces of the chip are covered with protective layers to balance the stress applied to the chip, which is a measure for reducing the thickness of the chip.

  The protective layer 2 includes a lower protective layer 7 and an upper protective layer 8. The lower protective layer 7 covers the entire integrated circuit chip 3, and is provided on the upper surface and the terminal portion 3 provided on the upper surface side of the integrated circuit chip 3. Is formed so as to have a covering portion 7a covering with a thickness of about several μm. A via hole penetrating through the covering layer 7a in the thickness direction is formed in the covering portion 7a located on the integrated circuit chip 3, and the via hole is connected to the terminal portion 3a of the integrated circuit chip 3 in the via hole. A lower via wiring (inner upper and lower conductor portions) 7b made of a conductive material reaching the upper surface side of each of the first and second lower conductor wirings 7b is formed on the upper surface side of the covering portion 7a. An extended wiring portion 5 is formed in which a plurality of wiring portions 7c that are individually connected to each other are formed. These wiring portions 7c are formed wider than the vertical width or the horizontal width of the planar shape of the region where the terminal portion 3a of the integrated circuit chip 3 is formed. In the example of FIG. 7, an example in which the width of the integrated circuit chip 3 is expanded to about twice the width is shown. However, the expanded size is a socket or prober for test and burn-in test that can perform all electrical characteristics and electrical tests including high frequency tests. For example, the current terminal test and burn-in test socket terminal pitch is 80-90 μm, which is much smaller than the narrowest pitch 300 μm of the current package product, but on the chip. The narrowest pitch is larger than 20 μm.

  The upper protective layer 8 is formed to cover the lower protective layer 7 and the extended wiring portion 5 formed thereon, and has a thickness of about several μm. The upper protective layer 8 located on the extended wiring portion 5 is connected to the wiring portion 7c of the extended wiring portion 5 through the upper protective layer 8 in the thickness direction and reaches the upper surface side of the upper protective layer 8. In the via hole, a plurality of upper via wires (outer side upper and lower conductor portions) 9 made of a conductive material are formed in accordance with each wiring portion 7c, and the upper protective layer 8 has a plurality of upper portions on the upper surface side. A plurality of terminal portions (surface expansion terminal portions) 10 individually connected to the via wiring 9 are formed.

In the integrated circuit chip component A of the terminal part formation area expansion type having the above-described configuration, the integrated circuit chip 3 accommodated therein is thin and small, and the terminal part 3a is a general inspection device. The prober probe of a general-purpose inspection apparatus capable of inspecting a high frequency range of several hundred MHz or more, for example, in a fine region or a fine pitch that cannot be arranged for low cost and mass productivity. Even if the structure is arranged in a fine region or a fine pitch that cannot be arranged or burn-in test, it is formed in a wide region by expanding the area, and the terminal portion 10 that itself has a large area is also formed. It can be used for sufficient electrical characteristics and burn-in inspection. Further, the terminal area of the integrated circuit chip 3 can be made smaller than the terminal area of the integrated circuit chip 3 in accordance with the progress of the socket technology in the future. You can also do it.
The layout of the terminal portions 3a of the integrated circuit chip 3 and the layout of the component terminal portions 10 are not necessarily the same. The layout of the component terminal portion 10 is determined so as to be optimal for the electrical characteristic test and the wiring of the integrated circuit chip component A to be integrated.
As for the size of the integrated circuit chip component A, the integration density of the stack increases as the thickness decreases. For example, if the total thickness is 30 μm or less, the thickness of the via wiring portion in the module integration process can be about 15 μm or less, and the hole for forming the via wiring portion can be easily formed by a laser even if etching cannot be performed. If the thickness is further reduced, all patterning including via wiring portions can be performed by development (in the case of a photosensitive resin) or etching. The shape of the integrated circuit chip component A is slightly inclined and tapered on the side surface so that the side surface is completely covered with resin as shown in FIG.

In the integrated circuit chip part A with the terminal part formation area expansion type configured as described above, since the inspection process is the final process, there is no damage and yield loss after the inspection process, and the integrated circuit chip 3 is further protected by an insulating material. Since it is covered with the layer 2, the semiconductor circuit and components provided in the integrated circuit chip 3 have a double-sealed structure, which is excellent in reliability and has an expanded product test area. Since the unit 10 can easily inspect even the high frequency characteristics with a general-purpose inspection apparatus, it is possible to provide a non-defective integrated circuit chip component A including the integrated circuit chip 3 that can be completely determined as non-defective. Further, by using only the integrated circuit chip component A that can be determined as a non-defective product for the integration described later, it is possible to obtain a later-described multichip module that has a very low probability of occurrence of defects.
Further, these modules can be further integrated, and the configuration will be described later.

"Manufacturing method of integrated circuit chip parts"
Next, a manufacturing method of the integrated circuit chip component A of the terminal part formation area expansion type having the configuration shown in FIG. 7 will be described with reference to FIGS.
In order to manufacture the integrated circuit chip component A, a resin film as an insulator or a coating type resin insulating layer 12 is formed on a substrate 1 as shown in FIG. Install the required number with the terminal part facing up. The integrated circuit chip 3 used here is one that has been inspected in advance, such as a general energization test through a probe test by a normal inspection device, and has been determined to be non-defective. However, the test in the high frequency range of several hundred MHz or higher is not possible because the prober of the inspection device cannot handle high frequency, or the inspection device compatible with high frequency is too expensive to be used normally. The integrated circuit chip 3 may be in a state where a difficult burn-in test is not performed on the wafer. The integrated circuit chip 3 is usually thinned with a back grinder or an etching solution. However, when the thickness is 100 μm or less, the warp or the like becomes large, and thus a film or a resin may be attached to the back surface.
In FIG. 1 to FIG. 3, the terminal portion of the integrated circuit chip 3 is omitted for simplification of description, and a case where three integrated circuit chips 3 are manufactured on the substrate 1 will be described. The required number of integrated circuit chips 3 to be manufactured can be installed according to the size of the area of the substrate 1.
Next, a resin such as a phenol-based photosensitive resin is applied to cover the resin insulating layer 12 and the integrated circuit chip 3 to form a coating insulating layer 13 as shown in FIG.
The covering insulating layer 13 formed here can be formed to a thickness that covers the upper surface (terminal portion forming surface) of the integrated circuit chip 3 by about several μm. For example, if a phenol-based photosensitive resin is used, it can be exposed to H, G, and I lines. If this type of resin is used, high temperature resistance of 300 ° C., dielectric constant of 3.7, cure temperature of 190 ° C., curing shrinkage of 10%, aspect ratio of 1.0 to 2.0, excellent chemical resistance, Since the range can be easily adjusted in the range of 3 to 25 μm, it can be suitably used for the purpose of the present invention.
The covering insulating layer 13 is pre-baked and heat-treated to be hardened, thereby joining and integrating with the lower resin insulating layer 12 to form a protective layer 7 that covers the integrated circuit chip 3, and processing the protective layer 7 Thus, the extended wiring portion 5 is formed. Further, the thickness of the covering portion 7a is set to such a thickness that a via wiring for vertical conduction described later can be formed.

As shown in FIG. 3, the extended wiring portion 5 is formed on the upper side of each integrated circuit chip 3 from the previous state. The method for forming the extended wiring portion 5 is based on the partial enlarged views shown in FIGS. This will be described below.
In order to form the extended wiring portion 5, the terminal portion 3 a of the integrated circuit chip 3 is formed in the protective layer 7 around the integrated circuit chip 3 as shown in FIG. Since the cover portion 7a is formed on the upper side of the cover portion 7a, a mask (not shown) is provided on the cover portion 7a, and a photolithography process for performing exposure and etching is performed. As shown in FIG. A via hole 15 communicating with 3a is formed, and a conductive material layer is formed in the via hole 15 by a film formation method such as seed layer sputtering and plating or vapor deposition, or by plating to form a lower via wiring (inner upper and lower conductor portion) 7b. Form. For example, as one example, when forming the lower via wiring 7b, after forming or plating the via hole 15 and its periphery, a resist material is formed on these films and plating layers, and the resist material is partially coated. The lower via wiring 7b made of a conductive material can be formed only on the inner side of the via hole 15 by etching and removing the resist material except for the portion filled with the conductive material in the via hole 15 by etching.
A typical photolithography process in the case of using the phenol-based resin will be described. After applying the resin layer constituting the protective layer 7, pre-baking 110 ° C./3 minutes, light irradiation 300 mJ / cm ² , post-exposure baking 110 It can be realized in a low temperature process with a mixture of environmental measures by a series of steps of ℃ / 3 minutes, development 2.38% / 60 minutes, rinsing 30 seconds, post-baking 190 ° C / 60 minutes. In the photolithography process described below, the time changes depending on the thickness of the bare chip used, and basically, the same process can be used.

After forming the lower via wiring 7b, the extended wiring section 5 can be formed by forming the wiring section 7c connected to the lower via wiring 7b on the upper surface of the lower protective layer 7. In order to form the wiring portion 7c, a mask material may be formed on the upper surface of the lower protective layer 7, and then a photolithography process for performing exposure, development, and selective etching may be performed, or a wiring layer may be formed by forming a plating layer. Alternatively, a general method used for forming a wiring circuit on a substrate, such as forming a wiring circuit by pressing a thin body made of a conductive material, may be adopted.
Wiring is basically performed by plating, and a seed layer such as Ti or Cr is sputtered into the base, and the wiring pattern is made of a plating-resistant resist. After plating, the resist is peeled off and the seed layer is etched. Wiring can be done by filling with insulating material.
When the wiring part 7c is formed, the upper protective layer is coated on the lower protective layer 7 using a method such as resin coating, coating, or resin film so as to cover the upper surface of the lower protective layer 7 and the wiring part 7c. 8 is formed, and the lower protective layer 7 and the upper protective layer 8 are joined by pre-baking or heat treatment.
Thereafter, the upper via wiring 9 is formed using the same method as that for forming the previous lower via wiring 7b, and the terminal portion (surface expansion terminal portion) 10 is further formed on the upper surface of the upper protective layer 8, The terminal part formation area expansion type integrated circuit chip component A having the configuration shown in FIG. 7 can be obtained.
Although the above shows details, in actual manufacturing, the lower via wiring 7b, the wiring portion 7c, the upper via wiring 9 and the terminal are used in the resist patterning and development, the base plating etching, and the insulating layer coating process in order to improve productivity. It is possible to make the part 10 in the same process. Further, the horizontal wiring can be not only a single layer but also a multilayer wiring. As for the process, a process similar to the rewiring process currently mass-produced on the wafer level is performed on the substrate.

  When manufacturing the integrated circuit chip component A with the terminal portion forming area expansion type by the method described above, the resin insulating layer 12 is formed on the substrate 1, the integrated circuit chip 3 is installed thereon, and the covering insulating layer 13 is formed. A via hole 15 is formed using a photolithography process, a lower via wiring 7b made of a conductive material for vertical conduction is formed therein, an extended wiring portion 5 is formed, and an upper protective layer 8 is further formed. However, it can be easily realized by combining the method generally formed in the semiconductor circuit manufacturing, in which the upper via wiring 9 and the terminal portion 10 are formed there. Therefore, the process of manufacturing the integrated circuit chip component A is not complicated as compared with general circuit formation.

When the integrated circuit chip component A having the configuration shown in FIG. 7 is manufactured, all the electrical characteristics, that is, the electrical characteristics test such as the function, the high frequency, the AC, the parameters, etc., and the burn-in test are performed when initial reliability defects are excluded.
FIG. 8 simply shows a continuous state on the board as an illustration. However, if there is no prober capable of the above test, an integrated circuit chip component can be separately separated using a test socket and a burn-in socket. A complete test is performed by matching the terminal portion 10 of A with the terminal of the socket, and a non-defective product is determined. Here, the formation pitch and formation region of the terminal portions 10 are formed larger than the formation pitch and formation region of the terminal portions 3a of the integrated circuit chip 3 accommodated therein (expanded wiring (fan-out). Therefore, all test items including high frequency can be tested.
That is, if it is the integrated circuit chip component A of this invention, it can be discriminate | determined whether it is a complete good product which exhibits all the functions including reliability and a high frequency characteristic, or it is a defective product.

8 is performed on all the integrated circuit chip components A on the substrate 1 shown in FIG. 8, and as a result of determining whether it is a non-defective product or a defective product, only the components that are all determined to be non-defective are integrated. For the production of multi-chip modules of layers, it is arranged on an insulator protective layer on a substrate.
In the case of the integrated circuit chip component A with the terminal portion formation area expansion type having the configuration shown in FIG. 10, the integrated circuit chip 3 is extremely thin, for example, about 10 μm or less in thickness, and there is a risk of cracking or chipping. Even if it is impossible to handle, the protective layer 2 of the insulating material covers the periphery thereof, so that it can be handled and has a feature that there is little risk of cracking or chipping. Further, since the inspection process is the final process, there is no damage and yield loss after the inspection process.
Next, when the test terminals on the protective layer of the integrated circuit chip to be integrated are extended in the same area, that is, connected through the rewiring in the protective layer connected from the test terminal of the integrated circuit chip. In the case where the test terminal is on the surface area of the protective layer equivalent to the surface area of the integrated circuit chip, probing on the wafer and a mature wafer-level burn-in product do not cause an initial reliability failure without a burn-in test. Further, when KDG is guaranteed by adding a post-inspection process (cutting or the like), the terminal portion formation area same type integrated circuit chip component B shown in FIG. 10B is shown as a component of the module.
In this example, the integrated circuit chip component B of the terminal area forming type expansion type wafer probe level may be omitted after the rewiring of the integrated circuit chip terminal and the terminal are arranged on the insulator protection layer on the wafer level. Manufactured by burn-in and cutting processes. However, it is not necessary to form the terminal connection portions such as bumps and solder found in the wafer level package in the protective layer shape, and a plated wiring connection terminal may be used. If the thickness of the chip is 50 μm or less, an insulating lower protective layer 7 is also required on the lower surface of the chip for the same reason as that of the integrated circuit chip component having an extended terminal area. In some cases, the lower protective layer is covered on the side surface for quality improvement. Therefore, even if the integrated circuit chip 3 ′ is not exposed on the side surface side of the integrated circuit chip component B as shown in FIG. A covering structure may be used.

"Multi-chip module laminated with single-layer single-chip module and multi-chip module"
Next, a single-layer single-chip module and a multi-chip module are constructed using the integrated circuit chip component A shown in FIG. 10 separated from the substrate 1, and further laminated to make a three-dimensional structure, thereby producing a laminated multi-chip module. How to do will be described. In the following description, an integrated circuit chip component A having a terminal portion formation area expansion type is mainly described as a constituent element, but may be an integrated circuit chip component B having the same terminal portion formation area type, or a mixture thereof.
Using the integrated circuit chip component A that has been determined to be non-defective manufactured by the previous process, the required number of integrated circuit chip components A are spaced on a separately prepared substrate 1 through a resin layer such as a coated resin layer or a resin film. Open one layer. In this embodiment, as shown in FIG. 11, integrated circuit chip components A1, A2, and A3 are arranged on the substrate 1, and each of the integrated circuit chip components A1, A2, and A3 that need to be connected to each other. An example will be described in which a single layer multichip module C is formed after connecting the parts by horizontal wiring 22 as necessary, and then a laminated multichip module.
A resin is applied so as to surround these integrated circuit chip components A1, A2 and A3, and on top of these so as to cover about several tens of μm, and this resin layer is cured to integrate the integrated circuit chip components A1, A2, In the manufacturing process of the previous integrated circuit chip component A, the protective layer 20 covering A3 is configured, and the covering layer 21 covering the upper side of the integrated circuit chip components A1, A2, A3 of the protective layer 20 is formed. A photolithography process equivalent to the performed photolithography process is performed to form a horizontal wiring portion 22 for connecting the integrated circuit chip components A1, A2, and A3 and a wiring for pulling out the terminals 10 of A1, A2, and A3 in the vertical direction, and covering Terminal portions 23 are individually formed so as to be exposed on the upper surface of the layer 21.
Although the above shows details, in actual manufacturing, the horizontal wiring portion 22 and the vertical wiring and the terminal portion 23 are simultaneously formed in resist patterning and development, base plating etching, and insulating layer coating processes in order to improve productivity. It is possible to make this process. Moreover, not only a single layer but also a multilayer wiring can be used. As for the process, a process similar to the rewiring process mass-produced on the current wafer level is performed on the substrate 1. The integrated integration of the integrated circuit chip components A1, A2, and A3 into the module is basically performed by thermosetting by hard baking of the resin before forming each wiring (plating) pattern. A configuration in which a plurality of integrated circuit chip components A1, A2, and A3 are arranged in a single layer as described above can be referred to as a one-layer multichip module C. If only one layer of the integrated circuit chip component A1 is arranged in a single layer, it can be referred to as a single layer single chip module.

Next, in order to laminate the second-layer integrated circuit chip component, an intermediate layer 25 such as a coating resin layer or a resin film is laminated with the lower multi-chip module so as to cover the upper surface of the coating layer 21 and the terminal portion 23. In order to integrate the integrated circuit chip components to be formed, they are formed and pre-baked as shown in FIG. In addition, the non-defective inspected integrated circuit chip components A4, A5, and A6 manufactured in the same manner as in the previous manufacturing method are placed on the first-layer integrated circuit chip components A1, A2, and A3 as shown in FIG. So as to overlap with each other in plan view.
Next, a protective layer 26 is first formed on the upper surface side around the integrated circuit chip components A1, A2, and A3 as shown in FIG. 13, and then a via hole that vertically penetrates the protective layer 26 and the coating layer 27 is formed. Are formed by a photolithography process or laser irradiation, and at the same time, the lower multichip module, the protective layer 26 and the covering layer 27 are integrated, and the integrated circuit chip components A4, A5 and A6 are also integrated. Next, the upper and lower conductor portions 28 made of a conductive material are formed, and the coating layer 27 on the integrated circuit chip components A1, A2, and A3 is subjected to a photolithography process or laser irradiation performed in the same manner as the previous process. Then, a via hole is formed, and the upper and lower conductor portions 30 made of a conductive material are formed there.
By these upper and lower conductor portions 28 and 30, the first-layer integrated circuit chip components A1, A2, and A3 and the second-layer integrated circuit chip components A4, A5, and A6 can be led out on the uppermost coating layer 27. . Further, the horizontal rewiring for selectively connecting the terminals formed on the coating layer 27 and the upper and lower conductor portions 30 from the integrated circuit chips A4, A5, A6, and further the terminal for the next lamination or external connection on the protective layer. (Like the horizontal wiring portions 22 and 23 in the first layer). Here too, the second-layer integrated circuit chip components A4, A5, and A6 are closely integrated into the module by thermosetting by hard baking of the resin before forming the wiring (plating) pattern of each protective layer.
Through the above steps, as shown in FIG. 13, the multilayer module D having the two-layer structure having the integrated circuit chip parts A1 to A3 in the first layer and the integrated circuit chip parts A4 to A6 in the second layer, the two-layer multi-layer A chip module (2 Layer Single Chip Module) can be obtained. The multilayer module D can be referred to as a single chip 2 layer module when the integrated circuit chip components used for each layer are only single chips A1 and A4.

11 to 13, the integrated circuit chip components A1 to A6 are abbreviated in a chip shape. The structures of these integrated circuit chip components A1 to A6 are described in more detail in FIGS. .
FIG. 14 shows a state at the same stage as FIG. 12, and FIG. 15 shows a state in which a protective layer 26 and a covering layer 27 are formed on and around the second-layer integrated circuit chip components A4 and A5. FIG. 16 shows a state in which the upper and lower conductor portions 28 and 30 are formed on the protective layer 26 and the covering layer 27. Further, wiring for selectively connecting the upper and lower conductor portions 28 formed on the covering layer 26 and the upper and lower conductor portions 30 of A4, A5, and A6, and further terminals for the next lamination or external connection are formed on the protective layer. (It is formed like the horizontal wiring portion 22 of the first layer).
Although the above shows details, in actual manufacturing, the horizontal wiring portions 22 and 23 may be formed by a simultaneous process in resist patterning and development, base plating etching, and insulating layer coating processes in order to improve productivity. obtain. Moreover, not only a single layer but also a multilayer wiring can be used. As for the process, a process similar to the rewiring process currently mass-produced on the wafer level is performed on the substrate.

When the multi-chip module D having the two-layer structure shown in FIGS. 14 and 16 is further laminated to form a multilayer, the integrated circuit chip components may be repeatedly laminated up to the target number of layers as shown in FIG. Thereby, the protective layers 20, 26... 26n provided with the integrated circuit chip components A1, A2, A3... An-2, An-1, and An (n is a natural number corresponding to the number of integrated circuit chip components used) were provided. A multilayer module E having a multilayer structure can be obtained.
In the multilayer module E having this structure, each terminal portion of the first-layer integrated circuit chip components A1, A2, and A3 is connected to the upper and lower conductor portions 28 via the horizontal wiring portion 22, and penetrates the protective layer 26 vertically. Is connected to the upper and lower conductor portions 28 on the upper layer side, and reaches the upper and lower conductor portions 28 of the uppermost layer 26n sequentially through the upper and lower conductor portions 28, and the wiring extends to the upper surface side of the multilayer module E. Has been.

FIG. 18 shows a state in which an intermediate layer 36 for terminal connection is formed on the upper surface of the multilayer module E having the multilayer structure shown in FIG. 17, and this intermediate layer 36 is formed into a necessary circuit shape and terminal shape by a photolithography process. By processing, external connection terminals and connection circuits as the multilayer module E can be formed on the upper surface side of the multilayer module E.
FIG. 19A shows a product structure of a multi-chip module F constituted by an integrated circuit chip component A with an extended terminal area forming type, and FIG. 19B shows an integrated circuit chip component A with an expanded terminal area forming type. A product structure of a multi-chip module F2 composed of a mixture of integrated circuit chip components B of the same type and terminal portion formation area or any of the integrated circuit chip components.
19A, 19B, and 20 show the integration of the integrated circuit chip 3 as shown in FIG. 20 when the integrated circuit chip components A1 to An and B1 to Bn shown in FIG. It shows that. A structure of a multilayer module G in which the integrated circuit chip 3 is built and laminated as shown in FIG. 20 may be adopted.

FIGS. 21 to 26 show a form in which a wiring board 40 in which a wiring circuit is formed in advance is used in the present invention instead of the board 1 used in the above embodiments.
A wiring board 40 in which a wiring circuit 39 is previously formed on the upper surface side is used, an intermediate layer 25 equivalent to that used in the previous embodiment is formed on the wiring board 40, and the previous configuration is formed on the intermediate layer 25. The integrated circuit chip parts A1 to An are installed, and the protective layer 20 and the covering layer 27 are formed so as to cover these integrated circuit chip parts A1 to An as in the previous embodiment. The covering layer 27 covering the upper side of the circuit chip components A is subjected to a photolithography process equivalent to the photolithography process performed in the manufacturing process of the integrated circuit chip component A and arranged in the horizontal direction. A horizontal wiring portion 22 for connecting the integrated circuit chip components A1 to An is formed, and a terminal portion is formed so as to be exposed on the upper surface of the covering layer 21.
Through these steps, a multichip module H having a plurality of integrated circuit chip components A can be obtained.
In this embodiment, an integrated circuit chip component A having an extended terminal portion formation area may be appropriately selected and mixed with an integrated circuit chip component B having the same terminal portion formation area.
For example, in FIG. 19B or FIG. 25, the first layer is the integrated circuit chip component B having the same terminal portion formation area type and the second layer is the integrated circuit chip component A having the terminal portion formation area expansion type. Only the module may be appropriately replaced with the same type of terminal part formation area or the terminal part formation area expansion type. Alternatively, one of the first layers may be the terminal part forming area expansion type integrated circuit chip part A1, and one of the second layer may be the expansion wiring type integrated circuit chip part A2. In this case, an integrated circuit chip component having the same area as that of the extended wiring type is mixed in the multilayer module. In the case of the chip multilayer type, for example, it can be referred to as a multi-chip multilayer module (Multi Chip Multi-layer Module). For example, in the case of a single-chip multi-chip mixed stack, for example, a single-chip multi-chip mixed multi-layer module (Single and Multi Chip Mixed) Multi layer module).

  21, 22, and 23, the integrated circuit chip component A formed by replacing the substrate 1 with the wiring substrate 40 in the structure of the integrated circuit chip component A described above with reference to FIG. 3 or FIG. 7. Is a multi-chip module J with built-in. That is, first, as shown in FIG. 21, an intermediate layer 25 for tightly integrating the wiring board and the integrated circuit chip component is applied or stretched on the wiring board, and the integrated circuit chip component A is arranged thereon, and FIG. In the same manner as shown in FIGS. 15 and 16, the resin is covered, cured, integrated, and wired. However, in this case, the vertical wiring is started from the terminal on the wiring board.

Based on the multilayer circuit multichip module H shown in FIG. 23, the process of sequentially installing the integrated circuit chip components A and forming the protective layer thereon is repeatedly performed, so that the multilayer structure shown in FIG. A multilayer module K can be used.
Further, in this embodiment, the integrated circuit chip component A having the terminal portion forming area expansion type is appropriately selected and mixed with the integrated circuit chip component B having the same terminal portion forming area type or only the integrated circuit chip component B having the same terminal portion forming area type. It is also possible to use the configuration.

  For example, in FIG. 25, the first layer is the integrated circuit chip component B of the same type as the terminal portion formation area and the second layer is the integrated circuit chip component A of the terminal portion formation area expansion type, or only the module at the required position is the terminal portion. It may be appropriately replaced with the same formation area type or the terminal part formation area expansion type. Alternatively, one of the first layers may be the terminal part forming area expansion type integrated circuit chip part A1, and one of the second layer may be the expansion wiring type integrated circuit chip part A2. In this case, an integrated circuit chip component having the same area as that of the extended wiring type is mixed in the multilayer module. In the case of the chip multilayer type, for example, it can be referred to as a multi-chip multi-layer module (Multi Chip Multi-layer Module). For example, in the case of a single-chip multi-chip mixed stack, for example, a single-chip multi-chip mixed multi-layer module (Single and Multi Chip Mixed) Multi layer module).

  FIG. 26 shows that the integration of the integrated circuit chip component is the integration of the integrated circuit chip 3, that is, the integrated circuit chip component 3 is covered with a double insulator protective layer and an external insulator. It is shown that it is integrated and embedded in.

FIG. 27 shows a multi-chip module having a multilayer structure shown in FIG. 20 or FIG. 26, in which a plurality of integrated circuit chip components are installed in the horizontal direction, and a plurality of extended wiring type or same area integrated circuit chip components in the thickness direction. 1 shows an example of a structure in which layers are arbitrarily stacked, and an example of one line of circuit wiring in the stacking direction.
As the wiring pattern for connecting the extended circuit type integrated circuit chip parts A1 to An or the same area type integrated circuit chip parts B1 to Bn of the previous example, every other integrated circuit chip part arranged vertically is arranged. Alternatively, a plurality of wirings may be provided, or the layers may be connected sequentially.
For example, a wiring YIb1 that connects the first-layer integrated circuit chip component A1 to the second-layer integrated circuit chip component A2, and a wiring that connects the first-layer integrated circuit chip component A1 to the third-layer integrated circuit chip component A2. YIb2, the first-layer integrated circuit chip component A1 can be wired as a wiring YIbn that connects to the n-th layer integrated circuit chip component An. Further, external connection wirings Y⊥b1 to Y⊥bn can be provided as vertical wirings for individually connecting these integrated circuit chip components A1 to An.
In addition to these wirings, wirings YIa such as commonly used address wirings and common power supply wirings can be provided for mutual connection to the integrated circuit chip components A1 to An.

FIG. 28 shows another example of the horizontal wiring structure in the multi-chip module having the multilayer structure shown in FIG.
In FIG. 28, in addition to the wiring pattern for connecting the integrated circuit chip components A1 to An or the integrated circuit chip components B1 to Bn having the same area, other components such as the control chips CT1 to CTn and the processor chips PT1 to PTn. This is an example in which buffer chips BT1 to BTn are stacked.
In the structure shown in FIG. 28, the integrated circuit chip components A1 to An and the control chip CT, the processor chips PT1 to PTn, and the buffer chip BT that are installed in the horizontal direction in each layer are all wired in common and common power Wirings Xa1 to Xan such as wirings are provided, and further, selection wirings Xb1 to Xbn are provided to connect only the necessary components to the integrated circuit chip components A1 to An, the control chip CT, and the buffer chip BT. it can.
As described above, as shown in FIG. 27 and FIG. 28, in the multi-chip module having a multilayer structure according to the present invention, common wiring, individual wiring, or external wiring can be used in either the horizontal direction or the vertical direction. Can be used in any combination.
Of course, these various wirings are not applied only to the laminated structure of this configuration, and any of these wirings (wirings Xa1 to Xan, selection wirings Xb1 to Xbn) is shown in the multichip module C shown in FIG. The present invention may be applied to the multichip module D shown, the multichip module E shown in FIGS. 17 and 18, and the multichip modules F, F2, and G shown in FIGS.
The electrical signals of this type of semiconductor multilayer substrate are power signals, ground signals, clock signals, address signals, chip select signals, various control signals, data signals, command signals, etc., so that these signals are transmitted. The structure of the present invention can be applied to various substrates such as an actual memory substrate, a video board substrate, and a motherboard substrate by selecting the necessary wirings from the above and providing the necessary number.

  As described above, according to the present invention, for example, 32 or more integrated circuit chips 3 corresponding to the integration of the fifth generation of silicon technology are integrated into a multilayer module structure having a thickness of 1 mm without requiring a special silicon process. The cost of manufacturing is much less than the cost of developing and manufacturing silicon technology. In addition to existing mass-produced memories, high-density multi-layer integration of memory with good performance but difficult cell structure miniaturization, high integration of system devices that are difficult to achieve high integration on a single wafer due to different silicon processes It has a feature that enables it at low cost. In addition, passive components that are different from the integrated circuit chip 3 can be incorporated in the protective layers 2 and 20 having the above-described structure, and the application range can be expanded.

The integrated structure of the present invention has a structure in which minute integrated circuit chip parts not existing in the prior art are arranged in a three-dimensional manner, and will be basically the same in future generations regardless of the integration density and chip thickness. The manufacturing method is basically the same and uses the multi-layer plating wiring, planarization, and lithography techniques already used in the silicon process, so that there is little cost burden and risk for development and manufacturing and application.
Further, the integrated circuit chip components A and B, which are the basic elements to be constructed, are selected according to the product standard test and sealed as compared with the bare chip, so that the maximum integration problem of yield is minimized. In other words, the final electrical characteristic assurance test at the time of mass production of the module is basically only the function and characteristic test of the wiring (connection state, electrical resistance, impedance, inductance, capacitance, noise, etc.) after the evaluation of the system and process of the multichip module. The burden is greatly reduced, and it can be directly connected to low cost, high quality and high reliability. The integration process also eliminates the stress imbalance with respect to the chip surface and is sealed to improve reliability after shipment.
Further, according to the present invention, since the wiring is basically plated and the pattern is also formed by lithography and does not have metal bonding, wiring having much finer, high density, wiring quality, and diversity can be obtained than in the prior art. Wiring substrates, three-dimensionally arranged elements, and wiring boards can be arbitrarily connected, and the wiring diameter can be several μm or less. Since multiple power supplies, grounds, and signal lines can be arranged arbitrarily, pattern accuracy and signal quality (SI) are also improved, and different types of chips such as high-frequency chips, digital, analog, logic, and memory can be easily integrated. The final product can be manufactured. Furthermore, it is possible to manufacture functional parts such as antennas and coils and to dissipate heat by thick plating. That is, the present invention satisfies all the requirements for high density and high performance chip modules.
In summary, according to the present invention, it is possible to provide a multilayer module having a capability far surpassing that of the prior art, which greatly contributes to the industry and consumers.

Sectional drawing which shows the state which has arrange | positioned the integrated circuit chip on the insulating lower protective layer on a board | substrate. Sectional drawing which shows the state which formed the upper protective layer in the circumference | surroundings of the integrated circuit chip on a board | substrate. Sectional drawing of the integrated circuit chip component before the test which mounted the integrated circuit chip on the board | substrate. Sectional drawing which shows the state which embed | buried one integrated circuit chip inside the protective layer on a board | substrate. Sectional drawing which shows the state which formed the upper and lower conductor part in the coating layer on an integrated circuit chip. Sectional drawing which shows the state which formed the extended wiring part on the coating layer. Sectional drawing which shows the state which formed the upper and lower conductor part and the terminal part on the extended wiring part. Sectional drawing which shows the state which test | inspects an integrated circuit chip with a prober (or socket) through a terminal part. Sectional drawing which shows the position which cuts off the integrated circuit chip provided in the protective layer on a board | substrate. FIG. 10A is a cross-sectional view of an integrated circuit chip component of an extended terminal area forming integrated circuit chip provided with an integrated circuit chip inside the protective layer, and FIG. 10B is a formed terminal portion including an integrated circuit chip inside the protective layer. Sectional drawing of integrated circuit chip components of the same area type. Sectional drawing which shows the state which provided the integrated circuit chip component inside the protective layer on a board | substrate. Sectional drawing which shows the state which laminated | stacked two layers of integrated circuit chip components on the board | substrate. Sectional drawing which shows the state which enclosed and wired the integrated circuit chip component of the 2nd step | paragraph on the board | substrate with the protective layer. Sectional drawing which shows the state which laminated | stacked two layers of integrated circuit chip components on the board | substrate. Sectional drawing which shows the state which enclosed and wired the integrated circuit chip component of the 2nd step | paragraph on the board | substrate with the protective layer. Sectional drawing which shows the state wired around the 2nd step | paragraph of integrated circuit chip components. Sectional drawing of an example of a multilayer multichip module. Sectional drawing by which the external connection layer and the terminal were arrange | positioned on a multilayer multichip module. FIG. 19A is a cross-sectional view showing a state separated from the base of the multi-layer multichip module, and FIG. 19B is an integrated circuit chip component A1-An having a terminal part forming area expansion type, the same type of terminal part forming surface. Sectional drawing which shows the mixed state of integrated circuit chip components and B1-Bn. Sectional drawing of a multilayer multichip module. Sectional drawing which shows the state which formed the insulating layer on the wiring board. Sectional drawing which shows the state which has arrange | positioned the terminal part formation area expansion type integrated circuit chip component on the insulating layer. Sectional drawing which shows an example of the state which formed the horizontal wiring on the integrated circuit chip component of a terminal part formation area expansion type. FIG. 3 is a cross-sectional view showing an integrated circuit chip with an extended terminal area forming type on a wiring board as a one-layer multichip module. FIG. 25 is a cross-sectional view showing a mixed state of the integrated circuit chip parts A1 to An of the terminal part forming area expansion type, the integrated circuit chip parts of the same type of the terminal part forming surface, and B1 to Bn on the wiring board. Sectional drawing by which an integrated circuit chip is shown as a multilayer multichip module on the wiring board. Sectional drawing of a multichip module provided with the wiring part which selectively connects the integrated circuit chip components laminated | stacked on the upper and lower multilayer. Sectional drawing of a multichip module provided with the wiring part which selectively connects the integrated circuit chip components arrange | positioned in the horizontal direction among the integrated circuit chip components laminated | stacked on upper and lower multilayer.

Explanation of symbols

A, A1, A2, A3, A4, An... Terminal portion forming area expansion type integrated circuit chip component,
B, B1, B2, B3, B4, Bn ... Integrated circuit chip parts having the same type of terminal area,
C, D, H, J ... single chip module or multi chip module,
E, F, G, K ... multilayer modules,
1 ... base, 2 ... protective layer (a protective layer in which the lower protective layer 7 and the upper protective layer 8 are combined),
3 ... Integrated circuit chip, 5 ... Extension wiring part, 6 ... Plane extension terminal part,
7 ... Protective layer (protective layer in which the insulator lower protective layer 12 and the upper protective layer 13 are integrated),
7a ... coating layer, 7b ... lower via wiring part (inner side upper and lower conductor part),
8 ... (for rewiring) upper protective layer, 9 ... upper via wiring (outer side upper and lower conductors), 20 ... protective layer,
DESCRIPTION OF SYMBOLS 10 ... Terminal part (surface expansion terminal part), 12 ... Insulator lower protective layer, 13 ... Upper protective layer,
18 ... Insulator lower protective layer for disposing the integrated circuit chip component,
19 ... Integrated circuit chip component rewiring coating protective layer,
20 ... Further protective layer covering the integrated circuit chip component (a protective layer combined with 18, 19),
22 ... Horizontal wiring, 25 ... Insulating material on the wiring board,
26, 26n ... laminated protective layer, 27 ... laminated rewiring coating protective layer,
28: Upper and lower integrated circuit chip component interlayer conductors,
30: Upper and lower conductor portions on the integrated circuit chip component,
36 ... External connection protective layer and external connection terminal, 39 ... Terminal on the wiring board, 40 ... Wiring board,
Yta, ... via wiring Ytb1, Ytb2, Ytb3, Ytbn for connecting all the integrated circuit chip components above and below the wiring board terminal, via wiring for selectively connecting the integrated circuit chip parts above and below the wiring board terminal,
Yia,... Via wiring for connecting all the integrated circuit chip components above and below the integrated circuit chip components in the module Yib1, Yib2, Yibn,... Vias for selectively connecting the integrated circuit chip components above and below the integrated circuit chip components in the module A wiring Xa1, Xan ... Horizontal wiring Xb1, Xb2, Xb3, Xbn for connecting all the integrated circuit chip parts in the lateral direction from the integrated circuit chip parts in the module. Integrated circuit chip parts in the lateral direction from the integrated circuit chip parts in the module Selectively connect the wiring

Claims (20)

  An extended wiring portion connecting at least a terminal portion forming surface of an integrated circuit chip having a terminal portion with a protective layer made of an insulating material having a larger area than the terminal portion forming surface and connecting the terminal portion to the protective layer And the rearranged terminal portion is formed, and the extended wiring portion extends from the terminal portion in the thickness direction of the protective layer, and the protection from the inner side upper and lower conductor portion. A conductor portion extending in the surface direction of the layer, an external upper and lower conductor portion for drawing the conductor portion to the outside of the protective layer, and an external upper and lower conductor portion connected to the outer side of the protective layer. An integrated circuit chip component characterized in that it is of a terminal part forming area expansion type comprising a rearranged terminal part provided in the above-described manner. An extended wiring portion connecting at least a terminal portion forming surface of an integrated circuit chip having a terminal portion with a protective layer made of an insulating material having a larger area than the terminal portion forming surface and connecting the terminal portion to the protective layer And the rearranged terminal portion is formed, and the extended wiring portion extends from the terminal portion in the thickness direction of the protective layer, and the protection from the inner side upper and lower conductor portion. A conductor portion extending in the surface direction of the layer, an external upper and lower conductor portion for drawing the conductor portion to the outside of the protective layer, and an external upper and lower conductor portion connected to the outer side of the protective layer. An integrated circuit chip component of a terminal part forming area expansion type comprising a rearranged terminal part provided
A terminal portion forming surface of an integrated circuit chip having a terminal portion is covered with a protective layer made of an insulating material having the same area as the terminal portion forming surface, and the protective layer is covered with the protective layer from the terminal portion of the integrated circuit chip. Provided with at least one of integrated circuit chip parts of the same type of terminal part formation area provided with a wiring part connected to a terminal part provided on the outside side,
One or a plurality of integrated circuit chip components of the terminal part formation area expansion type and the terminal part formation area same type are arranged two-dimensionally or three-dimensionally in a further protective layer. A multi-chip module, wherein horizontal wiring or vertical wiring for arbitrarily connecting the plurality of integrated circuit chip components arranged two-dimensionally or three-dimensionally in a protective layer is formed.   Any one of the plurality of integrated circuit chip components arranged two-dimensionally or three-dimensionally in the further protective layer is configured to be connectable from the outside via the horizontal wiring or vertical wiring. The multichip module according to claim 2, wherein   A single chip module or the multichip module formed by disposing a single integrated circuit chip component in the protective layer is formed on a wiring board, and electrode bonding between the single chip module or the multichip module and the wiring board is performed. 3. The method according to claim 2, wherein the protective layer of the single chip module or the multichip module is adhered to the wiring board, and the single chip module or the multichip module is integrated with the wiring board. Or the multichip module of 3.   The integrated circuit chip component is covered in parallel or stacked in a further protective layer, and wiring for connecting the terminals of the internal integrated circuit chip component to each other is provided in the further protective layer. Another terminal is arranged by extending the connection on the further protective layer, the protective layers are integrated with each other, and the plurality of integrated circuit chip components are arranged separately in the further protective layer. The multichip module according to any one of claims 2 to 4.   The integrated circuit chip component is assembled in a state of being mixed with an integrated circuit chip or a passive element, in which a plurality of protective layers are integrated and wired to an internal integrated circuit chip. Item 6. The multichip module according to any one of Items 2 to 5.   100% or more high frequency, function, AC, parameter, etc. electrical characteristics test and burn-in test have been satisfied or equivalent quality reliability is satisfied through the terminal part of the terminal part forming area expansion type integrated circuit chip part 7. The multichip module according to claim 2, wherein protective layers of the integrated circuit chip component are integrated with a further protective layer.   The multichip module according to any one of claims 2 to 7, wherein a vertical wiring or a horizontal wiring for selectively connecting the terminals of the integrated circuit chip component, the integrated circuit chip, and the passive component inside the protective layer is provided. A multi-chip module, wherein the multi-chip module is disposed on a protective layer outside any one of the integrated circuit chip component, the integrated circuit chip, and the passive component.   A test terminal for a multilayer circuit chip component in the multichip module on the lower layer side and an integrated circuit chip of the multichip module on the upper layer side by upper and lower conductor portions that vertically communicate with the protective layer on the outer side of the internal integrated circuit chip component. The multi-chip module according to claim 2, wherein the multi-chip module is electrically connected to a test terminal.   In the multichip module according to any one of claims 2 to 9, from an external terminal of the multichip module and an arbitrary connection terminal of any integrated circuit chip component or integrated circuit chip or passive component in the multichip module, The connection to any connection terminal of any integrated circuit chip component, integrated circuit chip, and passive component in the multichip module is connected via a connection terminal other than the integrated circuit chip component, the integrated circuit chip, and the passive component. The multichip module according to claim 2, further comprising a wiring that can be selected as to whether or not.   The integrated circuit chip component according to claim 1, a protective layer covering the integrated circuit chip component, a wiring connected to a terminal of the previous integrated circuit chip component in the protective layer, A one-layer chip module is formed by forming a horizontal wiring that connects an integrated circuit chip component of the same layer as a via wiring that connects a wiring terminal and an interlayer, and is laminated and manufactured by repeating the manufacturing process of the one-layer chip module. A method for manufacturing a chip module.   3. The integrated circuit chip component according to claim 1 or 2 is placed on an insulating material lower protective layer on a substrate with the terminal portion facing upward, and then the integrated circuit chip component is covered on the lower protective layer. Forming an upper protective layer of an insulating material, and forming an inner upper and lower conductor portion exposed on the upper protective layer by connecting to the terminal portion of the integrated circuit chip component on the upper protective layer, Forming an extended wiring portion connected to the inner upper and lower conductor portions on the upper surface of the lower protective layer for stacking the integrated circuit chip components, and mounting the integrated circuit chip components and then extending the extended wiring portion on the lower protective layer An upper protective layer covering the upper protective layer, and an external upper and lower conductor portion connected to the extended wiring portion and reaching the upper surface side of the upper protective layer is formed on the upper protective layer. Located on the upper surface of the upper protective layer on the upper side Method for producing a chip module and forming a that terminal unit.   The integrated circuit chip component according to claim 1 or 2 is placed on an insulating material lower protective layer formed on a wiring board with a terminal portion of the integrated circuit chip component facing upward, and then the lower protection Form via wiring and terminals to be connected to the wiring board terminals in the layer, and further form an upper protective layer of an insulating material so as to cover the integrated circuit chip component, and connect to the upper protective layer to the lower protective layer upper terminal Forming via wiring and a terminal exposed on the upper protective layer, and connecting the terminal portion of the integrated circuit chip component to the terminal, and an inner upper and lower conductor on the upper surface of the upper protective layer A method of manufacturing a chip module, wherein an extended wiring portion connected to the portion is formed.   A plurality of integrated circuit chip components arranged in a horizontal direction are arranged on the lower protective layer, and a horizontal wiring for connecting the extension wiring portions of the plurality of integrated circuit chip components in a horizontal direction is formed. The manufacturing method of the chip module in any one of Claims 11-13.   Electrical characteristics test and burn-in test for high frequency, function, AC, parameters, etc. of 100 MHz or higher that meet the required requirements via the terminal part of the terminal part forming area extended type or the terminal part extended area same type integrated circuit chip part The method for manufacturing a chip module according to claim 11, wherein the protective layers of the integrated circuit chip parts that have already been formed are integrated.   An integrated circuit chip having a terminal portion is placed on an insulating material lower protective layer on a base with the terminal portion facing upward, and then an upper protective layer of an insulating material so as to cover the integrated circuit chip on the lower protective layer And forming an inner upper and lower conductor portion exposed on the upper protective layer by connecting to the terminal portion of the integrated circuit chip on the upper protective layer, and then forming the inner side on the upper surface of the upper protective layer. Forming an extension wiring part connected to the upper and lower conductor parts, and then forming an upper protection layer covering the extension wiring part on the lower protection layer, and connecting the extension wiring part to the upper protection layer and An integrated circuit chip, wherein an external upper and lower conductor portion reaching the upper surface side of the protective layer is formed, and thereafter a terminal portion positioned on the upper surface of the upper protective layer is formed on the upper side of the outer upper and lower conductor portion. A manufacturing method for parts.   A plurality of chip modules obtained by the manufacturing method according to any one of claims 11 to 16, wherein a plurality of chip modules are connected, and a wiring portion of the chip module on the upper layer side and a wiring portion of the chip module on the lower layer side are connected by the upper and lower conductor portions. A method for manufacturing a chip module, comprising:   A plurality of chip modules are obtained by the manufacturing method according to any one of claims 11 to 16, and the chip modules are stacked, and a wiring portion of the chip module on the upper layer side and a wiring portion of the chip module on the lower layer side In the connection of the chip module, any connection terminal of any chip module in the final chip module and any connection terminal of any chip module in the chip module or the external terminal of the chip module are the other in the chip module. A method of manufacturing a multi-chip module, characterized in that selection is made to connect to any connection terminal of the chip module.   As a method of three-dimensionally arranging a plurality of integrated circuit chips in an insulator together with wiring for arbitrarily connecting the plurality of integrated circuit chips, a multichip module integrated in the insulator is manufactured as an integrated circuit. Chip components or various chip modules are embedded in an insulator or covered with an insulator, and before forming a wiring pattern on the insulator, these integrated circuit chip components or chip modules are cured by curing the insulator. Are combined, integrated, and integrated. A method for manufacturing a multichip module. All the elements constituting the chip module according to any one of claims 11 to 19 have guaranteed electrical characteristics and reliability. In that case, as a method for ensuring the electrical function and characteristics of the chip module The method for manufacturing a multichip module according to any one of claims 11 to 19, wherein only the wiring function and characteristics in the chip module are tested.

Images