JP2004296464A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- JP2004296464A JP2004296464A JP2003082608A JP2003082608A JP2004296464A JP 2004296464 A JP2004296464 A JP 2004296464A JP 2003082608 A JP2003082608 A JP 2003082608A JP 2003082608 A JP2003082608 A JP 2003082608A JP 2004296464 A JP2004296464 A JP 2004296464A
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Abstract
Description
【0001】
【発明の属する技術分野】
本発明は、複数個の外部接続用のパッドを有する半導体基板を備える半導体装置に関する。
【0002】
【従来の技術】
この種の半導体装置としては、例えばマイコン等のICチップがある。このICチップは回路基板に搭載され、ICチップにおける外部接続用のパッドと回路基板とをボンディングワイヤ等にて電気的に接続することにより、実装され、回路基板とともに回路装置を構成する。
【0003】
このようにして上記回路装置を製造する場合、ICチップのバーンイン検査が必要である。バーンイン検査とは、一般に行われている検査であって、ICチップに対して熱および電圧の負荷を加えて動作試験を行い、良品と不良品を選別するものである。
【0004】
このバーンイン検査を考慮した回路装置の製造方法として、一般的には、ウェハからICチップを個別に取り出し、個々のICチップについてバーンイン検査を行い、良品と判定されたICチップのみをワイヤボンディング等の実装方法にて回路基板に実装する方法が挙げられる。
【0005】
現状では、ICチップを個別にバーンイン検査する場合、図7に示すように、専用のソケット400を用いて行う。このソケット400は、ICチップ900の一面901に配列して形成された複数個の外部接続用のパッド902に対応する位置に突起状の電極410が形成されたものである。そして、ICチップ900をソケット400にセットした後、検査装置500を介して所望の環境にて動作試験を行う。
【0006】
しかし、一般に、ICチップ900上のパッド902における配列のピッチ寸法が0.5mm以上の大きさでないと、バーンイン検査が困難となる。これは、当該ピッチ寸法が0.5mm未満になると、ICチップ900のパッド902とソケット400の電極410との位置あわせが難しくなる等の問題があり、そのような狭ピッチ化に対応したソケットを製造することが著しく困難となるためである。
【0007】
他方、ICチップにおける外部接続用のパッドのピッチ寸法は、高密度化のニーズから、年々小さくなり、現在では、0.1mmを下回るICチップが製造されている。
【0008】
ここにおいて、ICチップとリードフレームとをボンディングワイヤで結線したものを樹脂でモールドしてなる半導体パッケージ、いわゆる樹脂モールドパッケージの場合では、このようなパッドのピッチ寸法が小さいICチップを使用しても問題はない。
【0009】
その理由としては、一つのICチップのみをリードフレームとワイヤ接続した後に、バーンイン検査を行うため、ソケットの電極と接触するのはリードフレームとなり、このリードフレームを使用することによってピッチを広げることができるためである。
【0010】
その結果、従来の電極ピッチを有する安価なソケットを使用できることになる。また、このような樹脂モールドパッケージでは、ICチップをリードフレームに実装した後にバーンイン検査を行っても、実装コストが安いため、不良率の影響が小さい。
【0011】
しかしながら、上述したようにICチップを回路基板に実装する場合には、実装するICチップにおける外部接続用のパッドにおける配列のピッチ寸法が、0.5mmより小さくなってくると、リードフレームを使用しないがゆえに、個別のICチップを実装前に検査することが著しく困難となる。
【0012】
また、ICチップの一面に外部接続用のパッドとバーンイン検査用のパッドとを分けて形成する手法(特許文献1、2参照)も提案されているが、上記したバーンイン検査用のパッドにおける配列の狭ピッチ化に対するソケットの問題については、解決案は示されていない。
【0013】
【特許文献1】
特開昭62−67846号公報(第1図)
【0014】
【特許文献2】
特開平7−122604号公報(第3頁、第1−2図)
【0015】
【発明が解決しようとする課題】
本発明は上記事情に鑑みてなされたものであり、複数個の配列された外部接続用のパッドを有する半導体装置において、外部接続用のパッドの配列ピッチが狭ピッチ化されてもバーンイン検査を適切に行うことができるようにすることを目的とする。
【0016】
【課題を解決するための手段】
上記目的を達成するため、請求項1に記載の発明では、半導体基板(1)を有し、半導体基板の一面(1a)には、複数個の外部接続用のパッド(2)が配列されており、さらに、半導体基板の一面には、外部接続用のパッドに個々に電気的に接続された検査用のパッド(3)が、外部接続用のパッドの配列のピッチ寸法(T1)よりも大きなピッチ寸法(T2)にて配列されていることを特徴とする。
【0017】
それによれば、複数個の外部接続用のパッドの個々について、検査用のパッドが電気的に接続され、これら検査用のパッドの配列のピッチ寸法が外部接続用のパッドのそれよりも大きいものになっている。
【0018】
そのため、バーンイン検査を行う際には、この大きなピッチ寸法にて配列された検査用のパッドに対して、ソケットを接続すればよいことになり、一方、外部接続用のパッドについては、狭ピッチ化を進めることができる。よって、本発明によれば、外部接続用のパッドの配列ピッチが狭ピッチ化されてもバーンイン検査を適切に行うことができる。
【0019】
ここで、請求項2に記載の発明では、半導体基板(1)の一面(1a)において、それぞれの外部接続用のパッドに電気的に接続された再配線(6a)が形成されており、外部接続用のパッドと接続された部位から延設された再配線の一部が、検査用のパッド(3)として構成されていることを特徴とする。
【0020】
再配線はその構成上、多層化することができる。そのため、外部接続用のパッドに接続された再配線の一部を検査用のパッドとすれば、外部接続用のパッドが数多くある場合であっても、それに対応した検査用のパッドまでの再配線の経路の配置自由度を大きくすることができ、有利である。
【0021】
さらに、請求項3に記載の発明では、半導体基板(1)の一面(1a)において再配線(6a)の下地膜(4、5)は2層構成を有するものであり、これら2層のうち上側の層(5)が下側の層(4)よりも軟らかいものであることを特徴とする。
【0022】
それによれば、バーンイン検査の際に、再配線の一部である検査用のパッドにソケットの電極が当たったとき、下地の軟らかい層にてその衝撃を緩和できるため、半導体基板に形成されている素子のダメージを極力防止できる。
【0023】
また、請求項4に記載の発明のように、外部接続用のパッド(2)としては、ワイヤボンディングされるものできる。
【0024】
また、請求項5に記載の発明のように、外部接続用のパッド(2)の配列のピッチ寸法(T1)が0.15mm以下と狭い場合であっても、検査用のパッド(3)の配列のピッチ寸法(T2)を0.5mm以上と広くすることができる。
【0025】
なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。
【0026】
【発明の実施の形態】
以下、本発明を図に示す実施形態について説明する。図1は本発明の実施形態に係る半導体装置100の実装構造を示す概略断面図、図2は図1中の半導体装置100の上視平面図、図3は図1中の丸で囲んだA部拡大図である。
【0027】
本実施形態の半導体装置100はICチップ100であり、このICチップ100はマイコン等の高密度集積化ICである。このICチップ100は、回路基板200に対して搭載され、回路基板200のランド210に導電性接着剤220等を介して接続されるとともに、回路基板200のランド211にボンディングワイヤ230を介して電気的に接続されている。
【0028】
また、回路基板200の上には、コンデンサ等からなる部品300が搭載されている。図示例では、この部品300はコンデンサ300であり、コンデンサ300は、回路基板200のランド212に導電性接着剤220または半田等を介して電気的に接続されている。そして、これらICチップ100、部品300および回路基板200により回路が構成され、全体として電子回路装置を形成している。
【0029】
図1、図2に示すように、ICチップ100は、シリコン基板等からなる半導体基板1を有している。この半導体基板1は、本例では10mm□の矩形板状のものである。
【0030】
半導体基板1の一面1a上には、複数個の外部接続用のパッド2および複数個の検査用のパッド3が形成されている。これらパッド2、3は、半導体基板1の一面1aに形成された後述する第3の保護膜7の開口部から露出した部分である。
【0031】
外部接続用のパッド2は、図2に示すように、ICチップ100の周辺部に所定のピッチ寸法T1で環状に一列に配列されている。この外部接続用のパッド2は、ボンディングワイヤ230が結線され電気的に接続されるパッドとして構成されている。
【0032】
この外部接続用のパッド2の配列のピッチ寸法T1は、0.15mm程度であり、本例では256個の外部接続用のパッド2が、0.15mmのピッチ寸法T1にてICチップ100の周辺部に配列されている。
【0033】
また、検査用のパッド3は、一つの外部接続用のパッドに対して一つずつ電気的に接続されたものであり、バーンイン検査の際に、バーンイン検査用のソケットの電極が接する部分である。
【0034】
この検査用のパッド3は、外部接続用のパッド2の配列のピッチ寸法T1よりも大きなピッチ寸法T2にて配列されている。このピッチ寸法T2は0.5mm以上であり、本例では、外部接続用のパッド2の内周部において、0.5mmのピッチ寸法T2にて16×16個の検査用のパッド3が、マトリクス状に配列されている。
【0035】
これらパッド2、3構成の詳細等について図3を参照して述べる。半導体基板1の一面1a上に形成されている外部接続用のパッド2は、本例では、ワイヤボンディングされている外部接続用のパッド2は、下側(半導体基板1側)の第1の層2aとその上側に位置しボンディングワイヤ230が直接接合される第2の層2bとからなる。
【0036】
ここで、外部接続用のパッド2の第1の層2aは、例えば、蒸着法やフォトリソグラフ技術等を用いて成膜されたアルミニウム(Al)等の膜からなるものである。
【0037】
また、半導体基板1の一面1a上には、第1の保護膜4が形成されている。この第1の保護膜4は、CVD(化学気相成長法)等により成膜されたシリコン窒化膜等からなり、また、この第1の保護膜4には、外部接続用のパッド2の第1の層2aを露出させるための開口部が形成されている。
【0038】
また、第1の保護膜4の上には、絶縁膜5が形成されている。この絶縁膜5は、スピンコート法等により成膜されたポリイミド膜等からなり、また、この絶縁膜5にも、上記第1の保護膜4と同様に、外部接続用のパッド2の第1の層2aを露出させるための開口部が形成されている。
【0039】
ここで、第1の保護膜4と絶縁膜5とを比べた場合、下側に位置する第1の保護膜4はICチップ保護膜として機能しており、上側に位置する絶縁膜5は、第1の保護膜よりも軟らかい層として構成されている。具体的には、上述したように、第1の保護膜4をシリコン窒化膜、絶縁膜5をポリイミド膜から構成すればよい。
【0040】
そして、この絶縁膜5の上には、第1の保護膜4および当該絶縁膜5を下地膜として配線層6が形成されている。この配線層6は、蒸着法やフォトリソグラフ技術等を用いて成膜されたAl膜や銅(Cu)膜等からなり、その一端部が、第1保護膜4および絶縁膜5に形成された上記開口部を介して外部接続用のパッド2の第1の層2aに電気的に接続されている。
【0041】
また、この配線層6は、第1の保護膜4および絶縁膜5に形成された上記開口部から、検査用パッド3の位置まで延設されている。そして、この配線層6および配線層6が形成されていない絶縁膜5の上には、第2の保護膜7が形成されている。
【0042】
この第2の保護膜7は、スピンコート法等により成膜されたポリイミド膜等からなる。そして、この第2の保護膜7には、上記配線層6の一部を露出させるための開口部が形成されており、この開口部から露出する上記配線層6の領域が、外部接続用のパッド2および検査用のパッド3として構成されている。
【0043】
つまり、外部接続用のパッド2は、上記第1の層2aと、その上部に位置しボンディングワイヤ230と直接接合される第2の層2bとからなる。なお、この第2の層2bは上記配線層6の一部でもある。一方、検査用のパッド3も第2の保護膜7の開口部から露出する配線層6の一部により構成されている。
【0044】
そして、配線層6のうち上記した外部接続用のパッド2となっている部分、すなわち外部接続用のパッド2の第2の層2bとなっている部分を除いた部分は、これら両パッド2、3を接続する再配線6aとして構成されている。
【0045】
言い換えれば、半導体基板1の一面1aにおいては、それぞれの外部接続用のパッド2に再配線6aが電気的に接続された形で形成されており、この接続部より延設された再配線6aの一部が検査用のパッド3として構成されていることになる。
【0046】
なお、これら半導体基板1に形成された各パッド2、3および絶縁膜としての各保護膜4、5、7等は、公知の半導体製造技術に用いられる成膜法やパターニング技術を用いて製造することができる。
【0047】
ところで、本実施形態のICチップ100によれば、複数個の外部接続用のパッド2の個々について、検査用のパッド3が電気的に接続され、これら検査用のパッド3の配列のピッチ寸法T2が外部接続用のパッド2の配列のピッチ寸法T1よりも大きいものになっている。
【0048】
そのため、バーンイン検査を行う際には、この大きなピッチ寸法T2にて配列された検査用のパッド3に対して、ソケットを接続すればよいことになり、一方、外部接続用のパッド2については、狭ピッチ化を進めることができる。よって、本実施形態によれば、外部接続用のパッド2の配列ピッチが狭ピッチ化されてもバーンイン検査を適切に行うことができる。
【0049】
具体的には、ウェハ状態にてチップ単位毎に上記ICチップ100を製造した後、各ICチップ100をダイシングカットにより分断する。そして、個々のICチップ100についてバーンイン検査を行う。
【0050】
その方法は、上記図7に示した一般的な方法と同様であり、ICチップ100の一面1aに形成された検査用のパッド3に対応する位置に突起状の電極が形成された専用のソケットを用意し、ICチップ100をソケットにセットした後、所望の環境にて動作試験を行う。
【0051】
次に、バーンイン検査にて良品となったICチップのみを、回路基板200の上に実装する。例えば、回路基板200のランド210に導電性接着剤220を印刷あるいはディスペンス法にて供給し、ICチップ100を搭載する。硬化した後に、ワイヤボンディングを行って、ボンディングワイヤ230による結線を行う。
【0052】
ここで、ボンディングワイヤ230としては、接合性が確保できるならば、Au、Al、Cu、Au−Pd等のいずれのワイヤを用いてもよい。また、このICチップ100の実装と合わせて、部品300の実装も行う。こうして、上記図1に示す実装構造ができあがる。
【0053】
また、本実施形態によれば、それぞれの外部接続用のパッド2に電気的に接続された再配線6aが形成されており、外部接続用のパッド2と接続された部位から延設された再配線6aの一部が検査用のパッド3として構成されている。
【0054】
再配線はその構成上、絶縁膜の間に介在させることによって多層化が容易である。そのため、外部接続用のパッド2に接続された再配線6aの一部を検査用のパッド3とすれば、外部接続用のパッド2が数多くある場合であっても、それに対応した検査用のパッド3までの再配線6aの経路の配置自由度を大きくすることができ、有利である。
【0055】
つまり、外部接続用のパッド2と検査用のパッド3とを同一面上に形成する場合、外部接続用のパッド2が多数ある場合、検査用のパッド3までの引き回し配線のレイアウトに制約が大きい。その点、再配線ならば、3次元的なレイアウトが可能であるため、制約が小さい。
【0056】
また、本実施形態では、半導体基板1の一面1aにおいて再配線6aの下地膜4、5すなわち第1の保護膜4および絶縁膜5は2層構成を有するものであり、これら2層のうち上側の層5が下側の層4よりも軟らかいものとしている。
【0057】
それによれば、バーンイン検査の際に、再配線6aの一部である検査用のパッド3にソケットの電極が当たったとき、下地の軟らかい層4にてその衝撃を緩和できるため、半導体基板1に形成されている素子(例えば、トランジスタ等)のダメージを極力防止できる。
【0058】
そして、本実施形態では、外部接続用のパッド2の配列のピッチ寸法T1が0.15mm以下と狭い場合であっても有効にバーンイン検査が行える。これは、上述したように、検査用のパッド3を形成することにより、検査用のパッド3の配列のピッチ寸法T2を0.5mm以上と広くすることができるためである。
【0059】
[変形例]
なお、従来より、フリップチップ実装を行うICチップの場合において、ICチップ上に再配線を形成し、ICチップの周辺に配置されているパッドを再配線を介してICチップの面内に新たな外部接続用のパッドとして配置し、この新たなパッドにバンプを形成する手法がある。
【0060】
しかし、この場合、当該新たなパッドの配列のピッチ寸法を大きくしてバーンイン検査を行いやすくできるものの、当該新たなパッド上にバンプを形成するという余分な工程が必要になる。
【0061】
その点、本実施形態のICチップ100では、外部接続用のパッド2は、ワイヤボンディングによって外部の回路基板200と接続できるため、バンプ形成工程は不要となる。さらに、本実施形態のICチップ100を用いれば、変形例として次の図4(a)、(b)に示すように、フリップチップ実装も可能である。
【0062】
この図4に示す例では、(a)ICチップ100における外部接続用のパッド2と回路基板200のランド211とを半田240を介して電気的に接続したり、(b)ICチップ100における外部接続用のパッド2に形成したAu等のバンプ250と回路基板200のランド211とを導電接着剤220を介して電気的に接続するようにしている。
【0063】
また、ICチップ100における外部接続用のパッド2および検査用のパッド3の配列形態は、上記図2に示す形態に限定されるものではない。例えば、次の図5(a)、(b)、(c)に示すような形態も可能である。
【0064】
図5において、(a)は外部接続用のパッド2がICチップ100の周辺部にて一部2列に配置されている例、(b)は外部接続用のパッド2がICチップ100の周辺部に加えて中央部にも一部配置されている例、(c)は検査用のパッド3がICチップ100の周辺部に配置され、外部接続用のパッド2がICチップ100の中央部寄りに配置されている例を示す。
【0065】
また、上記図3の例では、外部接続用のパッド2が、2層2a、2bからなるものであったが、図6に示すように、1層構成であってもよい。図6では、上記図3における第1の層2aのみが外部接続用のパッド2を構成している。
【0066】
つまり、配線層6と外部接続用のパッド2との接続部は、第2の保護膜7にて被覆されており、その接続部以外の外部接続用のパッド2の部分が、第2の保護膜7の開口部から露出している。そして、この場合、配線層6の全体が再配線6aとして構成されている。
【0067】
なお、上記実施形態において、バーンイン検査はウェハから切り出したチップ状態にて行ったが、可能であればウェハ状態で行ってもよい。つまり、ウェハ状態にてチップ単位毎に上記ICチップ100を製造した後であって、各ICチップ100をダイシングカットにより分断する前に、バーンイン検査を行うようにしてもよい。
【図面の簡単な説明】
【図1】本発明の実施形態に係る半導体装置としてのICチップの実装構造を示す概略断面図である。
【図2】図1中のICチップの上視平面図である。
【図3】図1中のA部拡大図である。
【図4】図1に示したICチップをフリップ実装する変形例を示す概略断面図である。
【図5】ICチップにおける外部接続用のパッドおよび検査用のパッド3の配列形態の変形例を示す平面図である。
【図6】ICチップにおける外部接続用のパッドの変形例を示す概略断面図である。
【図7】一般的なバーンイン検査の方法を示す図である。
【符号の説明】
1…半導体基板としてのICチップ、1a…ICチップの一面、
2…外部接続用のパッド、3…検査用のパッド、4…第1の保護膜、
5…絶縁膜、6a…再配線、
T1…外部接続用のパッドのピッチ寸法、
T2…検査用のパッドのピッチ寸法。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device provided with a semiconductor substrate having a plurality of external connection pads.
[0002]
[Prior art]
As this type of semiconductor device, for example, there is an IC chip such as a microcomputer. This IC chip is mounted on a circuit board, and is mounted by electrically connecting pads for external connection of the IC chip and the circuit board with bonding wires or the like, thereby constituting a circuit device together with the circuit board.
[0003]
When the above-described circuit device is manufactured in this manner, a burn-in inspection of the IC chip is required. The burn-in inspection is a commonly performed inspection, in which an operation test is performed by applying a heat and voltage load to an IC chip, and a good product and a defective product are selected.
[0004]
As a method of manufacturing a circuit device in consideration of the burn-in inspection, generally, an IC chip is individually taken out from a wafer, a burn-in inspection is performed on each IC chip, and only the IC chip determined as a non-defective product is subjected to wire bonding or the like. There is a method of mounting on a circuit board by a mounting method.
[0005]
At present, when performing burn-in inspection on individual IC chips, as shown in FIG. 7, the burn-in inspection is performed using a
[0006]
However, in general, the burn-in inspection becomes difficult unless the pitch dimension of the arrangement of the
[0007]
On the other hand, the pitch of pads for external connection in an IC chip is becoming smaller year by year due to the need for higher density. At present, IC chips smaller than 0.1 mm are manufactured.
[0008]
Here, in the case of a semiconductor package in which an IC chip and a lead frame are connected by a bonding wire and molded with a resin, that is, a so-called resin molded package, even if such an IC chip having a small pad pitch is used, No problem.
[0009]
The reason is that the burn-in test is performed after only one IC chip is connected to the lead frame by wire, so that the lead frame comes into contact with the electrode of the socket, and the pitch can be increased by using this lead frame. This is because we can do it.
[0010]
As a result, an inexpensive socket having the conventional electrode pitch can be used. Further, in such a resin mold package, even if the burn-in inspection is performed after the IC chip is mounted on the lead frame, the mounting cost is low, so that the influence of the defect rate is small.
[0011]
However, when the IC chip is mounted on the circuit board as described above, the lead frame is not used when the pitch of the arrangement of the external connection pads in the mounted IC chip becomes smaller than 0.5 mm. Therefore, it becomes extremely difficult to inspect individual IC chips before mounting.
[0012]
Further, a method of separately forming pads for external connection and pads for burn-in inspection on one surface of an IC chip (see
[0013]
[Patent Document 1]
JP-A-62-67846 (FIG. 1)
[0014]
[Patent Document 2]
JP-A-7-122604 (
[0015]
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances, and in a semiconductor device having a plurality of arranged pads for external connection, a burn-in inspection is appropriate even if the arrangement pitch of the pads for external connection is narrowed. The purpose is to be able to do.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, a semiconductor substrate (1) is provided, and a plurality of external connection pads (2) are arranged on one surface (1a) of the semiconductor substrate. Further, on one surface of the semiconductor substrate, the inspection pads (3) electrically connected to the external connection pads are larger than the pitch dimension (T1) of the arrangement of the external connection pads. It is characterized by being arranged in a pitch dimension (T2).
[0017]
According to this, the test pads are electrically connected to each of the plurality of external connection pads, and the pitch dimension of the arrangement of the test pads is larger than that of the external connection pads. Has become.
[0018]
Therefore, when performing a burn-in test, a socket may be connected to the test pads arranged with this large pitch dimension, while the external connection pads are reduced in pitch. Can proceed. Therefore, according to the present invention, the burn-in inspection can be appropriately performed even when the arrangement pitch of the pads for external connection is narrowed.
[0019]
According to the second aspect of the present invention, the rewiring (6a) electrically connected to each external connection pad is formed on one surface (1a) of the semiconductor substrate (1). A part of the rewiring extending from a portion connected to the connection pad is configured as a test pad (3).
[0020]
The rewiring can be multilayered due to its configuration. Therefore, if a part of the rewiring connected to the external connection pad is used as the inspection pad, even if there are many external connection pads, the rewiring up to the corresponding inspection pad is performed. This can advantageously increase the degree of freedom of arrangement of the path.
[0021]
Furthermore, in the invention according to
[0022]
According to this, at the time of burn-in inspection, when an electrode of a socket hits an inspection pad which is a part of rewiring, the impact can be reduced by a soft layer as an underlayer, so that it is formed on a semiconductor substrate. Element damage can be prevented as much as possible.
[0023]
Further, as in the invention according to
[0024]
Further, even when the pitch dimension (T1) of the arrangement of the external connection pads (2) is as narrow as 0.15 mm or less as in the invention according to
[0025]
It should be noted that reference numerals in parentheses of the above-described units are examples showing the correspondence with specific units described in the embodiments described later.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention shown in the drawings will be described. FIG. 1 is a schematic sectional view showing a mounting structure of a
[0027]
The
[0028]
On the
[0029]
As shown in FIGS. 1 and 2, the
[0030]
On one
[0031]
As shown in FIG. 2, the
[0032]
The pitch dimension T1 of the arrangement of the
[0033]
The
[0034]
The
[0035]
Details of the configuration of the
[0036]
Here, the
[0037]
In addition, a first
[0038]
An insulating
[0039]
Here, when the first
[0040]
The first
[0041]
The
[0042]
The second
[0043]
That is, the
[0044]
The portion of the
[0045]
In other words, on one
[0046]
The
[0047]
By the way, according to the
[0048]
Therefore, when performing a burn-in inspection, a socket may be connected to the
[0049]
Specifically, after manufacturing the IC chips 100 for each chip in a wafer state, each
[0050]
The method is the same as the general method shown in FIG. 7, and a dedicated socket having a protruding electrode formed at a position corresponding to the
[0051]
Next, only non-defective IC chips in the burn-in inspection are mounted on the
[0052]
Here, as the
[0053]
Further, according to the present embodiment, the
[0054]
Due to its structure, the rewiring can be easily multilayered by being interposed between insulating films. Therefore, if a part of the
[0055]
That is, when the
[0056]
In the present embodiment, the
[0057]
According to this, at the time of burn-in inspection, when the electrode of the socket hits the
[0058]
In this embodiment, even when the pitch dimension T1 of the arrangement of the
[0059]
[Modification]
Conventionally, in the case of an IC chip that is flip-chip mounted, a rewiring is formed on the IC chip, and a pad arranged around the IC chip is re-wired in the surface of the IC chip through the rewiring. There is a method of arranging pads as external connection pads and forming bumps on the new pads.
[0060]
However, in this case, although the burn-in inspection can be easily performed by increasing the pitch dimension of the arrangement of the new pads, an extra step of forming bumps on the new pads is required.
[0061]
In this regard, in the
[0062]
In the example shown in FIG. 4, (a) the
[0063]
Further, the arrangement of the
[0064]
5A shows an example in which
[0065]
Further, in the example of FIG. 3, the
[0066]
That is, the connection portion between the
[0067]
In the above embodiment, the burn-in inspection is performed in a chip state cut out from a wafer, but may be performed in a wafer state if possible. That is, a burn-in inspection may be performed after the IC chips 100 are manufactured for each chip in a wafer state and before each
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing a mounting structure of an IC chip as a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a plan view of the IC chip in FIG. 1 as viewed from above.
FIG. 3 is an enlarged view of a portion A in FIG. 1;
FIG. 4 is a schematic sectional view showing a modification in which the IC chip shown in FIG. 1 is flip-mounted.
FIG. 5 is a plan view showing a modification of the arrangement of pads for external connection and pads for
FIG. 6 is a schematic cross-sectional view showing a modified example of a pad for external connection in an IC chip.
FIG. 7 is a diagram showing a general burn-in inspection method.
[Explanation of symbols]
1 ... IC chip as semiconductor substrate, 1a ... one side of IC chip,
2 ... pad for external connection, 3 ... pad for inspection, 4 ... first protective film,
5: insulating film, 6a: rewiring,
T1: pitch dimension of pad for external connection,
T2: Pitch size of inspection pad.
Claims (5)
前記半導体基板の一面(1a)には、複数個の外部接続用のパッド(2)が配列されており、
さらに、前記半導体基板の一面には、前記外部接続用のパッドに個々に電気的に接続された検査用のパッド(3)が、前記外部接続用のパッドの配列のピッチ寸法(T1)よりも大きなピッチ寸法(T2)にて配列されていることを特徴とする半導体装置。Having a semiconductor substrate (1);
A plurality of external connection pads (2) are arranged on one surface (1a) of the semiconductor substrate.
Further, on one surface of the semiconductor substrate, a test pad (3) electrically connected to the external connection pad is larger than a pitch dimension (T1) of the arrangement of the external connection pad. A semiconductor device characterized by being arranged with a large pitch dimension (T2).
前記外部接続用のパッドと接続された部位から延設された前記再配線の一部が、前記検査用のパッド(3)として構成されていることを特徴とする請求項1に記載の半導体装置。On one surface (1a) of the semiconductor substrate (1), a rewiring (6a) electrically connected to each of the external connection pads is formed,
2. The semiconductor device according to claim 1, wherein a part of the rewiring extending from a portion connected to the external connection pad is configured as the inspection pad. .
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100665843B1 (en) * | 2005-02-21 | 2007-01-09 | 삼성전자주식회사 | Layout structure and method of pad in semiconductor device |
JP2007027685A (en) * | 2005-06-17 | 2007-02-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing the same |
WO2011115126A1 (en) * | 2010-03-17 | 2011-09-22 | 富士フイルム株式会社 | Solid-state image capture element, production method for same, and image capture device |
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JP2007027685A (en) * | 2005-06-17 | 2007-02-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing the same |
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WO2011115126A1 (en) * | 2010-03-17 | 2011-09-22 | 富士フイルム株式会社 | Solid-state image capture element, production method for same, and image capture device |
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