KR100665843B1 - Layout structure and method of pad in semiconductor device - Google Patents

Abstract

Disclosed is a layout structure of pads formed on a semiconductor device for use in operation testing or wire bonding of a semiconductor device. The arrangement of such pads is formed such that the size of one or more pads that will not be wire bonded is small compared to the size of one or more pads to be wire bonded on the semiconductor device. Thus, the present invention provides an improved pad arrangement structure in a semiconductor device, whereby a peripheral circuit can be further formed in a pad-formed area by increasing the pad pitch within a limited area, thereby achieving high integration of the semiconductor device. Has

Pad, package, probe, test

Description

Layout structure and method of pad in semiconductor device

1 is a schematic view showing a semiconductor memory device with conventional pads.

2 is an enlarged schematic view of pads in FIG. 1;

3 is a schematic view showing a pad arrangement structure in a semiconductor device according to an embodiment of the present invention.

4 is a schematic view showing a pad arrangement structure in a semiconductor device according to another embodiment of the present invention.

5 is a schematic view showing a semiconductor device having a pad arrangement structure according to FIG. 3.

<Description of the symbols for the main parts of the drawings>

PD311, PD313, PD411, PD413, PD501, PD503: first pad

PD312, PD314, PD412, PD414, PD502: second pad

301, 305, 401, 405: test area 302, 306, 402, 406: bonding area

311, 313, 315, 317, 411, 413, 415, 417: Probe Mark

MW: Width of the connection part

PAD_PIT1, PAD_PIT2, PAD_PIT3, PAD_PIT4, PAD_PIT5: Pad Pitch

511, 512, 513, 514: pad group

The present invention relates to a semiconductor device, and more particularly, to a pad arrangement structure and a pad arrangement method in a semiconductor device.

Typically, a semiconductor device such as a semiconductor memory device is provided with pads for enabling electrical connection between the semiconductor memory device and the outside of the semiconductor memory device. Signals related to command input, data read, and data write operations are input into the semiconductor memory device or output to the outside of the semiconductor memory device through the pads.

Recently, the manufacturing technology of semiconductor memory devices is on the trend of high integration due to the reduction of design rules. This high integration reduces the size of the semiconductor memory device, thereby increasing the number of net dies produced in the semiconductor wafer, thereby reducing the cost.

However, even if the integration of devices mounted in a semiconductor memory device doubles, for example, the number of the pads does not increase by about one or even one. On the contrary, considering the case where the density decreases in half, the number of the pads is reduced by about one or even not by one. Therefore, the area occupied by the pads is not a big issue in the high density memory or the like, but the area occupied by the pads is a significant problem in the low density memory with low integration compared with the high density memory. This is because the chip size is continuously reduced as the semiconductor device manufacturing process is advanced, but the size of the pad is not so reduced. That is, even if the total size of the chip is reduced, the size of the pads cannot be easily reduced due to reinvestment problems in bonding equipment or test equipment using the pads.

1 is a schematic diagram illustrating a semiconductor memory device having conventional pads.

Referring to FIG. 1, a semiconductor memory device 10 having a memory cell array 15 and pad groups 11, 12, 13, and 14 formed in a pad area among peripheral regions of the memory cell array 15 is illustrated. have.

The memory cell array 15 is formed such that bit lines and word lines are orthogonal to each other, and unit memory cells are formed in a matrix at intersections of the bit lines and word lines.

The pad group 13 includes pads PD1, PD2, PD3, ..., PDn-2, PDn-1, PDn. The pad group 14 includes pads PD11, PD12, PD13, PD14, ..., PDm-2, PDm-1, PDm.

The pads PD1, PD2, PD3,..., PDn-2, PDn-1, PDn, PD11, PD12, PD13, PD14, PDm-2, PDm-1, PDm are the semiconductor memory device 10. Electrical connection with the outside of the semiconductor memory device 10.

More specifically, the pads PD1, PD2, PD3, PD11, PD12, PD13, and PD14 may be pads to be tested and wire bonded to the outside of the semiconductor memory device 10 and the semiconductor. The pads used in the operation test of the memory device 10 but not used for wire bonding may be classified. The operation test may be performed by contacting the pads with a probe tip, and then, signals related to operations such as command input, data read, and data write in the equipment for the test may be stored in the semiconductor memory device 10. Or is outputted to the outside of the semiconductor memory device 10. In addition, a lead frame on a plastic of a package (for example, a plastic package) is connected to the pads to be wire bonded by metal wires (for example, gold wires).

Peripheral circuit elements (eg, buffers, delay elements, MOS transistors, etc.) for the operation of the semiconductor memory device are formed in the peripheral area adjacent to the pad area.

FIG. 2 is an enlarged schematic view of the pads of FIG. 1.

Referring to FIG. 2, pads PD11, PD12, PD13, and PD14 and a pad pitch PAD_PIT are shown.

The pads are classified into pads used for an operation test of a semiconductor memory device and wire bonding with an external device, and pads not used for wire bonding of the semiconductor memory device. For example, the pad PD11 is a pad to be wire bonded, the pad PD12 is a pad not to be wire bonded, the pad PD13 is a pad to be wire bonded, and the pad PD14 is not wire bonded. It may be a pad. Alternatively, the pad PD11 may be a pad to be wire bonded, the pad PD12 may be a pad to be wire bonded, the pad PD13 may be a pad to be wire bonded, and the pad PD14 may be a pad not to be wire bonded. Here, both the pad to be bonded and the pad to be bonded are formed to have a constant size. That is, the pads PD11, PD12, ... are not distinguished in terms of pads to be bonded from pads to be bonded.

The pad pitch PAD_PIT means a distance between adjacent pads, that is, a margin of width in which one pad may be formed. For example, the pad pitch PAD_PIT between the pad PD11 and the pad PD22 is from the left end of the pad PD11 to the left end of the pad PD12. In general, the size and pad pitch of the pads PD11, PD12, PD13 are generally constant.

Then, the bonding is avoided by avoiding a probe mark, which is a portion recessed by the probe pin at the time of wire bonding. Otherwise, the adhesive strength between the pad and the bonding wire is weakened and the yield of the package is lowered.

In the pads of FIGS. 1 and 2, the pad to be bonded is also tested so that a minimum size is required to ensure an area for probing and an area for wire bonding. In addition, pads that are not to be bonded need only at least ensure an area for probing.

As described above, in the conventional semiconductor memory device, pads that are used for the operation test and are not to be wire-bonded and pads for the operation test and the wire-bonding are generally formed to increase the pitch of the pad within a certain area. There is a problem that is difficult to make.

In addition, since the pads used for the operation test and not the wire bonding are formed to be substantially constant with the size of the pads for the operation test and the wire bonding, it is difficult to reduce the pad area where the pads should be formed. There is a limit to size reduction. Therefore, there is a problem that it is difficult to realize high integration of the semiconductor memory device. In addition to the semiconductor memory device, the above-described problems also exist in a semiconductor device (for example, a microprocessor or a CDD device) in which pads are formed.

Accordingly, an object of the present invention is to provide a pad arrangement structure of a semiconductor device that can form a peripheral circuit in a region where a pad has been conventionally formed by increasing the pad pitch within a limited region, thereby achieving high integration.

Another object of the present invention is to form a pad that is used for an operation test that is not used for wire bonding and a pad for an operation test and wire bonding, thereby reducing the area where the pads should be formed. To provide a pad arrangement structure and a pad arrangement method of the.

It is still another object of the present invention to provide a pad arrangement structure and a pad arrangement method of a semiconductor device capable of reducing the area where pads are to be formed by modifying the structure of the pad for conventional testing and wire bonding in various forms.

In order to achieve the above objects, an arrangement structure of pads formed on the semiconductor device for use in operation testing or wire bonding of the semiconductor device according to an aspect of the present invention may include the size of one or more pads to be wire bonded on the semiconductor device. Compared to the wire bond, the size of the at least one pad that is not to be formed is small.

Here, one or more pads to be wire bonded and one or more pads not to be wire bonded may be mixed and arranged in one row or one column.

In addition, the one or more pads that will not be wire bonded may be electrically connected in contact with the probe tip of the probe card during the operation test.

In addition, the one or more pads to be wire bonded may include a test area used for the operation test and a bonding area used for the wire bonding.

The test area may be electrically connected to the probe tip of the probe card during the operation test.

In addition, the bonding area may be bonded with a wire for electrical connection with the outside of the semiconductor device during the packaging process.

In order to achieve the above objects, a semiconductor device in which a pad for use in an operation test or wire bonding is formed according to an aspect of the present invention includes: one or more first pads to be used in both the operation test and the wire bonding of the semiconductor device; And at least one second pad having a smaller size than the first pad and not used for the wire bonding.

 Here, the first pad and the second pad may be mixed and arranged in one row or one column.

In addition, the second pad may be electrically connected to the probe tip of the probe card during the operation test.

In addition, the first pad may include a test area used for the operation test and a bonding area used for the wire bonding.

In addition, the size of the second pad may be substantially the same as the size of the test area.

In addition, the first pad may be a line-shaped pad having a width of the test area and the bonding area that is substantially the same to form a rectangular shape.

In addition, the first pad may be a stepped pad having a width substantially equal to that of the test region and a connecting portion of the bonding region and the test region narrower than the width of the bonding region.

The first pad may include a line-shaped pad having a width substantially equal to the width of the test area and the bonding area to form a rectangular shape, and a width of the bonding area substantially coinciding with a width of the test area. The connection portion of the test region may be any one pad selected from stepped pads narrower than the width of the bonding region.

In order to achieve the above objects, in accordance with an aspect of the present invention, a method of arranging pads formed on the semiconductor device for use in operation testing or wire bonding of the semiconductor device includes operating the semiconductor device in one row or one column. Placing first pads to be used for both test and wire bonding; And disposing second pads between the first pads, the second pads being less used for wire bonding of the semiconductor device and smaller in size than the first pads.

Here, each of the first pads may be formed of a test area used for the operation test and a bonding area used for the wire bonding.

In addition, each of the first pads may be formed such that the width of the test area and the bonding area is substantially coincident with each other to form a rectangular pad, and the width of the bonding area is substantially equal to the width of the test area. The connection portion between the bonding region and the test region may be any one pad selected from stepped pads narrower than the width of the bonding region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Since the descriptions in the following embodiments are merely illustrated and limited by way of example and without intention other than the intention of a person having ordinary knowledge in the art to which the present invention pertains more thorough understanding of the present invention, It should not be used to limit the scope.

3 is a schematic diagram illustrating a pad arrangement structure in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3, pads PD311, PD312, PD313, and PD314 and pad pitches PAD_PIT1 and PAD_PIT2 are illustrated.

Taking a semiconductor memory device as an example, among the semiconductor devices, the pads formed in the pad region in the semiconductor memory device enable electrical connection between the semiconductor memory device and the outside of the semiconductor memory device. Signals related to command input, data read, and data write operations are input into the semiconductor memory device or output to the outside of the semiconductor memory device through the pads. The command input, data read, and data write operations may be performed in a packaged state, and may be performed by test equipment (eg, probing equipment) for testing the operation of the semiconductor memory device before a package process. May be performed.

An arrangement structure of pads formed on the semiconductor device for use in operation testing or wire bonding of the semiconductor device according to an embodiment of the present invention may be applied to the size of one or more pads PD311 and PD313 to be wire bonded on the semiconductor device. In comparison, the size of one or more pads PD312 and PD314, which will not be wire bonded, is large.

Here, one or more pads PD311 and PD313 to be wire bonded on the semiconductor device are also used for the operation test of the semiconductor device. That is, the one or more pads PD311 and PD313 to be wire-bonded include test areas 301 and 305 used in the operation test and bonding areas 302 and 306 used in the wire bonding.

The test regions 301 and 305 are regions in contact with and electrically connected to the probe tips of the probe card during the operation test of the semiconductor device. That is, the probe tip of the probe card is contacted with the test areas 301 and 305 to test whether the operation of the semiconductor device is good or bad. Therefore, after the operation test, probe marks 311 and 315 are generated on the test areas 301 and 305.

The bonding regions 302 and 306 are regions in which wires for electrical connection with the outside of the semiconductor device are bonded during a packaging process.

Although the test areas 301 and 305 and the bonding areas 302 and 306 are distinguished from each other by dotted lines in FIG. 3, the test areas 301 and 305 may not be clearly distinguished in consideration of the number of operation tests or contact positions of the probe tips. have. In the package process, the probe marks 311 and 315 are preferably bonded to each other during wire bonding. Otherwise, the adhesion between the pad and the bonding wire is weak, which is a major cause of the package yield degradation.

One or more pads PD312 and PD314 not to be wire-bonded are electrically connected in contact with the probe tip of the probe card during the operation test. That is, the probe tip of the probe card is contacted to the pads PD312 and PD314 to test whether the semiconductor device is in good or bad condition. Therefore, the probe marks 313 and 317 are generated on the pads PD312 and PD314 after the operation test.

The pads PD311, PD312, PD313, and PD314 may have one or more pads PD311 and PD313 to be wire-bonded with one or more pads PD312 and PD314 not to be wire-bonded in one row or one. Can be arranged in rows. That is, the pad arrangement structure of the pads PD311 and PD313 and the pads PD312 and PD314 may be alternately arranged one by one (as shown in FIG. 3). It may also have a structure arranged in the order of the pad to be bonded, the pad to be bonded, the pad to be bonded, and the pad to be bonded. It may also be in the order of pads not to be bonded, pads to be bonded, pads not to be bonded and pads to be bonded, or pads to be bonded, pads not to be bonded and pads to be bonded. . The arrangement order is just a few examples of the arrangement in the pad region of the semiconductor device.

The pad pitches PAD_PIT1 and PAD_PIT2 are spaces between the pads and the pads (the distance from the top of the pad PD311 to the top of the pad PD311 or from the top of the pad PD311 to the top of the pad PD313 in FIG. 3). Means.

The semiconductor device having the pads PD311, PD313, PD312, and PD314 may have one or more pads PD311 and PD313 to be wire bonded on the semiconductor device, that is, a first pad and a smaller size than the first pad. One or more pads PD312 and PD314 that are not to be used for the wire bonding are provided, that is, second pads.

Here, the first pad and the second pad may be mixed and arranged in one row or one column.

In addition, the second pad is in electrical contact with the probe tip of the probe card during the operation test.

The first pad may include a test area used for the operation test and a bonding area used for the wire bonding. If the pad PD311 of the first pad and the pad PD312 of the second pad are described as an example, the pad PD311 may include a test area 301 and a bonding area 302. In the test area 301, after an operation test, a probe mark, which is a recessed portion of the probe tip of the probe card, is generated.

The size of the pad PD312 may be substantially the same as the size of the test area.

Here, although the side surface area of the pad PD313 is between the pad pitch PAD_PIT2, that is, between the pad PD311 and the pad PD313, a pad is formed according to an embodiment of the present invention. No pads are formed. That is, the pad pitch PAD_PIT2 may have been substantially the same as the pad pitch PAD_PIT1 according to the conventional pad arrangement structure. However, in the pad arrangement structure according to the exemplary embodiment of the present invention, the spacing is shown in FIG. 3. Widened. Therefore, peripheral circuits (eg, buffers, MOS transistors, capacitors, delay elements, etc.) necessary for the operation of the semiconductor device may be further formed in the region where the pad is not formed. Thus, the pad area and the peripheral circuit area in the semiconductor device are reduced, which is advantageous in the integration of the semiconductor device.

4 is a schematic view illustrating a pad arrangement structure in a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 4, pads PD411, PD412, PD413, PD414 and pad pitch PAD_PIT3, PAD_PIT4, PAD_PIT5 are shown.

According to another exemplary embodiment, a pad arrangement structure of a semiconductor device includes a first pad PD411 and PD413 to be wire bonded and a second pad PD312 and PD414 not to be wire bonded.

The first pads PD411 and PD414 are divided into a line pad PD411 and a step pad PD413. Each of the first pads PD411 and PD414 has test areas 401 and 405 and bonding areas 402 and 406. In the test areas 401 and 405, after the operation test of the semiconductor device, a probe mark, which is a portion where the probe tip of the probe card is contacted and recessed, is generated.

The line pad PD411 is a pad in which the widths of the test area and the bonding area are substantially coincident with each other to form a rectangular shape in cross section.

The stepped pad PD413 has a width in which the bonding area 406 substantially matches the width of the test area 405, and the width MW of a connection portion between the bonding area 406 and the test area 405. This pad is narrower than the width of the bonding region 406. That is, the cross section is similar to the step shape. In the stepped pad PD413, a connection portion between the bonding region 406 and the test region 405 is sufficient if the width MW is greater than or equal to a minimum width allowed by a design rule. .

Although not shown in FIG. 4, the first pad may be any one selected from the line pad and the stepped pad.

The pad pitches PAD_PIT3, PAD_PIT4, and PAD_PIT5 are intervals between pads. In particular, the pad pitch PAD_PIT4 is wider than the pad pitch PAD_PIT3 which can be seen as a conventional pad pitch. In particular, the pad pitch PAD_PIT5 is widened by the formation of the stepped pad PAD413. Therefore, peripheral circuits (eg, buffers, MOS transistors, capacitors, delay elements, etc.) necessary for the operation of the semiconductor device may be further formed in regions where the pad is not formed. Thus, the pad area and the peripheral circuit area in the semiconductor device are reduced, which is advantageous in the integration of the semiconductor device.

3 and 4, a method of arranging pads formed on the semiconductor device for use in operation testing or wire bonding of the semiconductor device is as follows.

According to at least one example embodiment of the inventive concepts, a method of arranging pads in a semiconductor device may include disposing first pads PD411 and PD413 in FIG. 4, and second pads PD412 and PD414 between the first pads. It includes the step of.

The first pads PD411 and PD413 are pads to be used for both the operation test and the wire bonding of the semiconductor device, and are disposed in one row or one column.

The second pads PD412 and PD414 are not used for wire bonding of the semiconductor device and are smaller in size than the first pads.

Here, each of the first pads PD411 and PD413 is formed of test areas 401 and 405 used in the operation test and bonding areas 402 and 406 used in the wire bonding.

In addition, the first pad may include a line pad PD411 having a width of the test area 401 and the bonding area 402 to form a rectangular shape, and a width of the bonding area 406. The stepped pad PD413 has a width substantially corresponding to the width of the test region 405 and the width MW of the connection portion between the bonding region 406 and the test region 405 is narrower than the width of the bonding region. It may be either pad.

5 is a schematic view illustrating a semiconductor device having a pad arrangement structure according to FIG. 3. It is a figure for demonstrating especially a semiconductor memory device among semiconductor devices as an example.

Referring to FIG. 5, the semiconductor memory device 500 includes a memory cell array 515 and pad groups 511, 512, 513, and 514 formed in a pad area among peripheral regions of the memory cell array 515. It is.

The memory cell array 515 may further include a plurality of sub memory cell arrays. In addition, a center pad region may be further provided between the sub memory cell arrays so that the pad groups may be formed in the center pad region. That is, not only an edge pad method in which pads are formed at an edge portion of a memory cell array of the semiconductor memory device but also a center pad method in which pads are formed between a plurality of sub memory cell arrays according to an embodiment of the present invention. The pad arrangement structure is applied.

For example, referring to one pad group 711, the pad group 711 may be pads PD501, PD503,..., PDn-2, PDn to be wire bonded and pads PD502 not to be bonded. PDn-1). As described with reference to FIG. 3 or 4, the first pad, which is the pad to be bonded, is a pad used for both an operation test and wire bonding, and the second pad, which is a pad that is not to be bonded, is not used for bonding. It is a pad used for operation test without.

Since the semiconductor memory device has the pad arrangement structure as described above, peripheral circuits (for example, buffers, MOS transistors, capacitors, delay elements, etc.) necessary for the operation of the semiconductor memory device are further formed in regions where the pads are not formed. Can be. Thus, the pad area and the peripheral circuit area in the semiconductor device are reduced, which is advantageous in the integration of the semiconductor device.

As described above, the pad arrangement structure according to the embodiment of the present invention may be applied to a semiconductor memory device, and further, a semiconductor including pads such as a central processing unit (CPU), a microprocessor, a CD, and an LCD driving device is formed. It can be variously applied to the device.

As described above, the present invention provides an improved pad arrangement structure and a method of arranging a semiconductor memory device, whereby a peripheral circuit can be further formed in a pad-formed area by increasing a pad pitch within a limited area. It is effective to realize high integration of

In addition, the present invention provides a pad arrangement structure and a pad arrangement method of a semiconductor memory device in which a pad used for an operation test and a wire bonding is different from a pad used for an operation test and wire bonding. There is an effect that can reduce the pad area to be formed.

In addition, the present invention provides a pad arrangement structure and a pad arrangement method of a semiconductor memory device having pads used for operation testing and wire bonding, which are formed in various forms, thereby reducing the pad area on which the pads are to be formed, thereby reducing the semiconductor memory. It can contribute to the high integration of the device.

delete

Claims (19)

In the arrangement structure of a pad formed on the semiconductor device for use in operation test or wire bonding of the semiconductor device: The size of the at least one pad that is not to be wire bonded is formed to be smaller than the size of the at least one pad to be wire bonded on the semiconductor device, At least one pad not to be wire bonded is contacted with a probe tip of a probe card during the operation test, and at least one pad to be wire bonded has a test area used for the operation test and a bonding area used for wire bonding. The pad arrangement structure in the semiconductor device characterized by the above-mentioned. delete delete delete The method of claim 1, And the test area is an area that is electrically connected to the probe tip of the probe card during the operation test. The method of claim 5, The bonding area is a pad arrangement structure, characterized in that the wire bonding area for the electrical connection to the outside of the semiconductor device during the packaging process. A semiconductor device in which pads are formed for use in operational testing or wire bonding: One or more first pads used for both the operation test and the wire bonding of the semiconductor device, the test pads used in the operation test and a bonding area used for the wire bonding; And And at least one second pad that is smaller in size than the first pad and is not used for the wire bonding, and which is to be contacted with the probe tip of the probe card during the operation test. delete delete delete The method of claim 7, wherein And the size of the second pad is substantially the same as the size of the test region. The method of claim 7, wherein And the test area is an area that is electrically connected to the probe tip of the probe card during the operation test. The method of claim 12, The bonding region is a semiconductor device, characterized in that for bonding the wire for bonding the semiconductor device to the outside of the semiconductor device during the packaging process. The method of claim 13, And the first pad is a line-shaped pad having a width substantially equal to that of the test region and the bonding region to form a rectangular shape. The method of claim 13, And the first pad is a stepped pad having a width substantially equal to that of the test region, and wherein a connection portion between the bonding region and the test region is narrower than the width of the bonding region. The method of claim 13, The first pad may include a line-shaped pad having a width substantially equal to the width of the test area and the bonding area to form a rectangular shape, and a width of the bonding area substantially coinciding with a width of the test area. And the connection portion of the test region is any one pad selected from stepped pads narrower than the width of the bonding region. A method of arranging pads formed on a semiconductor device for use in operation testing or wire bonding of a semiconductor device, the method comprising: One row or one column is used for both the operation test and the wire bonding of the semiconductor device, and each of the plurality of first pads is formed by a test area used for the operation test and a bonding area used for the wire bonding. step; And Disposing second pads between the first pads that are not used for wire bonding of the semiconductor device and smaller in size than the first pads. delete The method of claim 17, Each of the first pads may have a line-shaped pad having a width substantially equal to that of the test area and the bonding area to form a rectangular shape, and a width of the bonding area may substantially match the width of the test area. And a connecting portion of the test region and the test region is any one pad selected from stepped pads narrower than the width of the bonding region.

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