KR100652411B1 - Semiconductor memory device maximizing bonding pad - Google Patents

Abstract

The present invention relates to a semiconductor memory device capable of maximizing the number of pads while maintaining a center pad shape by improving a method of arranging pads on a semiconductor chip. The semiconductor memory device according to the present invention is formed on a semiconductor chip. And bonding pads electrically connected to the outside of the semiconductor chip to input and output data signals, control signals, and the like, wherein the bonding pads are positioned in a center area on the semiconductor chip and define a center area of the semiconductor chip. A first pad column including one or more bonding pads formed in a row direction, the first pad row being positioned in a center area on the semiconductor chip, and formed in a column direction along a center area of the semiconductor chip to be substantially perpendicular to the first pad row A second pad array including one or more bonding pads and an edge region on the semiconductor chip; And a third pad column including one or more bonding pads formed in a row direction and a column direction along an edge area of the semiconductor chip, and a pad and a data input / output signal for transmitting a control signal such as an address and a command. The pad for transferring is provided in different pad rows among the first to third pad rows.

Description

Semiconductor memory device maximizing bonding pad

1 is a diagram illustrating an example of a pad arrangement of a conventional semiconductor memory device.

2 is a diagram illustrating another example of a pad arrangement of a conventional semiconductor device.

3 is a view briefly illustrating an example of a bonding pad arrangement state in a semiconductor memory device according to the present invention.

4 is a diagram illustrating a package applied to a semiconductor memory device of the present invention and a connection state between the package and the bonding pad.

FIG. 5 is a diagram illustrating the semiconductor memory device shown in FIG. 4.

Explanation of symbols on the main parts of the drawings

20: semiconductor chip 21: first pad array

22: second pad row 23: third pad row

24: solder ball 30: the first PCB

40: second PCB 50: stripe

The present invention relates to a semiconductor memory device that maximizes the number of bonding pads. More particularly, the present invention relates to a method of arranging the bonding pads formed on a semiconductor chip, thereby maintaining the center pad shape. A semiconductor memory device that can be maximized.

BACKGROUND ART In general, a semiconductor memory device, for example, a DRAM (Dynamic Random Access Memory), has a rapidly decreasing chip size, but is becoming more rapidly and complicated in terms of functionality. In particular, the number of input / output pins is increased to increase the operation speed of the DRAM or to rapidly input / output data. That is, in the semiconductor memory device having the same clock frequency, the larger the number of the input / output pins, the higher the data bit input / output per same time, thereby increasing the operation speed.

Typically, bonding pads are disposed on the peripheral area of the semiconductor chip forming the semiconductor memory device to enable electrical connection with the outside of the chip. Signals related to an address, a command input, a data read and a data write operation may be input into the chip or may be output to the outside of the chip through the bonding pads.

On the other hand, as described above, when the number of input / output pins increases in order to improve the operation speed of the semiconductor memory device, the number of bonding pads to connect thereto increases, and the number of the bonding pads is usually twice the increase of the input / output pins. To three times as much.

This is because the number of input / output driving power pins for driving the input / output should increase, and the number of internal power pins may increase as necessary.

1 is a schematic diagram illustrating an example of a bonding pad arrangement of a conventional semiconductor memory device. In the conventional semiconductor memory device, when the bonding pads 11 are disposed on the semiconductor chip 10 along the center area of the chip, the semiconductor memory device is generally disposed in a shape as shown in FIG. 1. . In the case where the bonding pads 11 are arranged in the form of a center pad as shown in FIG. 1, the operation characteristics of the product may be excellent since the control circuits are collected in the center area inside the semiconductor chip. However, since the number of bonding pads 11 that may be disposed in the center area of the semiconductor chip 10 is limited, there is a limit in increasing the number of the bonding pads 11.

2 is a diagram showing another example of a pad arrangement of a conventional semiconductor device. In the conventional semiconductor memory device, when the bonding pads 11 formed on the semiconductor chip 10 are edge pads disposed along an edge area of the chip, the shape as shown in FIG. It is usually arranged as In the case where the bonding pads 11 are disposed along the edge area of the semiconductor chip 10 as shown in FIG. 2, when the bonding pads 11 are arranged in the center pad form as shown in FIG. 1. In comparison, a larger number of bonding pads 11 may be disposed. However, since the bonding pads 11 are disposed along the edge region of the semiconductor chip 10, there are disadvantages in that arrangement and connection of control circuits are difficult, and operation characteristics are also inferior to that of the center pad.

As semiconductor memory products become more dense and highly integrated as technology advances, the size of semiconductor chips becomes smaller at the same capacity. In addition, signals related to address, command input, data read, and data write operations may be physically connected to each other by bonding the bonding pads and pins in order to be input into or out of the semiconductor chip.

However, as the size of the semiconductor chip gradually decreases, it is difficult to reduce the size of the bonding pad because the bonding pad must be physically connected to the pin. As described above, when the bonding pads disposed in the semiconductor memory device are formed according to a conventional arrangement method, the number of the bonding pads cannot be appropriately increased in response to the increase in the number of pins, thereby facilitating the semiconductor package. There is a problem that cannot be designed.

On the other hand, when driving the semiconductor memory device at a high frequency, when the number of the bonding pads increases, there is a problem that the device characteristics are deteriorated under the influence of inter-channel interference and power noise. That is, due to the influence of different kinds of power noise interference, for example, noise transfer between input / output driving power and internal power for driving data input / output, or interference between data input / output signals and address / command signals The characteristics of the semiconductor memory device are greatly reduced.

For example, in the test mode of the semiconductor memory device, a characteristic difference between a simple pattern (a pattern that causes a small noise inside a semiconductor chip) and a noise pattern (a pattern that causes a large noise inside a semiconductor chip) may be determined. In comparison, about 30% or more of the characteristic degradation occurs in the noise pattern compared to the simple pattern.

That is, when the bonding pads disposed in the semiconductor memory device are conventionally arranged, not only the problem caused by the limited number of bonding pads that can be disposed on the semiconductor chip, but also when the semiconductor memory device is driven at a high frequency. There is a problem due to deterioration of device characteristics due to inter-channel interference and power noise.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and improves the problem of limiting the number of bonding pads that can be disposed by improving the arrangement of the bonding pads disposed on the semiconductor chip of the semiconductor memory device. An object of the present invention is to provide a semiconductor memory device capable of improving the problem of deterioration caused by power noise.

In order to achieve the above object, in the semiconductor memory device according to the first embodiment of the present invention, bonding pads electrically connected to the outside of the semiconductor chip to input and output data signals, control signals, and the like are formed on the semiconductor chip. And first bonding pads formed at a center area on the semiconductor chip, the first pad row including at least one bonding pad formed in a row direction along the semiconductor chip, and at the center area on the semiconductor chip. And a second pad row including one or more bonding pads formed in a column direction along the semiconductor chip to be substantially perpendicular to the first pad row, and positioned at an edge region of the semiconductor chip, wherein the edge region of the semiconductor chip is formed. And a third pad row including one or more bonding pads respectively formed in the row direction and the column direction, and Bus and the pad for transmitting a data pad and the input and output signals for transmitting a control signal of a command, such as is characterized by being provided with the first to third columns of each pad column, the other pad.

Preferably, the first pad column may have a structure including a plurality of rows in which the bonding pads are formed to be substantially parallel to each other.

Also preferably, the second pad row may have a structure including a plurality of rows in which the bonding pads are formed to be substantially parallel to each other.

The semiconductor memory device according to the second embodiment of the present invention may include bonding pads formed on a semiconductor chip and electrically connected to the outside of the semiconductor chip to input and output data signals and control signals. Bond pads are positioned in a center region on the semiconductor chip, and include a first pad column including at least one bonding pad formed in a row direction along a center region of the semiconductor chip, and located in a center region on the semiconductor chip. A second pad row including one or more bonding pads formed in a column direction along a center area of the semiconductor chip and substantially perpendicular to the first pad row, and positioned in an edge area on the semiconductor chip, the edge area of the semiconductor chip A third pad row including one or more bonding pads respectively formed in a row direction and a column direction along The package applied to the conductor chip may be disposed on one surface of the package connected to the first pad row and the second pad row, the third pad row, and the semiconductor chip, and connected to the first pad row and the second pad row. And a first PCB electrically connecting the semiconductor chip and the outside and a second PCB positioned on the other surface of the semiconductor chip and connected to the third pad row to electrically connect the semiconductor chip and the outside. do.

Preferably, the package type connected to the first pad row and the second pad row may apply a BOC (Ball on Circuit) type package.

Also preferably, the package type connected to the third pad row may include a package of a ball grid array (BGA) type.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that illustrate preferred embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a diagram briefly illustrating an example of a bonding pad arrangement state in the semiconductor memory device according to the present invention.

As shown in FIG. 3, on the semiconductor chip 20 included in the semiconductor memory device according to the present invention, bonding is performed to be electrically connected to the outside of the semiconductor chip 20 to input and output data signals, control signals, and the like. Pads 21 to 23 are formed.

The bonding pads 21 to 23 may be formed in the first pad row 21 and the second pad row 22 positioned in the center area of the semiconductor chip 20, and in the edge area of the semiconductor chip 20. The third pad row 23 is positioned.

The first pad column 21 includes one or more bonding pads formed in a row direction along the center area of the semiconductor chip 20. In addition, the second pad row 22 may include one or more bonding pads formed along a center area of the semiconductor chip 20 in a column direction.

In addition, preferably, the first pad row 21 has a structure in which a plurality of rows of the bonding pads are formed substantially parallel to each other, and the second pad row 22 is substantially parallel to the bonding pads. It is possible to have a structure consisting of a plurality of rows formed. In particular, in FIG. 3, the plurality of rows and the plurality of columns each include two rows and two columns. As such, the bonding pads may include a plurality of rows and a plurality of columns, thereby increasing the number of bonding pads 21 and 22 formed on the semiconductor chip 20 in the form of a center pad.

In the semiconductor memory device according to the present invention, a third pad row 23 is further formed on the semiconductor chip 20. In particular, the third pad row 23 is positioned at an edge region of the semiconductor chip 20, and includes one or more bonding pads respectively formed in a row direction and a column direction along an edge region of the semiconductor chip 20. Is done. Accordingly, since the bonding pads 21 to 23 are simultaneously formed in the form of a center pad and an edge pad on the semiconductor chip 20, a larger number of bonding pads are formed on the semiconductor chip 20 having the same area. can do.

Signals related to an address, a command input, a data read, and a data write operation may be input into the chip or may be output to the outside of the chip through the bonding pads of the semiconductor memory device formed as described above. The solder ball 24, which is not described in FIG. 3, is connected to the bonding pads so that the above-described signals are input into the chip or output to the outside of the chip.

In terms of characteristics of the semiconductor memory device, the address signal, the command input signal, and the like may be formed on the semiconductor chip 20 by forming a first pad row 21 and a second pad row 22. It is preferable to input and output to the outside of the semiconductor chip 20 through the (). In this case, control circuits for inputting and outputting the address signal, the command input signal, and the like may be collected in the center area of the semiconductor chip 20, thereby maintaining excellent operation characteristics of the semiconductor memory device.

In contrast, the signal related to the data input / output may be input / output to the outside of the semiconductor chip 20 through the third pad array 23 formed in the form of an edge pad on the semiconductor chip 20. . In the case described above, the semiconductor memory device is externally inputted and outputted through bonding pads disposed in different regions between input / output driving power and internal power for driving data input / output, and data input / output signals and address / command signals. Lose. Therefore, it is possible to prevent the deterioration of the characteristics of the device by minimizing the occurrence of different kinds of power noise interference or interference between the data input / output signal and the address / command signal.

Meanwhile, as described above, the semiconductor chip in which the bonding pad is formed may be combined with various types of packages, which will be described below.

4 is a diagram illustrating a package applied to a semiconductor memory device of the present invention and a connection state between the package and the bonding pad.

As illustrated in FIG. 4, a semiconductor memory device according to another embodiment of the present invention may include a semiconductor chip 20, a first PCB 30 located on one surface of the semiconductor chip 20, and the semiconductor chip 20. It includes a second PCB 40, a stripe (50) for coupling the semiconductor chip 20 and the second PCB 40 located on the other side of the.

Bonding pads 21 to 23 are formed on the semiconductor chip 20 to input and output data signals and control signals to and from the outside, and the bonding pads 21 to 23 may be formed as described above. The first pad row 21 and the second pad row 22 positioned in the center area on the semiconductor chip 20 and the third pad row 23 located in the edge area on the semiconductor chip 20. It is desirable to.

The first pad column 21 and the second pad column 22 may each include one or more bonding pads formed in a row direction and a column direction along the semiconductor chip 20, and may include a plurality of rows or It is desirable to have a structure consisting of a plurality of rows.

In addition, the third pad row 23 may be disposed in an edge region of the semiconductor chip 20, and may include one or more bonding pads respectively formed in a row direction and a column direction along an edge region of the semiconductor chip 20. It is made to include.

The package applied to the semiconductor chip 20 may include a package connected to the first pad row 21 and a second pad row 22 and a package connected to the third pad row 23. It may be configured to be located on different surfaces of the semiconductor chip 20, respectively. In FIG. 4, a package connected to the first pad row 21 and the second pad row 22 is a solder ball 24a attached to one surface of the first PCB 30 and the first PCB 30. It is made, including. In addition, the package connected to the third pad row 23 may include a second PCB 40 and solder balls 24b attached to one surface of the second PCB 40.

In the bonding pads 21 to 23, the first pad row 21 and the second pad row 22 may include a first PCB 30 and a first PCB located on one surface of the semiconductor chip 20. 30 is connected to the solder ball 24a attached to the wire through a wire bondig. In addition, the third pad row 23 may be wire bonded with a second PCB 40 located on the other surface of the semiconductor chip 20 and a solder ball 24b attached to the second PCB 40. ) Is connected.

In general, when bonding pads are formed in a center pad shape on a semiconductor chip, a BOC (Board On Chip) type package is suitable for applying the package to the semiconductor chip, and when the bonding pads are formed in an edge pad shape, A ball grid array (BGA) type package is more suitable than a board on chip (BOC) type package. Accordingly, in the bonding pad arrangement state of the semiconductor memory device of the present invention, the package form connected to the first pad row 21 and the second pad row 22 formed in the center pad form is the board on chip (BOC). It is desirable to apply a package of forms. In addition, as the package type connected to the third pad row 23, it is preferable to apply the BGA type package. The ball grid array (BGA) type package may be positioned on different surfaces on the board on chip (BOC) type package and the semiconductor chip 20.

According to the characteristics of the present invention, the bonding pads on the semiconductor chip having the shape of the center pad and the edge pad are simultaneously applied to both surfaces of the semiconductor chip as described above. Even when the pads are formed, the package can be effectively applied.

FIG. 5 is a diagram illustrating the semiconductor memory device shown in FIG. 4. As shown in FIG. 5, the semiconductor memory device 60 after the package is applied to the semiconductor chip, and solder balls are formed on both surfaces of the semiconductor memory device 60. Of the solder balls, the solder balls 24a formed in the center area of one surface of the semiconductor memory device 60 represent solder balls in a package of a board on chip (BOC) type, and the solder balls 24a of the other surface of the semiconductor memory device 60 are formed. The solder ball 24b formed in the edge region represents a solder ball in a package in the form of a ball grid array (BGA).

As described above, with respect to the bonding pads formed in the semiconductor chip, an address signal and a command input signal are input and output through the bonding pads formed in the form of a center pad, and in the form of an edge pad. Input and output data signals and the like through bonding pads formed, and packages are applied to both sides of the semiconductor chip. Accordingly, in the semiconductor memory device, it is possible to prevent the characteristics of the device from significantly deteriorating due to different kinds of power noise interference or interference between the data input / output signal and the address / command signal.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention as described above, by improving the method of arranging the pads on the semiconductor chip, the number of pads can be maximized while maintaining the center pad shape, and the operation characteristics of the semiconductor memory device even when operating at high frequency. There is an effect which can prevent this fall.

Claims (9)

Bonding pads formed on a semiconductor chip and electrically connected to the outside of the semiconductor chip to input and output data signals and control signals,  The bonding pads may include: a first pad column disposed in a center area on the semiconductor chip and including one or more bonding pads formed in a row direction along the center area of the semiconductor chip; A second pad row disposed in a center area on the semiconductor chip, the second pad row including one or more bonding pads formed in a column direction along a center area of the semiconductor chip and substantially perpendicular to the first pad row; And A third pad row disposed on an edge region of the semiconductor chip, the third pad array including one or more bonding pads respectively formed in a row direction and a column direction along an edge region of the semiconductor chip; And a pad for transmitting a control signal such as an address and a command and a pad for transmitting a data input / output signal are provided in different pad columns among the first to third pad rows. The method of claim 1, wherein the first pad row, And a plurality of rows of the bonding pads formed substantially parallel to each other. The method of claim 1, wherein the second pad row, And a plurality of rows of the bonding pads formed in substantially parallel to each other. Bonding pads formed on a semiconductor chip and electrically connected to the outside of the semiconductor chip to input and output data signals and control signals, The bonding pads may include: a first pad column disposed in a center area on the semiconductor chip and including one or more bonding pads formed in a row direction along the center area of the semiconductor chip; A second pad row disposed in a center area on the semiconductor chip, the second pad row including one or more bonding pads formed in a column direction along a center area of the semiconductor chip and substantially perpendicular to the first pad row; A third pad row positioned in an edge region of the semiconductor chip, the third pad array including one or more bonding pads formed in row and column directions along the edge region of the semiconductor chip; A first PCB positioned on one surface of the semiconductor chip and electrically connected to the first pad row and the second pad row to electrically connect the semiconductor chip to the outside; And And a second PCB positioned on the other surface of the semiconductor chip and electrically connected to the third pad row to electrically connect the semiconductor chip to the outside. delete delete The method of claim 4, wherein The package type connected to the first pad row and the second pad row is a package of a board on chip (BOC) type. The method of claim 7, wherein The package type connected to the third pad row is a package of a ball grid array (BGA) type. The method of claim 4, wherein And a pad for transmitting a control signal such as an address and a command and a pad for transmitting a data input / output signal are provided in different pad columns among the first to third pad rows.

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