JP6268990B2 - Semiconductor device, semiconductor device manufacturing method, substrate, and substrate manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor device, a semiconductor device manufacturing method, a substrate, and a substrate manufacturing method.

  A technique for providing a TSV (Through Silicon Via) on a semiconductor chip is known. A three-dimensional stacking technique is known in which another semiconductor chip is three-dimensionally arranged on a semiconductor chip provided with a TSV, and these semiconductor chips are electrically connected using the TSV.

JP 2008-258306 A JP 2013-168503 A

  In the three-dimensional stacking technology of semiconductor chips using the TSV as described above, semiconductor chips of different types and different positions of connection terminals are difficult to arrange three-dimensionally and be electrically connected. There may be restrictions on combinations of semiconductor chips that can be dimensioned.

According to one aspect of the present invention, a resin layer, a semiconductor chip embedded in the resin layer, a cylindrical insulator embedded in the resin layer and having one through-hole, and disposed in the through-hole. A semiconductor device and a substrate including the provided columnar conductor are provided.

According to another aspect of the present invention, a step of disposing a columnar insulator and a semiconductor chip on a support, and a resin layer in which the insulator and the semiconductor chip are embedded on the support. forming, on said insulator of said resin layer to form one through hole, a step of the insulating body in a cylindrical shape, in the through hole, and forming a columnar conductor A semiconductor device and a substrate manufacturing method are provided.

  According to the disclosed technology, a cylindrical insulator and a conductor provided in the through-hole are embedded in the resin layer together with the semiconductor chip, and the conductor provides a three-dimensional connection with another semiconductor chip. A semiconductor device capable of proper arrangement and electrical connection is realized. Thereby, various semiconductor chips can be arranged three-dimensionally and electrically connected.

It is a figure showing an example of a semiconductor device. It is a figure which shows an example of the laminated structure of a semiconductor device. It is explanatory drawing of the 1st formation process of a semiconductor device. It is explanatory drawing of the 2nd formation process of a semiconductor device. It is a figure showing an example of temporary fixation of a semiconductor chip. It is explanatory drawing of the 3rd formation process of a semiconductor device. It is explanatory drawing of the 4th formation process of a semiconductor device. It is explanatory drawing of the 5th formation process of a semiconductor device. It is a figure which shows an example of a pseudo SoC board | substrate. It is a figure which shows an example of the flow until a laminated structure is obtained from a pseudo SoC substrate. It is a figure which shows the example of mounting of a laminated structure. It is a figure (the 1) which shows another example of a laminated structure. It is a figure (the 2) which shows another example of a laminated structure. It is FIG. (1) which shows another example of the method of obtaining a laminated structure. It is FIG. (2) which shows another example of the method of obtaining a laminated structure. It is FIG. (The 3) which shows another example of a laminated structure. It is FIG. (4) which shows another example of a laminated structure.

FIG. 1 illustrates an example of a semiconductor device. Note that FIG. 1 schematically shows a cross-section of an essential part of an example of a semiconductor device.
A semiconductor device 10 shown in FIG. 1 includes a resin layer 11, a semiconductor chip 12, an insulator 13, a conductor (via) 14, and a wiring layer (rewiring layer) 15.

  A resin material is used for the resin layer 11. As a resin material used for the resin layer 11, an insulating resin material such as an epoxy resin can be used. The resin material used for the resin layer 11 contains, for example, an insulating filler such as silica.

  A semiconductor chip 12 is embedded in the resin layer 11. Here, as the semiconductor chip 12 embedded in the resin layer 11, two semiconductor chips 12a and 12b are illustrated in a cross-sectional view. The semiconductor chip 12 a and the semiconductor chip 12 b are embedded in the resin layer 11 such that the terminals 12 aa and terminals 12 ba are exposed from the surface 11 a of the resin layer 11.

  Here, the structure in which the surface opposite to the arrangement surface of the terminals 12aa and 12ba of the semiconductor chip 12a and the semiconductor chip 12b is covered with the resin layer 11 is illustrated. In addition, the semiconductor chip 12a and the semiconductor chip 12b have a structure in which the surface opposite to the arrangement surface of the terminal 12aa and the terminal 12ba is exposed from the resin layer 11 (the resin layer 11 is formed with such a thickness that these surfaces are exposed). Can also be formed).

  The semiconductor chip 12a and the semiconductor chip 12b may be of the same type (size, function) or different types. The semiconductor chip 12a and the semiconductor chip 12b are a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, a sensor chip, a memory chip, and the like.

  The insulator 13 and the via 14 are embedded in the resin layer 11 together with the semiconductor chip 12a and the semiconductor chip 12b. The insulator 13 and the via 14 are embedded in the resin layer 11 so as to penetrate the resin layer 11. A columnar via 14 is provided so as to penetrate the resin layer 11, and the insulator 13 covers a side surface of the via 14. In other words, the semiconductor device 10 has a structure in which a columnar via 14 is provided inside a cylindrical insulator 13 provided in the resin layer 11 and having a through hole 13b.

  A resin material is used for the insulator 13. As a resin material used for the insulator 13, for example, a silicone resin having a siloxane skeleton or a thermosetting resin can be used. Examples of such a resin material include organic SOG (Spin On Glass) formed by a sol-gel method, thermosetting silicone resin, phenol resin, epoxy resin, polyimide resin, and maleimide resin.

Various conductive materials can be used for the via 14. As the conductive material used for the via 14, various conductive materials such as copper (Cu) or a material containing copper can be used, for example.
The redistribution layer 15 is on the resin layer 11 in which the semiconductor chip 12a and the semiconductor chip 12b, and the insulator 13 and the via 14 are embedded (on the side where the terminals 12aa and 12ba of the semiconductor chip 12a and the semiconductor chip 12b are disposed). Is provided. The rewiring layer 15 includes a conductive portion 15a (wiring 15aa, via 15ab, terminal 15ac) electrically connected to the semiconductor chip 12a and the semiconductor chip 12b and the via 14, and an insulating portion 15b provided around the conductive portion 15a. have. A conductive material such as copper or a material containing copper can be used for the conductive portion 15a. A resin material such as an epoxy resin or a polyimide resin can be used for the insulating portion 15b.

  Here, a case where the via 14 is electrically connected to the semiconductor chip 12a and the semiconductor chip 12b via the wiring 15aa and the via 15ab is illustrated, but the via 14 is electrically connected to both or either of the semiconductor chip 12a and the semiconductor chip 12b. In some cases.

  Although not shown here, the semiconductor device 10 includes a conductive portion 15a electrically connected to the via 14 on the surface of the resin layer 11 opposite to the surface on which the rewiring layer 15 is disposed. And the rewiring layer 15 which has the insulation part 15b which covers the circumference | surroundings can be provided.

The semiconductor device 10 having the above configuration can be stacked with another semiconductor device including a terminal that can be electrically connected to the via 14.
FIG. 2 is a diagram illustrating an example of a stacked structure of a semiconductor device. Note that FIG. 2 schematically shows a cross-section of an essential part of an example of the laminated structure.

  FIG. 2 illustrates a structure (laminated structure) 30 in which the semiconductor device 10 having the above configuration is stacked on another semiconductor device 20. Here, as an example of the semiconductor device 20, similarly to the semiconductor device 10, the semiconductor device 20 includes a resin layer 21, a semiconductor chip 22, an insulator 23, a conductor (via) 24, and a wiring layer (rewiring layer) 25. Show.

  In the semiconductor device 20, one semiconductor chip 22 having a different type (size, function) from the semiconductor chip 12 a and the semiconductor chip 12 b of the semiconductor device 10 is embedded in the resin layer 21 in a cross-sectional view, for example. The semiconductor chip 22 is a CPU chip, a GPU chip, a sensor chip, a memory chip, or the like.

In the semiconductor device 20, a cylindrical insulator 23 and a columnar via 24 inside thereof are embedded in the resin layer 21 so as to penetrate the resin layer 21.
In the semiconductor device 20, the rewiring layer 25 is provided on the resin layer 21 in which the semiconductor chip 22, the insulator 23, and the via 24 are embedded. The redistribution layer 25 includes a conductive portion 25a (wiring 25aa, via 25ab, terminal 25ac) electrically connected to the terminal 22a and the via 24 of the semiconductor chip 22, and an insulating portion 25b provided around the conductive portion 25a. Have.

  Here, a case where the via 24 is electrically connected to the semiconductor chip 22 via the wiring 25aa and the via 25ab is illustrated, but the via 24 may be electrically separated from the semiconductor chip 22.

  The resin layer 21, the insulator 23, the via 24, and the rewiring layer 25 of the semiconductor device 20 are the materials described above for the resin layer 11, the insulator 13, the via 14, and the rewiring layer 15 of the semiconductor device 10, respectively. Can be used.

  The terminal 25ac of the redistribution layer 25 electrically connected to the via 24 of the semiconductor device 20 is provided at a position corresponding to the via 14 of the stacked semiconductor device 10. In the stacked structure 30 of the semiconductor device 10 and the semiconductor device 20 illustrated in FIG. 2, the via 14 of the semiconductor device 10 is electrically connected to the terminal 25ac of the semiconductor device 20 via a bump 31 such as solder. Yes.

  As described above, the stacked structure 30 has a structure in which the semiconductor device 10 and the semiconductor device 20 including the semiconductor chip 12 and the semiconductor chip 22 of different types are three-dimensionally arranged and electrically connected. .

  By the way, as one method for electrically connecting a plurality of semiconductor chips arranged three-dimensionally, there is a method using TSV. In this method, a TSV penetrating a silicon substrate used for a semiconductor chip is formed, and the three-dimensionally arranged semiconductor chips are electrically connected using the TSV. However, when the types of semiconductor chips to be connected are different and the positions of the connection terminals are different, it may happen that the semiconductor chips cannot be arranged three-dimensionally. For this reason, when three-dimensionally arranging semiconductor chips having different connection terminal positions, an interposer provided with a conductive portion that can electrically connect the semiconductor chips is separately formed and interposed therebetween. It may be necessary to make it.

  On the other hand, in the laminated structure 30 using the semiconductor device 10 and the semiconductor device 20 as described above, the semiconductor chip 12 is embedded in the resin layer 11 to form the via 14 in the resin layer 11, and the semiconductor chip 22 is replaced with the resin layer. A via 24 is formed in the resin layer 21 by being embedded in the resin layer 21. Then, the semiconductor device 10 and the semiconductor device 20 to be stacked are electrically connected using the via 14 and the via 24. Therefore, even semiconductor chips that are of different types and cannot be simply stacked and electrically connected, such as the semiconductor chip 12 and the semiconductor chip 22, can be three-dimensionally arranged. In the laminated structure 30, it is not necessary to use an interposer when the semiconductor chip 12 and the semiconductor chip 22 are three-dimensionally arranged. By adopting a structure such as the laminated structure 30, the degree of freedom of the combination of the semiconductor chips 12 and 22 arranged three-dimensionally can be increased.

  Here, the stacked structure 30 of the two semiconductor devices 10 and the semiconductor device 20 is illustrated, but three or more semiconductor devices are stacked, that is, on the semiconductor device 10 of the stacked structure 30 or the semiconductor device 20. It is also possible to stack another semiconductor device (10, 20 etc.) below.

  Next, an example of a method for forming the semiconductor device 10 and the semiconductor device 20 as described above will be described with reference to FIGS. Here, the formation method will be described by taking the semiconductor device 10 as an example.

FIG. 3 is an explanatory diagram of the first formation process of the semiconductor device. FIG. 3 schematically shows a cross section of the main part of the first formation step of the semiconductor device.
First, as shown in FIG. 3A, an adhesive layer 42 for temporarily fixing the semiconductor chip 12 is formed on a support (carrier substrate) 41. Various substrates such as a metal substrate, a glass substrate, a printed substrate, a semiconductor substrate, and a ceramic substrate are used for the carrier substrate 41. For the adhesive layer 42, in addition to an adhesive film in which an adhesive is provided on a predetermined base material, a carrier substrate 41 coated with an adhesive by a spin coating method, a spray coating method, a printing method, or the like is used.

  In the adhesive layer 42, a pseudo wafer (substrate) 40 can be formed as described later, and then the pseudo wafer 40 can be peeled off. For example, the adhesive strength can be reduced by heating or ultraviolet irradiation at the time of peeling. What can be used is used. Moreover, you may use what can peel the pseudo wafer 40, without performing processes, such as a heating and ultraviolet irradiation.

  After the adhesive layer 42 is formed on the carrier substrate 41, the insulating coating 13a is formed on the adhesive layer 42 as shown in FIG. For the insulating coating 13a, a material as described for the insulator 13, for example, a silicone resin having a siloxane skeleton or a thermosetting resin is used.

  After such an insulating film 13a is formed, as shown in FIG. 3B, for example, a photoresist is coated on the insulating film 13a, and exposure and development are performed. A resist pattern 43 is formed to cover a region where the internal via 14 is provided. For example, a planar circular resist pattern 43 is formed in a region where the insulator 13 and the via 14 inside the insulator 13 are provided.

  After the resist pattern 43 is formed, as shown in FIG. 3C, the insulating film 13a is dry-etched until the adhesive layer 42 is exposed using the resist pattern 43 as a mask to form a columnar shape (in this example, a cylindrical shape). The insulator 13 (insulating coating 13a) is formed.

  The planar shape of the insulator 13 is not limited to a circle, and may be other planar shapes such as an ellipse and a rectangle. Based on the planar shape of the insulator 13 to be formed, the planar shape of the resist pattern 43 formed in the step of FIG. 3B is set.

Thus, when forming the insulator 13 by dry-etching the insulating coating 13a, it is preferable to perform etching using plasma. At this time, the plasma used for dry etching is not particularly limited as long as the insulating coating 13a can be etched. For example, for dry etching of the insulating coating 13a, one kind of gas among fluorine-based gas, oxygen (O ₂ ) gas, argon (Ar) gas, hydrogen (H ₂ ) gas, nitrogen (N ₂ ) gas, or A mixed gas containing a plurality of species can be used.

After the insulator 13 is formed by dry etching of the insulating coating 13a in this way, the resist pattern 43 is removed from the insulator 13.
Alternatively, the columnar insulator 13 can be formed by using a photosensitive resin material for the insulating coating 13a, exposing it using a predetermined mask, and developing it. The opening shape of the mask is set based on the planar shape of the insulator 13 to be formed.

  Thus, when forming the insulator 13 by exposing and developing the insulating coating 13a, the type of the resin material used for the insulating coating 13a is not particularly limited as long as it has photosensitivity. However, the material used for the insulating coating 13a is a pseudo SoC (System on (a) Chip) substrate 40A, which will be described later, and the inside of the semiconductor device 10 separated by dicing from the pseudo SoC substrate 40A. Remain in. The pseudo SoC substrate 40A and the semiconductor device 10 are heated at a temperature of about 200 ° C. when bonded to other components using bumps 31 such as solder. Therefore, when the insulating film 13a is exposed and developed to form the insulator 13, the insulating film 13a is made of a material having a certain heat resistance, such as an epoxy resin, a phenol resin, a polyimide resin, a maleimide resin, or the like. It is preferable to use a permanent resist material.

FIG. 4 is an explanatory diagram of a second step of forming a semiconductor device. FIG. 4 schematically shows a cross section of the main part of the second formation step of the semiconductor device.
After the formation of the insulator 13 as described above, as shown in FIG. 4 (A), the wafer is diced from the wafer using a chip bonder on the adhesive layer 42 on which the insulator 13 is formed. The separated semiconductor chip 12 is temporarily fixed (reconstructed). The semiconductor chip 12 is temporarily fixed on the adhesive layer 42 with the arrangement surface of the terminals 12c (corresponding to the terminals 12aa and 12ba described above) facing the adhesive layer 42 side.

  FIG. 5 schematically shows an example of temporary fixing of the semiconductor chip 12 separated by dicing in this way. Note that the number and arrangement of the insulators 13 shown in FIG. 5 are merely examples, and the insulators 13 are not limited to the illustrated number and arrangement.

  FIG. 5 illustrates a case where a set of four semiconductor chips 12 diced from a plurality of wafers 50, for example, four wafers 50 as an example, is temporarily fixed to a plurality of locations on the adhesive layer 42. doing.

  The semiconductor chips 12 formed on each wafer 50 shown in FIG. 5 may be the same type as well as different types. The semiconductor chip 12 of each wafer 50 is a CPU chip, a GPU chip, a sensor chip, a memory chip, or the like. Dicing is performed on each of the wafers 50, and the semiconductor chips 12 formed on the wafers 50 are separated into individual pieces.

  The semiconductor chip 12 of each wafer 50 is subjected to a predetermined test, for example, before dicing, and sorted into a non-defective chip and a defective chip. The semiconductor chip 12 determined as a non-defective chip by a predetermined test of each wafer 50 is temporarily fixed on the adhesive layer 42 using a chip bonder after dicing. By doing in this way, it can suppress that a defective product chip mixes into the inside of the pseudo wafer 40 mentioned later, the pseudo SoC substrate 40A obtained from it, and also the semiconductor device 10 obtained from the pseudo SoC substrate 40A.

  Here, the case where the four semiconductor chips 12 respectively obtained from the four wafers 50 are temporarily fixed on the adhesive layer 42 as one set is illustrated. In addition to this, for example, a total of four semiconductor chips, that is, two semiconductor chips 12 obtained from one of the three wafers 50 and the semiconductor chip 12 obtained from the remaining two wafers 50 are taken as one set. It is also possible to temporarily fix it on the adhesive layer 42.

FIG. 4A shows two semiconductor chips 12 among the semiconductor chips 12 that are separated into pieces and temporarily fixed on the adhesive layer 42 as shown in FIG.
After temporarily fixing the semiconductor chip 12 on the adhesive layer 42, as shown in FIG. 4B, the resin layer 11 is formed so that the insulator 13 and the semiconductor chip 12 are embedded. For the resin layer 11, for example, a resin material (resin composition) such as an epoxy resin containing a filler such as silica is used. The resin layer 11 is, for example, a gold provided with a recess (inner surface) provided in accordance with the shape of the resin layer 11 formed from the resin composition supplied on the adhesive layer 42 provided with the insulator 13 and the semiconductor chip 12. It is formed by pressure molding (molding) using a mold.

  The resin layer 11 is cured by a method according to the type of the resin. Thereby, the pseudo wafer 40 in which the semiconductor chip 12 is covered (sealed) with the resin layer 11 is formed on the carrier substrate 41 and the adhesive layer 42. It should be noted that the resin layer 11 does not necessarily need to be completely cured at this stage, so that the pseudo wafer 40 peeled off from the adhesive layer 42 can be handled while maintaining its wafer state as will be described later. It is sufficient if it is cured. In addition, the curing condition of the resin layer 11 at this stage is set based on the materials of the resin layer 11 and the adhesive layer 42 such that the adhesive force of the adhesive layer 42 is maintained. Alternatively, the material of the adhesive layer 42 is set based on the material of the resin layer 11 and the curing conditions.

  After the resin layer 11 is formed, the pseudo wafer 40 is peeled off from the adhesive layer 42 and separated from the adhesive layer 42 and the carrier substrate 41 as shown in FIG. When the pseudo wafer 40 is peeled from the adhesive layer 42, for example, the adhesive layer 42 is subjected to treatment (heating, ultraviolet irradiation, etc.) for reducing the adhesive force. By such treatment, the adhesive force of the adhesive layer 42 is reduced, and the pseudo wafer 40 is peeled from the adhesive layer 42. After peeling, the resin layer 11 of the pseudo wafer 40 is further cured (completely cured) by a predetermined method corresponding to the type of the resin. The terminals 12 c of the semiconductor chip 12 and the columnar insulator 13 are exposed on the surface of the pseudo wafer 40 that has been peeled off from the adhesive layer 42.

  Note that the peeled pseudo wafer 40 is ground (back grind) from the surface opposite to the surface peeled from the adhesive layer 42 to make it thinner, or on the side opposite to the surface on which the terminals 12c of the semiconductor chip 12 are disposed. These surfaces may be exposed from the resin layer 11.

FIG. 6 is an explanatory diagram of a third formation step of the semiconductor device. FIG. 6 schematically illustrates a cross-section of the main part of the third formation step of the semiconductor device.
After the pseudo wafer 40 is separated from the adhesive layer 42 and the carrier substrate 41, a photoresist 44 is coated on the surface of the pseudo wafer 40 from which the adhesive layer 42 has been peeled, as shown in FIG. Then, the photoresist 44 is exposed and developed, and an opening 44a is formed inside the edge of the insulator 13 as shown in FIG. 6B. Etching is performed using the photoresist 44 having such an opening 44 a as a mask, and the insulator 13 (or the resin layer 11) is placed inside the edge of the insulator 13 as shown in FIG. 6C. A penetrating through hole 13b is formed. Thereby, the cylindrical (for example, cylindrical) insulator 13 is formed from the columnar (in this example, columnar) insulator 13.

  The planar shape of the through-hole 13b formed in the insulator 13 is not limited to a circle, and may be other planar shapes such as an ellipse and a rectangle. Based on the planar shape of the through hole 13b to be formed, the planar shape of the opening 44a of the photoresist 44 formed in the step of FIG. 6B is set.

  As described above, by using the photolithography technique and the etching technique, first, the columnar insulator 13 is formed in the resin layer 11, and then the through hole 13 b is formed in the insulator 13, thereby penetrating the resin layer 11. The through hole 13b can be formed with high accuracy. For example, when a through hole is to be formed directly in the resin layer 11 by laser processing, if the resin layer 11 contains a filler, a through hole having a predetermined dimension cannot be accurately formed at a predetermined position. Can happen. On the other hand, as described above, the columnar insulator 13 is formed in the resin layer 11 using the photolithography technique and the etching technique, and the through-hole 13b is formed in the insulator 13, so that the predetermined position is obtained. The insulator 13 and the through hole 13b having predetermined dimensions can be formed with high accuracy.

FIG. 7 is an explanatory diagram of a fourth formation step of the semiconductor device. FIG. 7 schematically shows a cross-section of the main part of the fourth formation step of the semiconductor device.
After the formation of the insulator 13 having the through hole 13b, for example, as shown in FIGS. 7A to 7C, a conductive material is formed in the through hole 13b, and the via 14 is formed.

  In this case, for example, after removing the photoresist 44 used in forming the through hole 13b, as shown in FIG. 7A, the terminals 12c are arranged on the pseudo wafer 40 in which the through hole 13b is formed. A conductive foil, for example, copper foil 45 is attached to the surface opposite to the installation surface. Next, for example, copper electroplating using the copper foil 45 as a power supply layer is performed, and as shown in FIG. 7B, copper is embedded in the through hole 13 b to form the via 14. After the via 14 is formed, the copper foil 45 is removed by wet etching, so that a columnar (in this example, circular) is formed inside the cylindrical (cylindrical in this example) insulator 13 as shown in FIG. A pseudo wafer 40 in which a (columnar) copper via 14 is formed is formed.

  The planar shape of the via 14 is not limited to a circle, but may be other planar shapes such as an ellipse or a rectangle. Based on the planar shape of the via 14 to be formed, the opening 44 a of the photoresist 44, and the through-hole are formed. The planar shape of the hole 13b is set.

  Here, after removing the photoresist 44 used at the time of forming the through-hole 13b, the via 14 is formed using the electrolytic plating method. However, the electrolytic plating method is used without removing the photoresist 44. Vias 14 can also be formed. In this case, after the via 14 is formed, the photoresist 44 is removed.

  Here, the vias 14 are formed using the electrolytic plating method, but the vias 14 can also be formed using the electroless plating method. In that case, without removing the photoresist 44 used when forming the through-hole 13b, a mask is provided on the surface of the pseudo wafer 40 opposite to the photoresist 44, and then, for example, electroless plating of copper is performed. Then, the via 14 is formed in the through hole 13b. After the via 14 is formed, the photoresist 44 and the mask provided on the opposite surface are removed.

  Also, the via 14 can be formed by combining such an electroless plating method and the above-described electrolytic plating method. In addition to the electrolytic plating method and the electroless plating method, the via 14 can be formed by filling the through hole 13b with a conductive paste containing a predetermined conductive material such as copper or silver (Ag) as a resin material. It is.

  The via 14 is formed in the through hole 13 b of the cylindrical insulator 13 provided in the resin layer 11. In this way, by providing a structure in which the periphery of the via 14 is covered with the insulator 13, the highly reliable via 14 can be provided in the resin layer 11. In addition, the via 14 is formed in the through hole 13b formed by forming the columnar insulator 13 using the photolithography technique and the etching technique instead of directly on the resin layer 11 and processing it. By using such a method, the via 14 having a predetermined size can be accurately formed at a predetermined position.

  On the via 14 formed as described above, a land having a larger planar size (diameter) may be provided. In the case of providing such a land, for example, in the step of FIG. 6A, a land pattern such as copper is provided on the insulator 13, and then a photoresist 44 is formed. Then, after an opening 44a as shown in FIG. 6B is formed at a predetermined position of the photoresist 44, an opening is first formed in the land pattern by wet etching or the like using the photoresist 44 as a mask. Then, the insulator 13 is etched. Thereby, the through-hole 13b as shown in FIG. Thereafter, by using an electroplating method or the like as shown in FIGS. 7A to 7C, a conductive material is embedded in the through hole 13b, so that the via 14 having the land connected to the end portion is formed. Can be formed.

FIG. 8 is an explanatory diagram of the fifth formation step of the semiconductor device. FIG. 8 schematically shows a cross section of the main part of the fifth formation step of the semiconductor device.
After the via 14 is formed, the rewiring layer 15 as described above is formed on the pseudo wafer 40 as shown in FIGS. 8A to 8B, for example.

  In that case, first, as shown in FIG. 8A, photosensitive resin 60 such as photosensitive epoxy, photosensitive polybenzoxazole, photosensitive polyimide, or the like is provided on the side of the pseudo wafer 40 where the terminals 12c are provided. Apply. The photosensitive resin 60 becomes a part of the insulating portion 15b shown in FIG.

  Next, the applied photosensitive resin 60 is exposed and developed, and as shown in FIG. 8B, an opening 60a leading to the terminal 12c of the semiconductor chip 12 and the via 14 (land is formed on the via 14). If there is, an opening 60b leading to the land is formed.

  Next, an adhesion layer such as titanium (Ti) or chromium (Cr), and copper are formed by a sputtering method to form a seed layer. Thereafter, a resist pattern (not shown) having an opening at a portion where vias and wirings are formed is formed, and electrolytic plating using copper or the like using the previously formed seed layer as a power feeding layer is performed. After the resist pattern is peeled off, the seed layer remaining in the region where the resist pattern has been formed is removed by etching. In this manner, first-layer vias 15ab and wirings 15aa connected to the terminals 12c and the vias 14 (or lands) of the semiconductor chip 12 are formed as shown in FIG.

  A first wiring layer is formed on the pseudo wafer 40 by the processes shown in FIGS. 8A to 8C. When forming the second and subsequent wiring layers, the same procedure as in FIGS. 8A to 8C is repeated to form the vias 15ab and the wirings 15aa having a predetermined arrangement. In this way, the rewiring layer 15 including a predetermined number of wiring layers is formed.

In this way, a pseudo SoC substrate, which is a substrate in which the rewiring layer 15 is formed on the pseudo wafer 40, is obtained.
An example of the pseudo SoC substrate is shown in FIG. The number and arrangement of the vias 14 shown in FIG. 9 are merely examples, and the vias 14 are not limited to the illustrated number and arrangement. FIG. 9A is a schematic perspective view of the main part of the pseudo SoC substrate, and FIG. 9B is a schematic cross-sectional view of the main part of the structure corresponding to the X part of FIG.

  As shown in FIG. 9A, the pseudo SoC substrate 40A includes a plurality of vias 14 each surrounded by an insulator 13 and a plurality (four in this example) of semiconductor chips 12 as a set. The part is provided at a plurality of locations.

  In each structure portion, as shown in FIG. 9B, a via 14 surrounded by a semiconductor chip 12 and an insulator 13 is embedded in the resin layer 11, and a rewiring layer 15 is provided thereon. ing. The rewiring layer 15 is formed as shown in FIGS. 8A to 8C, and a predetermined number of vias 15ab and wirings 15aa (conductive portions 15a) and a photosensitive resin covering the periphery thereof. 60 (insulating portion 15b). On the uppermost wiring 15aa, as shown in FIG. 9B, a protective film 61 (insulating portion 15b) such as a solder resist is formed so that a part of the wiring 15aa is exposed. The part of the wiring 15aa exposed from the protective film 61 functions as a terminal 15ac for external connection. Although illustration is omitted here, a multilayer film of nickel (Ni) and gold (Au) or the like may be provided on the terminal 15ac exposed from the protective film 61 as a surface layer.

  Through the steps as described above, the pseudo SoC substrate 40A in which the rewiring layer 15 is formed on the pseudo wafer 40 is obtained. Thus, in the pseudo SoC substrate 40A in which the rewiring layer 15 is formed on one surface of the pseudo wafer 40 (the surface on the side where the terminals 12c are disposed), the surface opposite to the rewiring layer 15 (the surface on which the terminals 12c are disposed) The end surface of the via 14 exposed on the opposite surface) is used as an external connection terminal.

  Here, the case where the rewiring layer 15 is provided only on the side of the pseudo wafer 40 where the terminals 12c are provided is illustrated. In addition, a rewiring layer 15 having a conductive portion 15a electrically connected to the via 14 and an insulating portion 15b covering the periphery thereof may also be provided on the surface opposite to the surface on which the terminal 12c is disposed. it can.

  After the formation of the pseudo SoC substrate 40A, the pseudo wafer 40 and the redistribution layer 15 include the semiconductor chip 12 and the via 14 surrounded by the insulator 13, and the conductive portion 15a electrically connected thereto. Dicing at a position outside the area. As a result, individual semiconductor devices 10 (semiconductor devices having a cross-sectional structure as shown in FIG. 9B) are obtained.

  Here, the method for forming the semiconductor device 10 shown in FIGS. 1 and 2 has been described as an example. However, the semiconductor device 20 shown in FIG. 2 has the same procedure as that described for the semiconductor device 10. Can be formed and obtained.

By stacking the semiconductor device 10 and the semiconductor device 20 obtained in this way and electrically connecting them, a stacked structure 30 as shown in FIG. 2 is obtained.
FIG. 10 is a diagram showing an example of a flow until a laminated structure is obtained from the pseudo SoC substrate.

  3 to 9, the pseudo SoC substrate 40A in which the rewiring layer 15 is formed on the pseudo wafer 40 including the semiconductor chip 12 and the via 14 surrounded by the insulator 13 in the resin layer 11 is formed. (FIG. 10A). Then, the semiconductor device 10 is obtained by dicing the pseudo SoC substrate 40A (FIG. 10B).

  Further, according to the example of FIGS. 3 to 9 described above, the pseudo SoC substrate 70A in which the rewiring layer 25 is formed on the pseudo wafer 70 including the semiconductor chip 22 and the via 24 surrounded by the insulator 23 in the resin layer 21 is formed. It is formed (FIG. 10C). Thereafter, the semiconductor device 20 is obtained by dicing the pseudo SoC substrate 70A (FIG. 10D).

  By stacking the obtained semiconductor device 10 and the semiconductor device 20 (here, the semiconductor device 10 is stacked on the semiconductor device 20) and electrically connecting them through bumps 31 (FIG. 2) such as solder, for example. Then, the laminated structure 30 is obtained (FIG. 10E and FIG. 2).

  As described above, the semiconductor chip 12 determined as a non-defective chip by the predetermined test is used as the pseudo SoC substrate 40A, and the semiconductor chip 22 determined as the non-defective chip by the predetermined test is also used for the pseudo SoC substrate 70A. Can be used. Thereby, mixing of defective chips into the pseudo SoC substrate 40A and the pseudo SoC substrate 70A is suppressed, and accordingly, defective products to the semiconductor device 10 and the semiconductor device 20 obtained by dicing the pseudo SoC substrate 40A and the pseudo SoC substrate 70A. Chip contamination is also suppressed. Therefore, the laminated structure 30 including the non-defective chips can be obtained with a high yield.

The laminated structure 30 obtained as described above can be mounted on another electronic component such as a semiconductor device or a circuit board.
FIG. 11 is a diagram showing an example of mounting a laminated structure. 11A and 11B schematically illustrate a cross-section of a main part of a device (electronic device) when the circuit board 100 is used as an electronic component and the laminated structure 30 is mounted thereon. ing.

  For example, as shown in FIG. 11A, the stacked structure 30 is arranged with the semiconductor device 20 side facing the circuit board 100 side. Then, the via 24 of the semiconductor device 20 and the terminal 101 of the circuit board 100 provided at the corresponding position are electrically connected via bumps 32 such as solder.

  In addition, the stacked structure 30 is disposed with the semiconductor device 10 side facing the circuit board 100 side, for example, as shown in FIG. Then, the terminal 15ac connected to the via 14 of the semiconductor device 10 and the terminal 101 of the circuit board 100 provided at the corresponding position are electrically connected via bumps 32 such as solder.

  Here, the case where the laminated structure 30 is mounted on the circuit board 100 is illustrated. In addition, when the stacked structure 30 is mounted on various semiconductor devices including terminals (a semiconductor device having a pseudo SoC structure, a semiconductor chip, a semiconductor package including a semiconductor chip, etc.), the bump 32 is used in the same arrangement as described above. It is possible to install.

  In the above description, as shown in FIG. 2, the semiconductor device 10 is stacked on the semiconductor device 20, and the vias 14 of the semiconductor device 10 and the terminals 25ac connected to the vias 24 of the semiconductor device 20 are interposed via the bumps 31. The laminated structure 30 electrically connected is illustrated.

Here, another example of the laminated structure will be described with reference to FIGS. 12 and 13 schematically show a cross section of a main part of another example of the laminated structure.
The stacked structure 30A shown in FIG. 12 has a structure in which a semiconductor device 20A on which the semiconductor device 10 is stacked has a semiconductor chip 22 embedded in a resin layer 21 and a rewiring layer 25 formed thereon. . The semiconductor device 20 </ b> A does not include the insulator 23 and the via 24 as described above in the resin layer 21, the redistribution layer 25 is electrically connected to the semiconductor chip 22, and the terminal 25 ac is connected to the semiconductor chip 22. A conductive portion 25a rearranged (Fan-out) is provided outside the area. In the stacked structure 30A, the semiconductor device 10 is stacked on the semiconductor device 20A so that the vias 14 are connected to the terminals 25ac via the bumps 31. In this respect, the laminated structure 30A shown in FIG. 12 is different from the laminated structure 30 shown in FIG.

  Further, the stacked structure 30B shown in FIG. 13 is shown in FIG. 2 in that the semiconductor device 20 is stacked on the semiconductor device 10, that is, the vertical relationship between the semiconductor device 10 and the semiconductor device 20 is inverted. This is different from the laminated structure 30. In the stacked structure 30B, the semiconductor device 20 is stacked on the semiconductor device 10 in this way, and the terminal 15ac connected to the via 14 of the semiconductor device 10 and the via 24 of the semiconductor device 20 are connected via the bumps 31.

Using the semiconductor device 10 described above, a stacked structure 30A and a stacked structure 30B as shown in FIGS. 12 and 13 can be realized.
It is also possible to stack another semiconductor device on the semiconductor device 10 having the stacked structure 30A, on the semiconductor device 10 having the stacked structure 30B, or below the semiconductor device 20.

  In the above description, the semiconductor device 10 obtained by dicing the pseudo SoC substrate 40A and the semiconductor device 20 obtained by dicing the pseudo SoC substrate 70A are stacked as shown in FIG. The method of obtaining was illustrated.

  Here, another example of a method for obtaining a laminated structure will be described with reference to FIGS. 14 and 15 schematically show a cross section of the main part of another example of a method for obtaining a laminated structure. 14 and 15 illustrate a method for obtaining the laminated structure 30B shown in FIG.

  In the method shown in FIG. 14, when the stacked structure 30B shown in FIG. 13 is obtained, first, the pseudo SoC substrate 40A and the semiconductor device 20 obtained by dicing the pseudo SoC substrate 70A are prepared. Then, the diced semiconductor devices 20 are stacked on the portions of the pseudo SoC substrate 40A that become the individual semiconductor devices 10 by dicing. At this time, as shown in FIG. 13, the terminal 15ac connected to the via 14 in the portion that becomes the semiconductor device 10 and the via 24 of the stacked semiconductor device 20 are connected via the bumps 31.

  In this manner, after the diced semiconductor device 20 is stacked on the pseudo SoC substrate 40A, dicing is performed at a position outside the portion of the pseudo SoC substrate 40A that becomes the individual semiconductor device 10. As a result, the stacked structure 30 </ b> B of FIG. 13 in which the semiconductor device 20 is stacked on the semiconductor device 10 is obtained.

  Here, the case where one layer of the semiconductor device 20 is stacked on the pseudo SoC substrate 40A is illustrated. In addition, another semiconductor device may be stacked on the semiconductor device 20 stacked on the pseudo SoC substrate 40A, or a stacked structure of two or more semiconductor devices stacked in advance may be stacked on the pseudo SoC substrate 40A. You can also.

  According to the example of the method shown in FIG. 14, a laminated structure 30 in which the semiconductor device 10 is laminated on the semiconductor device 20 as shown in FIG. 2 can be obtained. That is, in that case, first, the semiconductor device 10 obtained by dicing the pseudo SoC substrate 40A and the pseudo SoC substrate 70A are prepared. Then, the diced semiconductor devices 10 are stacked on the portions of the pseudo SoC substrate 70A that become the individual semiconductor devices 20 by dicing. At this time, as shown in FIG. 2, the terminal 25ac connected to the via 24 of the portion that becomes the semiconductor device 20 and the via 14 of the stacked semiconductor device 10 are connected via the bumps 31.

  As described above, after the diced semiconductor device 10 is stacked on the pseudo SoC substrate 70A, dicing is performed at a position outside the portion of the pseudo SoC substrate 70A that becomes the individual semiconductor device 20. Thereby, the stacked structure 30 in FIG. 2 in which the semiconductor device 10 is stacked on the semiconductor device 20 is obtained.

  In the method shown in FIG. 15, when obtaining the laminated structure 30B shown in FIG. 13, first, the pseudo SoC substrate 40A and the pseudo SoC substrate 70A are prepared. Then, the positions of the portions of the pseudo SoC substrate 40A that become the individual semiconductor devices 10 by dicing and the portions of the pseudo SoC substrate 70A that become the individual semiconductor devices 20 by dicing are aligned, and the portions on the pseudo SoC substrate 40A are simulated. The SoC substrate 70A is stacked. At this time, as shown in FIG. 13, the terminal 15ac connected to the via 14 in the portion serving as the semiconductor device 10 on the pseudo SoC substrate 40A side and the via in the portion serving as the semiconductor device 20 on the pseudo SoC substrate 70A side to be stacked. 24 are connected via bumps 31.

  As described above, after the pseudo SoC substrate 70A is stacked on the pseudo SoC substrate 40A, dicing is performed at positions outside the portions of the pseudo SoC substrate 40A and the pseudo SoC substrate 70A that become the individual semiconductor devices 10 and the semiconductor devices 20. I do. As a result, the stacked structure 30 </ b> B of FIG. 13 in which the semiconductor device 20 is stacked on the semiconductor device 10 is obtained.

  Here, a case where one pseudo SoC substrate 70A is stacked on the pseudo SoC substrate 40A is illustrated. In addition, another pseudo SoC substrate is laminated on the pseudo SoC substrate 70A laminated on the pseudo SoC substrate 40A, or a laminated structure of two or more pseudo SoC substrates laminated in advance is laminated on the pseudo SoC substrate 40A. You can also do it.

  In accordance with the example of the method shown in FIG. 15, the pseudo SoC substrate 40A is stacked on the pseudo SoC substrate 70A and dicing is performed, so that the semiconductor device 10 is formed on the semiconductor device 20 as shown in FIG. It is also possible to obtain a laminated structure 30 in which are stacked.

  12 also includes a method of stacking the pseudo SoC substrate including the semiconductor device 20A and the semiconductor device 10 (or the pseudo SoC substrate 40A and the semiconductor device 20A in accordance with the example of the method illustrated in FIG. It is possible to form it using a method of stacking. Further, according to the example of the method shown in FIG. 15, the pseudo SoC substrate including the semiconductor device 20A and the pseudo SoC substrate 40A can be formed and stacked.

Further, the semiconductor device 10 or the like as described above can be stacked with a semiconductor device including a semiconductor chip including a TSV or a semiconductor chip including a TSV.
Here, another example of the laminated structure will be described with reference to FIGS. 16 and 17 schematically show a cross section of the main part of another example of the laminated structure.

  A stacked structure 30 </ b> C illustrated in FIG. 16 has a structure in which the semiconductor device 10 as described above is stacked on the semiconductor device 80. The semiconductor device 80 includes a resin layer 81, a semiconductor chip 82 embedded in the resin layer 81 and provided with a TSV 82a, and a conductive portion 85a provided on the resin layer 81 and the semiconductor chip 82 and electrically connected thereto. And a rewiring layer 85 provided. The semiconductor device 10 is stacked on the semiconductor device 80, and the TSV 82 a of the semiconductor device 80 and the via 14 of the semiconductor device 10 are electrically connected via the conductive portion 85 a and the bump 31.

Note that another semiconductor device can be stacked on the semiconductor device 10 of the stacked structure 30C or below the semiconductor device 80.
It is also possible to stack the semiconductor device 80 on the semiconductor device 10 and electrically connect the vias 14 and the TSV 82a via the conductive portions 15a and the bumps 31. It is also possible to stack semiconductor devices.

  A stacked structure 30D illustrated in FIG. 17 has a structure in which the semiconductor device 10 as described above is stacked on a semiconductor chip 90 including the TSV 90a. The semiconductor device 10 is stacked on the semiconductor chip 90, and the TSV 90 a of the semiconductor chip 90 and the via 14 of the semiconductor device 10 are electrically connected via the bumps 31.

It is possible to stack another semiconductor device on the semiconductor device 10 having the stacked structure 30D or below the semiconductor chip 90.
Further, it is possible to stack the semiconductor chip 90 on the semiconductor device 10 and to electrically connect the vias 14 and the TSV 90a via the conductive portions 15a and the bumps 31. It is also possible to stack semiconductor devices.

  Such a laminated structure 30C and laminated structure 30D are obtained by laminating the semiconductor device 80 and the semiconductor device 10 obtained by dicing or the semiconductor chip 90 and the semiconductor device 10 in accordance with the example of the method shown in FIG. It is possible to form.

  The stacked structure 30C is formed using a method of stacking the pseudo SoC substrate on which the semiconductor device 80 is formed and the semiconductor device 10 or the pseudo SoC substrate 40A and the semiconductor device 80 in accordance with the example of the method shown in FIG. It is also possible. Further, in accordance with the example of the method shown in FIG. 15, the pseudo SoC substrate on which the semiconductor device 80 is formed and the pseudo SoC substrate 40A can be formed and stacked.

  The stacked structure 30D may be formed by using the method of stacking the wafer on which the semiconductor chip 90 is formed and the semiconductor device 10 or the pseudo SoC substrate 40A and the semiconductor chip 90 in accordance with the example of the method shown in FIG. Is possible. Further, according to the example of the method shown in FIG. 15, it is also possible to form by using a method of stacking the wafer on which the semiconductor chip 90 is formed and the pseudo SoC substrate 40A.

Examples are shown below.
〔Example〕
First, a non-defective test semiconductor chip having a daisy chain with a planar size of 10 mm × 10 mm was prepared. Then, according to the examples of FIGS. 3 to 9, a pseudo wafer having vias surrounded by the prepared test semiconductor chip and insulator is formed in the resin layer, and a rewiring layer is formed on the pseudo wafer. Thus, a pseudo SoC substrate was obtained.

  Also, a non-defective test semiconductor chip having a daisy chain with a planar size of 15 mm × 15 mm was prepared. Then, according to the examples of FIGS. 3 to 9, a pseudo wafer having vias surrounded by the prepared test semiconductor chip and insulator is formed in the resin layer, and a rewiring layer is formed on the pseudo wafer. Thus, a pseudo SoC substrate was obtained.

  The two types of pseudo SoC substrates obtained in this way were laminated together by aligning the positions of the respective semiconductor devices (37 in this example) by dicing and connected via solder bumps. As a result, the bumps and the semiconductor chip in the part of the laminated structure of the semiconductor device were electrically connected by dicing.

When a continuity test was performed on the obtained laminated body of the pseudo SoC substrate, it was confirmed that the daisy chain was able to conduct in all the parts to be a semiconductor device.
In the above description, a method of stacking semiconductor devices including different semiconductor chips, a semiconductor device including different semiconductor chips and a pseudo SoC substrate, or pseudo SoC substrates including different semiconductor chips is illustrated. In addition, the above method can be similarly applied to a case where semiconductor devices including the same kind of semiconductor chips are stacked, a semiconductor device including the same kind of semiconductor chips and a pseudo SoC substrate, or a pseudo SoC substrate including the same kind of semiconductor chip. is there.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Appendix 1) Resin layer;
A semiconductor chip embedded in the resin layer;
A cylindrical insulator embedded in the resin layer and having a through hole;
A semiconductor device comprising: a conductor disposed in the through hole.

(Additional remark 2) The semiconductor device of Additional remark 1 characterized by further including the wiring layer provided on the said resin layer and including the conductor part electrically connected to the said conductor.
(Additional remark 3) The 1st semiconductor device which has the said resin layer, the said semiconductor chip, the said insulator, and the said conductor,
The semiconductor device according to appendix 1 or 2, further comprising: a second semiconductor device stacked on the first semiconductor device and electrically connected to the conductor.

(Appendix 4) A step of disposing a columnar insulator and a semiconductor chip on a support;
Forming a resin layer in which the insulator and the semiconductor chip are embedded on the support;
Forming a through hole in the insulator in the resin layer;
Forming a conductor in the through hole. A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 5) The step of providing the insulator and the semiconductor chip includes:
Forming an insulating coating on the support;
The method for manufacturing a semiconductor device according to appendix 4, further comprising: forming the columnar insulator by processing the insulating coating.

(Additional remark 6) The manufacturing method of the semiconductor device of Additional remark 4 or 5 further including the process of peeling the said support body after the process of forming the said resin layer.
(Appendix 7) The step of forming the through-hole includes
Forming a mask covering an edge of the insulator;
The method for manufacturing a semiconductor device according to any one of appendices 4 to 6, further comprising: etching the inside from the edge using the mask.

  (Additional remark 8) The semiconductor device in any one of additional remark 4 thru | or 7 further including the process of forming the wiring layer containing the conductor part electrically connected to the said conductor on the said resin layer. Manufacturing method.

  (Supplementary note 9) The semiconductor device according to any one of supplementary notes 4 to 8, further comprising a step of dicing the resin layer at a position outside a region including the conductor and the semiconductor chip. Production method.

(Appendix 10) a resin layer;
A semiconductor chip embedded in the resin layer;
A cylindrical insulator embedded in the resin layer and having a through hole;
And a conductor disposed in the through hole.

(Additional remark 11) The 1st board | substrate which has the said resin layer, the said semiconductor chip, the said insulator, and the said conductor,
The substrate according to claim 10, further comprising: a semiconductor device stacked on the first substrate and electrically connected to the conductor.

(Additional remark 12) The 1st board | substrate which has the said resin layer, the said semiconductor chip, the said insulator, and the said conductor,
The substrate according to appendix 10, further comprising: a second substrate laminated on the first substrate and electrically connected to the conductor.

(Additional remark 13) The process of arrange | positioning a columnar insulator and a semiconductor chip on a support body,
Forming a resin layer in which the insulator and the semiconductor chip are embedded on the support;
Forming a through hole in the insulator in the resin layer;
And a step of forming a conductor in the through hole.

(Additional remark 14) The manufacturing method of the board | substrate of Additional remark 13 further including the process of laminating | stacking a semiconductor device on the 1st board | substrate after formation of the said conductor, and electrically connecting to the said conductor.
(Supplementary note 15) The method of manufacturing a substrate according to supplementary note 13, further comprising a step of stacking a second substrate on the first substrate after the formation of the conductor and electrically connecting to the conductor. .

  (Additional remark 16) The manufacturing of the board | substrate in any one of additional remark 13 thru | or 15 further including the process of dicing in the position outside the area | region where the said conductor and the said semiconductor chip are contained of the said resin layer. Method.

10, 20, 20A, 80 Semiconductor device 11, 21, 81 Resin layer 11a Surface 12, 12a, 12b, 22, 82, 90 Semiconductor chip 12aa, 12ba, 12c, 15ac, 22a, 25ac, 101 Terminal 13, 23 Insulator 13a Insulating coating 13b Through hole 14, 15ab, 24, 25ab Via 15, 25, 85 Redistribution layer 15a, 25a, 85a Conducting portion 15aa, 25aa Wiring 15b, 25b Insulating portion 30, 30A, 30B, 30C, 30D Laminated structure 31 , 32 Bump 40, 70 Pseudo wafer 40A, 70A Pseudo SoC substrate 41 Carrier substrate 42 Adhesive layer 43 Resist pattern 44 Photo resist 44a, 60a, 60b Opening 45 Copper foil 50 Wafer 60 Photosensitive resin 61 Protective film 82a, 90a TSV
100 circuit board

Claims (9)

A resin layer;
A semiconductor chip embedded in the resin layer;
A cylindrical insulator embedded in the resin layer and having one through hole;
A semiconductor device comprising: a columnar conductor disposed in the through hole. A first semiconductor device having the resin layer, the semiconductor chip, the insulator, and the conductor;
The semiconductor device according to claim 1, further comprising: a second semiconductor device stacked on the first semiconductor device and electrically connected to the conductor. A step of disposing a columnar insulator and a semiconductor chip on a support;
Forming a resin layer in which the insulator and the semiconductor chip are embedded on the support;
Forming one through hole in the insulator in the resin layer, and making the insulator cylindrical ;
Forming a columnar conductor in the through hole. A method for manufacturing a semiconductor device, comprising: The step of providing the insulator and the semiconductor chip includes:
Forming an insulating coating on the support;
The method for manufacturing a semiconductor device according to claim 3, further comprising: processing the insulating film to form the columnar insulator. The step of forming the through hole includes:
Forming a mask covering an edge of the insulator;
5. The method of manufacturing a semiconductor device according to claim 3, further comprising: etching the inside from the edge using the mask. A resin layer;
A semiconductor chip embedded in the resin layer;
A cylindrical insulator embedded in the resin layer and having one through hole;
And a columnar conductor disposed in the through hole. A first substrate having the resin layer, the semiconductor chip, the insulator and the conductor;
The substrate according to claim 6, further comprising: a semiconductor device stacked on the first substrate and electrically connected to the conductor. A first substrate having the resin layer, the semiconductor chip, the insulator and the conductor;
The substrate according to claim 6, further comprising: a second substrate stacked on the first substrate and electrically connected to the conductor. A step of disposing a columnar insulator and a semiconductor chip on a support;
Forming a resin layer in which the insulator and the semiconductor chip are embedded on the support;
Forming one through hole in the insulator in the resin layer, and making the insulator cylindrical ;
And a step of forming a columnar conductor in the through hole.

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