JP2014110337A - Electronic component device manufacturing method, electronic component device and electronic device - Google Patents

Electronic component device manufacturing method, electronic component device and electronic device Download PDF

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JP2014110337A
JP2014110337A JP2012264412A JP2012264412A JP2014110337A JP 2014110337 A JP2014110337 A JP 2014110337A JP 2012264412 A JP2012264412 A JP 2012264412A JP 2012264412 A JP2012264412 A JP 2012264412A JP 2014110337 A JP2014110337 A JP 2014110337A
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electronic component
layer
columnar conductor
conductive
resin composition
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JP5942823B2 (en
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Motoaki Tani
元昭 谷
Yoshikatsu Ishizuki
義克 石月
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Fujitsu Ltd
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Fujitsu Ltd
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

PROBLEM TO BE SOLVED: To stably manufacture an electronic component device including a columnar conductor, with a suppressed fall of the columnar conductor.SOLUTION: On an adhesion layer 20 disposed on a support 10, a conductor film 70a having an aperture 71 is provided. An electronic component 30 is provided on the adhesion layer 20 of the aperture 71, so that a columnar conductor 80 is erected on a conductive film 70a. From the above state, a pseudo wafer 50 is formed by coating the conductive film 70a, the electronic component 30 and the columnar conductor 80 with a resin composition layer 40. After the separation of the pseudo wafer 50 from the adhesion layer 20, the conductive film 70a of the pseudo wafer 50 is partially removed to form a conductive pattern 70. On the pseudo wafer 50 having the formed conductive pattern 70, a re-wiring layer is formed and dicing is performed to form the electronic component device.

Description

本発明は、電子部品装置の製造方法、電子部品装置及び電子装置に関する。   The present invention relates to an electronic component device manufacturing method, an electronic component device, and an electronic device.

半導体チップ（半導体素子）等の電子部品を含む電子部品装置（パッケージ）の１つとして、ＷＬＰ（Wafer Level Package）（ＷＬ−ＣＳＰ（Wafer Level-Chip Size Package）、Ｗ−ＣＳＰ（Wafer-Chip Size Package）とも称される）が知られている。ＷＬＰは、電子部品の端子をその部品エリア内に再配置（ファンイン（Fan-in））することを可能にする。また、電子部品の多端子化に伴い、その部品エリアだけでは端子の再配置が困難になることに鑑み、部品エリア外に端子を再配置（ファンアウト（Fan-out））するＷＬＰも開発されている。   As one of electronic component devices (packages) including electronic components such as semiconductor chips (semiconductor elements), WLP (Wafer Level Package) (WL-CSP (Wafer Level-Chip Size Package)), W-CSP (Wafer-Chip Size) Also known as “Package”). WLP makes it possible to rearrange (Fan-in) the terminals of an electronic component within its component area. In addition, with the increase in the number of terminals of electronic components, WLP that rearranges terminals outside the component area (fan-out) has also been developed in view of the difficulty in rearranging terminals only in the component area. ing.

このようなパッケージの製造に関し、例えば、支持体上に半導体チップを配置し、その半導体チップを樹脂組成物で封止して所謂擬似ウェハとし、その擬似ウェハを支持体から剥離する方法を用いる技術が知られている。その擬似ウェハの、支持体から剥離した面上に配線層が設けられ、ダイシングにより個片化されて、個々の電子部品装置が得られる。   Regarding the manufacture of such a package, for example, a technique using a method of disposing a semiconductor chip on a support, sealing the semiconductor chip with a resin composition to form a so-called pseudo wafer, and peeling the pseudo wafer from the support It has been known. A wiring layer is provided on the surface of the pseudo wafer peeled from the support, and is separated into pieces by dicing to obtain individual electronic component devices.

また、支持体上に形成した導電パターンに、半田等を用いて半導体チップ及び柱状導体をそれぞれ配置し、それらを、予め切断等で板形状にした樹脂組成物に埋設した後、支持体を取り去り、電子部品装置を得る技術も知られている。更に、得られた電子部品装置を積層する技術、樹脂組成物の層にレーザー加工等を利用して貫通ビアを形成する技術、樹脂組成物の層の表裏面に導電パターンを設ける技術等も知られている。   In addition, the semiconductor chip and the columnar conductor are respectively disposed on the conductive pattern formed on the support using solder or the like, and after embedding them in a resin composition that has been formed into a plate shape by cutting or the like, the support is removed. A technique for obtaining an electronic component device is also known. In addition, the technology for laminating the obtained electronic component device, the technology for forming through vias using laser processing etc. on the resin composition layer, the technology for providing conductive patterns on the front and back surfaces of the resin composition layer, etc. are also known. It has been.

米国特許出願公開第２００６／０１８３２６９号明細書US Patent Application Publication No. 2006/0183269 特開２００１−３０８１１６号公報JP 2001-308116 A 特開２００２−１３４６５３号公報JP 2002-134653 A

電子部品装置において、半導体チップ等の電子部品を封止する樹脂組成物の層に貫通ビアを設けると、複数の電子部品装置を積層したり、樹脂組成物の層の両面に導電パターン、配線層を形成したりすることが可能になる。それにより、実装密度の向上を図ることが可能になる。   In an electronic component device, when a through via is provided in a resin composition layer that seals an electronic component such as a semiconductor chip, a plurality of electronic component devices are stacked, or a conductive pattern and a wiring layer are formed on both surfaces of the resin composition layer. Can be formed. As a result, it is possible to improve the mounting density.

しかし、このような貫通ビアを設けるために、樹脂組成物の層にレーザー加工で貫通孔を形成して導電材料を埋め込む方法を用いると、レーザー加工、埋め込みに時間がかかる場合がある。   However, in order to provide such a through via, if a method of forming a through hole in a resin composition layer by laser processing and embedding a conductive material is used, it may take time for laser processing and embedding.

また、半導体チップ等の電子部品と共に柱状導体を樹脂組成物で封止する方法では、封止の際、柱状導体が配置された導電パターンと支持体との接続が弱いと、封止時の圧力で導電パターンが支持体から剥がれ、柱状導体が倒れてしまう場合がある。   Further, in the method of sealing a columnar conductor with a resin composition together with an electronic component such as a semiconductor chip, when sealing, if the connection between the conductive pattern on which the columnar conductor is arranged and the support is weak, the pressure at the time of sealing Thus, the conductive pattern may be peeled off from the support, and the columnar conductor may fall down.

本発明の一観点によれば、支持体上に粘着層を設ける工程と、前記粘着層上に、開口部を有する導電膜を設ける工程と、前記開口部の前記粘着層上に電子部品を設ける工程と、前記導電膜上に柱状導体を立てる工程と、前記粘着層上に、前記導電膜、前記電子部品及び前記柱状導体を樹脂組成物で被覆した基板を形成する工程と、前記基板を前記粘着層から分離する工程と、前記粘着層から分離された前記基板の前記導電膜を部分的に除去し、前記柱状導体に対応する部分を含む導電パターンを形成する工程と、前記基板の前記導電パターンが形成された第１面上に、前記電子部品及び前記導電パターンに電気的に接続された第１導電部を有する第１配線層を形成する工程とを含む電子部品装置の製造方法が提供される。   According to one aspect of the present invention, a step of providing an adhesive layer on a support, a step of providing a conductive film having an opening on the adhesive layer, and providing an electronic component on the adhesive layer of the opening A step of standing a columnar conductor on the conductive film, a step of forming a substrate in which the conductive film, the electronic component, and the columnar conductor are covered with a resin composition on the adhesive layer; and A step of separating from the adhesive layer, a step of partially removing the conductive film of the substrate separated from the adhesive layer, forming a conductive pattern including a portion corresponding to the columnar conductor, and the conductive of the substrate Forming a first wiring layer having a first conductive portion electrically connected to the electronic component and the conductive pattern on a first surface on which a pattern is formed. Is done.

また、本発明の一観点によれば、上記のような方法を用いて製造される電子部品装置、及びそのような電子部品装置を含む電子装置が提供される。   Moreover, according to one aspect of the present invention, an electronic component device manufactured using the method as described above, and an electronic device including such an electronic component device are provided.

開示の技術によれば、樹脂組成物の層内に電子部品及び柱状導体を含み、高密度実装が可能な電子部品装置を、柱状導体の倒れを抑えて安定的に製造することが可能になる。   According to the disclosed technology, it is possible to stably manufacture an electronic component device that includes an electronic component and a columnar conductor in a layer of the resin composition and can be mounted at high density while suppressing the collapse of the columnar conductor. .

電子部品装置の製造方法の一例を示す図（その１）である。It is a figure (the 1) which shows an example of the manufacturing method of an electronic component apparatus. 電子部品装置の製造方法の一例を示す図（その２）である。It is FIG. (2) which shows an example of the manufacturing method of an electronic component apparatus. 電子部品装置の製造方法の別例を示す図（その１）である。It is FIG. (1) which shows another example of the manufacturing method of an electronic component apparatus. 電子部品装置の製造方法の別例を示す図（その２）である。It is FIG. (2) which shows another example of the manufacturing method of an electronic component apparatus. 第１の実施の形態に係る電子部品装置の製造方法の説明図（その１）である。It is explanatory drawing (the 1) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. 第１の実施の形態に係る電子部品装置の製造方法の説明図（その２）である。It is explanatory drawing (the 2) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. 第１の実施の形態に係る電子部品装置の製造方法の説明図（その３）である。It is explanatory drawing (the 3) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. 第１の実施の形態に係る電子部品装置の製造方法の説明図（その４）である。It is explanatory drawing (the 4) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. 第１の実施の形態に係る電子部品装置の製造方法の説明図（その５）である。It is explanatory drawing (the 5) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. 第１の実施の形態に係る電子部品装置の製造方法の説明図（その６）である。It is explanatory drawing (the 6) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. 第１の実施の形態に係る電子部品装置の製造方法の説明図（その７）である。It is explanatory drawing (the 7) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. 第１の実施の形態に係る電子部品装置の製造方法の説明図（その８）である。It is explanatory drawing (the 8) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. 第１の実施の形態に係る電子部品装置の製造方法の説明図（その９）である。It is explanatory drawing (the 9) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. 第２の実施の形態に係る電子部品装置の製造方法の説明図（その１）である。It is explanatory drawing (the 1) of the manufacturing method of the electronic component apparatus which concerns on 2nd Embodiment. 第２の実施の形態に係る電子部品装置の製造方法の説明図（その２）である。It is explanatory drawing (the 2) of the manufacturing method of the electronic component apparatus which concerns on 2nd Embodiment. 電子装置の第１構成例を示す図である。It is a figure which shows the 1st structural example of an electronic device. 電子装置の第２構成例を示す図である。It is a figure which shows the 2nd structural example of an electronic device. 電子装置の第３構成例を示す図である。It is a figure which shows the 3rd structural example of an electronic device. 電子装置の第４構成例を示す図である。It is a figure which shows the 4th structural example of an electronic apparatus. 電子装置の別例を示す図である。It is a figure which shows another example of an electronic device.

図１及び図２は電子部品装置の製造方法の一例を示す図である。尚、図１（Ａ）〜図１（Ｅ）はそれぞれ、電子部品装置の各製造工程の要部断面模式図である。図２は、図１（Ｂ）に示す製造工程の平面模式図である。   1 and 2 are diagrams illustrating an example of a method for manufacturing an electronic component device. 1A to 1E are schematic cross-sectional views of the main part of each manufacturing process of the electronic component device. FIG. 2 is a schematic plan view of the manufacturing process shown in FIG.

この方法では、まず図１（Ａ）に示すように、支持体１０上に粘着層２０を設ける。支持体１０には、金属基板、ガラス基板、プリント基板、半導体基板、セラミックス基板等が用いられる。粘着層２０には、所定の基材上に粘着剤を設けた粘着フィルムのほか、支持体１０上に粘着剤をスピンコート法、スプレーコート法、印刷法等で塗布したものが用いられる。粘着層２０には、後述のように擬似ウェハ５０Ａを形成した後、その擬似ウェハ５０Ａを剥離することができるもの、例えば、剥離時に加熱や紫外線照射でその粘着力を低下させることができるものが用いられる。このような粘着層２０として、加熱により発泡して粘着力が低下する熱発泡型粘着層、紫外線照射により発泡して粘着力が低下する紫外線発泡型粘着層が用いられる。また、加熱や紫外線照射といった処理を行わずに擬似ウェハ５０Ａを剥離することができるものを用いてもよい。   In this method, first, an adhesive layer 20 is provided on a support 10 as shown in FIG. As the support 10, a metal substrate, a glass substrate, a printed substrate, a semiconductor substrate, a ceramic substrate, or the like is used. For the adhesive layer 20, in addition to an adhesive film in which an adhesive is provided on a predetermined substrate, a material obtained by applying an adhesive on the support 10 by a spin coating method, a spray coating method, a printing method, or the like is used. The adhesive layer 20 can peel the pseudo wafer 50A after forming the pseudo wafer 50A as will be described later, for example, one that can reduce the adhesive strength by heating or ultraviolet irradiation at the time of peeling. Used. As such a pressure-sensitive adhesive layer 20, a heat-foaming pressure-sensitive adhesive layer that foams by heating and decreases in adhesive strength, or an ultraviolet-foamable pressure-sensitive adhesive layer that foams by irradiation with ultraviolet rays and decreases in adhesive strength is used. Moreover, you may use what can peel 50 A of pseudo wafers, without performing processes, such as a heating and ultraviolet irradiation.

支持体１０上に粘着層２０を設けた後、図１（Ｂ）に示すように、粘着層２０上に、半導体素子等の電子部品３０を、その電極３１が設けられている面（電極面）３０ａを粘着層２０側に向けて設ける。図１（Ｂ）には１つの電子部品３０を図示しているが、粘着層２０上には、図２に示すように、複数（ここでは一例として４つ）の電子部品３０が、それぞれ所定の箇所に、図１（Ｂ）と同様に各電極面３０ａを粘着層２０側に向けて、設けられる。尚、ここでは便宜上、１つの電子部品３０に着目し、以降の工程について説明する。   After the adhesive layer 20 is provided on the support 10, as shown in FIG. 1B, an electronic component 30 such as a semiconductor element is provided on the adhesive layer 20 on the surface (electrode surface) on which the electrode 31 is provided. ) 30a is provided toward the adhesive layer 20 side. Although one electronic component 30 is illustrated in FIG. 1B, a plurality (four as an example here) of electronic components 30 are respectively predetermined on the adhesive layer 20 as shown in FIG. In the same manner as in FIG. 1B, each electrode surface 30a is provided toward the adhesive layer 20 side. Here, for convenience, attention is focused on one electronic component 30 and the subsequent steps will be described.

粘着層２０上に電子部品３０を設けた後、粘着層２０上に樹脂組成物を供給し、それを成型して、図１（Ｃ）に示すような樹脂組成物層４０を形成する。樹脂組成物層４０に用いる樹脂組成物には、絶縁性の樹脂及びフィラーが含まれる。樹脂組成物の樹脂には、熱硬化性樹脂、熱可塑性樹脂、紫外線照射によって硬化する樹脂等が用いられる。樹脂組成物のフィラーには、非導電性フィラー、例えば、酸化アルミニウム、酸化シリコン、水酸化アルミニウム、窒化アルミニウム等の無機フィラーが用いられる。粘着層２０上に供給した樹脂組成物を、形成する樹脂組成物層４０の形状に合わせて設けられた凹部（内面）を備える金型（モールド）を用いて加圧成型（モールド成型）することで、粘着層２０上に樹脂組成物層４０を形成する。   After the electronic component 30 is provided on the pressure-sensitive adhesive layer 20, a resin composition is supplied onto the pressure-sensitive adhesive layer 20, and is molded to form a resin composition layer 40 as shown in FIG. The resin composition used for the resin composition layer 40 includes an insulating resin and a filler. As the resin of the resin composition, a thermosetting resin, a thermoplastic resin, a resin that is cured by ultraviolet irradiation, or the like is used. As the filler of the resin composition, a non-conductive filler, for example, an inorganic filler such as aluminum oxide, silicon oxide, aluminum hydroxide, or aluminum nitride is used. The resin composition supplied onto the adhesive layer 20 is pressure-molded (molded) using a mold (mold) having a recess (inner surface) provided in accordance with the shape of the resin composition layer 40 to be formed. Thus, the resin composition layer 40 is formed on the adhesive layer 20.

形成された樹脂組成物層４０は、その樹脂の種類に応じた手法で硬化される。これにより、粘着層２０上に、電子部品３０が樹脂組成物層４０で被覆（封止）された擬似ウェハ（基板）５０Ａが形成される。尚、樹脂組成物層４０は、この段階では必ずしも完全に硬化されていることを要せず、後述のように粘着層２０から剥離した擬似ウェハ５０Ａをそのウェハ状態を保持して取り扱うことができる程度に硬化されていれば足りる。また、この段階での樹脂組成物層４０の硬化条件は、樹脂組成物層４０及び粘着層２０の材料に基づき、粘着層２０の粘着力が保持されるような条件に設定される。或いはまた、樹脂組成物層４０の材料及び硬化条件に基づき、粘着層２０の材料が設定される。   The formed resin composition layer 40 is cured by a technique according to the type of the resin. Thereby, a pseudo wafer (substrate) 50 </ b> A in which the electronic component 30 is coated (sealed) with the resin composition layer 40 is formed on the adhesive layer 20. In addition, the resin composition layer 40 does not necessarily need to be completely cured at this stage, and the pseudo wafer 50A peeled off from the adhesive layer 20 can be handled while maintaining its wafer state as will be described later. It only needs to be cured to a certain extent. In addition, the curing condition of the resin composition layer 40 at this stage is set based on the materials of the resin composition layer 40 and the adhesive layer 20 so that the adhesive strength of the adhesive layer 20 is maintained. Alternatively, the material of the adhesive layer 20 is set based on the material of the resin composition layer 40 and the curing conditions.

擬似ウェハ５０Ａの形成後は、図１（Ｄ）に示すように、擬似ウェハ５０Ａを、粘着層２０から剥離し、粘着層２０及び支持体１０から分離する。擬似ウェハ５０Ａを粘着層２０から剥離する際には、例えば、その粘着層２０に対し、その粘着力を低下させる処理（加熱、紫外線照射等）を行う。このような処理によって粘着層２０の粘着力を低下させ、擬似ウェハ５０Ａを粘着層２０から剥離する。剥離後、擬似ウェハ５０Ａの樹脂組成物層４０は、その樹脂の種類に応じた所定の手法で更に硬化（完全硬化）される。剥離された擬似ウェハ５０Ａを、粘着層２０から剥離された面と反対側の面側から研削（バックグラインド）するようにしてもよい。   After the formation of the pseudo wafer 50A, the pseudo wafer 50A is peeled off from the adhesive layer 20 and separated from the adhesive layer 20 and the support 10 as shown in FIG. When peeling the pseudo wafer 50 </ b> A from the adhesive layer 20, for example, the adhesive layer 20 is subjected to a process (heating, ultraviolet irradiation, etc.) for reducing the adhesive force. By such treatment, the adhesive force of the adhesive layer 20 is reduced, and the pseudo wafer 50A is peeled from the adhesive layer 20. After peeling, the resin composition layer 40 of the pseudo wafer 50A is further cured (completely cured) by a predetermined method according to the type of the resin. The peeled pseudo wafer 50 </ b> A may be ground (back grind) from the surface opposite to the surface peeled from the adhesive layer 20.

擬似ウェハ５０Ａの、粘着層２０から剥離された面には、図１（Ｅ）に示すように、配線層（再配線層）６０Ａを形成する。再配線層６０Ａは、電子部品３０の電極３１に電気的に接続されたビア及び配線等の導電部６１、並びに、導電部６１の周りに設けられた絶縁部６２を含む。導電部６１には、銅、銅合金、アルミニウム等の導電材料が用いられる。絶縁部６２には、エポキシ樹脂、ポリイミド樹脂等の絶縁材料が用いられる。この例に示す擬似ウェハ５０Ａでは、電子部品３０の電極３１が、再配線層６０Ａによってその電子部品３０のエリア外の端子６３に再配置（Fan-out）されている。   As shown in FIG. 1E, a wiring layer (rewiring layer) 60A is formed on the surface of the pseudo wafer 50A that has been peeled off from the adhesive layer 20. The rewiring layer 60 </ b> A includes a conductive portion 61 such as a via and a wiring electrically connected to the electrode 31 of the electronic component 30, and an insulating portion 62 provided around the conductive portion 61. For the conductive portion 61, a conductive material such as copper, copper alloy, or aluminum is used. An insulating material such as an epoxy resin or a polyimide resin is used for the insulating portion 62. In the pseudo wafer 50A shown in this example, the electrode 31 of the electronic component 30 is rearranged (Fan-out) to the terminal 63 outside the area of the electronic component 30 by the rewiring layer 60A.

擬似ウェハ５０Ａには、複数の電子部品３０が含まれており、図１（Ｅ）に示すような構造部が複数含まれる。再配線層６０Ａが形成された擬似ウェハ５０Ａは、この図１（Ｅ）に示すような構造部の周囲の位置でダイシングが行われ、それにより、個々の電子部品装置１Ａに個片化される。電子部品装置１Ａは、再配線層６０Ａを用いて、他の電子部品装置や回路基板に実装することができる。   The pseudo wafer 50A includes a plurality of electronic components 30, and includes a plurality of structural portions as shown in FIG. The pseudo wafer 50A on which the rewiring layer 60A is formed is diced at a position around the structure as shown in FIG. 1E, and is thereby separated into individual electronic component devices 1A. . The electronic component device 1A can be mounted on another electronic component device or a circuit board using the rewiring layer 60A.

上記のような電子部品装置１Ａに対し、その樹脂組成物層４０を貫通し、再配線層６０Ａに電気的に接続されるような導体、例えば貫通ビアを設けることもできる。このような貫通ビアを設けると、樹脂組成物層４０の、再配線層６０Ａと反対側の面に露出する貫通ビアを端子に用いることが可能になる。また、貫通ビアを設けると、樹脂組成物層４０の、再配線層６０Ａと反対側の面に、貫通ビアでその再配線層６０Ａと電気的に接続される別の再配線層を形成し、その再配線層に端子を設けることも可能になる。貫通ビアを設けることで得られる端子を利用することで、その電子部品装置１Ａの上にも他の電子部品装置を実装することができるようになるため、高密度実装を実現することが可能になる。   For the electronic component device 1A as described above, a conductor that penetrates through the resin composition layer 40 and is electrically connected to the rewiring layer 60A, for example, a through via, may be provided. When such a through via is provided, the through via exposed on the surface of the resin composition layer 40 opposite to the rewiring layer 60A can be used as a terminal. Further, when the through via is provided, another rewiring layer electrically connected to the rewiring layer 60A through the through via is formed on the surface of the resin composition layer 40 opposite to the rewiring layer 60A. It is also possible to provide terminals in the rewiring layer. By using the terminal obtained by providing the through via, it becomes possible to mount another electronic component device on the electronic component device 1A, so that high-density mounting can be realized. Become.

貫通ビアを樹脂組成物層４０に形成する方法として、樹脂組成物層４０にレーザー加工で貫通孔を形成し、その貫通孔を導電材料で埋め込む方法が考えられる。しかし、この方法では、レーザー加工を行う樹脂組成物層４０の厚みによっては、そのレーザー加工に要する時間が長くなったり、貫通孔への導電材料の埋め込みに要する時間が長くなったりする場合がある。   As a method of forming the through via in the resin composition layer 40, a method of forming a through hole in the resin composition layer 40 by laser processing and embedding the through hole with a conductive material can be considered. However, in this method, depending on the thickness of the resin composition layer 40 on which laser processing is performed, the time required for the laser processing may be increased, or the time required for embedding the conductive material in the through hole may be increased. .

また、別の方法として、樹脂組成物層４０内に電子部品３０と共に柱状導体を設け、これを貫通ビアとして用いる方法も考えられる。以下に、このような柱状導体を用いる方法について説明する。   As another method, a method in which a columnar conductor is provided together with the electronic component 30 in the resin composition layer 40 and this is used as a through via is also conceivable. Hereinafter, a method using such a columnar conductor will be described.

図３及び図４は電子部品装置の製造方法の別例を示す図である。尚、図３（Ａ）〜図３（Ｃ）はそれぞれ、電子部品装置の各製造工程の要部断面模式図である。図４は、図３（Ａ）に示す製造工程の平面模式図である。   3 and 4 are diagrams showing another example of a method for manufacturing an electronic component device. 3A to 3C are schematic cross-sectional views of the main part of each manufacturing process of the electronic component device. FIG. 4 is a schematic plan view of the manufacturing process shown in FIG.

この方法では、図３（Ａ）及び図４に示すように、支持体１０上に設けられた粘着層２０の上に、電極パッド（導電パターン）７０Ａを設ける。粘着層２０上には、例えば、複数の導電パターン７０Ａが、後述のように柱状導体８０を設ける位置にそれぞれ設けられる。導電パターン７０Ａには、銅等の金属材料が用いられる。   In this method, as shown in FIGS. 3A and 4, an electrode pad (conductive pattern) 70 </ b> A is provided on the adhesive layer 20 provided on the support 10. On the adhesive layer 20, for example, a plurality of conductive patterns 70 </ b> A are provided at positions where columnar conductors 80 are provided as will be described later. A metal material such as copper is used for the conductive pattern 70A.

導電パターン７０Ａを設けた後、図３（Ｂ）に示すように、粘着層２０上に半導体チップ等の電子部品３０を設け、粘着層２０上の導電パターン７０Ａの上に柱状導体８０を設ける。電子部品３０は、その電極面３０ａが粘着層２０に貼付され、柱状導体８０は、導電材料９０を用いて、導電パターン７０Ａ上に立てて接合される。柱状導体８０には、導電性のピン、例えば、銅等の金属ピンが用いられる。導電材料９０には、例えば、半田等の金属材料、金属材料を用いた導電性ペーストが用いられる。   After providing the conductive pattern 70A, as shown in FIG. 3B, an electronic component 30 such as a semiconductor chip is provided on the adhesive layer 20, and a columnar conductor 80 is provided on the conductive pattern 70A on the adhesive layer 20. As for the electronic component 30, the electrode surface 30a is affixed on the adhesion layer 20, and the columnar conductor 80 is joined upright on the conductive pattern 70A using the conductive material 90. For the columnar conductor 80, a conductive pin, for example, a metal pin such as copper is used. As the conductive material 90, for example, a metal material such as solder, or a conductive paste using a metal material is used.

上記のようにして粘着層２０上に電子部品３０並びに、導電パターン７０、導電材料９０及び柱状導体８０が設けられた後、その粘着層２０上に、図３（Ｃ）に示すように、樹脂組成物層４０を設ける。しかし、この樹脂組成物層４０を上記同様モールド成型によって設けようとすると、図３（Ｃ）に示すように、柱状導体８０が、導電材料９０で接合された導電パターン７０Ａと共に、モールド成型時に加圧される樹脂組成物に押されて倒れてしまう場合がある。   After the electronic component 30, the conductive pattern 70, the conductive material 90, and the columnar conductor 80 are provided on the adhesive layer 20 as described above, a resin is formed on the adhesive layer 20 as shown in FIG. A composition layer 40 is provided. However, if the resin composition layer 40 is provided by molding as described above, the columnar conductor 80 is added together with the conductive pattern 70A joined by the conductive material 90 at the time of molding as shown in FIG. There is a case where the resin composition is pressed and falls down.

この原因として、樹脂組成物が樹脂にフィラーを含有しているため比較的その粘度が高いこと、及び、柱状導体８０の断面サイズに合わせたサイズの導電パターン７０Ａを設けると導電パターン７０Ａと粘着層２０の接着面積が小さいこと等を挙げることができる。一方、半田等の導電材料９０で接合される柱状導体８０と導電パターン７０Ａとの接合強度は、導電パターン７０Ａと粘着層２０との接着強度に比べると高い。そのため、柱状導体８０が、モールド成型時に加圧される比較的粘度の高い樹脂組成物に押され、柱状導体８０を導電材料９０で接合した導電パターン７０Ａが粘着層２０から剥がれ、柱状導体８０が倒れてしまう。   This is because the resin composition contains a filler in the resin and thus has a relatively high viscosity, and when the conductive pattern 70A having a size matching the cross-sectional size of the columnar conductor 80 is provided, the conductive pattern 70A and the adhesive layer The adhesion area of 20 is small. On the other hand, the bonding strength between the columnar conductor 80 bonded to the conductive material 90 such as solder and the conductive pattern 70A is higher than the bonding strength between the conductive pattern 70A and the adhesive layer 20. Therefore, the columnar conductor 80 is pressed by a resin composition having a relatively high viscosity that is pressed during molding, and the conductive pattern 70A in which the columnar conductor 80 is bonded with the conductive material 90 is peeled off from the adhesive layer 20, and the columnar conductor 80 is removed. It falls down.

１枚の擬似ウェハ５０Ａについて、このようなモールド成型時の導電パターン７０Ａの剥離によって全ての柱状導体８０が倒れてしまう場合や、倒れたり倒れなかったりした柱状導体８０が混在する場合が起こり得る。また、擬似ウェハ５０Ａ内の１つの電子部品装置に相当する構造部内に、倒れた柱状導体８０と倒れなかった柱状導体８０が混在する場合等が起こり得る。図３及び図４に示すような方法では、柱状導体８０を上記のように貫通ビアとして用いる電子部品装置を、安定的に製造することができない場合がある。   With respect to one pseudo wafer 50A, there may be a case where all the columnar conductors 80 are collapsed due to the peeling of the conductive pattern 70A at the time of such molding, or a case where the columnar conductors 80 are collapsed or not collapsed. In addition, there may be a case in which the columnar conductor 80 that has fallen and the columnar conductor 80 that has not collapsed coexist in a structure corresponding to one electronic component device in the pseudo wafer 50A. In the method as shown in FIGS. 3 and 4, an electronic component device using the columnar conductor 80 as a through via as described above may not be manufactured stably.

そこで、このようなモールド成型時の柱状導体８０の倒れに鑑み、以下に実施の形態として示すような方法を用いる。
図５〜図１３は第１の実施の形態に係る電子部品装置の製造方法の説明図である。以下、図５〜図１３を参照して、第１の実施の形態に係る電子部品装置の製造方法の一例について説明する。 Therefore, in view of such collapse of the columnar conductor 80 during molding, a method as described below as an embodiment is used.
5-13 is explanatory drawing of the manufacturing method of the electronic component apparatus based on 1st Embodiment. Hereinafter, an example of a method for manufacturing the electronic component device according to the first embodiment will be described with reference to FIGS.

図５（Ａ）は第１の実施の形態に係る粘着層配設工程の要部断面模式図、図５（Ｂ）は第１の実施の形態に係る導電膜配設工程の要部断面模式図、図５（Ｃ）は第１の実施の形態に係る電子部品及び柱状導体配設工程の要部断面模式図である。図６（Ａ）〜図６（Ｃ）はそれぞれ、図５（Ａ）〜図５（Ｃ）に示す各製造工程の平面模式図である。   FIG. 5A is a schematic cross-sectional view of the main part of the adhesive layer disposing step according to the first embodiment, and FIG. 5B is a schematic cross-sectional view of the main part of the conductive film disposing step according to the first embodiment. FIG. 5C is a schematic cross-sectional view of the main part of the electronic component and columnar conductor arranging step according to the first embodiment. 6 (A) to 6 (C) are schematic plan views of the respective manufacturing steps shown in FIGS. 5 (A) to 5 (C).

この方法では、上記同様、図５（Ａ）及び図６（Ａ）に示すように、支持体１０上に粘着層２０を設けた後、図５（Ｂ）及び図６（Ｂ）に示すように、粘着層２０上に、開口部７１を有する導電膜７０ａを設ける。導電膜７０ａには、金属膜を用いることができる。導電膜７０ａとして用いる金属膜には、銅のほか、アルミニウム、ニッケル等の金属材料が用いられる。導電膜７０ａの開口部７１は、半導体チップ等の電子部品３０を配置する領域に設けられる。   In this method, as shown above, as shown in FIGS. 5 (A) and 6 (A), after the adhesive layer 20 is provided on the support 10, as shown in FIGS. 5 (B) and 6 (B). In addition, a conductive film 70 a having an opening 71 is provided on the adhesive layer 20. A metal film can be used for the conductive film 70a. In addition to copper, a metal material such as aluminum or nickel is used for the metal film used as the conductive film 70a. The opening 71 of the conductive film 70a is provided in a region where the electronic component 30 such as a semiconductor chip is disposed.

金属膜を導電膜７０ａとして形成する場合、導電膜７０ａは、粘着層２０上に金属箔や金属板を貼付したり、スパッタ法や蒸着法により堆積したりすることで、形成することができる。このような方法を用いて導電膜７０ａを粘着層２０上に形成した後、その導電膜７０ａに開口部７１を形成する。開口部７１は、粘着層２０上の導電膜７０ａに対するエッチング加工により、形成することができる。導電膜７０ａの材料には、良好な導電性を有すると共に、このようなエッチング加工が比較的容易に行える上記のような銅、アルミニウム、ニッケル等の材料が好適である。   When the metal film is formed as the conductive film 70a, the conductive film 70a can be formed by attaching a metal foil or a metal plate on the adhesive layer 20, or depositing the film by a sputtering method or a vapor deposition method. After the conductive film 70a is formed on the adhesive layer 20 using such a method, the opening 71 is formed in the conductive film 70a. The opening 71 can be formed by etching the conductive film 70 a on the adhesive layer 20. The material of the conductive film 70a is preferably a material such as copper, aluminum, or nickel as described above, which has good conductivity and can perform such etching process relatively easily.

尚、開口部７１を有する導電膜７０ａを粘着層２０上に設ける方法としては、このほか、予め開口部７１を設けた金属箔等の導電膜７０ａを準備し、それを粘着層２０上に貼付する方法を用いることもできる。   In addition, as a method of providing the conductive film 70 a having the opening 71 on the adhesive layer 20, a conductive film 70 a such as a metal foil provided with the opening 71 in advance is prepared, and this is applied to the adhesive layer 20. It is also possible to use a method of

上記のようにして粘着層２０上に導電膜７０ａを設けた後、図５（Ｃ）及び図６（Ｃ）に示すように、その導電膜７０ａの開口部７１に露出する粘着層２０上に、電子部品３０をその電極面３０ａを粘着層２０側に向けて設ける。電子部品３０は、フリップチップボンダーやマウンターを用いて粘着層２０上に設けることができる。   After providing the conductive film 70a on the adhesive layer 20 as described above, as shown in FIGS. 5C and 6C, on the adhesive layer 20 exposed in the opening 71 of the conductive film 70a. The electronic component 30 is provided with the electrode surface 30a facing the adhesive layer 20 side. The electronic component 30 can be provided on the adhesive layer 20 using a flip chip bonder or a mounter.

導電膜７０ａ上には、図５（Ｃ）及び図６（Ｃ）に示すように、柱状導体８０を、導電材料９０を用いて接合する。柱状導体８０は、例えば、開口部７１の粘着層２０上に設けられる電子部品３０の周囲に、導電膜７０ａ上の所定の位置に立てて、設ける。柱状導体８０を設ける位置は、導電膜７０ａの開口部７１の位置（例えば開口部７１の角）を基準にして、設定することができる。   As shown in FIGS. 5C and 6C, a columnar conductor 80 is bonded onto the conductive film 70 a using a conductive material 90. The columnar conductor 80 is provided, for example, in a predetermined position on the conductive film 70a around the electronic component 30 provided on the adhesive layer 20 of the opening 71. The position where the columnar conductor 80 is provided can be set based on the position of the opening 71 of the conductive film 70a (for example, the corner of the opening 71).

柱状導体８０は、例えば、次の図７又は図８に示すような方法を用いて導電膜７０ａ上に設けることができる。
図７は柱状導体配置方法の第１の例を示す図である。 The columnar conductor 80 can be provided on the conductive film 70a using, for example, a method as shown in FIG. 7 or FIG.
FIG. 7 is a diagram showing a first example of a columnar conductor arrangement method.

この方法では、まず図７（Ａ）に示すような、ステンレス等の金属板１１０ａに貫通孔１１０ｂを形成した金型１１０を準備する。このような金型１１０を、支持体１０上の粘着層２０の上に設けられた導電膜７０ａに対向させて配置する。柱状導体８０の片側の先端部には、図７（Ｂ）に示すように、予め半田等の導電材料９０を設ける。このように先端部に導電材料９０を設けた柱状導体８０を、金型１１０の貫通孔１１０ｂに挿通し、導電材料９０の溶融、凝固により、導電膜７０ａ上に接合する。   In this method, first, as shown in FIG. 7A, a mold 110 in which a through hole 110b is formed in a metal plate 110a such as stainless steel is prepared. Such a mold 110 is disposed so as to face the conductive film 70 a provided on the adhesive layer 20 on the support 10. As shown in FIG. 7B, a conductive material 90 such as solder is provided in advance at one end of the columnar conductor 80. Thus, the columnar conductor 80 having the conductive material 90 provided at the tip portion is inserted into the through hole 110b of the mold 110 and joined to the conductive film 70a by melting and solidification of the conductive material 90.

尚、ここでは柱状導体８０の先端部に予め導電材料９０を設け、それを金型１１０の貫通孔１１０ｂに挿通する場合を例示した。このほか、導電材料９０は、予め導電膜７０ａ上に設けておき、金型１１０の貫通孔１１０ｂには単体の柱状導体８０を挿通し、導電材料９０の溶融と凝固により、柱状導体８０を導電膜７０ａ上に接合するようにしてもよい。貫通孔１１０ｂは、先端部に導電材料９０が設けられた柱状導体８０或いは単体の柱状導体８０が挿通可能な内径とされる。   Here, the case where the conductive material 90 is provided in advance at the tip of the columnar conductor 80 and is inserted into the through hole 110b of the mold 110 is illustrated. In addition, the conductive material 90 is provided in advance on the conductive film 70 a, and a single columnar conductor 80 is inserted into the through hole 110 b of the mold 110, and the columnar conductor 80 is made conductive by melting and solidifying the conductive material 90. You may make it join on the film | membrane 70a. The through hole 110b has an inner diameter through which the columnar conductor 80 provided with the conductive material 90 at the tip or a single columnar conductor 80 can be inserted.

図８は柱状導体配置方法の第２の例を示す図である。
この方法では、図８（Ａ）に示すような柱状導体８０を用いる。図８（Ａ）に示す柱状導体８０は、軸部８１と、それよりも大径の頭部８２を有する。頭部８２には、予め半田等の導電材料９０を設ける。このような柱状導体８０の軸部８１を、ステンレス等の金属板１２０ａに貫通孔１２０ｂを形成した金型１２０の、その貫通孔１２０ｂに挿入する。貫通孔１２０ｂは、柱状導体８０の頭部８２よりも小径とされ、貫通孔１２０ｂに上方から軸部８１が挿入された柱状導体８０は、その頭部８２で金型１２０の上面に引っ掛かり、支持される。 FIG. 8 is a diagram showing a second example of the columnar conductor arrangement method.
In this method, a columnar conductor 80 as shown in FIG. A columnar conductor 80 shown in FIG. 8A has a shaft portion 81 and a head portion 82 having a diameter larger than that of the shaft portion 81. A conductive material 90 such as solder is provided on the head 82 in advance. The shaft portion 81 of the columnar conductor 80 is inserted into the through hole 120b of the mold 120 in which the through hole 120b is formed in the metal plate 120a such as stainless steel. The through hole 120b has a smaller diameter than the head portion 82 of the columnar conductor 80, and the columnar conductor 80 in which the shaft portion 81 is inserted into the through hole 120b from above is hooked on the upper surface of the mold 120 and supported by the head portion 82. Is done.

図８（Ａ）に示すように、粘着層２０及び導電膜７０ａが設けられた支持体１０は、柱状導体８０及び導電材料９０を設けた金型１２０の上方（柱状導体８０の頭部８２側）に、導電膜７０ａと金型１２０が対向するように配置される。そして、例えば、柱状導体８０及び導電材料９０を設けた金型１２０を導電膜７０ａ側に押圧し、導電材料９０の溶融、凝固により、図８（Ｂ）に示すように、柱状導体８０を導電材料９０で導電膜７０ａ上に接合する。   As shown in FIG. 8A, the support 10 provided with the adhesive layer 20 and the conductive film 70a is above the mold 120 provided with the columnar conductor 80 and the conductive material 90 (on the head 82 side of the columnar conductor 80). ) Is disposed so that the conductive film 70a and the mold 120 face each other. Then, for example, the mold 120 provided with the columnar conductor 80 and the conductive material 90 is pressed toward the conductive film 70a, and the conductive material 90 is melted and solidified to conduct the columnar conductor 80 as shown in FIG. The material 90 is bonded onto the conductive film 70a.

図５（Ｃ）及び図６（Ｃ）に示す工程では、この図７又は図８のような方法を用いて、柱状導体８０を導電材料９０で導電膜７０ａ上に接合することができる。
導電材料９０には、半田等、比較的低融点の金属材料が用いられる。導電材料９０に用いる金属材料としては、例えば、錫、鉛、銀、銅、ビスマス、アンチモン、インジウムのうち少なくとも１種を含む材料を用いることが好ましい。更に、導電材料９０には、柱状導体８０と導電膜７０ａとの接合時に、溶融によって融点がその溶融前の融点よりも高温側にシフトするような金属材料を用いることが好ましい。例えば、予め導電材料９０に、接合時の溶融、凝固によって、その融点が高温側にシフトするような成分を所定濃度含めておく。 In the steps shown in FIGS. 5C and 6C, the columnar conductor 80 can be bonded to the conductive film 70a with the conductive material 90 by using the method shown in FIG. 7 or FIG.
As the conductive material 90, a metal material having a relatively low melting point such as solder is used. As the metal material used for the conductive material 90, for example, a material containing at least one of tin, lead, silver, copper, bismuth, antimony, and indium is preferably used. Further, as the conductive material 90, it is preferable to use a metal material whose melting point shifts to a higher temperature side than the melting point before melting when the columnar conductor 80 and the conductive film 70a are joined. For example, the conductive material 90 includes in advance a predetermined concentration of a component whose melting point shifts to a high temperature side due to melting and solidification during bonding.

柱状導体８０は、開口部７１の粘着層２０上に電子部品３０を設けた後、導電膜７０ａ上に導電材料９０で接合することができる。或いは、導電膜７０ａ上に導電材料９０で柱状導体８０を接合した後、開口部７１の粘着層２０上に電子部品３０を設けることもできる。   The columnar conductor 80 can be bonded to the conductive film 70 a with the conductive material 90 after the electronic component 30 is provided on the adhesive layer 20 of the opening 71. Alternatively, after the columnar conductor 80 is bonded to the conductive film 70 a with the conductive material 90, the electronic component 30 can be provided on the adhesive layer 20 in the opening 71.

尚、図５（Ｃ）には１つの電子部品３０を図示するが、粘着層２０上には、図６（Ｃ）に示すように、複数（ここでは一例として４つ）の電子部品３０が、それぞれ所定の箇所に、図５（Ｃ）と同様に各電極面３０ａを粘着層２０側に向けて設けられる。各電子部品３０の周囲に複数の柱状導体８０が設けられる。柱状導体８０の個数、配置は、図６（Ｃ）の例に限定されるものではない。尚、ここでは便宜上、１つの電子部品３０とその周囲の柱状導体８０に着目し、続く図９及び図１０の工程について説明する。   FIG. 5C shows one electronic component 30, but a plurality (four as an example) of electronic components 30 are provided on the adhesive layer 20 as shown in FIG. 6C. As in FIG. 5C, each electrode surface 30a is provided at a predetermined location, facing the adhesive layer 20 side. A plurality of columnar conductors 80 are provided around each electronic component 30. The number and arrangement of the columnar conductors 80 are not limited to the example of FIG. Here, for the sake of convenience, attention is focused on one electronic component 30 and the columnar conductor 80 around it, and the subsequent steps of FIGS. 9 and 10 will be described.

図９（Ａ）は第１の実施の形態に係る樹脂組成物層形成工程の要部断面模式図、図９（Ｂ）は第１の実施の形態に係る擬似ウェハ分離工程の要部断面模式図、図９（Ｃ）は第１の実施の形態に係るレジストパターン形成工程の要部断面模式図、図９（Ｄ）は第１の実施の形態に係る導電パターン形成工程の要部断面模式図である。図１０（Ａ）は第１の実施の形態に係るバックグラインド工程の要部断面模式図、図１０（Ｂ）は第１の実施の形態に係る第１再配線層形成工程の要部断面模式図、図１０（Ｃ）は第１の実施の形態に係る第２再配線層形成工程の要部断面模式図である。   FIG. 9A is a schematic cross-sectional view of an essential part of a resin composition layer forming step according to the first embodiment, and FIG. 9B is a schematic cross-sectional view of an essential part of a pseudo wafer separation process according to the first embodiment. FIG. 9C is a schematic cross-sectional view of the relevant part of the resist pattern forming process according to the first embodiment, and FIG. 9D is a schematic cross-sectional view of the relevant part of the conductive pattern forming process according to the first embodiment. FIG. 10A is a schematic cross-sectional view of the main part of the back grinding process according to the first embodiment, and FIG. 10B is a schematic cross-sectional view of the main part of the first redistribution layer forming process according to the first embodiment. FIG. 10C is a schematic cross-sectional view of the relevant part in the second rewiring layer forming step according to the first embodiment.

上記図５（Ｃ）及び図６（Ｃ）のように、導電膜７０ａの開口部７１の粘着層２０上に電子部品３０を設け、導電膜７０ａ上に導電材料９０で柱状導体８０を設けた後、図９（Ａ）に示すように、それらを被覆する樹脂組成物層４０を形成する。樹脂組成物層４０は、上記同様、絶縁性の樹脂及びフィラーを含む樹脂組成物をモールド成型することで形成する。樹脂組成物層４０は、その樹脂の種類に応じた手法で硬化又は半硬化される。これにより、粘着層２０上の導電膜７０ａ、その開口部７１に設けられた電子部品３０、及び導電膜７０ａ上に導電材料９０で接合された柱状導体８０が、樹脂組成物層４０で被覆された擬似ウェハ５０が、粘着層２０上に形成される。   5C and 6C, the electronic component 30 is provided on the adhesive layer 20 in the opening 71 of the conductive film 70a, and the columnar conductor 80 is provided with the conductive material 90 on the conductive film 70a. Thereafter, as shown in FIG. 9A, a resin composition layer 40 covering them is formed. The resin composition layer 40 is formed by molding a resin composition containing an insulating resin and a filler as described above. The resin composition layer 40 is cured or semi-cured by a method according to the type of the resin. As a result, the conductive film 70a on the adhesive layer 20, the electronic component 30 provided in the opening 71 thereof, and the columnar conductor 80 bonded to the conductive film 70a with the conductive material 90 are covered with the resin composition layer 40. The pseudo wafer 50 is formed on the adhesive layer 20.

ここで、柱状導体８０は、導電材料９０で導電膜７０ａ上に接合されており、この導電膜７０ａは、上記の図３及び図４に示したような導電パターン７０Ａに比べ、より大きな面積で粘着層２０に接着されている。そのため、導電膜７０ａ上に導電材料９０で接合された柱状導体８０が、モールド成型時に比較的粘度の高い樹脂組成物で押されても、導電膜７０ａの粘着層２０からの剥離が抑えられ、柱状導体８０の倒れが抑えられる。これにより、擬似ウェハ５０内、或いは擬似ウェハ５０内の１つの電子部品装置に相当する構造部内に、倒れた柱状導体８０が含まれるような事態を効果的に抑制することができる。   Here, the columnar conductor 80 is joined to the conductive film 70a by the conductive material 90. The conductive film 70a has a larger area than the conductive pattern 70A as shown in FIGS. Bonded to the adhesive layer 20. Therefore, even if the columnar conductor 80 joined with the conductive material 90 on the conductive film 70a is pressed with a relatively high viscosity resin composition at the time of molding, peeling of the conductive film 70a from the adhesive layer 20 is suppressed, The collapse of the columnar conductor 80 is suppressed. Thereby, the situation where the fallen columnar conductor 80 is contained in the pseudo wafer 50 or the structure part corresponding to one electronic component device in the pseudo wafer 50 can be effectively suppressed.

樹脂組成物層４０の形成後、図９（Ｂ）に示すように、擬似ウェハ５０を粘着層２０から分離する。例えば、粘着層２０に対し、その粘着力を低下させる処理（加熱、紫外線照射等）を行い、擬似ウェハ５０を粘着層２０から剥離する。粘着層２０から剥離された擬似ウェハ５０の一面（表面５０ａ）には、導電膜７０ａ、及び電子部品３０の電極面３０ａが露出する。   After the formation of the resin composition layer 40, the pseudo wafer 50 is separated from the adhesive layer 20 as shown in FIG. For example, the adhesive layer 20 is subjected to a process for reducing the adhesive force (heating, ultraviolet irradiation, etc.), and the pseudo wafer 50 is peeled from the adhesive layer 20. The conductive film 70 a and the electrode surface 30 a of the electronic component 30 are exposed on one surface (surface 50 a) of the pseudo wafer 50 that is peeled from the adhesive layer 20.

擬似ウェハ５０の剥離後、図９（Ｃ）に示すように、擬似ウェハ５０の、導電膜７０ａが露出する表面５０ａ上に、レジストパターン１３０を形成する。レジストパターン１３０は、導電膜７０ａ上で、擬似ウェハ５０内の柱状導体８０に対応する部分を含む領域に、形成される。レジストパターン１３０は、導電膜７０ａの開口部７１の位置を基準にして、柱状導体８０に対応する部分を含む領域に形成される。また、レジストパターン１３０は、導電膜７０ａと共に露出する電子部品３０の上にも形成される。   After peeling off the pseudo wafer 50, as shown in FIG. 9C, a resist pattern 130 is formed on the surface 50a of the pseudo wafer 50 where the conductive film 70a is exposed. The resist pattern 130 is formed in a region including a portion corresponding to the columnar conductor 80 in the pseudo wafer 50 on the conductive film 70a. The resist pattern 130 is formed in a region including a portion corresponding to the columnar conductor 80 with reference to the position of the opening 71 of the conductive film 70a. The resist pattern 130 is also formed on the electronic component 30 exposed together with the conductive film 70a.

レジストパターン１３０の形成後、そのレジストパターン１３０をマスクにして導電膜７０ａのエッチングを行い、図９（Ｄ）に示すように、柱状導体８０に対応する部分を含む領域に、導電パターン７０を形成する。導電パターン７０の形成は、ウェットエッチングで行うことができる。ウェットエッチングの際、図９（Ｃ）に示したように、導電パターン７０の形成領域のほか、電子部品３０の上にもレジストパターン１３０を設けておくことで、電子部品３０の電極面３０ａがエッチング液から保護される。   After the resist pattern 130 is formed, the conductive film 70a is etched using the resist pattern 130 as a mask, and the conductive pattern 70 is formed in a region including a portion corresponding to the columnar conductor 80 as shown in FIG. 9D. To do. The conductive pattern 70 can be formed by wet etching. During wet etching, as shown in FIG. 9C, by providing a resist pattern 130 on the electronic component 30 in addition to the region where the conductive pattern 70 is formed, the electrode surface 30a of the electronic component 30 is formed. Protected from etchant.

図９（Ｄ）の工程で形成する導電パターン７０としては、柱状導体８０に対応する部分に設けられる電極パッドを形成することができる。また、導電パターン７０として、柱状導体８０に対応する部分に設けられる電極パッドと、その電極パッドから延在された配線とを形成することもできる。更にまた、このような電極パッド、或いは電極パッドから延在された配線のほか、柱状導体８０に対応する部分からは独立した配線を導電パターン７０として形成することもできる。図９（Ｃ）の工程では、この図９（Ｄ）の工程で所定の導電パターン７０が形成されるように、レジストパターン１３０が形成される。導電パターン７０の形成後、レジストパターン１３０は除去される。   As the conductive pattern 70 formed in the step of FIG. 9D, an electrode pad provided in a portion corresponding to the columnar conductor 80 can be formed. In addition, as the conductive pattern 70, an electrode pad provided in a portion corresponding to the columnar conductor 80 and a wiring extending from the electrode pad can be formed. Furthermore, in addition to such an electrode pad or a wiring extending from the electrode pad, a wiring independent from a portion corresponding to the columnar conductor 80 can be formed as the conductive pattern 70. In the step of FIG. 9C, the resist pattern 130 is formed so that the predetermined conductive pattern 70 is formed in the step of FIG. 9D. After the formation of the conductive pattern 70, the resist pattern 130 is removed.

導電パターン７０の形成後、図１０（Ａ）に示すように、擬似ウェハ５０の、導電パターン７０の形成面（表面５０ａ）と反対側の面（裏面５０ｂ）を研削し、柱状導体８０を露出させる。その際は、柱状導体８０の端面が、電子部品３０の電極面３０ａと反対側の面（背面）３０ｂよりも高く残るようにすることが好ましい。これは、金属材料を用いた柱状導体８０と、半導体チップ等の電子部品３０とを同時に研削すると、柱状導体８０の研削屑が、電子部品３０の背面３０ｂに付着する可能性があるためである。電子部品３０の背面３０ｂに付着した柱状導体８０の研削屑は、例えば、その後加熱が行われた時に、その成分が電子部品３０の内部等に拡散する可能性があり、その場合、電子部品３０の性能劣化が生じる恐れがある。このようなことから、擬似ウェハ５０の研削は、柱状導体８０の端面が、電子部品３０の背面３０ｂよりも高い位置となるように、即ち、電子部品３０の背面３０ｂが樹脂組成物層４０で被覆されている状態の位置まで、行うことが好ましい。   After the formation of the conductive pattern 70, as shown in FIG. 10A, the surface (back surface 50b) opposite to the formation surface (front surface 50a) of the pseudo wafer 50 is ground to expose the columnar conductor 80. Let In that case, it is preferable that the end surface of the columnar conductor 80 remain higher than the surface (back surface) 30b on the side opposite to the electrode surface 30a of the electronic component 30. This is because if the columnar conductor 80 using a metal material and the electronic component 30 such as a semiconductor chip are ground at the same time, grinding scraps of the columnar conductor 80 may adhere to the back surface 30b of the electronic component 30. . The grinding scraps of the columnar conductor 80 adhering to the back surface 30b of the electronic component 30 may have its components diffused into the electronic component 30 or the like, for example, when heated thereafter. There is a risk of performance degradation. Thus, the grinding of the pseudo wafer 50 is performed so that the end surface of the columnar conductor 80 is positioned higher than the back surface 30b of the electronic component 30, that is, the back surface 30b of the electronic component 30 is the resin composition layer 40. It is preferable to carry out to the position of the coated state.

このように、導電パターン７０に導電材料９０で接合された柱状導体８０の端面を、擬似ウェハ５０の研削により、その表面５０ａと反対側の裏面５０ｂに露出させる。これにより、導電パターン７０、導電材料９０及び柱状導体８０を、擬似ウェハ５０を貫通する貫通ビアとして用いることが可能になる。   Thus, the end face of the columnar conductor 80 joined to the conductive pattern 70 with the conductive material 90 is exposed to the back surface 50b opposite to the front surface 50a by grinding the pseudo wafer 50. Accordingly, the conductive pattern 70, the conductive material 90, and the columnar conductor 80 can be used as a through via that penetrates the pseudo wafer 50.

尚、この図１０（Ａ）に示す、柱状導体８０を露出させる研削は、次の図１０（Ｂ）に示す再配線層６０の形成後に行うこともできる。
擬似ウェハ５０の表面５０ａ、即ち電子部品３０の電極面３０ａ及び導電パターン７０の形成面の側には、図１０（Ｂ）に示すように、再配線層６０を形成する。再配線層６０は、電子部品３０の電極３１及び導電パターン７０に電気的に接続されたビア及び配線等の導電部６１、並びに、導電部６１の周りに設けられた絶縁部６２を含む。導電部６１には、銅、銅合金、アルミニウム等の導電材料が用いられる。絶縁部６２には、エポキシ樹脂、ポリイミド樹脂等の絶縁材料が用いられる。擬似ウェハ５０では、電子部品３０の電極３１が、再配線層６０によってその電子部品３０のエリア外の端子６３に再配置（Fan-out）される。再配線層６０の導電部６１は、導電パターン７０、導電材料９０及び柱状導体８０によって、擬似ウェハ５０の裏面５０ｂに引き出される。 Note that the grinding for exposing the columnar conductor 80 shown in FIG. 10A can also be performed after the formation of the rewiring layer 60 shown in FIG. 10B.
A rewiring layer 60 is formed on the surface 50a of the pseudo wafer 50, that is, on the side of the electrode surface 30a of the electronic component 30 and the surface on which the conductive pattern 70 is formed, as shown in FIG. The rewiring layer 60 includes a conductive portion 61 such as a via and a wiring electrically connected to the electrode 31 and the conductive pattern 70 of the electronic component 30, and an insulating portion 62 provided around the conductive portion 61. For the conductive portion 61, a conductive material such as copper, copper alloy, or aluminum is used. An insulating material such as an epoxy resin or a polyimide resin is used for the insulating portion 62. In the pseudo wafer 50, the electrode 31 of the electronic component 30 is rearranged (Fan-out) by the rewiring layer 60 to the terminal 63 outside the area of the electronic component 30. The conductive portion 61 of the redistribution layer 60 is drawn to the back surface 50 b of the pseudo wafer 50 by the conductive pattern 70, the conductive material 90, and the columnar conductor 80.

擬似ウェハ５０上の再配線層６０は、例えば、次の図１１に示すような方法を用いて形成することができる。
図１１は再配線層の形成方法の一例を示す図である。ここでは、電子部品３０の電極３１及び導電パターン７０に電気的に接続される導電部６１を例に、再配線層６０の形成方法を説明する。図１１（Ａ）〜図１１（Ｅ）は再配線層の各形成工程の要部断面模式図である。 The rewiring layer 60 on the pseudo wafer 50 can be formed, for example, using a method as shown in FIG.
FIG. 11 is a diagram illustrating an example of a method for forming a rewiring layer. Here, a method of forming the rewiring layer 60 will be described by taking the conductive portion 61 electrically connected to the electrode 31 and the conductive pattern 70 of the electronic component 30 as an example. FIG. 11A to FIG. 11E are schematic cross-sectional views of the relevant part in each step of forming the rewiring layer.

まず図１１（Ａ）に示すように、擬似ウェハ５０の表面５０ａ側、即ち電子部品３０の電極面３０ａ及び導電パターン７０の側に、感光性エポキシ、感光性ポリベンゾオキサゾール、感光性ポリイミド等の感光性樹脂６２ａを塗布する。そして、塗布した感光性樹脂６２ａの露光、現像、キュアを行い、電子部品３０の電極３１に通じる開口部６２ｂ、及び導電パターン７０に通じる開口部６２ｃを形成する。尚、感光性樹脂６２ａのキュア後にはプラズマ処理を行ってもよい。   First, as shown in FIG. 11A, photosensitive epoxy, photosensitive polybenzoxazole, photosensitive polyimide, or the like is formed on the surface 50a side of the pseudo wafer 50, that is, on the electrode surface 30a and the conductive pattern 70 side of the electronic component 30. Photosensitive resin 62a is applied. Then, the applied photosensitive resin 62 a is exposed, developed, and cured to form an opening 62 b that communicates with the electrode 31 of the electronic component 30 and an opening 62 c that communicates with the conductive pattern 70. Note that plasma treatment may be performed after the photosensitive resin 62a is cured.

次いで、チタン、クロム等の金属密着層と、銅をスパッタ法で形成し、シード層を形成する。その後、ビア及び配線が形成される部分を開口したレジストパターン（図示せず）を形成し、先に形成したシード層を用いた銅の電気めっきを行う。そして、レジストパターンの剥離後、そのレジストパターンが形成されていた領域に残存するシード層をエッチングにより除去する。エッチングには、ウェットエッチングを用いてもよいし、ドライエッチングを用いてもよい。このようにして、図１１（Ｂ）に示すような、電子部品３０の電極３１に繋がるビア６１ａ及び配線６１ｂを形成する。配線６１ｂには、密着性向上等の目的で、更に表面処理を行ってもよい。図１１（Ａ）及び図１１（Ｂ）に示すような方法により、擬似ウェハ５０の表面５０ａ側に、第１層目の配線層が形成される。   Next, a metal adhesion layer such as titanium or chromium and copper are formed by a sputtering method to form a seed layer. Thereafter, a resist pattern (not shown) having an opening at a portion where vias and wirings are formed is formed, and copper electroplating is performed using the previously formed seed layer. After the resist pattern is peeled off, the seed layer remaining in the region where the resist pattern has been formed is removed by etching. For the etching, wet etching or dry etching may be used. In this way, vias 61a and wirings 61b connected to the electrodes 31 of the electronic component 30 are formed as shown in FIG. The wiring 61b may be further subjected to a surface treatment for the purpose of improving adhesion. A first wiring layer is formed on the surface 50a side of the pseudo wafer 50 by the method as shown in FIGS. 11A and 11B.

第２層目の配線層を形成する場合は、第１層目の配線層上に、上記同様、図１１（Ｃ）に示すように、感光性樹脂６２ｄの塗布、露光、現像、キュアを行い、配線６１ｂに通じる開口部６２ｅを形成する。次いで、上記同様、シード層の形成、レジストパターンの形成、銅の電気めっき、レジストパターンの剥離、シード層のエッチングを行い、図１１（Ｄ）に示すようなビア６１ｃ及び配線６１ｄを形成する。図１１（Ｃ）及び図１１（Ｄ）に示すような方法により、擬似ウェハ５０の表面５０ａ側に、第２層目の配線層が形成される。   When the second wiring layer is formed, the photosensitive resin 62d is applied, exposed, developed, and cured as shown in FIG. 11C on the first wiring layer, as described above. Then, an opening 62e communicating with the wiring 61b is formed. Next, similarly to the above, formation of a seed layer, formation of a resist pattern, electroplating of copper, peeling of the resist pattern, and etching of the seed layer are performed to form a via 61c and a wiring 61d as shown in FIG. A second wiring layer is formed on the surface 50a side of the pseudo wafer 50 by a method as shown in FIGS. 11C and 11D.

擬似ウェハ５０の表面５０ａ側に３層目以降の配線層を形成する場合には、上記の図１１（Ａ）及び図１１（Ｂ）に示した工程（或いは上記の図１１（Ｃ）及び図１１（Ｄ）に示した工程）と同様の工程を繰り返せばよい。   When the third and subsequent wiring layers are formed on the front surface 50a side of the pseudo wafer 50, the steps shown in FIGS. 11A and 11B (or FIGS. 11C and 11B described above) are performed. Steps similar to those shown in FIG. 11 (D) may be repeated.

再配線層６０の最表面の配線層、この例では第２層目の配線６１ｄ上には、図１１（Ｅ）に示すように、配線６１ｄの一部（外部接続端子）が露出するように保護膜（ソルダーレジスト）６２ｆを形成する。保護膜６２ｆから露出する配線６１ｄの領域には、例えば、図１１（Ｅ）に示すように、ニッケル６１ｅと金６１ｆの表面処理を行ってもよい。外部接続端子として機能する配線６１ｄの領域（ニッケル６１ｅと金６１ｆの表面処理を行った場合はその処理後の表面）には、例えば、半田ボール等のバンプ（図示せず）が搭載される。   As shown in FIG. 11E, a part (external connection terminal) of the wiring 61d is exposed on the outermost wiring layer of the rewiring layer 60, in this example, the wiring 61d of the second layer. A protective film (solder resist) 62f is formed. For example, as shown in FIG. 11E, surface treatment of nickel 61e and gold 61f may be performed on the region of the wiring 61d exposed from the protective film 62f. For example, bumps (not shown) such as solder balls are mounted on the region of the wiring 61d functioning as the external connection terminal (the surface after the surface treatment of the nickel 61e and the gold 61f).

図１０（Ｂ）に示すように、擬似ウェハ５０の表面５０ａ側に再配線層６０を形成する場合には、擬似ウェハ５０の裏面５０ｂ側に露出する柱状導体８０の端面は、外部接続端子として利用することができる。   As shown in FIG. 10B, when the rewiring layer 60 is formed on the front surface 50a side of the pseudo wafer 50, the end surface of the columnar conductor 80 exposed on the back surface 50b side of the pseudo wafer 50 serves as an external connection terminal. Can be used.

擬似ウェハ５０には、このように表面５０ａ側に再配線層６０を形成することができるほか、更に図１０（Ｃ）に示すように、裏面５０ｂ側にも同様にして再配線層６０を形成することができる。   In the pseudo wafer 50, the rewiring layer 60 can be formed on the front surface 50a side as described above. Further, as shown in FIG. 10C, the rewiring layer 60 is similarly formed on the back surface 50b side. can do.

この場合は、擬似ウェハ５０の裏面５０ｂ側に対し、上記の図１１（Ａ）と同様に、感光性樹脂の塗布、露光、現像、キュアを行い、柱状導体８０に通じる開口部を形成する。そして、上記の図１１（Ｂ）と同様に、シード層の形成、レジストパターンの形成、銅の電気めっき、レジストパターンの剥離、シード層のエッチングを行い、ビア及び配線を形成する。これにより、擬似ウェハ５０の裏面５０ｂ側に、第１層目の配線層が形成される。擬似ウェハ５０の裏面５０ｂ側に２層目以降の配線層を形成する場合も、上記の図１１（Ａ）及び図１１（Ｂ）に示した工程（或いは上記の図１１（Ｃ）及び図１１（Ｄ）に示した工程）と同様の工程を繰り返せばよい。   In this case, similar to FIG. 11A, the photosensitive resin is applied, exposed, developed, and cured on the back surface 50b side of the pseudo wafer 50 to form an opening leading to the columnar conductor 80. Then, similarly to FIG. 11B described above, formation of a seed layer, formation of a resist pattern, electroplating of copper, peeling of the resist pattern, and etching of the seed layer are performed to form vias and wirings. As a result, a first wiring layer is formed on the back surface 50b side of the pseudo wafer 50. Even when the second and subsequent wiring layers are formed on the back surface 50b side of the pseudo wafer 50, the steps shown in FIGS. 11A and 11B (or FIGS. 11C and 11 described above) are used. What is necessary is just to repeat the process similar to the process shown to (D).

導電パターン７０、導電材料９０及び柱状導体８０は、このように擬似ウェハ５０の表面５０ａ側と裏面５０ｂ側に形成される再配線層６０の導電部６１同士を電気的に接続する貫通ビアとして機能する。   The conductive pattern 70, the conductive material 90, and the columnar conductor 80 function as through vias that electrically connect the conductive portions 61 of the rewiring layer 60 formed on the front surface 50a side and the back surface 50b side of the pseudo wafer 50 in this way. To do.

尚、擬似ウェハ５０の表面５０ａ側と裏面５０ｂ側の双方に再配線層６０を形成する場合には、例えば、次のような手順で各配線層（ビア及び配線）を形成することができる。即ち、表面５０ａ側に１層目の配線層を形成した後、裏面５０ｂ側に１層目の配線層を形成し、次いで表面５０ａ側に２層目の配線層を形成するというように、各配線層を表面５０ａ側、裏面５０ｂ側に交互に形成していく。このような手順を用いると、再配線層６０を形成する際の擬似ウェハ５０の反りを抑制することができる。   When the rewiring layer 60 is formed on both the front surface 50a side and the back surface 50b side of the pseudo wafer 50, for example, each wiring layer (via and wiring) can be formed by the following procedure. That is, after the first wiring layer is formed on the front surface 50a side, the first wiring layer is formed on the back surface 50b side, and then the second wiring layer is formed on the front surface 50a side. Wiring layers are alternately formed on the front surface 50a side and the back surface 50b side. When such a procedure is used, it is possible to suppress warping of the pseudo wafer 50 when the rewiring layer 60 is formed.

擬似ウェハ５０の表面５０ａ側、又は表面５０ａ側と裏面５０ｂ側の双方に再配線層６０を形成した後は、擬似ウェハ５０及び再配線層６０を所定の位置で切断（ダイシング）し、個々の電子部品装置に分割する。   After the rewiring layer 60 is formed on the front surface 50a side or both the front surface 50a side and the back surface 50b side of the pseudo wafer 50, the pseudo wafer 50 and the rewiring layer 60 are cut (diced) at predetermined positions. Divide into electronic component devices.

図１２及び図１３は第１の実施の形態に係るダイシング工程の要部断面模式図である。尚、図１２（Ａ）は擬似ウェハの表面側に再配線層を形成した構造体を示す図、図１２（Ｂ）はダイシング後の電子部品装置を示す図である。図１３（Ａ）は擬似ウェハの表面側と裏面側の双方に再配線層を形成した構造体を示す図、図１３（Ｂ）はダイシング後の電子部品装置を示す図である。   12 and 13 are schematic cross-sectional views of the relevant part in the dicing process according to the first embodiment. 12A is a view showing a structure in which a rewiring layer is formed on the surface side of a pseudo wafer, and FIG. 12B is a view showing an electronic component device after dicing. FIG. 13A is a view showing a structure in which a rewiring layer is formed on both the front side and the back side of the pseudo wafer, and FIG. 13B is a view showing an electronic component device after dicing.

擬似ウェハ５０の表面５０ａ側に再配線層６０を形成し、裏面５０ｂ側に再配線層６０を形成しない構造体には、図１２（Ａ）に示すように、図１０（Ｂ）のような構造部１ａが複数（ここでは一例として２つ）含まれる。図１２（Ａ）の例では、各構造部１ａの周囲の位置（図１２（Ａ）に鎖線で示す位置）でダイシングが行われ、図１２（Ｂ）に示すような、個々の電子部品装置１に個片化される。   As shown in FIG. 12A, a structure in which the rewiring layer 60 is formed on the front surface 50a side of the pseudo wafer 50 and the rewiring layer 60 is not formed on the back surface 50b side is as shown in FIG. A plurality (two here as an example) of the structure portions 1a are included. In the example of FIG. 12A, dicing is performed at positions around each structure portion 1a (positions indicated by chain lines in FIG. 12A), and individual electronic component devices as shown in FIG. It is divided into 1 pieces.

擬似ウェハ５０の表面５０ａ側と裏面５０ｂ側の双方に再配線層６０を形成した構造体には、図１３（Ａ）に示すように、図１０（Ｃ）のような構造部１ｂが複数（ここでは一例として２つ）含まれる。図１３（Ａ）の例では、各構造部１ｂの周囲の位置（図１３（Ａ）に鎖線で示す位置）でダイシングが行われ、図１３（Ｂ）に示すような、個々の電子部品装置１に個片化される。   In the structure in which the rewiring layer 60 is formed on both the front surface 50a side and the back surface 50b side of the pseudo wafer 50, as shown in FIG. 13A, a plurality of structure portions 1b as shown in FIG. Here, two are included as an example. In the example of FIG. 13A, dicing is performed at a position around each structure portion 1b (position indicated by a chain line in FIG. 13A), and individual electronic component devices as shown in FIG. It is divided into 1 pieces.

以上説明したように、この第１の実施の形態に係る電子部品装置１の製造方法では、粘着層２０上に、電子部品３０を配置する開口部７１を設けた導電膜７０ａを形成し、その導電膜７０ａ上に導電材料９０で柱状導体８０を接合する。柱状導体８０が接合される導電膜７０ａと粘着層２０との接着面積を増大させることで、モールド成型時の導電膜７０ａの剥離、それによる柱状導体８０の倒れを効果的に抑制することが可能になる。それにより、貫通ビアとして利用可能な柱状導体８０とそれに導電材料９０で接合される導電パターン７０を、擬似ウェハ５０内に安定的に設けることが可能になり、貫通ビアを有する電子部品装置１を安定的に製造することが可能になる。   As described above, in the method of manufacturing the electronic component device 1 according to the first embodiment, the conductive film 70a provided with the opening 71 for arranging the electronic component 30 is formed on the adhesive layer 20, and the A columnar conductor 80 is bonded to the conductive film 70a with a conductive material 90. By increasing the adhesion area between the conductive layer 70a to which the columnar conductor 80 is bonded and the adhesive layer 20, it is possible to effectively suppress the peeling of the conductive layer 70a during molding and the collapse of the columnar conductor 80. become. As a result, the columnar conductor 80 that can be used as a through via and the conductive pattern 70 bonded to the conductive material 90 can be stably provided in the pseudo wafer 50, and the electronic component device 1 having the through via can be provided. It becomes possible to manufacture stably.

尚、以上述べた柱状導体８０には、円柱状のもののほか、角柱状のものを用いることもできる。また、柱状導体８０には、ピン状のもののほか、板状のものを用いることもできる。   The columnar conductor 80 described above can be a prismatic one in addition to a cylindrical one. Further, the columnar conductor 80 may be a plate-like one in addition to a pin-like one.

また、以上の説明では、各電子部品装置１に半導体チップ等の電子部品３０が１つ含まれるものを例にして述べたが、各電子部品装置には複数の電子部品３０が含まれていてもよい。また、各電子部品装置には、半導体チップ等の電子部品３０のほか、受動部品、例えばチップコンデンサ等のチップ部品が含まれていてもよい。   In the above description, each electronic component device 1 has been described as an example in which one electronic component 30 such as a semiconductor chip is included. However, each electronic component device includes a plurality of electronic components 30. Also good. In addition to the electronic component 30 such as a semiconductor chip, each electronic component device may include a passive component such as a chip component such as a chip capacitor.

以下に、半導体チップ等の電子部品やチップコンデンサ等の受動部品といった各種部品を複数含む電子部品装置の製造方法の一例を、第２の実施の形態として述べる。
図１４及び図１５は第２の実施の形態に係る電子部品装置の製造方法の説明図である。以下、図１４及び図１５を参照して、第２の実施の形態に係る電子部品装置の製造方法の一例について説明する。 Hereinafter, an example of a manufacturing method of an electronic component device including a plurality of various components such as electronic components such as semiconductor chips and passive components such as chip capacitors will be described as a second embodiment.
14 and 15 are explanatory views of a method for manufacturing the electronic component device according to the second embodiment. Hereinafter, an example of a method for manufacturing the electronic component device according to the second embodiment will be described with reference to FIGS.

図１４（Ａ）は第２の実施の形態に係る部品及び柱状導体配設工程の要部断面模式図、図１４（Ｂ）は第２の実施の形態に係る樹脂組成物層形成工程の要部断面模式図、図１４（Ｃ）は第２の実施の形態に係る擬似ウェハ分離工程の要部断面模式図、図１４（Ｄ）は第２の実施の形態に係るレジストパターン形成工程の要部断面模式図、図１４（Ｅ）は第２の実施の形態に係る導電パターン形成工程の要部断面模式図である。図１５（Ａ）は第２の実施の形態に係るバックグラインド工程の要部断面模式図、図１５（Ｂ）は第２の実施の形態に係る第１再配線層形成工程の要部断面模式図、図１５（Ｃ）は第２の実施の形態に係る第２再配線層形成工程の要部断面模式図である。   FIG. 14A is a schematic cross-sectional view of the main part of the component and columnar conductor arranging step according to the second embodiment, and FIG. 14B is the essential part of the resin composition layer forming step according to the second embodiment. 14C is a schematic cross-sectional view of a main part of a pseudo wafer separation process according to the second embodiment, and FIG. 14D is a schematic diagram of a resist pattern forming process according to the second embodiment. FIG. 14E is a schematic cross-sectional view of an essential part of a conductive pattern forming step according to the second embodiment. FIG. 15A is a schematic cross-sectional view of the main part of the back grinding process according to the second embodiment, and FIG. 15B is a schematic cross-sectional view of the main part of the first rewiring layer forming process according to the second embodiment. FIG. 15C is a schematic cross-sectional view of the relevant part in the second rewiring layer forming step according to the second embodiment.

まず、図１４（Ａ）に示すように、支持体１０上に設けられた粘着層２０の上に、開口部７１を有する導電膜７０ａを設ける。開口部７１は、半導体チップ等の電子部品３０が配置される領域、及びチップコンデンサ等の受動部品１４０が配置される領域を包含する領域に設けられる。このような開口部７１を有する導電膜７０ａは、所定の箔、板又は膜を粘着層２０上に形成した後、所定の領域に開口部７１をエッチング加工で形成することで、設けることができる。或いは、導電膜７０ａは、予め開口部７１を設けた箔等を粘着層２０上に貼付することで、設けることができる。   First, as shown in FIG. 14A, a conductive film 70 a having an opening 71 is provided on the adhesive layer 20 provided on the support 10. The opening 71 is provided in a region including a region where the electronic component 30 such as a semiconductor chip is disposed and a region where the passive component 140 such as a chip capacitor is disposed. The conductive film 70a having such an opening 71 can be provided by forming a predetermined foil, plate, or film on the adhesive layer 20 and then forming the opening 71 in a predetermined region by etching. . Or the electrically conductive film 70a can be provided by sticking the foil etc. which provided the opening part 71 previously on the adhesion layer 20. FIG.

上記のようにして粘着層２０上に導電膜７０ａを設けた後、その導電膜７０ａの開口部７１に露出する粘着層２０上に、電子部品３０及び受動部品１４０を設ける。
導電膜７０ａ上には、柱状導体８０を、導電材料９０を用いて接合する。柱状導体８０は、例えば、開口部７１の粘着層２０上に設けられる電子部品３０及び受動部品１４０の周囲に、導電膜７０ａ上の所定の位置に立てて、設ける。柱状導体８０を設ける位置は、導電膜７０ａの開口部７１の位置を基準にして、設定することができる。尚、柱状導体８０は、例えば、上記の図７又は図８のような方法を用いて設けることができる。 After providing the conductive film 70a on the adhesive layer 20 as described above, the electronic component 30 and the passive component 140 are provided on the adhesive layer 20 exposed in the opening 71 of the conductive film 70a.
A columnar conductor 80 is bonded onto the conductive film 70 a using a conductive material 90. The columnar conductor 80 is provided, for example, in a predetermined position on the conductive film 70 a around the electronic component 30 and the passive component 140 provided on the adhesive layer 20 of the opening 71. The position where the columnar conductor 80 is provided can be set with reference to the position of the opening 71 of the conductive film 70a. The columnar conductor 80 can be provided using, for example, the method shown in FIG. 7 or FIG.

次いで、図１４（Ｂ）に示すように、粘着層２０上の導電膜７０ａ、電子部品３０、受動部品１４０、並びに、導電膜７０ａ上の導電材料９０及び柱状導体８０を被覆する樹脂組成物層４０を形成し、粘着層２０上に擬似ウェハ５０を形成する。樹脂組成物層４０は、所定の樹脂組成物を用いたモールド成型によって形成される。   Next, as shown in FIG. 14B, the resin composition layer covering the conductive film 70a, the electronic component 30, the passive component 140 on the adhesive layer 20, and the conductive material 90 and the columnar conductor 80 on the conductive film 70a. 40 is formed, and a pseudo wafer 50 is formed on the adhesive layer 20. The resin composition layer 40 is formed by molding using a predetermined resin composition.

ここで、柱状導体８０が導電材料９０で接合される導電膜７０ａは、比較的大面積で粘着層２０に接着されているため、モールド成型時に柱状導体８０が樹脂組成物で押されても、導電膜７０ａの粘着層２０からの剥離、それによる柱状導体８０の倒れが抑えられる。これにより、擬似ウェハ５０内、或いは擬似ウェハ５０内の１つの電子部品装置に相当する構造部内に、倒れた柱状導体８０が含まれるような事態が効果的に抑えられる。   Here, since the conductive film 70a to which the columnar conductor 80 is bonded with the conductive material 90 is bonded to the adhesive layer 20 with a relatively large area, even if the columnar conductor 80 is pressed with a resin composition during molding, The peeling of the conductive film 70a from the adhesive layer 20 and the collapse of the columnar conductor 80 due to this are suppressed. Thereby, the situation where the fallen columnar conductor 80 is contained in the pseudo wafer 50 or the structure corresponding to one electronic component device in the pseudo wafer 50 is effectively suppressed.

擬似ウェハ５０の形成後は、図１４（Ｃ）に示すように、擬似ウェハ５０を粘着層２０から剥離する。
そして、図１４（Ｄ）に示すように、擬似ウェハ５０の、粘着層２０から剥離された表面５０ａ上に、レジストパターン１３０を形成する。レジストパターン１３０は、導電膜７０ａ上で、擬似ウェハ５０内の柱状導体８０に対応する部分を含む領域に、形成される。また、レジストパターン１３０は、導電膜７０ａと共に露出する電子部品３０及び受動部品１４０の上にも形成される。 After the pseudo wafer 50 is formed, the pseudo wafer 50 is peeled from the adhesive layer 20 as shown in FIG.
Then, as illustrated in FIG. 14D, a resist pattern 130 is formed on the surface 50 a of the pseudo wafer 50 that has been peeled off from the adhesive layer 20. The resist pattern 130 is formed in a region including a portion corresponding to the columnar conductor 80 in the pseudo wafer 50 on the conductive film 70a. The resist pattern 130 is also formed on the electronic component 30 and the passive component 140 that are exposed together with the conductive film 70a.

このようなレジストパターン１３０の形成後、それをマスクにして導電膜７０ａのエッチングを行い、図１４（Ｅ）に示すように、柱状導体８０に対応する部分を含む領域に、導電パターン７０を形成する。導電パターン７０の形成後、レジストパターン１３０は除去される。   After the resist pattern 130 is formed, the conductive film 70a is etched using the resist pattern 130 as a mask, and the conductive pattern 70 is formed in a region including a portion corresponding to the columnar conductor 80 as shown in FIG. To do. After the formation of the conductive pattern 70, the resist pattern 130 is removed.

導電パターン７０の形成後、図１５（Ａ）に示すように、擬似ウェハ５０の裏面５０ｂを研削し、柱状導体８０を露出させる。その際は、柱状導体８０の研削屑が電子部品３０及び受動部品１４０に付着するとそれらに悪影響を及ぼす可能性があることに鑑み、柱状導体８０の端面が、電子部品３０及び受動部品１４０よりも高く残るようにすることが好ましい。柱状導体８０の端面を擬似ウェハ５０の裏面５０ｂに露出させことで、導電パターン７０、導電材料９０及び柱状導体８０を、擬似ウェハ５０を貫通する貫通ビアとして用いることが可能になる。   After the formation of the conductive pattern 70, the back surface 50b of the pseudo wafer 50 is ground to expose the columnar conductor 80, as shown in FIG. In that case, if the grinding scraps of the columnar conductor 80 adhere to the electronic component 30 and the passive component 140, the end surfaces of the columnar conductor 80 may be more than the electronic component 30 and the passive component 140. It is preferable to keep it high. By exposing the end face of the columnar conductor 80 to the back surface 50 b of the pseudo wafer 50, the conductive pattern 70, the conductive material 90, and the columnar conductor 80 can be used as a through via penetrating the pseudo wafer 50.

尚、この図１５（Ａ）に示す、柱状導体８０を露出させる研削は、次の図１５（Ｂ）に示す再配線層６０の形成後に行うこともできる。
擬似ウェハ５０の表面５０ａ側には、図１５（Ｂ）に示すように、再配線層６０を形成する。再配線層６０は、電子部品３０の電極３１、受動部品１４０の電極１４１及び導電パターン７０に電気的に接続されたビア及び配線等の導電部６１、並びに、導電部６１の周りに設けられた絶縁部６２を含む。再配線層６０の導電部６１は、導電パターン７０、導電材料９０及び柱状導体８０によって、擬似ウェハ５０の裏面５０ｂに引き出される。擬似ウェハ５０の裏面５０ｂ側に露出する柱状導体８０の端面は、外部接続端子として利用することができる。 The grinding for exposing the columnar conductor 80 shown in FIG. 15A can also be performed after the formation of the rewiring layer 60 shown in FIG. 15B.
A rewiring layer 60 is formed on the surface 50a side of the pseudo wafer 50 as shown in FIG. The redistribution layer 60 is provided around the conductive portion 61, such as vias and wirings electrically connected to the electrode 31 of the electronic component 30, the electrode 141 of the passive component 140 and the conductive pattern 70, and the conductive portion 61. Insulating part 62 is included. The conductive portion 61 of the redistribution layer 60 is drawn to the back surface 50 b of the pseudo wafer 50 by the conductive pattern 70, the conductive material 90, and the columnar conductor 80. The end face of the columnar conductor 80 exposed on the back surface 50b side of the pseudo wafer 50 can be used as an external connection terminal.

擬似ウェハ５０には、図１５（Ｃ）に示すように、擬似ウェハ５０の裏面５０ｂ側にも同様に、裏面５０ｂ側に露出する柱状導体８０に電気的に接続された導電部６１を有する再配線層６０を形成することができる。導電パターン７０、導電材料９０及び柱状導体８０は、擬似ウェハ５０の表面５０ａ側と裏面５０ｂ側に形成される再配線層６０の導電部６１同士を電気的に接続する貫通ビアとして機能する。   As shown in FIG. 15C, the pseudo wafer 50 also includes a conductive portion 61 that is electrically connected to the columnar conductor 80 exposed on the back surface 50b side on the back surface 50b side of the pseudo wafer 50 as well. The wiring layer 60 can be formed. The conductive pattern 70, the conductive material 90, and the columnar conductor 80 function as a through via that electrically connects the conductive portions 61 of the rewiring layer 60 formed on the front surface 50 a side and the back surface 50 b side of the pseudo wafer 50.

尚、擬似ウェハ５０上の再配線層６０は、例えば、上記の図１１に示すような方法を用いて形成することができる。また、その際は、表面５０ａ側及び裏面５０ｂ側の再配線層６０に含まれる各配線層を、表面５０ａ側、裏面５０ｂ側に交互に形成していくと、再配線層６０を形成する際の擬似ウェハ５０の反りを抑制することができる。   The rewiring layer 60 on the pseudo wafer 50 can be formed using, for example, the method shown in FIG. In this case, when the wiring layers included in the rewiring layer 60 on the front surface 50a side and the back surface 50b side are alternately formed on the front surface 50a side and the back surface 50b side, the rewiring layer 60 is formed. Warpage of the pseudo wafer 50 can be suppressed.

擬似ウェハ５０の表面５０ａ側、又は表面５０ａ側と裏面５０ｂ側の双方に再配線層６０を形成した後は、上記の図１２及び図１３の例に従い、擬似ウェハ５０及び再配線層６０を所定の位置で切断し、個々の電子部品装置に分割する。   After the rewiring layer 60 is formed on the front surface 50a side or both the front surface 50a side and the back surface 50b side of the pseudo wafer 50, the pseudo wafer 50 and the rewiring layer 60 are set in accordance with the example of FIGS. And cut into individual electronic component devices.

このように、電子部品３０及び受動部品１４０を含む電子部品装置を製造する場合にも、粘着層２０上に、電子部品３０及び受動部品１４０を配置する開口部７１を設けた導電膜７０ａを形成し、その上に導電材料９０で柱状導体８０を接合する。これにより、モールド成型時の導電膜７０ａの剥離、それによる柱状導体８０の倒れを効果的に抑制することが可能になり、擬似ウェハ５０内に貫通ビアを安定的に設け、貫通ビアを有する電子部品装置を安定的に製造することが可能になる。   As described above, even when an electronic component device including the electronic component 30 and the passive component 140 is manufactured, the conductive film 70 a provided with the opening 71 for arranging the electronic component 30 and the passive component 140 is formed on the adhesive layer 20. Then, the columnar conductors 80 are joined with the conductive material 90 thereon. As a result, peeling of the conductive film 70a at the time of molding and the resulting collapse of the columnar conductor 80 can be effectively suppressed, and through vias can be stably provided in the pseudo-wafer 50. The component device can be stably manufactured.

尚、ここでは、導電膜７０ａに１つの開口部を設け、そこに電子部品３０と受動部品１４０を共に配置する場合を例示したが、導電膜７０ａには、電子部品３０を配置する開口部と、受動部品１４０を配置する開口部とを、それぞれ設けるようにしてもよい。   Here, the case where one opening portion is provided in the conductive film 70a and the electronic component 30 and the passive component 140 are both disposed therein is illustrated. However, the conductive film 70a includes an opening portion in which the electronic component 30 is disposed. In addition, an opening for disposing the passive component 140 may be provided.

また、擬似ウェハ５０内の個々の電子部品装置に相当する構造部内、擬似ウェハ５０とその上の再配線層６０を分割して得られる個々の電子部品装置内には、複数の電子部品３０が含まれていてもよく、複数の受動部品１４０が含まれていてもよい。このような場合も、上記同様の方法を用いることで、貫通ビアを設けた電子部品装置を安定的に製造することが可能である。   In addition, a plurality of electronic components 30 are provided in a structure portion corresponding to each electronic component device in the pseudo wafer 50 and in each electronic component device obtained by dividing the pseudo wafer 50 and the redistribution layer 60 thereon. It may be included, and a plurality of passive components 140 may be included. Even in such a case, by using the same method as described above, it is possible to stably manufacture an electronic component device provided with through vias.

上記のようにして得られる電子部品装置は、他の電子部品装置や回路基板に実装することができる。また、上記のようにして得られる電子部品装置に、他の電子部品装置を積層し、実装することができる。   The electronic component device obtained as described above can be mounted on another electronic component device or a circuit board. Further, another electronic component device can be stacked and mounted on the electronic component device obtained as described above.

ここで、電子部品装置を積層したデバイス（電子装置）の構成例を図１６〜図１９に示す。
図１６は電子装置の第１構成例を示す図である。尚、図１６には、第１構成例の電子装置の要部断面を模式的に図示している。 Here, structural examples of devices (electronic devices) in which electronic component devices are stacked are shown in FIGS.
FIG. 16 is a diagram illustrating a first configuration example of the electronic device. FIG. 16 schematically shows a cross-section of the main part of the electronic device of the first configuration example.

図１６に示す電子装置２００Ａは、下側の電子部品装置２１０と、その上に積層、実装された上側の電子部品装置２２０を備えている。
下側の電子部品装置２１０は、上記第１及び第２の実施の形態で述べたような方法を用いて形成される。電子部品装置２１０は、樹脂組成物層４０内に複数の半導体チップ等の電子部品３０（ここでは一例として２つを図示）、及び複数のチップコンデンサ等の受動部品１４０（ここでは一例として３つを図示）を含み、樹脂組成物層４０を貫通する貫通ビア１５０を含む。貫通ビア１５０には、上記のような柱状導体８０が含まれる。このような樹脂組成物層４０の一面に電子部品３０、受動部品１４０及び貫通ビア１５０に電気的に接続された導電部を有する再配線層６０が形成されている。尚、図１６において、電子部品装置２１０の貫通ビア１５０及び再配線層６０は、便宜上、簡略化して図示している。 An electronic device 200A shown in FIG. 16 includes a lower electronic component device 210 and an upper electronic component device 220 stacked and mounted thereon.
The lower electronic component device 210 is formed by using the method described in the first and second embodiments. The electronic component device 210 includes a plurality of electronic components 30 such as semiconductor chips (two shown here as examples) and a plurality of passive components 140 such as chip capacitors (here three as examples) in the resin composition layer 40. And a through via 150 penetrating through the resin composition layer 40. The through via 150 includes the columnar conductor 80 as described above. A rewiring layer 60 having a conductive portion electrically connected to the electronic component 30, the passive component 140, and the through via 150 is formed on one surface of the resin composition layer 40. In FIG. 16, the through via 150 and the rewiring layer 60 of the electronic component device 210 are simplified for convenience.

このような下側の電子部品装置２１０の再配線層６０に設けられる端子上に、半田ボール等のバンプ１５１が搭載される。再配線層６０と反対の側で樹脂組成物層４０から露出する貫通ビア１５０は、上側の電子部品装置２２０と電気的に接続される端子１５２となる。   Bumps 151 such as solder balls are mounted on the terminals provided in the rewiring layer 60 of the lower electronic component device 210. The through via 150 exposed from the resin composition layer 40 on the side opposite to the rewiring layer 60 becomes a terminal 152 that is electrically connected to the upper electronic component device 220.

上側の電子部品装置２２０は、基板（パッケージ基板）２２１と、その上に搭載されてワイヤ２２２で接続された半導体チップ２２３とを含む。パッケージ基板２２１上のワイヤ２２２及び半導体チップ２２３は、樹脂組成物層２２４で被覆されている。例えば、この上側の電子部品装置２２０は、その半導体チップ２２３として半導体メモリを用いたメモリパッケージである。   The upper electronic component device 220 includes a substrate (package substrate) 221 and a semiconductor chip 223 mounted thereon and connected by wires 222. The wire 222 and the semiconductor chip 223 on the package substrate 221 are covered with a resin composition layer 224. For example, the upper electronic component device 220 is a memory package using a semiconductor memory as the semiconductor chip 223.

このような上側の電子部品装置２２０のパッケージ基板２２１に設けられる端子上に、半田ボール等のバンプ２２５が搭載される。上側の電子部品装置２２０のバンプ２２５は、下側の電子部品装置２１０の端子１５２（貫通ビア１５０）に接合され、これにより、下側の電子部品装置２１０と上側の電子部品装置２２０とが電気的に接続される。   Bumps 225 such as solder balls are mounted on the terminals provided on the package substrate 221 of the upper electronic component device 220. The bumps 225 of the upper electronic component device 220 are joined to the terminals 152 (through vias 150) of the lower electronic component device 210, whereby the lower electronic component device 210 and the upper electronic component device 220 are electrically connected. Connected.

図１７は電子装置の第２構成例を示す図である。尚、図１７には、第２構成例の電子装置の要部断面を模式的に図示している。
図１７に示す電子装置２００Ｂは、下側と上側に同種の電子部品装置２１０を備えている。下側と上側の電子部品装置２１０は、いずれも上記図１６に示したものと同様の構造を有している。下側と上側の電子部品装置２１０は、いずれも上記第１及び第２の実施の形態で述べたような方法を用いて形成される。 FIG. 17 is a diagram illustrating a second configuration example of the electronic apparatus. FIG. 17 schematically shows a cross-section of the main part of the electronic device of the second configuration example.
An electronic device 200B illustrated in FIG. 17 includes electronic component devices 210 of the same type on the lower side and the upper side. The lower and upper electronic component devices 210 have the same structure as that shown in FIG. The lower and upper electronic component devices 210 are both formed using the methods described in the first and second embodiments.

下側の電子部品装置２１０の再配線層６０に設けられる端子上、上側の電子部品装置２１０の再配線層６０に設けられる端子上には、それぞれ所定数のバンプ１５１が搭載される。上側の電子部品装置２１０のバンプ１５１は、下側の電子部品装置２１０の端子１５２（貫通ビア１５０）に接合され、これにより、下側の電子部品装置２１０と上側の電子部品装置２１０とが電気的に接続される。   A predetermined number of bumps 151 are mounted on the terminals provided on the rewiring layer 60 of the lower electronic component device 210 and on the terminals provided on the rewiring layer 60 of the upper electronic component device 210. The bump 151 of the upper electronic component device 210 is joined to the terminal 152 (through via 150) of the lower electronic component device 210, whereby the lower electronic component device 210 and the upper electronic component device 210 are electrically connected. Connected.

図１８は電子装置の第３構成例を示す図である。尚、図１８には、第３構成例の電子装置の要部断面を模式的に図示している。
図１８に示す電子装置２００Ｃは、下側の電子部品装置２１０ａと、その上に積層、実装された上側の電子部品装置２２０を備えている。下側の電子部品装置２１０ａは、樹脂組成物層４０の、上側の電子部品装置２２０が積層される側に、端子１５２（貫通ビア１５０）に電気的に接続される導電部を有する再配線層６０が設けられている点で、上記図１６に示した電子部品装置２１０と相違する。下側の電子部品装置２１０ａは、上記第１及び第２の実施の形態で述べたような方法を用いて形成される。 FIG. 18 is a diagram illustrating a third configuration example of the electronic apparatus. FIG. 18 schematically shows a cross section of the main part of the electronic device of the third configuration example.
An electronic device 200C shown in FIG. 18 includes a lower electronic component device 210a and an upper electronic component device 220 stacked and mounted thereon. The lower electronic component device 210a has a rewiring layer having a conductive portion electrically connected to the terminal 152 (through via 150) on the side of the resin composition layer 40 on which the upper electronic component device 220 is laminated. 16 is different from the electronic component device 210 shown in FIG. 16 in that 60 is provided. The lower electronic component device 210a is formed by using the method described in the first and second embodiments.

上側の電子部品装置２２０のバンプ２２５は、下側の電子部品装置２１０ａの再配線層６０に設けられる端子に接合され、これにより、下側の電子部品装置２１０ａと上側の電子部品装置２２０とが電気的に接続される。   The bumps 225 of the upper electronic component device 220 are joined to terminals provided in the rewiring layer 60 of the lower electronic component device 210a, whereby the lower electronic component device 210a and the upper electronic component device 220 are connected. Electrically connected.

図１９は電子装置の第４構成例を示す図である。尚、図１９には、第４構成例の電子装置の要部断面を模式的に図示している。
図１９に示す電子装置２００Ｄは、下側の電子部品装置２１０ａと、その上に積層、実装された上側の電子部品装置２１０を備えている。下側の電子部品装置２１０ａは、上記図１８に示したものと同様の構造を有している。上側の電子部品装置２１０は、上記図１７に示したものと同様の構造を有している。下側の電子部品装置２１０ａ及び上側の電子部品装置２１０は、いずれも上記第１及び第２の実施の形態で述べたような方法を用いて形成される。 FIG. 19 is a diagram illustrating a fourth configuration example of the electronic device. FIG. 19 schematically illustrates a cross-section of the main part of the electronic device of the fourth configuration example.
An electronic device 200D shown in FIG. 19 includes a lower electronic component device 210a and an upper electronic component device 210 stacked and mounted thereon. The lower electronic component device 210a has the same structure as that shown in FIG. The upper electronic component device 210 has the same structure as that shown in FIG. The lower electronic component device 210a and the upper electronic component device 210 are both formed using the methods described in the first and second embodiments.

上側の電子部品装置２１０のバンプ１５１は、下側の電子部品装置２１０ａの再配線層６０に設けられる端子に接合され、これにより、下側の電子部品装置２１０ａと上側の電子部品装置２１０とが電気的に接続される。   The bumps 151 of the upper electronic component device 210 are bonded to terminals provided on the rewiring layer 60 of the lower electronic component device 210a, whereby the lower electronic component device 210a and the upper electronic component device 210 are connected. Electrically connected.

尚、図１６〜図１９に示した電子装置２００Ａ，２００Ｂ，２００Ｃ，２００Ｄの、上側の電子部品装置２２０，２１０の更に上には、他の電子部品装置を積層、実装することが可能である。   Note that other electronic component devices can be stacked and mounted on the upper electronic component devices 220 and 210 of the electronic devices 200A, 200B, 200C, and 200D shown in FIGS. .

また、図１６〜図１９に示した電子装置２００Ａ，２００Ｂ，２００Ｃ，２００Ｄはいずれも、下側の電子部品装置２１０，２１０ａのバンプ１５１を用いて、回路基板に実装することが可能である。   Also, any of the electronic devices 200A, 200B, 200C, and 200D shown in FIGS. 16 to 19 can be mounted on the circuit board using the bumps 151 of the lower electronic component devices 210 and 210a.

図２０は電子装置の別例を示す図である。
図２０には、第１構成例の電子装置２００Ａを、下側の電子部品装置２１０のバンプ１５１を用いて、回路基板２３０に実装した場合の電子装置の要部断面を模式的に図示している。ここでは電子装置２００Ａを回路基板２３０に実装した場合を例示したが、他の電子装置２００Ｂ，２００Ｃ，２００Ｄも同様に、回路基板２３０に実装することが可能である。 FIG. 20 is a diagram illustrating another example of the electronic apparatus.
FIG. 20 schematically illustrates a cross-section of the main part of the electronic device when the electronic device 200A of the first configuration example is mounted on the circuit board 230 using the bumps 151 of the lower electronic component device 210. Yes. Although the case where the electronic device 200A is mounted on the circuit board 230 is illustrated here, other electronic devices 200B, 200C, and 200D can be similarly mounted on the circuit board 230.

上記第１及び第２の実施の形態で述べた方法を用いることで、電子部品装置内に貫通ビアを安定的に設けることができ、貫通ビアを利用して複数の電子部品装置を積層し、実装密度の高い電子装置を実現することができる。   By using the method described in the first and second embodiments, a through via can be stably provided in the electronic component device, and a plurality of electronic component devices are stacked using the through via. An electronic device with high packaging density can be realized.

以下、電子部品装置及び電子装置の実施例について述べる。
〔実施例１〕
支持体として縦１７０ｍｍ×横１７０ｍｍ×厚さ０．３ｍｍのステンレス基板を用い、そのステンレス基板上に熱発泡型の粘着層を貼付し、その粘着層上に、厚さ３μｍの銅箔を貼付した。その銅箔上にドライフィルムレジストを形成し、ドライフィルムレジストに縦６ｍｍ×横６ｍｍの開口パターンを１２ｍｍピッチで１０行×１０列形成し、これをマスクにして銅箔をエッチングし、銅箔に縦６ｍｍ×横６ｍｍの開口部を形成した。 Examples of the electronic component device and the electronic device will be described below.
[Example 1]
A stainless steel substrate having a length of 170 mm × width of 170 mm × thickness of 0.3 mm was used as a support, a heat-foaming adhesive layer was stuck on the stainless steel substrate, and a copper foil with a thickness of 3 μm was stuck on the adhesive layer. . A dry film resist is formed on the copper foil, an opening pattern of 6 mm in length and 6 mm in width is formed in the dry film resist in 10 rows by 10 columns at a pitch of 12 mm, and this is used as a mask to etch the copper foil. An opening 6 mm long × 6 mm wide was formed.

このようにして形成した銅箔の開口部から露出する粘着層上にそれぞれ、フリップチップボンダーを用いて、縦５ｍｍ×横５ｍｍ×厚さ０．４ｍｍのベアチップ（半導体チップ）をその電極面が粘着層の表面に接するように配置した。また、直径０．２ｍｍ、長さ０．５ｍｍの銅ピンを準備し、その片側の先端部に、銅と錫とビスマスを含む半田（低融点金属）を設け、これを、ステンレス板に貫通孔を形成した金型を用いて、ベアチップ周囲の銅箔上の所定位置に接合した。   Using a flip chip bonder, a bare chip (semiconductor chip) having a length of 5 mm, a width of 5 mm, and a thickness of 0.4 mm is adhered to the adhesive layer exposed from the opening of the copper foil thus formed. It arrange | positioned so that the surface of a layer might be touched. In addition, a copper pin having a diameter of 0.2 mm and a length of 0.5 mm is prepared, and solder (low melting point metal) containing copper, tin, and bismuth is provided at the tip of one side thereof, and this is provided with a through hole in a stainless steel plate. Using the metal mold formed with, was bonded to a predetermined position on the copper foil around the bare chip.

その後、モールド成型用の金型を用いて樹脂組成物層を形成し、その樹脂組成物層を硬化して、粘着層上に、厚さ０．６ｍｍ、直径１５０ｍｍの擬似ウェハを形成した。このモールド成型時には、粘着層とその上の銅箔との接着面積が比較的大きく、このような銅箔に接合された銅ピンは、樹脂組成物層に押されても倒れることがなかった。   Thereafter, a resin composition layer was formed using a mold for molding, the resin composition layer was cured, and a pseudo wafer having a thickness of 0.6 mm and a diameter of 150 mm was formed on the adhesive layer. At the time of molding, the adhesive area between the adhesive layer and the copper foil thereon was relatively large, and the copper pin joined to such a copper foil did not fall even when pressed by the resin composition layer.

モールド成型後、１８０℃で加熱し、熱発泡型の粘着層の粘着力を低下させ、粘着層から擬似ウェハを剥離した。その後、２００℃、１時間で加熱処理を行い、擬似ウェハを完全硬化した。この擬似ウェハの銅箔の、銅ピンを立てた部分に対応する領域に、その銅箔の開口部の角で位置合わせを行って直径０．３ｍｍのレジストパターンを形成し、これをマスクにして銅箔をエッチングし、銅ピンを立てた部分に対応する領域に電極パッドを形成した。このエッチングの際には、銅箔の開口部に設けられているベアチップの電極面にもレジストパターンを形成しておき、電極面をエッチングから保護するようにした。   After molding, heating was performed at 180 ° C. to reduce the adhesive strength of the heat-foaming adhesive layer, and the pseudo wafer was peeled from the adhesive layer. Thereafter, heat treatment was performed at 200 ° C. for 1 hour to completely cure the pseudo wafer. A resist pattern having a diameter of 0.3 mm is formed on the copper foil of the pseudo wafer in a region corresponding to the portion where the copper pin is erected at the corner of the opening of the copper foil, and this is used as a mask. The copper foil was etched to form an electrode pad in a region corresponding to the portion where the copper pin was raised. In this etching, a resist pattern was also formed on the electrode surface of the bare chip provided in the opening of the copper foil so that the electrode surface was protected from etching.

次いで、擬似ウェハの、ベアチップの電極面が露出する表面側に、感光性エポキシワニスをスピンコート法で塗布し、プリベーク、露光、現像、キュアを行い、更に酸素プラズマ処理を行った。これにより、膜厚８μｍで、ベアチップの電極に通じる直径３０μｍの開口部を設けた絶縁層を形成した。次いで、スパッタ法でチタンと銅をそれぞれ０．１μｍ、０．３μｍの厚さで形成し、シード層を形成した。その後、ビア及び配線を形成する領域を開口したレジストパターンを形成し、先に形成したシード層を用いて銅の電気めっきを行い、ビア及び配線を形成した。電気めっき後、レジストパターンを剥離し、そのレジストパターンで覆われていた部分のシード層を、ウェットエッチングとドライエッチングで除去した。その後、配線を部分的に露出させてソルダーレジストを形成し、露出する配線表面にニッケルと金の表面処理を行った。   Next, a photosensitive epoxy varnish was applied by spin coating on the surface side of the pseudo wafer where the bare chip electrode surface was exposed, prebaked, exposed, developed and cured, and further subjected to oxygen plasma treatment. Thus, an insulating layer having a film thickness of 8 μm and an opening having a diameter of 30 μm leading to the bare chip electrode was formed. Next, titanium and copper were formed to a thickness of 0.1 μm and 0.3 μm, respectively, by sputtering, and a seed layer was formed. Thereafter, a resist pattern having openings in areas for forming vias and wirings was formed, and copper was electroplated using the previously formed seed layer to form vias and wirings. After electroplating, the resist pattern was peeled off, and the portion of the seed layer covered with the resist pattern was removed by wet etching and dry etching. Thereafter, the wiring was partially exposed to form a solder resist, and the exposed wiring surface was subjected to nickel and gold surface treatment.

その後、このようにして配線層を設けた擬似ウェハの裏面側から樹脂組成物層を厚さ０．１１ｍｍ研削し、銅ピンの端面を露出させた。そして、このようにして擬似ウェハに配線層を設け、銅ピンを露出させた基板を、所定の位置で切断し、個片化された電子部品装置（パッケージ）を得た。
〔実施例２〕
支持体として縦１７０ｍｍ×横１７０ｍｍ×厚さ０．３ｍｍのガラス基板を用い、そのガラス基板上に紫外線発泡型の粘着層を貼付した。その粘着層上に、厚さ７μｍの銅箔であって、予めドライフィルムレジストを用いたエッチングによって縦６ｍｍ×横６ｍｍの開口部を１２ｍｍピッチで１０行×１０列形成した銅箔を貼付した。 Thereafter, the resin composition layer was ground by a thickness of 0.11 mm from the back surface side of the pseudo wafer provided with the wiring layer in this manner to expose the end face of the copper pin. Then, the wiring layer was provided on the pseudo wafer in this way, and the substrate from which the copper pins were exposed was cut at a predetermined position to obtain an individualized electronic component device (package).
[Example 2]
A glass substrate having a length of 170 mm × width of 170 mm × thickness of 0.3 mm was used as a support, and an ultraviolet foam adhesive layer was stuck on the glass substrate. On the adhesive layer, a copper foil having a thickness of 7 [mu] m and having 10 mm * 10 columns of openings of 6 mm in length and 6 mm in width formed in advance by etching using a dry film resist was pasted.

この銅箔の開口部から露出する粘着層上にそれぞれ、マウンターを用いて、縦４ｍｍ×横４ｍｍ×厚さ０．５ｍｍのベアチップ（半導体チップ）と、０６０３型（縦０．６ｍｍ×横０．３ｍｍ×厚さ０．３ｍｍ）のチップコンデンサをそれらの電極面が粘着層の表面に接するように配置した。また、直径０．１５ｍｍ、長さ０．６ｍｍの銅ピンを準備し、その片側の先端部に、銅と錫と銀とビスマスを含む低融点金属を設け、これを、ステンレス板に貫通孔を形成した金型を用いて、ベアチップ及びチップコンデンサ周囲の銅箔上の所定位置に接合した。   On the adhesive layer exposed from the opening of the copper foil, using a mounter, a 4 mm long × 4 mm wide × 0.5 mm thick bare chip (semiconductor chip) and 0603 type (vertical 0.6 mm × width 0. 3 mm × thickness 0.3 mm) chip capacitors were arranged so that their electrode surfaces were in contact with the surface of the adhesive layer. In addition, a copper pin having a diameter of 0.15 mm and a length of 0.6 mm was prepared, and a low melting point metal containing copper, tin, silver and bismuth was provided at the tip of one side, and this was provided with a through hole in a stainless steel plate. Using the formed mold, bonding was performed at a predetermined position on the copper foil around the bare chip and the chip capacitor.

その後、モールド成型用の金型を用いて樹脂組成物層を形成し、その樹脂組成物層を硬化して、粘着層上に、厚さ０．７ｍｍ、直径１５０ｍｍの擬似ウェハを形成した。このモールド成型時には、粘着層とその上の銅箔との接着面積が比較的大きく、このような銅箔に接合された銅ピンは、樹脂組成物層に押されても倒れることがなかった。   Thereafter, a resin composition layer was formed using a mold for molding, the resin composition layer was cured, and a pseudo wafer having a thickness of 0.7 mm and a diameter of 150 mm was formed on the adhesive layer. At the time of molding, the adhesive area between the adhesive layer and the copper foil thereon was relatively large, and the copper pin joined to such a copper foil did not fall even when pressed by the resin composition layer.

モールド成型後、ガラス基板側から紫外線を照射し、紫外線発泡型の粘着層の粘着力を低下させ、粘着層から擬似ウェハを剥離した。その後、２００℃、１時間で加熱処理を行い、擬似ウェハを完全硬化した。この擬似ウェハの銅箔の、銅ピンを立てた部分に対応する領域に、その銅箔の開口部の角で位置合わせを行って直径０．３ｍｍのレジストパターンを形成し、これをマスクにして銅箔をエッチングし、銅ピンを立てた部分に対応する領域に電極パッドを形成した。このエッチングの際には、銅箔の開口部に設けられているベアチップ及びチップコンデンサの電極面にもレジストパターンを形成しておき、電極面をエッチングから保護するようにした。   After molding, ultraviolet rays were irradiated from the glass substrate side to reduce the adhesive strength of the ultraviolet foam adhesive layer, and the pseudo wafer was peeled from the adhesive layer. Thereafter, heat treatment was performed at 200 ° C. for 1 hour to completely cure the pseudo wafer. A resist pattern having a diameter of 0.3 mm is formed on the copper foil of the pseudo wafer in a region corresponding to the portion where the copper pin is erected at the corner of the opening of the copper foil, and this is used as a mask. The copper foil was etched to form an electrode pad in a region corresponding to the portion where the copper pin was raised. In this etching, a resist pattern was formed on the electrode surfaces of the bare chip and the chip capacitor provided in the opening of the copper foil to protect the electrode surface from etching.

次いで、擬似ウェハの、ベアチップ及びチップコンデンサの電極面が露出する表面側と反対の裏面側から樹脂組成物層を厚さ０．１１ｍｍ研削し、銅ピンの端面を露出させた。その後、擬似ウェハの表面側に、感光性エポキシワニスをスピンコート法で塗布し、プリベーク、露光、現像、キュアを行い、更に酸素プラズマ処理を行った。これにより、膜厚８μｍで、ベアチップ及びチップコンデンサの電極に通じる直径５０μｍの開口部を設けた絶縁層を形成した。次いで、スパッタ法でチタンと銅をそれぞれ０．１μｍ、０．３μｍの厚さで形成し、シード層を形成した。その後、ビア及び配線を形成する領域を開口したレジストパターンを形成し、先に形成したシード層を用いて銅の電気めっきを行い、ビア及び配線を形成した。電気めっき後、レジストパターンを剥離し、そのレジストパターンで覆われていた部分のシード層を、ウェットエッチングとドライエッチングで除去した。擬似ウェハの裏面側にも同様にして、銅ピンに接続されるビア及び配線を形成した。その後、表裏面の配線をそれぞれ部分的に露出させてソルダーレジストを形成し、露出する配線表面にニッケルと金の表面処理を行った。   Next, the resin composition layer was ground to a thickness of 0.11 mm from the back surface side of the pseudo wafer opposite to the surface side where the bare chip and chip capacitor electrode surfaces were exposed, and the end surfaces of the copper pins were exposed. Thereafter, a photosensitive epoxy varnish was applied to the surface side of the pseudo wafer by spin coating, prebaked, exposed, developed, and cured, and further subjected to oxygen plasma treatment. As a result, an insulating layer having a film thickness of 8 μm and an opening having a diameter of 50 μm communicating with the bare chip and the electrode of the chip capacitor was formed. Next, titanium and copper were formed to a thickness of 0.1 μm and 0.3 μm, respectively, by sputtering, and a seed layer was formed. Thereafter, a resist pattern having openings in areas for forming vias and wirings was formed, and copper was electroplated using the previously formed seed layer to form vias and wirings. After electroplating, the resist pattern was peeled off, and the portion of the seed layer covered with the resist pattern was removed by wet etching and dry etching. Similarly, vias and wirings connected to the copper pins were formed on the back side of the pseudo wafer. Thereafter, a solder resist was formed by partially exposing the wiring on the front and back surfaces, and surface treatment of nickel and gold was performed on the exposed wiring surface.

擬似ウェハにこのようにして配線層を設けた基板を、所定の位置で切断し、個片化された電子部品装置（パッケージ）を得た。更に、このパッケージ上に、ＦＢＧＡ（Fine pitch Ball Grid Array）のパッケージを、半田バンプを用いて積層接合し、積層パッケージ型の電子装置を得た。
〔実施例３〕
支持体として縦１７０ｍｍ×横１７０ｍｍ×厚さ０．３ｍｍのガラス基板を用い、そのガラス基板上に紫外線発泡型の粘着層を貼付し、その粘着層上に、真空蒸着によって厚さ０．２μｍのニッケル膜を形成した。そのニッケル膜上にドライフィルムレジストを形成し、ドライフィルムレジストに縦７ｍｍ×横７ｍｍの開口パターンを１２ｍｍピッチで１０行×１０列形成し、これをマスクにしてニッケル膜をエッチングし、銅箔に縦７ｍｍ×横７ｍｍの開口部を形成した。 The substrate on which the wiring layer was thus provided on the pseudo wafer was cut at a predetermined position to obtain an individualized electronic component device (package). Further, an FBGA (Fine pitch Ball Grid Array) package was laminated on the package using solder bumps to obtain a stacked package type electronic device.
Example 3
A glass substrate having a length of 170 mm × width of 170 mm × thickness of 0.3 mm was used as a support, and an ultraviolet foam-type adhesive layer was stuck on the glass substrate, and a thickness of 0.2 μm was formed on the adhesive layer by vacuum deposition. A nickel film was formed. A dry film resist is formed on the nickel film, and an opening pattern of 7 mm length × 7 mm width is formed on the dry film resist in 10 rows × 10 columns at a pitch of 12 mm, and the nickel film is etched using this as a mask to form a copper foil. An opening of length 7 mm × width 7 mm was formed.

このニッケル膜の開口部から露出する粘着層上にそれぞれ、マウンターを用いて、縦５ｍｍ×横５ｍｍ×厚さ０．５ｍｍのベアチップ（半導体チップ）と、１００５型（縦１．０ｍｍ×横０．５ｍｍ×厚さ０．５ｍｍ）のチップコンデンサをそれらの電極面が粘着層の表面に接するように配置した。また、直径０．２ｍｍ、長さ０．６ｍｍの銅ピンを準備し、その片側の先端部に銀ペーストを設け、これを、ステンレス板に貫通孔を形成した金型を用いて、ベアチップ及びチップコンデンサ周囲のニッケル膜上の所定位置に接合した。   On the adhesive layer exposed from the opening of the nickel film, using a mounter, a bare chip (semiconductor chip) having a length of 5 mm × width 5 mm × thickness 0.5 mm and a type 1005 (length 1.0 mm × width 0. 5 mm × thickness 0.5 mm) chip capacitors were arranged so that their electrode surfaces were in contact with the surface of the adhesive layer. In addition, a copper pin having a diameter of 0.2 mm and a length of 0.6 mm was prepared, a silver paste was provided at the tip of one side, and this was used as a bare chip and a chip using a mold in which a through hole was formed in a stainless steel plate. Bonded to a predetermined position on the nickel film around the capacitor.

その後、モールド成型用の金型を用いて樹脂組成物層を形成し、その樹脂組成物層を硬化して、粘着層上に、厚さ０．６ｍｍ、直径１５０ｍｍの擬似ウェハを形成した。このモールド成型時には、粘着層とその上のニッケル膜との接着面積が比較的大きく、このようなニッケル膜に接合された銅ピンは、樹脂組成物層に押されても倒れることがなかった。   Thereafter, a resin composition layer was formed using a mold for molding, the resin composition layer was cured, and a pseudo wafer having a thickness of 0.6 mm and a diameter of 150 mm was formed on the adhesive layer. At the time of molding, the adhesion area between the pressure-sensitive adhesive layer and the nickel film thereon was relatively large, and the copper pin joined to such a nickel film did not fall even when pressed by the resin composition layer.

モールド成型後、ガラス基板側から紫外線を照射し、紫外線発泡型の粘着層の粘着力を低下させ、粘着層から擬似ウェハを剥離した。その後、２００℃、１時間で加熱処理を行い、擬似ウェハを完全硬化した。この擬似ウェハのニッケル膜の、銅ピンを立てた部分に対応する領域に、そのニッケル膜の開口部の角で位置合わせを行って直径０．３ｍｍのレジストパターンを形成し、これをマスクにしてニッケル膜をエッチングし、銅ピンを立てた部分に対応する領域に電極パッドを形成した。このエッチングの際には、ニッケル膜の開口部に設けられているベアチップ及びチップコンデンサの電極面にもレジストパターンを形成しておき、電極面をエッチングから保護するようにした。   After molding, ultraviolet rays were irradiated from the glass substrate side to reduce the adhesive strength of the ultraviolet foam adhesive layer, and the pseudo wafer was peeled from the adhesive layer. Thereafter, heat treatment was performed at 200 ° C. for 1 hour to completely cure the pseudo wafer. A resist pattern having a diameter of 0.3 mm is formed by aligning the nickel film of the pseudo wafer with the corner of the opening of the nickel film in a region corresponding to the portion where the copper pin is erected, and using this as a mask The nickel film was etched to form an electrode pad in a region corresponding to the portion where the copper pin was raised. At the time of this etching, a resist pattern was also formed on the bare chip and chip capacitor electrode surfaces provided in the opening of the nickel film to protect the electrode surfaces from etching.

次いで、擬似ウェハの、ベアチップ及びチップコンデンサの電極面が露出する表面側と反対の裏面側から樹脂組成物層を厚さ０．１５ｍｍ研削し、銅ピンの端面を露出させた。その後、擬似ウェハの表面側に、感光性エポキシワニスをスピンコート法で塗布し、プリベーク、露光、現像、キュアを行い、更に酸素プラズマ処理を行った。これにより、膜厚８μｍで、ベアチップ及びチップコンデンサの電極に通じる直径５０μｍの開口部を設けた絶縁層を形成した。次いで、スパッタ法でチタンと銅をそれぞれ０．１μｍ、０．３μｍの厚さで形成し、シード層を形成した。その後、ビア及び配線を形成する領域を開口したレジストパターンを形成し、先に形成したシード層を用いて銅の電気めっきを行い、ビア及び配線を形成した。電気めっき後、レジストパターンを剥離し、そのレジストパターンで覆われていた部分のシード層を、ウェットエッチングとドライエッチングで除去した。擬似ウェハの裏面側にも同様にして、銅ピンに接続されるビア及び配線を形成した。その後、表裏面の配線をそれぞれ部分的に露出させてソルダーレジストを形成し、露出する配線表面にニッケルと金の表面処理を行った。   Next, the resin composition layer was ground by a thickness of 0.15 mm from the back surface side of the pseudo wafer opposite to the surface side from which the bare chip and chip capacitor electrode surfaces were exposed to expose the end surfaces of the copper pins. Thereafter, a photosensitive epoxy varnish was applied to the surface side of the pseudo wafer by spin coating, prebaked, exposed, developed, and cured, and further subjected to oxygen plasma treatment. As a result, an insulating layer having a film thickness of 8 μm and an opening having a diameter of 50 μm communicating with the bare chip and the electrode of the chip capacitor was formed. Next, titanium and copper were formed to a thickness of 0.1 μm and 0.3 μm, respectively, by sputtering, and a seed layer was formed. Thereafter, a resist pattern having openings in areas for forming vias and wirings was formed, and copper was electroplated using the previously formed seed layer to form vias and wirings. After electroplating, the resist pattern was peeled off, and the portion of the seed layer covered with the resist pattern was removed by wet etching and dry etching. Similarly, vias and wirings connected to the copper pins were formed on the back side of the pseudo wafer. Thereafter, a solder resist was formed by partially exposing the wiring on the front and back surfaces, and surface treatment of nickel and gold was performed on the exposed wiring surface.

擬似ウェハにこのようにして配線層を設けた基板を、所定の位置で切断し、個片化された電子部品装置（パッケージ）を得た。更に、このようにして得られたパッケージ同士を、半田バンプを用いて積層接合し、積層パッケージ型の電子装置を得た。   The substrate on which the wiring layer was thus provided on the pseudo wafer was cut at a predetermined position to obtain an individualized electronic component device (package). Furthermore, the packages thus obtained were laminated and bonded using solder bumps to obtain a laminated package type electronic device.

以上説明した実施の形態に関し、更に以下の付記を開示する。
（付記１） 支持体上に粘着層を設ける工程と、
前記粘着層上に、開口部を有する導電膜を設ける工程と、
前記開口部の前記粘着層上に電子部品を設ける工程と、
前記導電膜上に柱状導体を立てる工程と、
前記粘着層上に、前記導電膜、前記電子部品及び前記柱状導体を樹脂組成物で被覆した基板を形成する工程と、
前記基板を前記粘着層から分離する工程と、
前記粘着層から分離された前記基板の前記導電膜を部分的に除去し、前記柱状導体に対応する部分を含む導電パターンを形成する工程と、
前記基板の前記導電パターンが形成された第１面上に、前記電子部品及び前記導電パターンに電気的に接続された第１導電部を有する第１配線層を形成する工程と
を含むことを特徴とする電子部品装置の製造方法。 Regarding the embodiment described above, the following additional notes are further disclosed.
(Additional remark 1) The process of providing an adhesion layer on a support body,
Providing a conductive film having an opening on the adhesive layer;
Providing an electronic component on the adhesive layer of the opening;
Erecting columnar conductors on the conductive film;
On the adhesive layer, forming a substrate in which the conductive film, the electronic component, and the columnar conductor are covered with a resin composition;
Separating the substrate from the adhesive layer;
Partially removing the conductive film of the substrate separated from the adhesive layer and forming a conductive pattern including a portion corresponding to the columnar conductor;
Forming a first wiring layer having a first conductive portion electrically connected to the electronic component and the conductive pattern on a first surface of the substrate on which the conductive pattern is formed. A method for manufacturing an electronic component device.

（付記２） 前記柱状導体を立てる工程は、前記導電膜上に導電材料を用いて前記柱状導体を固定する工程を含むことを特徴とする付記１に記載の電子部品装置の製造方法。
（付記３） 前記導電膜上に前記導電材料を用いて前記柱状導体を固定する工程は、
流動性の前記導電材料を介して前記柱状導体を前記導電膜上に配置する工程と、
前記導電材料を凝固させて前記柱状導体を前記導電膜上に固定する工程と
を含むことを特徴とする付記２に記載の電子部品装置の製造方法。 (Additional remark 2) The process of standing the said columnar conductor includes the process of fixing the said columnar conductor using the electrically-conductive material on the said electrically conductive film, The manufacturing method of the electronic component apparatus of Additional remark 1 characterized by the above-mentioned.
(Supplementary Note 3) The step of fixing the columnar conductor using the conductive material on the conductive film,
Disposing the columnar conductor on the conductive film via the fluid conductive material;
The method for manufacturing an electronic component device according to claim 2, further comprising a step of solidifying the conductive material and fixing the columnar conductor on the conductive film.

（付記４） 前記導電材料は、溶融する材料であって、溶融し凝固することによって溶融前よりも融点が高温側に変化する材料であることを特徴とする付記２又は３に記載の電子部品装置の製造方法。   (Supplementary note 4) The electronic component according to Supplementary note 2 or 3, wherein the conductive material is a material that melts and has a melting point that changes to a higher temperature side than before melting by melting and solidifying. Device manufacturing method.

（付記５） 前記第１配線層を形成する工程前、又は、前記第１配線層を形成する工程後に、前記基板の前記第１面と反対側の第２面を研削する工程を更に含むことを特徴とする付記１乃至４のいずれかに記載の電子部品装置の製造方法。   (Supplementary Note 5) The method further includes a step of grinding the second surface of the substrate opposite to the first surface before the step of forming the first wiring layer or after the step of forming the first wiring layer. The method for manufacturing an electronic component device according to any one of appendices 1 to 4, wherein:

（付記６） 前記第１配線層を形成する工程後に、前記電子部品、前記柱状導体、前記導電パターン及び前記第１導電部を含む領域の周囲で、前記樹脂組成物の層及び前記第１配線層を切断する工程を更に含むことを特徴とする付記１乃至５のいずれかに記載の電子部品装置の製造方法。   (Supplementary Note 6) After the step of forming the first wiring layer, the resin composition layer and the first wiring around the region including the electronic component, the columnar conductor, the conductive pattern, and the first conductive portion. The method for manufacturing an electronic component device according to any one of appendices 1 to 5, further comprising a step of cutting the layer.

（付記７） 前記第１配線層を形成する工程後に、前記基板の前記第１面と反対側の第２面上に、前記柱状導体に電気的に接続された第２導電部を有する第２配線層を形成する工程を更に含むことを特徴とする付記１乃至５のいずれかに記載の電子部品装置の製造方法。   (Supplementary Note 7) After the step of forming the first wiring layer, a second conductive portion electrically connected to the columnar conductor is provided on the second surface opposite to the first surface of the substrate. The method for manufacturing an electronic component device according to any one of appendices 1 to 5, further comprising a step of forming a wiring layer.

（付記８） 前記第２配線層を形成する工程後に、前記電子部品、前記柱状導体、前記導電パターン、前記第１導電部及び前記第２導電部を含む領域の周囲で、前記樹脂組成物の層、前記第１配線層及び前記第２配線層を切断する工程を更に含むことを特徴とする付記７に記載の電子部品装置の製造方法。   (Supplementary Note 8) After the step of forming the second wiring layer, the resin composition is formed around a region including the electronic component, the columnar conductor, the conductive pattern, the first conductive portion, and the second conductive portion. The method of manufacturing an electronic component device according to appendix 7, further comprising a step of cutting the layer, the first wiring layer, and the second wiring layer.

（付記９） 樹脂組成物層と、
前記樹脂組成物層内に設けられ、前記樹脂組成物層の第１面に電極が露出する電子部品と、
前記樹脂組成物層内に設けられた柱状導体と、
前記柱状導体上に設けられ、前記第１面から上面及び側面が露出する導電パターンと、
前記第１面上に設けられ、前記電極及び前記導電パターンに電気的に接続された第１導電部を有する第１配線層と
を含むことを特徴とする電子部品装置。 (Appendix 9) a resin composition layer;
An electronic component provided in the resin composition layer and having an electrode exposed on the first surface of the resin composition layer;
A columnar conductor provided in the resin composition layer;
A conductive pattern provided on the columnar conductor and exposing an upper surface and side surfaces from the first surface;
An electronic component device comprising: a first wiring layer provided on the first surface and having a first conductive portion electrically connected to the electrode and the conductive pattern.

（付記１０） 前記樹脂組成物層の前記第１面と反対側の第２面上に設けられ、前記柱状導体に電気的に接続された第２導電部を有する第２配線層を更に含むことを特徴とする付記９に記載の電子部品装置。   (Additional remark 10) It is provided on the 2nd surface on the opposite side to the said 1st surface of the said resin composition layer, and further contains the 2nd wiring layer which has the 2nd electroconductive part electrically connected to the said columnar conductor. Item 9. The electronic component device according to appendix 9, wherein

（付記１１） 第１電子部品装置と、
前記第１電子部品装置に実装された第２電子部品装置と
を有し、
前記第１電子部品装置は、
樹脂組成物層と、
前記樹脂組成物層内に設けられ、前記樹脂組成物層の第１面に電極が露出する電子部品と、
前記樹脂組成物層内に設けられた柱状導体と、
前記柱状導体上に設けられ、前記第１面から上面及び側面が露出する導電パターンと、
前記第１面上に設けられ、前記電極及び前記導電パターンに電気的に接続された第１導電部を有する第１配線層と
を含み、
前記第２電子部品装置は、前記樹脂組成物層の前記第１面と反対の第２面側に実装され、前記柱状導体を用いて前記第１電子部品装置と電気的に接続されていることを特徴とする電子装置。 (Appendix 11) a first electronic component device;
A second electronic component device mounted on the first electronic component device,
The first electronic component device is
A resin composition layer;
An electronic component provided in the resin composition layer and having an electrode exposed on the first surface of the resin composition layer;
A columnar conductor provided in the resin composition layer;
A conductive pattern provided on the columnar conductor and exposing an upper surface and side surfaces from the first surface;
A first wiring layer provided on the first surface and having a first conductive portion electrically connected to the electrode and the conductive pattern;
The second electronic component device is mounted on the second surface side opposite to the first surface of the resin composition layer, and is electrically connected to the first electronic component device using the columnar conductor. An electronic device characterized by the above.

（付記１２） 前記柱状導体の端面が前記第２面に露出し、
前記第２電子部品装置は、前記第２面に露出する前記端面に電気的に接続されていることを特徴とする付記１１に記載の電子装置。 (Additional remark 12) The end surface of the said columnar conductor is exposed to the said 2nd surface,
The electronic device according to appendix 11, wherein the second electronic component device is electrically connected to the end surface exposed on the second surface.

（付記１３） 前記第１電子部品装置は、前記第２面上に設けられ、前記柱状導体に電気的に接続された第２導電部を有する第２配線層を更に含み、
前記第２電子部品装置は、前記第２配線層に電気的に接続されていることを特徴とする付記１１に記載の電子装置。 (Supplementary Note 13) The first electronic component device further includes a second wiring layer provided on the second surface and having a second conductive portion electrically connected to the columnar conductor,
The electronic device according to appendix 11, wherein the second electronic component device is electrically connected to the second wiring layer.

（付記１４） 前記第１電子部品装置の前記第１配線層側に配置され、前記第１配線層に電気的に接続された回路基板を更に含むことを特徴とする付記１１乃至１３のいずれかに記載の電子装置。   (Additional remark 14) Any one of additional remarks 11 thru | or 13 further including the circuit board arrange | positioned at the said 1st wiring layer side of the said 1st electronic component apparatus and electrically connected to the said 1st wiring layer. An electronic device according to 1.

１，１Ａ，２１０，２１０ａ，２２０ 電子部品装置
１ａ，１ｂ 構造部
１０ 支持体
２０ 粘着層
３０ 電子部品
３０ａ 電極面
３０ｂ 背面
３１，１４１ 電極
４０，２２４ 樹脂組成物層
５０，５０Ａ 擬似ウェハ
５０ａ 表面
５０ｂ 裏面
６０，６０Ａ 再配線層
６１ 導電部
６１ａ，６１ｃ ビア
６１ｂ，６１ｄ 配線
６１ｅ ニッケル
６１ｆ 金
６２ 絶縁部
６２ａ，６２ｄ 感光性樹脂
６２ｂ，６２ｃ，６２ｅ，７１ 開口部
６２ｆ 保護膜
６３，１５２ 端子
７０，７０Ａ 導電パターン
７０ａ 導電膜
８０ 柱状導体
８１ 軸部
８２ 頭部
９０ 導電材料
１１０，１２０ 金型
１１０ａ，１２０ａ 金属板
１１０ｂ，１２０ｂ 貫通孔
１３０ レジストパターン
１４０ 受動部品
１５０ 貫通ビア
１５１，２２５ バンプ
２００Ａ，２００Ｂ，２００Ｃ，２００Ｄ 電子装置
２２１ パッケージ基板
２２２ ワイヤ
２２３ 半導体チップ
２３０ 回路基板 1, 1A, 210, 210a, 220 Electronic component device 1a, 1b Structure 10 Support body 20 Adhesive layer 30 Electronic component 30a Electrode surface 30b Rear surface 31, 141 Electrode 40, 224 Resin composition layer 50, 50A Pseudo wafer 50a Surface 50b Back surface 60, 60A Rewiring layer 61 Conductive part 61a, 61c Via 61b, 61d Wiring 61e Nickel 61f Gold 62 Insulating part 62a, 62d Photosensitive resin 62b, 62c, 62e, 71 Opening 62f Protective film 63, 152 Terminal 70, 70A Conductive pattern 70a Conductive film 80 Columnar conductor 81 Shaft part 82 Head 90 Conductive material 110, 120 Mold 110a, 120a Metal plate 110b, 120b Through hole 130 Resist pattern 140 Passive component 150 Through via 151, 225 Bump 200A, 200B, 20 C, 200D electronic device 221 package substrate 222 wire 223 semiconductor chip 230 circuit board

Claims (8)

支持体上に粘着層を設ける工程と、
前記粘着層上に、開口部を有する導電膜を設ける工程と、
前記開口部の前記粘着層上に電子部品を設ける工程と、
前記導電膜上に柱状導体を立てる工程と、
前記粘着層上に、前記導電膜、前記電子部品及び前記柱状導体を樹脂組成物で被覆した基板を形成する工程と、
前記基板を前記粘着層から分離する工程と、
前記粘着層から分離された前記基板の前記導電膜を部分的に除去し、前記柱状導体に対応する部分を含む導電パターンを形成する工程と、
前記基板の前記導電パターンが形成された第１面上に、前記電子部品及び前記導電パターンに電気的に接続された第１導電部を有する第１配線層を形成する工程と
を含むことを特徴とする電子部品装置の製造方法。 Providing an adhesive layer on the support;
Providing a conductive film having an opening on the adhesive layer;
Providing an electronic component on the adhesive layer of the opening;
Erecting columnar conductors on the conductive film;
On the adhesive layer, forming a substrate in which the conductive film, the electronic component, and the columnar conductor are covered with a resin composition;
Separating the substrate from the adhesive layer;
Partially removing the conductive film of the substrate separated from the adhesive layer and forming a conductive pattern including a portion corresponding to the columnar conductor;
Forming a first wiring layer having a first conductive portion electrically connected to the electronic component and the conductive pattern on a first surface of the substrate on which the conductive pattern is formed. A method for manufacturing an electronic component device. 前記柱状導体を立てる工程は、前記導電膜上に導電材料を用いて前記柱状導体を固定する工程を含むことを特徴とする請求項１に記載の電子部品装置の製造方法。   The method of manufacturing an electronic component device according to claim 1, wherein the step of raising the columnar conductor includes a step of fixing the columnar conductor using a conductive material on the conductive film. 前記第１配線層を形成する工程前、又は、前記第１配線層を形成する工程後に、前記基板の前記第１面と反対側の第２面を研削する工程を更に含むことを特徴とする請求項１又は２に記載の電子部品装置の製造方法。   The method further includes a step of grinding a second surface opposite to the first surface of the substrate before the step of forming the first wiring layer or after the step of forming the first wiring layer. The manufacturing method of the electronic component apparatus of Claim 1 or 2. 前記第１配線層を形成する工程後に、前記電子部品、前記柱状導体、前記導電パターン及び前記第１導電部を含む領域の周囲で、前記樹脂組成物の層及び前記第１配線層を切断する工程を更に含むことを特徴とする請求項１乃至３のいずれかに記載の電子部品装置の製造方法。   After the step of forming the first wiring layer, the resin composition layer and the first wiring layer are cut around a region including the electronic component, the columnar conductor, the conductive pattern, and the first conductive portion. The method for manufacturing an electronic component device according to claim 1, further comprising a step. 前記第１配線層を形成する工程後に、前記基板の前記第１面と反対側の第２面上に、前記柱状導体に電気的に接続された第２導電部を有する第２配線層を形成する工程を更に含むことを特徴とする請求項１乃至３のいずれかに記載の電子部品装置の製造方法。   After the step of forming the first wiring layer, a second wiring layer having a second conductive portion electrically connected to the columnar conductor is formed on the second surface of the substrate opposite to the first surface. The method for manufacturing an electronic component device according to claim 1, further comprising a step of: 前記第２配線層を形成する工程後に、前記電子部品、前記柱状導体、前記導電パターン、前記第１導電部及び前記第２導電部を含む領域の周囲で、前記樹脂組成物の層、前記第１配線層及び前記第２配線層を切断する工程を更に含むことを特徴とする請求項５に記載の電子部品装置の製造方法。   After the step of forming the second wiring layer, around the region including the electronic component, the columnar conductor, the conductive pattern, the first conductive portion, and the second conductive portion, the layer of the resin composition, the first 6. The method of manufacturing an electronic component device according to claim 5, further comprising a step of cutting one wiring layer and the second wiring layer. 樹脂組成物層と、
前記樹脂組成物層内に設けられ、前記樹脂組成物層の第１面に電極が露出する電子部品と、
前記樹脂組成物層内に設けられた柱状導体と、
前記柱状導体上に設けられ、前記第１面から上面及び側面が露出する導電パターンと、
前記第１面上に設けられ、前記電極及び前記導電パターンに電気的に接続された第１導電部を有する第１配線層と
を含むことを特徴とする電子部品装置。 A resin composition layer;
An electronic component provided in the resin composition layer and having an electrode exposed on the first surface of the resin composition layer;
A columnar conductor provided in the resin composition layer;
A conductive pattern provided on the columnar conductor and exposing an upper surface and side surfaces from the first surface;
An electronic component device comprising: a first wiring layer provided on the first surface and having a first conductive portion electrically connected to the electrode and the conductive pattern. 第１電子部品装置と、
前記第１電子部品装置に実装された第２電子部品装置と
を有し、
前記第１電子部品装置は、
樹脂組成物層と、
前記樹脂組成物層内に設けられ、前記樹脂組成物層の第１面に電極が露出する電子部品と、
前記樹脂組成物層内に設けられた柱状導体と、
前記柱状導体上に設けられ、前記第１面から上面及び側面が露出する導電パターンと、
前記第１面上に設けられ、前記電極及び前記導電パターンに電気的に接続された第１導電部を有する第１配線層と
を含み、
前記第２電子部品装置は、前記樹脂組成物層の前記第１面と反対の第２面側に実装され、前記柱状導体を用いて前記第１電子部品装置と電気的に接続されていることを特徴とする電子装置。 A first electronic component device;
A second electronic component device mounted on the first electronic component device,
The first electronic component device is
A resin composition layer;
An electronic component provided in the resin composition layer and having an electrode exposed on the first surface of the resin composition layer;
A columnar conductor provided in the resin composition layer;
A conductive pattern provided on the columnar conductor and exposing an upper surface and side surfaces from the first surface;
A first wiring layer provided on the first surface and having a first conductive portion electrically connected to the electrode and the conductive pattern;
The second electronic component device is mounted on the second surface side opposite to the first surface of the resin composition layer, and is electrically connected to the first electronic component device using the columnar conductor. An electronic device characterized by the above.
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