JP2014110337A - Electronic component device manufacturing method, electronic component device and electronic device - Google Patents

Electronic component device manufacturing method, electronic component device and electronic device Download PDF

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JP2014110337A
JP2014110337A JP2012264412A JP2012264412A JP2014110337A JP 2014110337 A JP2014110337 A JP 2014110337A JP 2012264412 A JP2012264412 A JP 2012264412A JP 2012264412 A JP2012264412 A JP 2012264412A JP 2014110337 A JP2014110337 A JP 2014110337A
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electronic component
conductive
layer
columnar conductor
resin composition
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JP2012264412A
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JP5942823B2 (en
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Motoaki Tani
元昭 谷
Yoshikatsu Ishizuki
義克 石月
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Fujitsu Ltd
富士通株式会社
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    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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Abstract

An electronic component device including a columnar conductor is stably manufactured while suppressing the collapse of the columnar conductor.
A conductive film having an opening is provided on an adhesive layer provided on a support, an electronic component is provided on the adhesive layer in the opening, and a columnar shape is provided on the conductive film. The conductor 80 is erected. From this state, the conductive film 70a, the electronic component 30 and the columnar conductor 80 are covered with the resin composition layer 40 to form the pseudo wafer 50, and after separating it from the adhesive layer 20, the conductive film 70a of the pseudo wafer 50 is formed. The conductive pattern 70 is formed by partially removing. A rewiring layer is formed on the pseudo wafer 50 on which the conductive pattern 70 is formed, and dicing is performed to form an electronic component device.
[Selection] Figure 9

Description

  The present invention relates to an electronic component device manufacturing method, an electronic component device, and an electronic device.

  As one of electronic component devices (packages) including electronic components such as semiconductor chips (semiconductor elements), WLP (Wafer Level Package) (WL-CSP (Wafer Level-Chip Size Package)), W-CSP (Wafer-Chip Size) Also known as “Package”). WLP makes it possible to rearrange (Fan-in) the terminals of an electronic component within its component area. In addition, with the increase in the number of terminals of electronic components, WLP that rearranges terminals outside the component area (fan-out) has also been developed in view of the difficulty in rearranging terminals only in the component area. ing.

  Regarding the manufacture of such a package, for example, a technique using a method of disposing a semiconductor chip on a support, sealing the semiconductor chip with a resin composition to form a so-called pseudo wafer, and peeling the pseudo wafer from the support It has been known. A wiring layer is provided on the surface of the pseudo wafer peeled from the support, and is separated into pieces by dicing to obtain individual electronic component devices.

  In addition, the semiconductor chip and the columnar conductor are respectively disposed on the conductive pattern formed on the support using solder or the like, and after embedding them in a resin composition that has been formed into a plate shape by cutting or the like, the support is removed. A technique for obtaining an electronic component device is also known. In addition, the technology for laminating the obtained electronic component device, the technology for forming through vias using laser processing etc. on the resin composition layer, the technology for providing conductive patterns on the front and back surfaces of the resin composition layer, etc. are also known. It has been.

US Patent Application Publication No. 2006/0183269 JP 2001-308116 A JP 2002-134653 A

  In an electronic component device, when a through via is provided in a resin composition layer that seals an electronic component such as a semiconductor chip, a plurality of electronic component devices are stacked, or a conductive pattern and a wiring layer are formed on both surfaces of the resin composition layer. Can be formed. As a result, it is possible to improve the mounting density.

  However, in order to provide such a through via, if a method of forming a through hole in a resin composition layer by laser processing and embedding a conductive material is used, it may take time for laser processing and embedding.

  Further, in the method of sealing a columnar conductor with a resin composition together with an electronic component such as a semiconductor chip, when sealing, if the connection between the conductive pattern on which the columnar conductor is arranged and the support is weak, the pressure at the time of sealing Thus, the conductive pattern may be peeled off from the support, and the columnar conductor may fall down.

  According to one aspect of the present invention, a step of providing an adhesive layer on a support, a step of providing a conductive film having an opening on the adhesive layer, and providing an electronic component on the adhesive layer of the opening A step of standing a columnar conductor on the conductive film, a step of forming a substrate in which the conductive film, the electronic component, and the columnar conductor are covered with a resin composition on the adhesive layer; and A step of separating from the adhesive layer, a step of partially removing the conductive film of the substrate separated from the adhesive layer, forming a conductive pattern including a portion corresponding to the columnar conductor, and the conductive of the substrate Forming a first wiring layer having a first conductive portion electrically connected to the electronic component and the conductive pattern on a first surface on which a pattern is formed. Is done.

  Moreover, according to one aspect of the present invention, an electronic component device manufactured using the method as described above, and an electronic device including such an electronic component device are provided.

  According to the disclosed technology, it is possible to stably manufacture an electronic component device that includes an electronic component and a columnar conductor in a layer of the resin composition and can be mounted at high density while suppressing the collapse of the columnar conductor. .

It is a figure (the 1) which shows an example of the manufacturing method of an electronic component apparatus. It is FIG. (2) which shows an example of the manufacturing method of an electronic component apparatus. It is FIG. (1) which shows another example of the manufacturing method of an electronic component apparatus. It is FIG. (2) which shows another example of the manufacturing method of an electronic component apparatus. It is explanatory drawing (the 1) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. It is explanatory drawing (the 2) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. It is explanatory drawing (the 3) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. It is explanatory drawing (the 4) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. It is explanatory drawing (the 5) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. It is explanatory drawing (the 6) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. It is explanatory drawing (the 7) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. It is explanatory drawing (the 8) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. It is explanatory drawing (the 9) of the manufacturing method of the electronic component apparatus which concerns on 1st Embodiment. It is explanatory drawing (the 1) of the manufacturing method of the electronic component apparatus which concerns on 2nd Embodiment. It is explanatory drawing (the 2) of the manufacturing method of the electronic component apparatus which concerns on 2nd Embodiment. It is a figure which shows the 1st structural example of an electronic device. It is a figure which shows the 2nd structural example of an electronic device. It is a figure which shows the 3rd structural example of an electronic device. It is a figure which shows the 4th structural example of an electronic apparatus. It is a figure which shows another example of an electronic device.

  1 and 2 are diagrams illustrating an example of a method for manufacturing an electronic component device. 1A to 1E are schematic cross-sectional views of the main part of each manufacturing process of the electronic component device. FIG. 2 is a schematic plan view of the manufacturing process shown in FIG.

  In this method, first, an adhesive layer 20 is provided on a support 10 as shown in FIG. As the support 10, a metal substrate, a glass substrate, a printed substrate, a semiconductor substrate, a ceramic substrate, or the like is used. For the adhesive layer 20, in addition to an adhesive film in which an adhesive is provided on a predetermined substrate, a material obtained by applying an adhesive on the support 10 by a spin coating method, a spray coating method, a printing method, or the like is used. The adhesive layer 20 can peel the pseudo wafer 50A after forming the pseudo wafer 50A as will be described later, for example, one that can reduce the adhesive strength by heating or ultraviolet irradiation at the time of peeling. Used. As such a pressure-sensitive adhesive layer 20, a heat-foaming pressure-sensitive adhesive layer that foams by heating and decreases in adhesive strength, or an ultraviolet-foamable pressure-sensitive adhesive layer that foams by irradiation with ultraviolet rays and decreases in adhesive strength is used. Moreover, you may use what can peel 50 A of pseudo wafers, without performing processes, such as a heating and ultraviolet irradiation.

  After the adhesive layer 20 is provided on the support 10, as shown in FIG. 1B, an electronic component 30 such as a semiconductor element is provided on the adhesive layer 20 on the surface (electrode surface) on which the electrode 31 is provided. ) 30a is provided toward the adhesive layer 20 side. Although one electronic component 30 is illustrated in FIG. 1B, a plurality (four as an example here) of electronic components 30 are respectively predetermined on the adhesive layer 20 as shown in FIG. In the same manner as in FIG. 1B, each electrode surface 30a is provided toward the adhesive layer 20 side. Here, for convenience, attention is focused on one electronic component 30 and the subsequent steps will be described.

  After the electronic component 30 is provided on the pressure-sensitive adhesive layer 20, a resin composition is supplied onto the pressure-sensitive adhesive layer 20, and is molded to form a resin composition layer 40 as shown in FIG. The resin composition used for the resin composition layer 40 includes an insulating resin and a filler. As the resin of the resin composition, a thermosetting resin, a thermoplastic resin, a resin that is cured by ultraviolet irradiation, or the like is used. As the filler of the resin composition, a non-conductive filler, for example, an inorganic filler such as aluminum oxide, silicon oxide, aluminum hydroxide, or aluminum nitride is used. The resin composition supplied onto the adhesive layer 20 is pressure-molded (molded) using a mold (mold) having a recess (inner surface) provided in accordance with the shape of the resin composition layer 40 to be formed. Thus, the resin composition layer 40 is formed on the adhesive layer 20.

  The formed resin composition layer 40 is cured by a technique according to the type of the resin. Thereby, a pseudo wafer (substrate) 50 </ b> A in which the electronic component 30 is coated (sealed) with the resin composition layer 40 is formed on the adhesive layer 20. In addition, the resin composition layer 40 does not necessarily need to be completely cured at this stage, and the pseudo wafer 50A peeled off from the adhesive layer 20 can be handled while maintaining its wafer state as will be described later. It only needs to be cured to a certain extent. In addition, the curing condition of the resin composition layer 40 at this stage is set based on the materials of the resin composition layer 40 and the adhesive layer 20 so that the adhesive strength of the adhesive layer 20 is maintained. Alternatively, the material of the adhesive layer 20 is set based on the material of the resin composition layer 40 and the curing conditions.

  After the formation of the pseudo wafer 50A, the pseudo wafer 50A is peeled off from the adhesive layer 20 and separated from the adhesive layer 20 and the support 10 as shown in FIG. When peeling the pseudo wafer 50 </ b> A from the adhesive layer 20, for example, the adhesive layer 20 is subjected to a process (heating, ultraviolet irradiation, etc.) for reducing the adhesive force. By such treatment, the adhesive force of the adhesive layer 20 is reduced, and the pseudo wafer 50A is peeled from the adhesive layer 20. After peeling, the resin composition layer 40 of the pseudo wafer 50A is further cured (completely cured) by a predetermined method according to the type of the resin. The peeled pseudo wafer 50 </ b> A may be ground (back grind) from the surface opposite to the surface peeled from the adhesive layer 20.

  As shown in FIG. 1E, a wiring layer (rewiring layer) 60A is formed on the surface of the pseudo wafer 50A that has been peeled off from the adhesive layer 20. The rewiring layer 60 </ b> A includes a conductive portion 61 such as a via and a wiring electrically connected to the electrode 31 of the electronic component 30, and an insulating portion 62 provided around the conductive portion 61. For the conductive portion 61, a conductive material such as copper, copper alloy, or aluminum is used. An insulating material such as an epoxy resin or a polyimide resin is used for the insulating portion 62. In the pseudo wafer 50A shown in this example, the electrode 31 of the electronic component 30 is rearranged (Fan-out) to the terminal 63 outside the area of the electronic component 30 by the rewiring layer 60A.

  The pseudo wafer 50A includes a plurality of electronic components 30, and includes a plurality of structural portions as shown in FIG. The pseudo wafer 50A on which the rewiring layer 60A is formed is diced at a position around the structure as shown in FIG. 1E, and is thereby separated into individual electronic component devices 1A. . The electronic component device 1A can be mounted on another electronic component device or a circuit board using the rewiring layer 60A.

  For the electronic component device 1A as described above, a conductor that penetrates through the resin composition layer 40 and is electrically connected to the rewiring layer 60A, for example, a through via, may be provided. When such a through via is provided, the through via exposed on the surface of the resin composition layer 40 opposite to the rewiring layer 60A can be used as a terminal. Further, when the through via is provided, another rewiring layer electrically connected to the rewiring layer 60A through the through via is formed on the surface of the resin composition layer 40 opposite to the rewiring layer 60A. It is also possible to provide terminals in the rewiring layer. By using the terminal obtained by providing the through via, it becomes possible to mount another electronic component device on the electronic component device 1A, so that high-density mounting can be realized. Become.

  As a method of forming the through via in the resin composition layer 40, a method of forming a through hole in the resin composition layer 40 by laser processing and embedding the through hole with a conductive material can be considered. However, in this method, depending on the thickness of the resin composition layer 40 on which laser processing is performed, the time required for the laser processing may be increased, or the time required for embedding the conductive material in the through hole may be increased. .

  As another method, a method in which a columnar conductor is provided together with the electronic component 30 in the resin composition layer 40 and this is used as a through via is also conceivable. Hereinafter, a method using such a columnar conductor will be described.

  3 and 4 are diagrams showing another example of a method for manufacturing an electronic component device. 3A to 3C are schematic cross-sectional views of the main part of each manufacturing process of the electronic component device. FIG. 4 is a schematic plan view of the manufacturing process shown in FIG.

  In this method, as shown in FIGS. 3A and 4, an electrode pad (conductive pattern) 70 </ b> A is provided on the adhesive layer 20 provided on the support 10. On the adhesive layer 20, for example, a plurality of conductive patterns 70 </ b> A are provided at positions where columnar conductors 80 are provided as will be described later. A metal material such as copper is used for the conductive pattern 70A.

  After providing the conductive pattern 70A, as shown in FIG. 3B, an electronic component 30 such as a semiconductor chip is provided on the adhesive layer 20, and a columnar conductor 80 is provided on the conductive pattern 70A on the adhesive layer 20. As for the electronic component 30, the electrode surface 30a is affixed on the adhesion layer 20, and the columnar conductor 80 is joined upright on the conductive pattern 70A using the conductive material 90. For the columnar conductor 80, a conductive pin, for example, a metal pin such as copper is used. As the conductive material 90, for example, a metal material such as solder, or a conductive paste using a metal material is used.

  After the electronic component 30, the conductive pattern 70, the conductive material 90, and the columnar conductor 80 are provided on the adhesive layer 20 as described above, a resin is formed on the adhesive layer 20 as shown in FIG. A composition layer 40 is provided. However, if the resin composition layer 40 is provided by molding as described above, the columnar conductor 80 is added together with the conductive pattern 70A joined by the conductive material 90 at the time of molding as shown in FIG. There is a case where the resin composition is pressed and falls down.

  This is because the resin composition contains a filler in the resin and thus has a relatively high viscosity, and when the conductive pattern 70A having a size matching the cross-sectional size of the columnar conductor 80 is provided, the conductive pattern 70A and the adhesive layer The adhesion area of 20 is small. On the other hand, the bonding strength between the columnar conductor 80 bonded to the conductive material 90 such as solder and the conductive pattern 70A is higher than the bonding strength between the conductive pattern 70A and the adhesive layer 20. Therefore, the columnar conductor 80 is pressed by a resin composition having a relatively high viscosity that is pressed during molding, and the conductive pattern 70A in which the columnar conductor 80 is bonded with the conductive material 90 is peeled off from the adhesive layer 20, and the columnar conductor 80 is removed. It falls down.

  With respect to one pseudo wafer 50A, there may be a case where all the columnar conductors 80 are collapsed due to the peeling of the conductive pattern 70A at the time of such molding, or a case where the columnar conductors 80 are collapsed or not collapsed. In addition, there may be a case in which the columnar conductor 80 that has fallen and the columnar conductor 80 that has not collapsed coexist in a structure corresponding to one electronic component device in the pseudo wafer 50A. In the method as shown in FIGS. 3 and 4, an electronic component device using the columnar conductor 80 as a through via as described above may not be manufactured stably.

Therefore, in view of such collapse of the columnar conductor 80 during molding, a method as described below as an embodiment is used.
5-13 is explanatory drawing of the manufacturing method of the electronic component apparatus based on 1st Embodiment. Hereinafter, an example of a method for manufacturing the electronic component device according to the first embodiment will be described with reference to FIGS.

  FIG. 5A is a schematic cross-sectional view of the main part of the adhesive layer disposing step according to the first embodiment, and FIG. 5B is a schematic cross-sectional view of the main part of the conductive film disposing step according to the first embodiment. FIG. 5C is a schematic cross-sectional view of the main part of the electronic component and columnar conductor arranging step according to the first embodiment. 6 (A) to 6 (C) are schematic plan views of the respective manufacturing steps shown in FIGS. 5 (A) to 5 (C).

  In this method, as shown above, as shown in FIGS. 5 (A) and 6 (A), after the adhesive layer 20 is provided on the support 10, as shown in FIGS. 5 (B) and 6 (B). In addition, a conductive film 70 a having an opening 71 is provided on the adhesive layer 20. A metal film can be used for the conductive film 70a. In addition to copper, a metal material such as aluminum or nickel is used for the metal film used as the conductive film 70a. The opening 71 of the conductive film 70a is provided in a region where the electronic component 30 such as a semiconductor chip is disposed.

  When the metal film is formed as the conductive film 70a, the conductive film 70a can be formed by attaching a metal foil or a metal plate on the adhesive layer 20, or depositing the film by a sputtering method or a vapor deposition method. After the conductive film 70a is formed on the adhesive layer 20 using such a method, the opening 71 is formed in the conductive film 70a. The opening 71 can be formed by etching the conductive film 70 a on the adhesive layer 20. The material of the conductive film 70a is preferably a material such as copper, aluminum, or nickel as described above, which has good conductivity and can perform such etching process relatively easily.

  In addition, as a method of providing the conductive film 70 a having the opening 71 on the adhesive layer 20, a conductive film 70 a such as a metal foil provided with the opening 71 in advance is prepared, and this is applied to the adhesive layer 20. It is also possible to use a method of

  After providing the conductive film 70a on the adhesive layer 20 as described above, as shown in FIGS. 5C and 6C, on the adhesive layer 20 exposed in the opening 71 of the conductive film 70a. The electronic component 30 is provided with the electrode surface 30a facing the adhesive layer 20 side. The electronic component 30 can be provided on the adhesive layer 20 using a flip chip bonder or a mounter.

  As shown in FIGS. 5C and 6C, a columnar conductor 80 is bonded onto the conductive film 70 a using a conductive material 90. The columnar conductor 80 is provided, for example, in a predetermined position on the conductive film 70a around the electronic component 30 provided on the adhesive layer 20 of the opening 71. The position where the columnar conductor 80 is provided can be set based on the position of the opening 71 of the conductive film 70a (for example, the corner of the opening 71).

The columnar conductor 80 can be provided on the conductive film 70a using, for example, a method as shown in FIG. 7 or FIG.
FIG. 7 is a diagram showing a first example of a columnar conductor arrangement method.

  In this method, first, as shown in FIG. 7A, a mold 110 in which a through hole 110b is formed in a metal plate 110a such as stainless steel is prepared. Such a mold 110 is disposed so as to face the conductive film 70 a provided on the adhesive layer 20 on the support 10. As shown in FIG. 7B, a conductive material 90 such as solder is provided in advance at one end of the columnar conductor 80. Thus, the columnar conductor 80 having the conductive material 90 provided at the tip portion is inserted into the through hole 110b of the mold 110 and joined to the conductive film 70a by melting and solidification of the conductive material 90.

  Here, the case where the conductive material 90 is provided in advance at the tip of the columnar conductor 80 and is inserted into the through hole 110b of the mold 110 is illustrated. In addition, the conductive material 90 is provided in advance on the conductive film 70 a, and a single columnar conductor 80 is inserted into the through hole 110 b of the mold 110, and the columnar conductor 80 is made conductive by melting and solidifying the conductive material 90. You may make it join on the film | membrane 70a. The through hole 110b has an inner diameter through which the columnar conductor 80 provided with the conductive material 90 at the tip or a single columnar conductor 80 can be inserted.

FIG. 8 is a diagram showing a second example of the columnar conductor arrangement method.
In this method, a columnar conductor 80 as shown in FIG. A columnar conductor 80 shown in FIG. 8A has a shaft portion 81 and a head portion 82 having a diameter larger than that of the shaft portion 81. A conductive material 90 such as solder is provided on the head 82 in advance. The shaft portion 81 of the columnar conductor 80 is inserted into the through hole 120b of the mold 120 in which the through hole 120b is formed in the metal plate 120a such as stainless steel. The through hole 120b has a smaller diameter than the head portion 82 of the columnar conductor 80, and the columnar conductor 80 in which the shaft portion 81 is inserted into the through hole 120b from above is hooked on the upper surface of the mold 120 and supported by the head portion 82. Is done.

  As shown in FIG. 8A, the support 10 provided with the adhesive layer 20 and the conductive film 70a is above the mold 120 provided with the columnar conductor 80 and the conductive material 90 (on the head 82 side of the columnar conductor 80). ) Is disposed so that the conductive film 70a and the mold 120 face each other. Then, for example, the mold 120 provided with the columnar conductor 80 and the conductive material 90 is pressed toward the conductive film 70a, and the conductive material 90 is melted and solidified to conduct the columnar conductor 80 as shown in FIG. The material 90 is bonded onto the conductive film 70a.

In the steps shown in FIGS. 5C and 6C, the columnar conductor 80 can be bonded to the conductive film 70a with the conductive material 90 by using the method shown in FIG. 7 or FIG.
As the conductive material 90, a metal material having a relatively low melting point such as solder is used. As the metal material used for the conductive material 90, for example, a material containing at least one of tin, lead, silver, copper, bismuth, antimony, and indium is preferably used. Further, as the conductive material 90, it is preferable to use a metal material whose melting point shifts to a higher temperature side than the melting point before melting when the columnar conductor 80 and the conductive film 70a are joined. For example, the conductive material 90 includes in advance a predetermined concentration of a component whose melting point shifts to a high temperature side due to melting and solidification during bonding.

  The columnar conductor 80 can be bonded to the conductive film 70 a with the conductive material 90 after the electronic component 30 is provided on the adhesive layer 20 of the opening 71. Alternatively, after the columnar conductor 80 is bonded to the conductive film 70 a with the conductive material 90, the electronic component 30 can be provided on the adhesive layer 20 in the opening 71.

  FIG. 5C shows one electronic component 30, but a plurality (four as an example) of electronic components 30 are provided on the adhesive layer 20 as shown in FIG. 6C. As in FIG. 5C, each electrode surface 30a is provided at a predetermined location, facing the adhesive layer 20 side. A plurality of columnar conductors 80 are provided around each electronic component 30. The number and arrangement of the columnar conductors 80 are not limited to the example of FIG. Here, for the sake of convenience, attention is focused on one electronic component 30 and the columnar conductor 80 around it, and the subsequent steps of FIGS. 9 and 10 will be described.

  FIG. 9A is a schematic cross-sectional view of an essential part of a resin composition layer forming step according to the first embodiment, and FIG. 9B is a schematic cross-sectional view of an essential part of a pseudo wafer separation process according to the first embodiment. FIG. 9C is a schematic cross-sectional view of the relevant part of the resist pattern forming process according to the first embodiment, and FIG. 9D is a schematic cross-sectional view of the relevant part of the conductive pattern forming process according to the first embodiment. FIG. 10A is a schematic cross-sectional view of the main part of the back grinding process according to the first embodiment, and FIG. 10B is a schematic cross-sectional view of the main part of the first redistribution layer forming process according to the first embodiment. FIG. 10C is a schematic cross-sectional view of the relevant part in the second rewiring layer forming step according to the first embodiment.

  5C and 6C, the electronic component 30 is provided on the adhesive layer 20 in the opening 71 of the conductive film 70a, and the columnar conductor 80 is provided with the conductive material 90 on the conductive film 70a. Thereafter, as shown in FIG. 9A, a resin composition layer 40 covering them is formed. The resin composition layer 40 is formed by molding a resin composition containing an insulating resin and a filler as described above. The resin composition layer 40 is cured or semi-cured by a method according to the type of the resin. As a result, the conductive film 70a on the adhesive layer 20, the electronic component 30 provided in the opening 71 thereof, and the columnar conductor 80 bonded to the conductive film 70a with the conductive material 90 are covered with the resin composition layer 40. The pseudo wafer 50 is formed on the adhesive layer 20.

  Here, the columnar conductor 80 is joined to the conductive film 70a by the conductive material 90. The conductive film 70a has a larger area than the conductive pattern 70A as shown in FIGS. Bonded to the adhesive layer 20. Therefore, even if the columnar conductor 80 joined with the conductive material 90 on the conductive film 70a is pressed with a relatively high viscosity resin composition at the time of molding, peeling of the conductive film 70a from the adhesive layer 20 is suppressed, The collapse of the columnar conductor 80 is suppressed. Thereby, the situation where the fallen columnar conductor 80 is contained in the pseudo wafer 50 or the structure part corresponding to one electronic component device in the pseudo wafer 50 can be effectively suppressed.

  After the formation of the resin composition layer 40, the pseudo wafer 50 is separated from the adhesive layer 20 as shown in FIG. For example, the adhesive layer 20 is subjected to a process for reducing the adhesive force (heating, ultraviolet irradiation, etc.), and the pseudo wafer 50 is peeled from the adhesive layer 20. The conductive film 70 a and the electrode surface 30 a of the electronic component 30 are exposed on one surface (surface 50 a) of the pseudo wafer 50 that is peeled from the adhesive layer 20.

  After peeling off the pseudo wafer 50, as shown in FIG. 9C, a resist pattern 130 is formed on the surface 50a of the pseudo wafer 50 where the conductive film 70a is exposed. The resist pattern 130 is formed in a region including a portion corresponding to the columnar conductor 80 in the pseudo wafer 50 on the conductive film 70a. The resist pattern 130 is formed in a region including a portion corresponding to the columnar conductor 80 with reference to the position of the opening 71 of the conductive film 70a. The resist pattern 130 is also formed on the electronic component 30 exposed together with the conductive film 70a.

  After the resist pattern 130 is formed, the conductive film 70a is etched using the resist pattern 130 as a mask, and the conductive pattern 70 is formed in a region including a portion corresponding to the columnar conductor 80 as shown in FIG. 9D. To do. The conductive pattern 70 can be formed by wet etching. During wet etching, as shown in FIG. 9C, by providing a resist pattern 130 on the electronic component 30 in addition to the region where the conductive pattern 70 is formed, the electrode surface 30a of the electronic component 30 is formed. Protected from etchant.

  As the conductive pattern 70 formed in the step of FIG. 9D, an electrode pad provided in a portion corresponding to the columnar conductor 80 can be formed. In addition, as the conductive pattern 70, an electrode pad provided in a portion corresponding to the columnar conductor 80 and a wiring extending from the electrode pad can be formed. Furthermore, in addition to such an electrode pad or a wiring extending from the electrode pad, a wiring independent from a portion corresponding to the columnar conductor 80 can be formed as the conductive pattern 70. In the step of FIG. 9C, the resist pattern 130 is formed so that the predetermined conductive pattern 70 is formed in the step of FIG. 9D. After the formation of the conductive pattern 70, the resist pattern 130 is removed.

  After the formation of the conductive pattern 70, as shown in FIG. 10A, the surface (back surface 50b) opposite to the formation surface (front surface 50a) of the pseudo wafer 50 is ground to expose the columnar conductor 80. Let In that case, it is preferable that the end surface of the columnar conductor 80 remain higher than the surface (back surface) 30b on the side opposite to the electrode surface 30a of the electronic component 30. This is because if the columnar conductor 80 using a metal material and the electronic component 30 such as a semiconductor chip are ground at the same time, grinding scraps of the columnar conductor 80 may adhere to the back surface 30b of the electronic component 30. . The grinding scraps of the columnar conductor 80 adhering to the back surface 30b of the electronic component 30 may have its components diffused into the electronic component 30 or the like, for example, when heated thereafter. There is a risk of performance degradation. Thus, the grinding of the pseudo wafer 50 is performed so that the end surface of the columnar conductor 80 is positioned higher than the back surface 30b of the electronic component 30, that is, the back surface 30b of the electronic component 30 is the resin composition layer 40. It is preferable to carry out to the position of the coated state.

  Thus, the end face of the columnar conductor 80 joined to the conductive pattern 70 with the conductive material 90 is exposed to the back surface 50b opposite to the front surface 50a by grinding the pseudo wafer 50. Accordingly, the conductive pattern 70, the conductive material 90, and the columnar conductor 80 can be used as a through via that penetrates the pseudo wafer 50.

Note that the grinding for exposing the columnar conductor 80 shown in FIG. 10A can also be performed after the formation of the rewiring layer 60 shown in FIG. 10B.
A rewiring layer 60 is formed on the surface 50a of the pseudo wafer 50, that is, on the side of the electrode surface 30a of the electronic component 30 and the surface on which the conductive pattern 70 is formed, as shown in FIG. The rewiring layer 60 includes a conductive portion 61 such as a via and a wiring electrically connected to the electrode 31 and the conductive pattern 70 of the electronic component 30, and an insulating portion 62 provided around the conductive portion 61. For the conductive portion 61, a conductive material such as copper, copper alloy, or aluminum is used. An insulating material such as an epoxy resin or a polyimide resin is used for the insulating portion 62. In the pseudo wafer 50, the electrode 31 of the electronic component 30 is rearranged (Fan-out) by the rewiring layer 60 to the terminal 63 outside the area of the electronic component 30. The conductive portion 61 of the redistribution layer 60 is drawn to the back surface 50 b of the pseudo wafer 50 by the conductive pattern 70, the conductive material 90, and the columnar conductor 80.

The rewiring layer 60 on the pseudo wafer 50 can be formed, for example, using a method as shown in FIG.
FIG. 11 is a diagram illustrating an example of a method for forming a rewiring layer. Here, a method of forming the rewiring layer 60 will be described by taking the conductive portion 61 electrically connected to the electrode 31 and the conductive pattern 70 of the electronic component 30 as an example. FIG. 11A to FIG. 11E are schematic cross-sectional views of the relevant part in each step of forming the rewiring layer.

  First, as shown in FIG. 11A, photosensitive epoxy, photosensitive polybenzoxazole, photosensitive polyimide, or the like is formed on the surface 50a side of the pseudo wafer 50, that is, on the electrode surface 30a and the conductive pattern 70 side of the electronic component 30. Photosensitive resin 62a is applied. Then, the applied photosensitive resin 62 a is exposed, developed, and cured to form an opening 62 b that communicates with the electrode 31 of the electronic component 30 and an opening 62 c that communicates with the conductive pattern 70. Note that plasma treatment may be performed after the photosensitive resin 62a is cured.

  Next, a metal adhesion layer such as titanium or chromium and copper are formed by a sputtering method to form a seed layer. Thereafter, a resist pattern (not shown) having an opening at a portion where vias and wirings are formed is formed, and copper electroplating is performed using the previously formed seed layer. After the resist pattern is peeled off, the seed layer remaining in the region where the resist pattern has been formed is removed by etching. For the etching, wet etching or dry etching may be used. In this way, vias 61a and wirings 61b connected to the electrodes 31 of the electronic component 30 are formed as shown in FIG. The wiring 61b may be further subjected to a surface treatment for the purpose of improving adhesion. A first wiring layer is formed on the surface 50a side of the pseudo wafer 50 by the method as shown in FIGS. 11A and 11B.

  When the second wiring layer is formed, the photosensitive resin 62d is applied, exposed, developed, and cured as shown in FIG. 11C on the first wiring layer, as described above. Then, an opening 62e communicating with the wiring 61b is formed. Next, similarly to the above, formation of a seed layer, formation of a resist pattern, electroplating of copper, peeling of the resist pattern, and etching of the seed layer are performed to form a via 61c and a wiring 61d as shown in FIG. A second wiring layer is formed on the surface 50a side of the pseudo wafer 50 by a method as shown in FIGS. 11C and 11D.

  When the third and subsequent wiring layers are formed on the front surface 50a side of the pseudo wafer 50, the steps shown in FIGS. 11A and 11B (or FIGS. 11C and 11B described above) are performed. Steps similar to those shown in FIG. 11 (D) may be repeated.

  As shown in FIG. 11E, a part (external connection terminal) of the wiring 61d is exposed on the outermost wiring layer of the rewiring layer 60, in this example, the wiring 61d of the second layer. A protective film (solder resist) 62f is formed. For example, as shown in FIG. 11E, surface treatment of nickel 61e and gold 61f may be performed on the region of the wiring 61d exposed from the protective film 62f. For example, bumps (not shown) such as solder balls are mounted on the region of the wiring 61d functioning as the external connection terminal (the surface after the surface treatment of the nickel 61e and the gold 61f).

  As shown in FIG. 10B, when the rewiring layer 60 is formed on the front surface 50a side of the pseudo wafer 50, the end surface of the columnar conductor 80 exposed on the back surface 50b side of the pseudo wafer 50 serves as an external connection terminal. Can be used.

  In the pseudo wafer 50, the rewiring layer 60 can be formed on the front surface 50a side as described above. Further, as shown in FIG. 10C, the rewiring layer 60 is similarly formed on the back surface 50b side. can do.

  In this case, similar to FIG. 11A, the photosensitive resin is applied, exposed, developed, and cured on the back surface 50b side of the pseudo wafer 50 to form an opening leading to the columnar conductor 80. Then, similarly to FIG. 11B described above, formation of a seed layer, formation of a resist pattern, electroplating of copper, peeling of the resist pattern, and etching of the seed layer are performed to form vias and wirings. As a result, a first wiring layer is formed on the back surface 50b side of the pseudo wafer 50. Even when the second and subsequent wiring layers are formed on the back surface 50b side of the pseudo wafer 50, the steps shown in FIGS. 11A and 11B (or FIGS. 11C and 11 described above) are used. What is necessary is just to repeat the process similar to the process shown to (D).

  The conductive pattern 70, the conductive material 90, and the columnar conductor 80 function as through vias that electrically connect the conductive portions 61 of the rewiring layer 60 formed on the front surface 50a side and the back surface 50b side of the pseudo wafer 50 in this way. To do.

  When the rewiring layer 60 is formed on both the front surface 50a side and the back surface 50b side of the pseudo wafer 50, for example, each wiring layer (via and wiring) can be formed by the following procedure. That is, after the first wiring layer is formed on the front surface 50a side, the first wiring layer is formed on the back surface 50b side, and then the second wiring layer is formed on the front surface 50a side. Wiring layers are alternately formed on the front surface 50a side and the back surface 50b side. When such a procedure is used, it is possible to suppress warping of the pseudo wafer 50 when the rewiring layer 60 is formed.

  After the rewiring layer 60 is formed on the front surface 50a side or both the front surface 50a side and the back surface 50b side of the pseudo wafer 50, the pseudo wafer 50 and the rewiring layer 60 are cut (diced) at predetermined positions. Divide into electronic component devices.

  12 and 13 are schematic cross-sectional views of the relevant part in the dicing process according to the first embodiment. 12A is a view showing a structure in which a rewiring layer is formed on the surface side of a pseudo wafer, and FIG. 12B is a view showing an electronic component device after dicing. FIG. 13A is a view showing a structure in which a rewiring layer is formed on both the front side and the back side of the pseudo wafer, and FIG. 13B is a view showing an electronic component device after dicing.

  As shown in FIG. 12A, a structure in which the rewiring layer 60 is formed on the front surface 50a side of the pseudo wafer 50 and the rewiring layer 60 is not formed on the back surface 50b side is as shown in FIG. A plurality (two here as an example) of the structure portions 1a are included. In the example of FIG. 12A, dicing is performed at positions around each structure portion 1a (positions indicated by chain lines in FIG. 12A), and individual electronic component devices as shown in FIG. It is divided into 1 pieces.

  In the structure in which the rewiring layer 60 is formed on both the front surface 50a side and the back surface 50b side of the pseudo wafer 50, as shown in FIG. 13A, a plurality of structure portions 1b as shown in FIG. Here, two are included as an example. In the example of FIG. 13A, dicing is performed at a position around each structure portion 1b (position indicated by a chain line in FIG. 13A), and individual electronic component devices as shown in FIG. It is divided into 1 pieces.

  As described above, in the method of manufacturing the electronic component device 1 according to the first embodiment, the conductive film 70a provided with the opening 71 for arranging the electronic component 30 is formed on the adhesive layer 20, and the A columnar conductor 80 is bonded to the conductive film 70a with a conductive material 90. By increasing the adhesion area between the conductive layer 70a to which the columnar conductor 80 is bonded and the adhesive layer 20, it is possible to effectively suppress the peeling of the conductive layer 70a during molding and the collapse of the columnar conductor 80. become. As a result, the columnar conductor 80 that can be used as a through via and the conductive pattern 70 bonded to the conductive material 90 can be stably provided in the pseudo wafer 50, and the electronic component device 1 having the through via can be provided. It becomes possible to manufacture stably.

  The columnar conductor 80 described above can be a prismatic one in addition to a cylindrical one. Further, the columnar conductor 80 may be a plate-like one in addition to a pin-like one.

  In the above description, each electronic component device 1 has been described as an example in which one electronic component 30 such as a semiconductor chip is included. However, each electronic component device includes a plurality of electronic components 30. Also good. In addition to the electronic component 30 such as a semiconductor chip, each electronic component device may include a passive component such as a chip component such as a chip capacitor.

Hereinafter, an example of a manufacturing method of an electronic component device including a plurality of various components such as electronic components such as semiconductor chips and passive components such as chip capacitors will be described as a second embodiment.
14 and 15 are explanatory views of a method for manufacturing the electronic component device according to the second embodiment. Hereinafter, an example of a method for manufacturing the electronic component device according to the second embodiment will be described with reference to FIGS.

  FIG. 14A is a schematic cross-sectional view of the main part of the component and columnar conductor arranging step according to the second embodiment, and FIG. 14B is the essential part of the resin composition layer forming step according to the second embodiment. 14C is a schematic cross-sectional view of a main part of a pseudo wafer separation process according to the second embodiment, and FIG. 14D is a schematic diagram of a resist pattern forming process according to the second embodiment. FIG. 14E is a schematic cross-sectional view of an essential part of a conductive pattern forming step according to the second embodiment. FIG. 15A is a schematic cross-sectional view of the main part of the back grinding process according to the second embodiment, and FIG. 15B is a schematic cross-sectional view of the main part of the first rewiring layer forming process according to the second embodiment. FIG. 15C is a schematic cross-sectional view of the relevant part in the second rewiring layer forming step according to the second embodiment.

  First, as shown in FIG. 14A, a conductive film 70 a having an opening 71 is provided on the adhesive layer 20 provided on the support 10. The opening 71 is provided in a region including a region where the electronic component 30 such as a semiconductor chip is disposed and a region where the passive component 140 such as a chip capacitor is disposed. The conductive film 70a having such an opening 71 can be provided by forming a predetermined foil, plate, or film on the adhesive layer 20 and then forming the opening 71 in a predetermined region by etching. . Or the electrically conductive film 70a can be provided by sticking the foil etc. which provided the opening part 71 previously on the adhesion layer 20. FIG.

After providing the conductive film 70a on the adhesive layer 20 as described above, the electronic component 30 and the passive component 140 are provided on the adhesive layer 20 exposed in the opening 71 of the conductive film 70a.
A columnar conductor 80 is bonded onto the conductive film 70 a using a conductive material 90. The columnar conductor 80 is provided, for example, in a predetermined position on the conductive film 70 a around the electronic component 30 and the passive component 140 provided on the adhesive layer 20 of the opening 71. The position where the columnar conductor 80 is provided can be set with reference to the position of the opening 71 of the conductive film 70a. The columnar conductor 80 can be provided using, for example, the method shown in FIG. 7 or FIG.

  Next, as shown in FIG. 14B, the resin composition layer covering the conductive film 70a, the electronic component 30, the passive component 140 on the adhesive layer 20, and the conductive material 90 and the columnar conductor 80 on the conductive film 70a. 40 is formed, and a pseudo wafer 50 is formed on the adhesive layer 20. The resin composition layer 40 is formed by molding using a predetermined resin composition.

  Here, since the conductive film 70a to which the columnar conductor 80 is bonded with the conductive material 90 is bonded to the adhesive layer 20 with a relatively large area, even if the columnar conductor 80 is pressed with a resin composition during molding, The peeling of the conductive film 70a from the adhesive layer 20 and the collapse of the columnar conductor 80 due to this are suppressed. Thereby, the situation where the fallen columnar conductor 80 is contained in the pseudo wafer 50 or the structure corresponding to one electronic component device in the pseudo wafer 50 is effectively suppressed.

After the pseudo wafer 50 is formed, the pseudo wafer 50 is peeled from the adhesive layer 20 as shown in FIG.
Then, as illustrated in FIG. 14D, a resist pattern 130 is formed on the surface 50 a of the pseudo wafer 50 that has been peeled off from the adhesive layer 20. The resist pattern 130 is formed in a region including a portion corresponding to the columnar conductor 80 in the pseudo wafer 50 on the conductive film 70a. The resist pattern 130 is also formed on the electronic component 30 and the passive component 140 that are exposed together with the conductive film 70a.

  After the resist pattern 130 is formed, the conductive film 70a is etched using the resist pattern 130 as a mask, and the conductive pattern 70 is formed in a region including a portion corresponding to the columnar conductor 80 as shown in FIG. To do. After the formation of the conductive pattern 70, the resist pattern 130 is removed.

  After the formation of the conductive pattern 70, the back surface 50b of the pseudo wafer 50 is ground to expose the columnar conductor 80, as shown in FIG. In that case, if the grinding scraps of the columnar conductor 80 adhere to the electronic component 30 and the passive component 140, the end surfaces of the columnar conductor 80 may be more than the electronic component 30 and the passive component 140. It is preferable to keep it high. By exposing the end face of the columnar conductor 80 to the back surface 50 b of the pseudo wafer 50, the conductive pattern 70, the conductive material 90, and the columnar conductor 80 can be used as a through via penetrating the pseudo wafer 50.

The grinding for exposing the columnar conductor 80 shown in FIG. 15A can also be performed after the formation of the rewiring layer 60 shown in FIG. 15B.
A rewiring layer 60 is formed on the surface 50a side of the pseudo wafer 50 as shown in FIG. The redistribution layer 60 is provided around the conductive portion 61, such as vias and wirings electrically connected to the electrode 31 of the electronic component 30, the electrode 141 of the passive component 140 and the conductive pattern 70, and the conductive portion 61. Insulating part 62 is included. The conductive portion 61 of the redistribution layer 60 is drawn to the back surface 50 b of the pseudo wafer 50 by the conductive pattern 70, the conductive material 90, and the columnar conductor 80. The end face of the columnar conductor 80 exposed on the back surface 50b side of the pseudo wafer 50 can be used as an external connection terminal.

  As shown in FIG. 15C, the pseudo wafer 50 also includes a conductive portion 61 that is electrically connected to the columnar conductor 80 exposed on the back surface 50b side on the back surface 50b side of the pseudo wafer 50 as well. The wiring layer 60 can be formed. The conductive pattern 70, the conductive material 90, and the columnar conductor 80 function as a through via that electrically connects the conductive portions 61 of the rewiring layer 60 formed on the front surface 50 a side and the back surface 50 b side of the pseudo wafer 50.

  The rewiring layer 60 on the pseudo wafer 50 can be formed using, for example, the method shown in FIG. In this case, when the wiring layers included in the rewiring layer 60 on the front surface 50a side and the back surface 50b side are alternately formed on the front surface 50a side and the back surface 50b side, the rewiring layer 60 is formed. Warpage of the pseudo wafer 50 can be suppressed.

  After the rewiring layer 60 is formed on the front surface 50a side or both the front surface 50a side and the back surface 50b side of the pseudo wafer 50, the pseudo wafer 50 and the rewiring layer 60 are set in accordance with the example of FIGS. And cut into individual electronic component devices.

  As described above, even when an electronic component device including the electronic component 30 and the passive component 140 is manufactured, the conductive film 70 a provided with the opening 71 for arranging the electronic component 30 and the passive component 140 is formed on the adhesive layer 20. Then, the columnar conductors 80 are joined with the conductive material 90 thereon. As a result, peeling of the conductive film 70a at the time of molding and the resulting collapse of the columnar conductor 80 can be effectively suppressed, and through vias can be stably provided in the pseudo-wafer 50. The component device can be stably manufactured.

  Here, the case where one opening portion is provided in the conductive film 70a and the electronic component 30 and the passive component 140 are both disposed therein is illustrated. However, the conductive film 70a includes an opening portion in which the electronic component 30 is disposed. In addition, an opening for disposing the passive component 140 may be provided.

  In addition, a plurality of electronic components 30 are provided in a structure portion corresponding to each electronic component device in the pseudo wafer 50 and in each electronic component device obtained by dividing the pseudo wafer 50 and the redistribution layer 60 thereon. It may be included, and a plurality of passive components 140 may be included. Even in such a case, by using the same method as described above, it is possible to stably manufacture an electronic component device provided with through vias.

  The electronic component device obtained as described above can be mounted on another electronic component device or a circuit board. Further, another electronic component device can be stacked and mounted on the electronic component device obtained as described above.

Here, structural examples of devices (electronic devices) in which electronic component devices are stacked are shown in FIGS.
FIG. 16 is a diagram illustrating a first configuration example of the electronic device. FIG. 16 schematically shows a cross-section of the main part of the electronic device of the first configuration example.

An electronic device 200A shown in FIG. 16 includes a lower electronic component device 210 and an upper electronic component device 220 stacked and mounted thereon.
The lower electronic component device 210 is formed by using the method described in the first and second embodiments. The electronic component device 210 includes a plurality of electronic components 30 such as semiconductor chips (two shown here as examples) and a plurality of passive components 140 such as chip capacitors (here three as examples) in the resin composition layer 40. And a through via 150 penetrating through the resin composition layer 40. The through via 150 includes the columnar conductor 80 as described above. A rewiring layer 60 having a conductive portion electrically connected to the electronic component 30, the passive component 140, and the through via 150 is formed on one surface of the resin composition layer 40. In FIG. 16, the through via 150 and the rewiring layer 60 of the electronic component device 210 are simplified for convenience.

  Bumps 151 such as solder balls are mounted on the terminals provided in the rewiring layer 60 of the lower electronic component device 210. The through via 150 exposed from the resin composition layer 40 on the side opposite to the rewiring layer 60 becomes a terminal 152 that is electrically connected to the upper electronic component device 220.

  The upper electronic component device 220 includes a substrate (package substrate) 221 and a semiconductor chip 223 mounted thereon and connected by wires 222. The wire 222 and the semiconductor chip 223 on the package substrate 221 are covered with a resin composition layer 224. For example, the upper electronic component device 220 is a memory package using a semiconductor memory as the semiconductor chip 223.

  Bumps 225 such as solder balls are mounted on the terminals provided on the package substrate 221 of the upper electronic component device 220. The bumps 225 of the upper electronic component device 220 are joined to the terminals 152 (through vias 150) of the lower electronic component device 210, whereby the lower electronic component device 210 and the upper electronic component device 220 are electrically connected. Connected.

FIG. 17 is a diagram illustrating a second configuration example of the electronic apparatus. FIG. 17 schematically shows a cross-section of the main part of the electronic device of the second configuration example.
An electronic device 200B illustrated in FIG. 17 includes electronic component devices 210 of the same type on the lower side and the upper side. The lower and upper electronic component devices 210 have the same structure as that shown in FIG. The lower and upper electronic component devices 210 are both formed using the methods described in the first and second embodiments.

  A predetermined number of bumps 151 are mounted on the terminals provided on the rewiring layer 60 of the lower electronic component device 210 and on the terminals provided on the rewiring layer 60 of the upper electronic component device 210. The bump 151 of the upper electronic component device 210 is joined to the terminal 152 (through via 150) of the lower electronic component device 210, whereby the lower electronic component device 210 and the upper electronic component device 210 are electrically connected. Connected.

FIG. 18 is a diagram illustrating a third configuration example of the electronic apparatus. FIG. 18 schematically shows a cross section of the main part of the electronic device of the third configuration example.
An electronic device 200C shown in FIG. 18 includes a lower electronic component device 210a and an upper electronic component device 220 stacked and mounted thereon. The lower electronic component device 210a has a rewiring layer having a conductive portion electrically connected to the terminal 152 (through via 150) on the side of the resin composition layer 40 on which the upper electronic component device 220 is laminated. 16 is different from the electronic component device 210 shown in FIG. 16 in that 60 is provided. The lower electronic component device 210a is formed by using the method described in the first and second embodiments.

  The bumps 225 of the upper electronic component device 220 are joined to terminals provided in the rewiring layer 60 of the lower electronic component device 210a, whereby the lower electronic component device 210a and the upper electronic component device 220 are connected. Electrically connected.

FIG. 19 is a diagram illustrating a fourth configuration example of the electronic device. FIG. 19 schematically illustrates a cross-section of the main part of the electronic device of the fourth configuration example.
An electronic device 200D shown in FIG. 19 includes a lower electronic component device 210a and an upper electronic component device 210 stacked and mounted thereon. The lower electronic component device 210a has the same structure as that shown in FIG. The upper electronic component device 210 has the same structure as that shown in FIG. The lower electronic component device 210a and the upper electronic component device 210 are both formed using the methods described in the first and second embodiments.

  The bumps 151 of the upper electronic component device 210 are bonded to terminals provided on the rewiring layer 60 of the lower electronic component device 210a, whereby the lower electronic component device 210a and the upper electronic component device 210 are connected. Electrically connected.

  Note that other electronic component devices can be stacked and mounted on the upper electronic component devices 220 and 210 of the electronic devices 200A, 200B, 200C, and 200D shown in FIGS. .

  Also, any of the electronic devices 200A, 200B, 200C, and 200D shown in FIGS. 16 to 19 can be mounted on the circuit board using the bumps 151 of the lower electronic component devices 210 and 210a.

FIG. 20 is a diagram illustrating another example of the electronic apparatus.
FIG. 20 schematically illustrates a cross-section of the main part of the electronic device when the electronic device 200A of the first configuration example is mounted on the circuit board 230 using the bumps 151 of the lower electronic component device 210. Yes. Although the case where the electronic device 200A is mounted on the circuit board 230 is illustrated here, other electronic devices 200B, 200C, and 200D can be similarly mounted on the circuit board 230.

  By using the method described in the first and second embodiments, a through via can be stably provided in the electronic component device, and a plurality of electronic component devices are stacked using the through via. An electronic device with high packaging density can be realized.

Examples of the electronic component device and the electronic device will be described below.
[Example 1]
A stainless steel substrate having a length of 170 mm × width of 170 mm × thickness of 0.3 mm was used as a support, a heat-foaming adhesive layer was stuck on the stainless steel substrate, and a copper foil with a thickness of 3 μm was stuck on the adhesive layer. . A dry film resist is formed on the copper foil, an opening pattern of 6 mm in length and 6 mm in width is formed in the dry film resist in 10 rows by 10 columns at a pitch of 12 mm, and this is used as a mask to etch the copper foil. An opening 6 mm long × 6 mm wide was formed.

  Using a flip chip bonder, a bare chip (semiconductor chip) having a length of 5 mm, a width of 5 mm, and a thickness of 0.4 mm is adhered to the adhesive layer exposed from the opening of the copper foil thus formed. It arrange | positioned so that the surface of a layer might be touched. In addition, a copper pin having a diameter of 0.2 mm and a length of 0.5 mm is prepared, and solder (low melting point metal) containing copper, tin, and bismuth is provided at the tip of one side thereof, and this is provided with a through hole in a stainless steel plate. Using the metal mold formed with, was bonded to a predetermined position on the copper foil around the bare chip.

  Thereafter, a resin composition layer was formed using a mold for molding, the resin composition layer was cured, and a pseudo wafer having a thickness of 0.6 mm and a diameter of 150 mm was formed on the adhesive layer. At the time of molding, the adhesive area between the adhesive layer and the copper foil thereon was relatively large, and the copper pin joined to such a copper foil did not fall even when pressed by the resin composition layer.

  After molding, heating was performed at 180 ° C. to reduce the adhesive strength of the heat-foaming adhesive layer, and the pseudo wafer was peeled from the adhesive layer. Thereafter, heat treatment was performed at 200 ° C. for 1 hour to completely cure the pseudo wafer. A resist pattern having a diameter of 0.3 mm is formed on the copper foil of the pseudo wafer in a region corresponding to the portion where the copper pin is erected at the corner of the opening of the copper foil, and this is used as a mask. The copper foil was etched to form an electrode pad in a region corresponding to the portion where the copper pin was raised. In this etching, a resist pattern was also formed on the electrode surface of the bare chip provided in the opening of the copper foil so that the electrode surface was protected from etching.

  Next, a photosensitive epoxy varnish was applied by spin coating on the surface side of the pseudo wafer where the bare chip electrode surface was exposed, prebaked, exposed, developed and cured, and further subjected to oxygen plasma treatment. Thus, an insulating layer having a film thickness of 8 μm and an opening having a diameter of 30 μm leading to the bare chip electrode was formed. Next, titanium and copper were formed to a thickness of 0.1 μm and 0.3 μm, respectively, by sputtering, and a seed layer was formed. Thereafter, a resist pattern having openings in areas for forming vias and wirings was formed, and copper was electroplated using the previously formed seed layer to form vias and wirings. After electroplating, the resist pattern was peeled off, and the portion of the seed layer covered with the resist pattern was removed by wet etching and dry etching. Thereafter, the wiring was partially exposed to form a solder resist, and the exposed wiring surface was subjected to nickel and gold surface treatment.

Thereafter, the resin composition layer was ground by a thickness of 0.11 mm from the back surface side of the pseudo wafer provided with the wiring layer in this manner to expose the end face of the copper pin. Then, the wiring layer was provided on the pseudo wafer in this way, and the substrate from which the copper pins were exposed was cut at a predetermined position to obtain an individualized electronic component device (package).
[Example 2]
A glass substrate having a length of 170 mm × width of 170 mm × thickness of 0.3 mm was used as a support, and an ultraviolet foam adhesive layer was stuck on the glass substrate. On the adhesive layer, a copper foil having a thickness of 7 [mu] m and having 10 mm * 10 columns of openings of 6 mm in length and 6 mm in width formed in advance by etching using a dry film resist was pasted.

  On the adhesive layer exposed from the opening of the copper foil, using a mounter, a 4 mm long × 4 mm wide × 0.5 mm thick bare chip (semiconductor chip) and 0603 type (vertical 0.6 mm × width 0. 3 mm × thickness 0.3 mm) chip capacitors were arranged so that their electrode surfaces were in contact with the surface of the adhesive layer. In addition, a copper pin having a diameter of 0.15 mm and a length of 0.6 mm was prepared, and a low melting point metal containing copper, tin, silver and bismuth was provided at the tip of one side, and this was provided with a through hole in a stainless steel plate. Using the formed mold, bonding was performed at a predetermined position on the copper foil around the bare chip and the chip capacitor.

  Thereafter, a resin composition layer was formed using a mold for molding, the resin composition layer was cured, and a pseudo wafer having a thickness of 0.7 mm and a diameter of 150 mm was formed on the adhesive layer. At the time of molding, the adhesive area between the adhesive layer and the copper foil thereon was relatively large, and the copper pin joined to such a copper foil did not fall even when pressed by the resin composition layer.

  After molding, ultraviolet rays were irradiated from the glass substrate side to reduce the adhesive strength of the ultraviolet foam adhesive layer, and the pseudo wafer was peeled from the adhesive layer. Thereafter, heat treatment was performed at 200 ° C. for 1 hour to completely cure the pseudo wafer. A resist pattern having a diameter of 0.3 mm is formed on the copper foil of the pseudo wafer in a region corresponding to the portion where the copper pin is erected at the corner of the opening of the copper foil, and this is used as a mask. The copper foil was etched to form an electrode pad in a region corresponding to the portion where the copper pin was raised. In this etching, a resist pattern was formed on the electrode surfaces of the bare chip and the chip capacitor provided in the opening of the copper foil to protect the electrode surface from etching.

  Next, the resin composition layer was ground to a thickness of 0.11 mm from the back surface side of the pseudo wafer opposite to the surface side where the bare chip and chip capacitor electrode surfaces were exposed, and the end surfaces of the copper pins were exposed. Thereafter, a photosensitive epoxy varnish was applied to the surface side of the pseudo wafer by spin coating, prebaked, exposed, developed, and cured, and further subjected to oxygen plasma treatment. As a result, an insulating layer having a film thickness of 8 μm and an opening having a diameter of 50 μm communicating with the bare chip and the electrode of the chip capacitor was formed. Next, titanium and copper were formed to a thickness of 0.1 μm and 0.3 μm, respectively, by sputtering, and a seed layer was formed. Thereafter, a resist pattern having openings in areas for forming vias and wirings was formed, and copper was electroplated using the previously formed seed layer to form vias and wirings. After electroplating, the resist pattern was peeled off, and the portion of the seed layer covered with the resist pattern was removed by wet etching and dry etching. Similarly, vias and wirings connected to the copper pins were formed on the back side of the pseudo wafer. Thereafter, a solder resist was formed by partially exposing the wiring on the front and back surfaces, and surface treatment of nickel and gold was performed on the exposed wiring surface.

The substrate on which the wiring layer was thus provided on the pseudo wafer was cut at a predetermined position to obtain an individualized electronic component device (package). Further, an FBGA (Fine pitch Ball Grid Array) package was laminated on the package using solder bumps to obtain a stacked package type electronic device.
Example 3
A glass substrate having a length of 170 mm × width of 170 mm × thickness of 0.3 mm was used as a support, and an ultraviolet foam-type adhesive layer was stuck on the glass substrate, and a thickness of 0.2 μm was formed on the adhesive layer by vacuum deposition. A nickel film was formed. A dry film resist is formed on the nickel film, and an opening pattern of 7 mm length × 7 mm width is formed on the dry film resist in 10 rows × 10 columns at a pitch of 12 mm, and the nickel film is etched using this as a mask to form a copper foil. An opening of length 7 mm × width 7 mm was formed.

  On the adhesive layer exposed from the opening of the nickel film, using a mounter, a bare chip (semiconductor chip) having a length of 5 mm × width 5 mm × thickness 0.5 mm and a type 1005 (length 1.0 mm × width 0. 5 mm × thickness 0.5 mm) chip capacitors were arranged so that their electrode surfaces were in contact with the surface of the adhesive layer. In addition, a copper pin having a diameter of 0.2 mm and a length of 0.6 mm was prepared, a silver paste was provided at the tip of one side, and this was used as a bare chip and a chip using a mold in which a through hole was formed in a stainless steel plate. Bonded to a predetermined position on the nickel film around the capacitor.

  Thereafter, a resin composition layer was formed using a mold for molding, the resin composition layer was cured, and a pseudo wafer having a thickness of 0.6 mm and a diameter of 150 mm was formed on the adhesive layer. At the time of molding, the adhesion area between the pressure-sensitive adhesive layer and the nickel film thereon was relatively large, and the copper pin joined to such a nickel film did not fall even when pressed by the resin composition layer.

  After molding, ultraviolet rays were irradiated from the glass substrate side to reduce the adhesive strength of the ultraviolet foam adhesive layer, and the pseudo wafer was peeled from the adhesive layer. Thereafter, heat treatment was performed at 200 ° C. for 1 hour to completely cure the pseudo wafer. A resist pattern having a diameter of 0.3 mm is formed by aligning the nickel film of the pseudo wafer with the corner of the opening of the nickel film in a region corresponding to the portion where the copper pin is erected, and using this as a mask The nickel film was etched to form an electrode pad in a region corresponding to the portion where the copper pin was raised. At the time of this etching, a resist pattern was also formed on the bare chip and chip capacitor electrode surfaces provided in the opening of the nickel film to protect the electrode surfaces from etching.

  Next, the resin composition layer was ground by a thickness of 0.15 mm from the back surface side of the pseudo wafer opposite to the surface side from which the bare chip and chip capacitor electrode surfaces were exposed to expose the end surfaces of the copper pins. Thereafter, a photosensitive epoxy varnish was applied to the surface side of the pseudo wafer by spin coating, prebaked, exposed, developed, and cured, and further subjected to oxygen plasma treatment. As a result, an insulating layer having a film thickness of 8 μm and an opening having a diameter of 50 μm communicating with the bare chip and the electrode of the chip capacitor was formed. Next, titanium and copper were formed to a thickness of 0.1 μm and 0.3 μm, respectively, by sputtering, and a seed layer was formed. Thereafter, a resist pattern having openings in areas for forming vias and wirings was formed, and copper was electroplated using the previously formed seed layer to form vias and wirings. After electroplating, the resist pattern was peeled off, and the portion of the seed layer covered with the resist pattern was removed by wet etching and dry etching. Similarly, vias and wirings connected to the copper pins were formed on the back side of the pseudo wafer. Thereafter, a solder resist was formed by partially exposing the wiring on the front and back surfaces, and surface treatment of nickel and gold was performed on the exposed wiring surface.

  The substrate on which the wiring layer was thus provided on the pseudo wafer was cut at a predetermined position to obtain an individualized electronic component device (package). Furthermore, the packages thus obtained were laminated and bonded using solder bumps to obtain a laminated package type electronic device.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Additional remark 1) The process of providing an adhesion layer on a support body,
Providing a conductive film having an opening on the adhesive layer;
Providing an electronic component on the adhesive layer of the opening;
Erecting columnar conductors on the conductive film;
On the adhesive layer, forming a substrate in which the conductive film, the electronic component, and the columnar conductor are covered with a resin composition;
Separating the substrate from the adhesive layer;
Partially removing the conductive film of the substrate separated from the adhesive layer and forming a conductive pattern including a portion corresponding to the columnar conductor;
Forming a first wiring layer having a first conductive portion electrically connected to the electronic component and the conductive pattern on a first surface of the substrate on which the conductive pattern is formed. A method for manufacturing an electronic component device.

(Additional remark 2) The process of standing the said columnar conductor includes the process of fixing the said columnar conductor using the electrically-conductive material on the said electrically conductive film, The manufacturing method of the electronic component apparatus of Additional remark 1 characterized by the above-mentioned.
(Supplementary Note 3) The step of fixing the columnar conductor using the conductive material on the conductive film,
Disposing the columnar conductor on the conductive film via the fluid conductive material;
The method for manufacturing an electronic component device according to claim 2, further comprising a step of solidifying the conductive material and fixing the columnar conductor on the conductive film.

  (Supplementary note 4) The electronic component according to Supplementary note 2 or 3, wherein the conductive material is a material that melts and has a melting point that changes to a higher temperature side than before melting by melting and solidifying. Device manufacturing method.

  (Supplementary Note 5) The method further includes a step of grinding the second surface of the substrate opposite to the first surface before the step of forming the first wiring layer or after the step of forming the first wiring layer. The method for manufacturing an electronic component device according to any one of appendices 1 to 4, wherein:

  (Supplementary Note 6) After the step of forming the first wiring layer, the resin composition layer and the first wiring around the region including the electronic component, the columnar conductor, the conductive pattern, and the first conductive portion. The method for manufacturing an electronic component device according to any one of appendices 1 to 5, further comprising a step of cutting the layer.

  (Supplementary Note 7) After the step of forming the first wiring layer, a second conductive portion electrically connected to the columnar conductor is provided on the second surface opposite to the first surface of the substrate. The method for manufacturing an electronic component device according to any one of appendices 1 to 5, further comprising a step of forming a wiring layer.

  (Supplementary Note 8) After the step of forming the second wiring layer, the resin composition is formed around a region including the electronic component, the columnar conductor, the conductive pattern, the first conductive portion, and the second conductive portion. The method of manufacturing an electronic component device according to appendix 7, further comprising a step of cutting the layer, the first wiring layer, and the second wiring layer.

(Appendix 9) a resin composition layer;
An electronic component provided in the resin composition layer and having an electrode exposed on the first surface of the resin composition layer;
A columnar conductor provided in the resin composition layer;
A conductive pattern provided on the columnar conductor and exposing an upper surface and side surfaces from the first surface;
An electronic component device comprising: a first wiring layer provided on the first surface and having a first conductive portion electrically connected to the electrode and the conductive pattern.

  (Additional remark 10) It is provided on the 2nd surface on the opposite side to the said 1st surface of the said resin composition layer, and further contains the 2nd wiring layer which has the 2nd electroconductive part electrically connected to the said columnar conductor. Item 9. The electronic component device according to appendix 9, wherein

(Appendix 11) a first electronic component device;
A second electronic component device mounted on the first electronic component device,
The first electronic component device is
A resin composition layer;
An electronic component provided in the resin composition layer and having an electrode exposed on the first surface of the resin composition layer;
A columnar conductor provided in the resin composition layer;
A conductive pattern provided on the columnar conductor and exposing an upper surface and side surfaces from the first surface;
A first wiring layer provided on the first surface and having a first conductive portion electrically connected to the electrode and the conductive pattern;
The second electronic component device is mounted on the second surface side opposite to the first surface of the resin composition layer, and is electrically connected to the first electronic component device using the columnar conductor. An electronic device characterized by the above.

(Additional remark 12) The end surface of the said columnar conductor is exposed to the said 2nd surface,
The electronic device according to appendix 11, wherein the second electronic component device is electrically connected to the end surface exposed on the second surface.

(Supplementary Note 13) The first electronic component device further includes a second wiring layer provided on the second surface and having a second conductive portion electrically connected to the columnar conductor,
The electronic device according to appendix 11, wherein the second electronic component device is electrically connected to the second wiring layer.

  (Additional remark 14) Any one of additional remarks 11 thru | or 13 further including the circuit board arrange | positioned at the said 1st wiring layer side of the said 1st electronic component apparatus and electrically connected to the said 1st wiring layer. An electronic device according to 1.

1, 1A, 210, 210a, 220 Electronic component device 1a, 1b Structure 10 Support body 20 Adhesive layer 30 Electronic component 30a Electrode surface 30b Rear surface 31, 141 Electrode 40, 224 Resin composition layer 50, 50A Pseudo wafer 50a Surface 50b Back surface 60, 60A Rewiring layer 61 Conductive part 61a, 61c Via 61b, 61d Wiring 61e Nickel 61f Gold 62 Insulating part 62a, 62d Photosensitive resin 62b, 62c, 62e, 71 Opening 62f Protective film 63, 152 Terminal 70, 70A Conductive pattern 70a Conductive film 80 Columnar conductor 81 Shaft part 82 Head 90 Conductive material 110, 120 Mold 110a, 120a Metal plate 110b, 120b Through hole 130 Resist pattern 140 Passive component 150 Through via 151, 225 Bump 200A, 200B, 20 C, 200D electronic device 221 package substrate 222 wire 223 semiconductor chip 230 circuit board

Claims (8)

  1. Providing an adhesive layer on the support;
    Providing a conductive film having an opening on the adhesive layer;
    Providing an electronic component on the adhesive layer of the opening;
    Erecting columnar conductors on the conductive film;
    On the adhesive layer, forming a substrate in which the conductive film, the electronic component, and the columnar conductor are covered with a resin composition;
    Separating the substrate from the adhesive layer;
    Partially removing the conductive film of the substrate separated from the adhesive layer and forming a conductive pattern including a portion corresponding to the columnar conductor;
    Forming a first wiring layer having a first conductive portion electrically connected to the electronic component and the conductive pattern on a first surface of the substrate on which the conductive pattern is formed. A method for manufacturing an electronic component device.
  2.   The method of manufacturing an electronic component device according to claim 1, wherein the step of raising the columnar conductor includes a step of fixing the columnar conductor using a conductive material on the conductive film.
  3.   The method further includes a step of grinding a second surface opposite to the first surface of the substrate before the step of forming the first wiring layer or after the step of forming the first wiring layer. The manufacturing method of the electronic component apparatus of Claim 1 or 2.
  4.   After the step of forming the first wiring layer, the resin composition layer and the first wiring layer are cut around a region including the electronic component, the columnar conductor, the conductive pattern, and the first conductive portion. The method for manufacturing an electronic component device according to claim 1, further comprising a step.
  5.   After the step of forming the first wiring layer, a second wiring layer having a second conductive portion electrically connected to the columnar conductor is formed on the second surface of the substrate opposite to the first surface. The method for manufacturing an electronic component device according to claim 1, further comprising a step of:
  6.   After the step of forming the second wiring layer, around the region including the electronic component, the columnar conductor, the conductive pattern, the first conductive portion, and the second conductive portion, the layer of the resin composition, the first 6. The method of manufacturing an electronic component device according to claim 5, further comprising a step of cutting one wiring layer and the second wiring layer.
  7. A resin composition layer;
    An electronic component provided in the resin composition layer and having an electrode exposed on the first surface of the resin composition layer;
    A columnar conductor provided in the resin composition layer;
    A conductive pattern provided on the columnar conductor and exposing an upper surface and side surfaces from the first surface;
    An electronic component device comprising: a first wiring layer provided on the first surface and having a first conductive portion electrically connected to the electrode and the conductive pattern.
  8. A first electronic component device;
    A second electronic component device mounted on the first electronic component device,
    The first electronic component device is
    A resin composition layer;
    An electronic component provided in the resin composition layer and having an electrode exposed on the first surface of the resin composition layer;
    A columnar conductor provided in the resin composition layer;
    A conductive pattern provided on the columnar conductor and exposing an upper surface and side surfaces from the first surface;
    A first wiring layer provided on the first surface and having a first conductive portion electrically connected to the electrode and the conductive pattern;
    The second electronic component device is mounted on the second surface side opposite to the first surface of the resin composition layer, and is electrically connected to the first electronic component device using the columnar conductor. An electronic device characterized by the above.
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Cited By (6)

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