JP2008047753A - Semiconductor device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with a thin total thickness, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device P1 includes a semiconductor structure 4 having a plurality of externally connecting electrodes 5 on its upper surface, a support 1 for supporting the structure, and insulative layers 12 and 16 provided on sides of the structure. At least one or more re-wiring layers 18 are provided on the externally connecting electrodes and the insulative layers provided on the sides of the semiconductor structure. Conductor layers 2, 11 and 15 are provided on sides of the semiconductor structure, and a through-plated through-hole 20 is provided between the support and the conductor layers. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a wafer level CSP (wafer-level chip size package) is built in an organic substrate and is thinned, and a manufacturing method thereof.

  Recently, electronic devices have become lighter, thinner, and smaller, and a semiconductor device called wafer level CSP (wafer-level chip size package) mounted on the device is used. In this wafer level CSP, generally, a sealing material is provided on the upper surface of a bare semiconductor device in which a plurality of connection pads for external connection are formed, and then an opening is formed in a portion corresponding to each connection pad of the sealing material. Next, a rewiring connected to each connection pad through the opening is formed, and then a columnar external connection electrode is formed on the other connection portion of each rewiring and sealed with an insulating resin. After stopping, it is polished by polishing until the external connection electrode is exposed, and then solder is formed on the exposed external connection electrode (for example, see Patent Document 1).

  However, the wafer level CSP usually has external connection electrodes arranged in a matrix on the top surface of a bare chip semiconductor device, so that the size and pitch of the external connection electrodes are extremely small in a semiconductor device having a large number of external connection electrodes. As a result, there is a problem that it is difficult to connect to the motherboard. That is, if the pitch of the electrodes for external connection is reduced, not only the alignment with the mother board is difficult, but also the bonding strength is insufficient, and a short circuit between the electrodes occurs during bonding. In addition, there is a problem that the external connection electrode is disconnected due to the stress generated due to the difference in linear expansion coefficient between the semiconductor device made of silicon and the mother board.

  Furthermore, although it is possible to reduce the matrix wiring of the semiconductor device made of silicon to a narrow pitch, there has been a problem that the semiconductor device cannot be further reduced due to the high-precision connection with the mother board.

  Therefore, as shown in FIG. 10, a semiconductor device made of silicon is made smaller, a matrix-like narrow pitch wiring is formed, an external connection electrode is formed, and sealed with an insulating resin, and separated into individual pieces. There has been proposed a semiconductor device that enables a wiring pitch that can be accurately mounted on a mother board by embedding the body in an organic substrate and rewiring (see, for example, Patent Document 2).

  Here, an example of the manufacturing process of the conventional semiconductor device as shown in FIG. 10 will be described with reference to FIGS.

  First, as shown in FIG. 11A, a substrate P102 having a conductor layer 102 on both upper and lower surfaces of a support (insulating layer) 101 is prepared.

  Next, as shown in FIG. 11B, after forming an etching resist 103a on both upper and lower surfaces of the substrate P102, a circuit of the conductor layer 102 is formed, and a structure as shown in FIG. 11C is obtained.

  Next, as shown in FIG. 12D, the etching resist 103a is removed to obtain a substrate P103.

  Next, as shown in FIG. 12E, the semiconductor structure 104 is mounted on the substrate P103 via the adhesive layer 108 to obtain a structure P104 as shown in FIG. Here, the semiconductor structure 104 includes a plurality of external connection electrodes 105 on the upper surface of the silicon 107, and a sealing material 106 is formed on a side surface of the external connection electrode 105.

  Next, as shown in FIG. 13G, the structure P104 is laid up with an insulating embedding material 112 that has been punched into the semiconductor structure 104 by using a punching press, and a vacuum lamination press. A laminating press is performed using a machine to obtain a structure P105 as shown in FIG.

  Next, the insulating embedding material 112 that has also flowed onto the semiconductor structure 104 by the laminating press is subjected to surface polishing by a polishing machine to obtain a structure P106 as shown in FIG.

  Next, as shown in FIG. 14 (m), a build-up material 117 and a copper foil 118 are laid up on the front and back, and a lamination press is performed using a vacuum laminating press, and a structure as shown in FIG. 14 (n). A body P107 is obtained.

  Next, through holes and interlayer connection vias are drilled to obtain a structure P108 as shown in FIG.

  Next, as shown in FIG. 15 (r), after forming a plating layer 118a on the structure diagram P108, as shown in FIG. 15 (s), an etching resist 103b is formed on both upper and lower surfaces, and FIG. As shown in t), circuit formation is performed.

  Next, as shown in FIG. 16 (u), the etching resist 103b is peeled off to obtain a structure P110.

  Next, the rewiring layer 119 and the solder resist 103c are formed to obtain a semiconductor structure P111 as shown in FIG.

  However, the semiconductor device P111 is a manufacturing method using a so-called pin lamination in which holes formed on the outer periphery of each base material are placed in a reference pin and laid up and stacked, and the alignment accuracy between the base materials is There was a limit.

  In addition, if multiple layers of insulating layers are stacked on top of the semiconductor structure and rewiring is repeated, the total plate thickness will inevitably increase. Therefore, even if it is applied to mobile products such as mobile phone devices, it is not adopted due to thickness restrictions. There was also a problem.

On the other hand, in order to alleviate the difference in coefficient of linear expansion between the semiconductor device made of silicon and the insulating layer formed on the side, the height of the external connection electrode cannot be reduced to 50 μm or less. It takes a long time to reduce the thickness, and the wafer warp and the microcrack to the wafer are likely to occur, so that it is difficult to thin the wafer level CSP.
JP 2001-168128 A JP 2004-221417 A

  The present invention has been made in view of the above problems and actual circumstances, and an object of the present invention is to provide a semiconductor device having a thin total plate thickness and a manufacturing method thereof.

  The present invention according to claim 1 includes a semiconductor structure having a plurality of external connection electrodes on an upper surface, a support that supports the semiconductor structure, and an insulating layer provided on a side of the semiconductor structure. And a semiconductor device in which at least one rewiring layer is provided on the external connection electrode of the semiconductor structure and the insulating layer provided on the side, wherein The semiconductor device is provided with a conductor layer, and a through-plated through hole is provided between the support and the conductor layer.

  Thereby, since the conductor layer is provided on the side of the semiconductor structure, the inner conductor layer can be increased without increasing the total thickness. Further, since the increased conductor layers are connected by through-plating through holes, each layer on the side of the semiconductor structure is not limited by the processing condition range of the laser processing apparatus, that is, the processing limit as in the case of interlayer via connection. The thickness and the layer configuration can be freely set. Therefore, a semiconductor device having a thin total plate thickness can be obtained.

  The present invention according to claim 2 is characterized in that at least a part of the conductor layer is a metal foil.

  Thereby, the roughening process of a to-be-plated surface required before performing electroless plating becomes unnecessary, and the smoothness loss of the semiconductor structure surface by simultaneous roughening can be avoided although the roughening conditions differ.

  According to a third aspect of the present invention, there is provided a step of disposing a semiconductor structure having a plurality of external connection electrodes on an upper surface of a support, and a first insulating layer and a carrier on a side of the semiconductor structure. A step of disposing and laminating the first conductor layer provided; a step of peeling the carrier after the lamination step; and a second insulating layer and a second conductor layer on the side of the semiconductor structure after the peeling step. Arranging and laminating, a step of providing a through hole between the support, the first conductor layer and the second conductor layer, a step of providing a plating layer after the step of providing the through hole, Forming a rewiring layer on the external connection electrode of the semiconductor structure and on the first insulating layer and / or the second insulating layer disposed on the side. The above-described problems are solved by a device manufacturing method.

  Thereby, the curvature which generate | occur | produces when carrying out surface grinding | polishing of the insulating embedding material which also flowed on the semiconductor structure with the lamination press with a grinder is eased by peeling a carrier. Further, the thickness and layer configuration of each layer on the side of the semiconductor structure can be freely set without being limited by the range of processing conditions of the laser processing apparatus, that is, the processing limit. Therefore, a semiconductor device having a high alignment accuracy between the substrates and a thin total plate thickness can be obtained.

  The present invention according to claim 4 is characterized in that the first conductor layer and the second conductor layer are pre-windowed.

  Thereby, the adhesion defect with the base material laminated | stacked on a semiconductor structure and its immediate upper layer can be avoided.

  The present invention according to claim 5 is characterized in that the second conductor layer is a metal foil.

  Thereby, although the roughening conditions are different, it is possible to electrically connect all the conductors in contact with the through hole while avoiding the smoothness loss of the surface of the semiconductor structure due to the simultaneous roughening.

  According to the present invention, it is possible to provide a semiconductor device having a thin total plate thickness and a manufacturing method thereof.

  An embodiment according to claims 1 to 2 of the present invention will be described with reference to FIG.

  In FIG. 1, P <b> 1 is a semiconductor device, a support 1, a semiconductor structure 4 provided on the upper surface of the support 1 via an adhesive layer 8, and a conductor layer 2 provided on both upper and lower surfaces of the support 1. And an insulating layer 12 and a conductor layer 11 provided on the side of the semiconductor structure 4 and above the support 1, and an insulation provided on the side of the semiconductor structure 4 and above the insulating layer 12. The layer 16 and the conductor layer 15, the through-plating through hole 20 provided between the support 1 and the conductor layer 15, and the external connection electrode 5 of the semiconductor structure 4 are provided above and on the side. A rewiring layer 18 provided via a buildup material 17 and a solder resist 19 are formed above the insulating layer 16. The semiconductor structure 4 is composed of silicon 7, a plurality of external connection electrodes 5 provided on the upper surface of the silicon 7, and a sealing material 6 provided between the external connection electrodes 5. ing.

  In the semiconductor device P1, since the conductor layer 11 and the conductor layer 15 are provided on the side of the semiconductor structure 4, the inner conductor layer can be increased without increasing the total thickness. In addition, since the through-plating through hole 20 is provided between the support 1 and the conductor layer 15, the semiconductor structure is not limited by the processing condition range of the laser processing apparatus, that is, the processing limit, as in the case of interlayer via connection. The thickness and layer structure of each side layer can be freely set. Therefore, a semiconductor device having a thin total plate thickness can be obtained.

  Next, embodiments according to claims 3 to 5 of the present invention will be described with reference to FIGS.

  First, as shown to Fig.2 (a), the board | substrate P2 provided with the conductor layer 2 on the upper and lower surfaces of the support body (insulating layer) 1 is prepared. The substrate P2 may be a multilayer substrate.

  Next, as shown in FIG. 2B, portions where the upper and lower surfaces of the substrate P2 are not etched are covered with an etching resist 3a. The etching resist 3a may be a dry film or ink.

  Next, as shown in FIG. 2C, the conductor layer 2 is formed as a circuit, and then the etching resist 3a is peeled off to obtain a substrate P3 as shown in FIG. 3D.

  Next, as shown in FIG. 3E, the semiconductor structure 4 is mounted on the substrate P3 via the adhesive layer 8 to obtain a structure P4 as shown in FIG. The semiconductor structure 4 includes a plurality of external connection electrodes 5 on the upper surface of the silicon 7 as described above, and a sealing material 6 between the external connection electrodes 5.

  Next, as shown in FIG. 4G, a copper foil 9 with a carrier provided with a carrier 10 on a copper foil 11 and an insulating layer (insulating embedding material) 12 are punched using a punching press or the like, and the semiconductor structure After removing the window that fits into the body 4, the structure P4 is laid up, and a lamination press is performed using a vacuum lamination press or the like to obtain a structure P5 as shown in FIG. 4 (h).

  Next, the carrier 10 is peeled off to obtain a structure P6 as shown in FIG.

  Next, as shown in FIG. 5 (m), the portion where the structure P6 is not etched is covered with an etching resist 3b, and then the exposed portion is etched as shown in FIG. 5 (n). .

  Next, the etching resist 3b is peeled off to obtain a structure P7 as shown in FIG.

  Next, as shown in FIG. 6 (r), the copper foil 15 and the insulating layer (insulating embedding material) 16 are subjected to window opening of a necessary size using a punching press machine or the like, and then the structure P7 is laid out. And performing a lamination press using a vacuum lamination press or the like to obtain a structure P8 as shown in FIG. 6 (s).

  Next, through holes for front and back connection are formed by an NC drill device or a laser to obtain a structure P9 as shown in FIG. 6 (t).

  Next, as shown in FIG. 7 (u), a plating resist 3c is provided so as to cover the portion of the structure P9 that is not plated, and after forming the plating layer 15a as shown in FIG. The resist 3c is peeled off to obtain a structure P10 having through-plated through holes 20 as shown in FIG. 7 (w).

  Next, as shown in FIG. 8 (x), an etching resist 3d is provided so as to cover the portion of the structure P10 that is not etched, and after the circuit is formed as shown in FIG. 8 (y), the etching resist 3d is formed. Is peeled off to obtain a structure P11 as shown in FIG.

  Next, build-up materials 17 are provided on the front and back sides to obtain a structure P12 as shown in FIG.

  Next, through the respective steps of interlayer connection via formation, rewiring layer 18 formation, and solder resist 19 formation as in a normal substrate, a semiconductor device P13 as shown in FIG. 9B is obtained.

  In the description of the present invention, the above-described two embodiments have been described as examples. However, the configuration of the present invention is not limited to these, and is not limited to these examples. Various modifications within the range are possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional explanatory diagram illustrating an example of a semiconductor device of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional process explanatory diagram illustrating an example of a method for manufacturing a semiconductor device of the present invention. FIG. 3 is a schematic cross-sectional process explanatory diagram following FIG. 2. FIG. 4 is a schematic cross-sectional process explanatory diagram following FIG. 3. FIG. 5 is a schematic cross-sectional process explanatory diagram subsequent to FIG. 4. FIG. 6 is a schematic cross-sectional process explanatory diagram following FIG. 5. FIG. 7 is a schematic cross-sectional process explanatory diagram following FIG. 6. FIG. 8 is a schematic cross-sectional process explanatory diagram following FIG. 7. FIG. 9 is a schematic cross-sectional process explanatory diagram following FIG. 8. FIG. 10 is a schematic cross-sectional explanatory view showing an example of a conventional semiconductor device. FIG. 10 is a schematic cross-sectional process explanatory diagram illustrating an example of a conventional method for manufacturing a semiconductor device. FIG. 12 is a schematic cross-sectional process explanatory diagram following FIG. 11. FIG. 13 is a schematic cross-sectional process explanatory diagram following FIG. 12. FIG. 14 is a schematic cross-sectional process explanatory diagram following FIG. 13. FIG. 15 is a schematic cross-sectional process explanatory diagram following FIG. 14. FIG. 16 is a schematic cross-sectional process explanatory diagram following FIG. 15.

Explanation of symbols

1,101: Support (insulating layer)
2, 102: Conductive layers 3a, 3b, 3d, 103a, 103b: Etching resist 3c: Plating resist 4, 104: Semiconductor structure 5, 105: External connection electrode 6, 106: Sealing material 7, 107: Silicon 8 108: Adhesive layer 9: Copper foil with carrier 10: Carrier 11, 15, 118: Copper foil 12, 16, 112: Insulating layer (insulating embedding material)
15a: Plating layer 17, 117: Build-up material 18, 119: Rewiring layer 19, 103c: Solder resist 20: Through-plating through holes P2, P3, P102, P103: Substrates P4 to P12, P104 to P110: Structure P1 , P13, P101, P111: Semiconductor device

Claims (5)

  A semiconductor structure having a plurality of external connection electrodes on an upper surface; a support that supports the semiconductor structure; and an insulating layer provided on a side of the semiconductor structure; and the outside of the semiconductor structure A semiconductor device in which at least one or more redistribution layers are provided on a connection electrode and an insulating layer provided on the side, and a conductor layer is provided on a side of the semiconductor structure, A semiconductor device comprising a through-plated through hole between the support and the conductor layer.   The semiconductor device according to claim 1, wherein at least a part of the conductor layer is a metal foil.   A step of disposing a semiconductor structure having a plurality of external connection electrodes on the upper surface of the support, and a first conductor layer having a first insulating layer and a carrier on the side of the semiconductor structure A step of peeling the carrier after the laminating step, a step of arranging and laminating a second insulating layer and a second conductor layer on the side of the semiconductor structure after the peeling step, and the support. And a step of providing a through hole between the first conductor layer and the second conductor layer, a step of providing a plating layer after the step of providing the through hole, and an external connection electrode of the semiconductor structure; Forming a redistribution layer on the first insulating layer and / or the second insulating layer disposed on the side. The method for manufacturing a semiconductor device, comprising:   4. The method of manufacturing a semiconductor device according to claim 3, wherein the first conductor layer and the second conductor layer are pre-windowed.   5. The method of manufacturing a semiconductor device according to claim 3, wherein the second conductor layer is a metal foil.