JP2002057291A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device as well as its manufacturing method where a capacity element is mounted with no increase in a chip area. SOLUTION: A first conductor layer 5, a dielectrics layer 8, and a second conductor layer 10 are laminated on a circuit element formation region DA to form a solid capacity element. Or, the dielectrics layer 8 is provided in the gap between one side and the other side of the first conductor layers 5 so provided as to adjoin each other on a first protective film 4 to form a planar capacity element. The dielectrics layer 8 is provided in the gap between one side and the other side of the first conductor layer 5 and a post 6 so provided as to adjoin each other on the first protective film 4 to form a capacity element. Thus, a capacity element is mounted with no increase in a chip area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a CSP (Chip Siz
The present invention relates to a semiconductor device having an e-package structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a semiconductor device having a CSP structure in which a chip and a package have almost the same size has been known.
FIG. 24 shows an example of the structure. Semiconductor device 2 shown in FIG.
No. 0 has a so-called wafer-level CSP structure obtained by dicing a wafer, which has been subjected to a package process including protective film formation, conductor layer formation, post formation, and resin sealing, into individual chips. I have. That is, the semiconductor device 20 has a plurality of connection pads 2 made of an aluminum electrode or the like on the surface (circuit surface) side of the wafer (semiconductor substrate) 1, and the center of each connection pad 2 on the upper surface side of the connection pad 2. Passivation 3 made of silicon oxide, silicon nitride, or the like is formed so as to expose the portion.

[0005] On the upper surface side of the passivation 3, a protective film 4 is formed so as to open a central portion of each connection pad 2. The protective film 4 is formed, for example, by applying and curing a polyimide-based resin material over the entire circuit surface side of the wafer 1 and then performing resist patterning and protective film patterning using an etchant, and then stripping the resist. On the protective film 4 thus formed, a conductor layer 5 for electrically connecting each connection pad 2 and a post (columnar electrode) 6 described later is formed. A plurality of posts 6 which are columnar electrodes are provided at predetermined positions on the conductor layer 5. The sealing film 7 is formed by molding the entire circuit surface of the wafer 1 with a resin material such as polyimide or epoxy so as to cover the posts 6. The upper end surface of the sealing film 7 is cut and polished, and the exposed end surface 6a of the post 6 is removed of an oxide film on the surface thereof, and a metallizing process such as solder printing is performed thereon.

[0004]

[0005] By the way, Bluet
In a transceiver chip that implements a wireless I / F such as an ooth module, an RF functional element such as a PLL circuit, a VCO circuit, or a filter circuit is essential. These RF
In order to realize the functional elements, various passive elements such as capacitance elements (capacitors) are mounted on the circuit element formation area DA of the wafer 1 (FIG. 2).
5).

However, when a capacitor is formed in the circuit element forming area DA, the chip area is inevitably increased. In the semiconductor device 20 having the CSP structure described above, when the chip area increases, the number of chips that are singulated from one wafer decreases, and the manufacturing yield also deteriorates. Therefore, at present, various passive elements that implement the RF functional element are externally attached to the chip as discrete components.
In such a form, it is difficult to downsize the RF module.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device and a method of manufacturing a semiconductor device in which a capacitor can be mounted without increasing a chip area. And

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate having a circuit element forming region and a plurality of connection pads formed thereon; In a semiconductor device including the formed insulating film and a plurality of columnar electrodes connected to the connection pad, a first conductor layer formed on the insulating film;
A dielectric layer formed on the first conductor layer; and a second conductor layer provided on the dielectric layer, wherein the first conductor layer, the dielectric layer and the second A capacitor is formed with the conductor layer.

According to a second aspect of the present invention, in the semiconductor device, a semiconductor substrate having a circuit element formation region and a plurality of connection pads formed thereon, an insulating film formed on the circuit element formation region, and a connection to the connection pad are provided. A conductive layer adjacent to each other on the insulating film, and a dielectric layer formed in a gap between one side and the other side of the conductive layer. And a capacitive element formed by the conductive layer and the dielectric layer.

According to a third aspect of the present invention, there is provided a semiconductor device having a semiconductor substrate on which a circuit element formation region and a plurality of connection pads are formed, an insulating film formed on the circuit element formation region, and a connection to the connection pad. A plurality of pillar-shaped electrodes, and a conductor layer adjacent to each other on the insulating film, and a plate-shaped electrode provided on each of the conductor layers, and at least one of the adjacent plate-shaped electrodes. A dielectric layer formed in a gap between one side and the other side; and a capacitive element formed by the adjacent conductor layer and plate-like electrode, and the dielectric layer. .

According to a fourth aspect of the present invention, in the semiconductor device according to the second or third aspect, a columnar electrode is provided at one end and the other end of the capacitive element.

A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the first aspect.
The invention according to any one of the first to third aspects, wherein a periphery of the capacitor is covered with a protective film.

According to a sixth aspect of the present invention, there is provided a semiconductor device according to the first aspect.
The invention according to any one of the first to third aspects, wherein one end and the other end of the capacitive element are connected to the connection pad.

[0013] The semiconductor device according to the seventh aspect is the first aspect.
4. The invention according to any one of the first to third aspects, wherein one end of the capacitive element is connected to the connection pad, and a columnar electrode is provided at the other end.

[0014] The semiconductor device according to the eighth aspect is the first aspect.
4. The invention according to any one of the first to third aspects, wherein a plurality of the capacitive elements are provided.

According to a ninth aspect of the present invention, there is provided a semiconductor device according to the eighth aspect.
In the invention described in the above, the plurality of capacitive elements are configured such that one end and the other end are connected to the connection pad, one end is connected to the connection pad, and the other end is provided with a columnar electrode, and And at least two types of configurations in which a columnar electrode is provided at one end and the other end.

11. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor substrate has a circuit element formation region and a plurality of connection pads formed thereon, an insulating film formed on the circuit element formation region, and the connection pad. A plurality of columnar electrodes connected to
Forming a first conductor layer on a circuit element formation region of the semiconductor substrate via an insulating film; and forming a dielectric layer on the first conductor layer. Forming a second conductive layer on the dielectric layer and laminating the second conductive layer on the circuit element forming region to form a capacitive element.

12. The method of manufacturing a semiconductor device according to claim 11, wherein the semiconductor substrate has a circuit element formation region and a plurality of connection pads formed thereon, an insulating film formed on the circuit element formation region, and the connection pad. A plurality of columnar electrodes connected to
Forming a conductor layer on one side and a conductor layer on the other side adjacent to each other with a predetermined gap on the insulating film; and forming one side and the other side of the conductor layer on the insulating film. Forming a capacitive element planarly on the circuit element forming region by providing a dielectric layer in a gap between the capacitor element and the circuit element forming region.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a semiconductor substrate on which a circuit element forming region and a plurality of connection pads are formed; an insulating film formed on the circuit element forming region of the semiconductor substrate; A plurality of columnar electrodes connected to the connection pad, and a method of manufacturing a semiconductor device comprising:
Forming a conductor layer on one side and a conductor layer on the other side adjacent to each other with a predetermined gap on the insulating film; and forming a plate-shaped electrode on each of the adjacent conductor layers. A step of providing a dielectric layer at least in a gap between one side and the other side of the plate-like electrode to form a capacitive element in a planar manner on the circuit element forming region.

14. A method of manufacturing a semiconductor device according to claim 13, wherein a semiconductor wafer substrate having a plurality of chip formation regions having a circuit element formation region and a plurality of connection pads is provided, and a circuit element of each of the chip formation regions is provided. Forming an insulating film on the formation region, forming a capacitive element on the insulating film with a conductor layer and a dielectric layer, and forming at least one columnar electrode connected to the plurality of connection pads. Forming, and forming a plurality of semiconductor devices by dividing the semiconductor wafer substrate for each chip formation region,
It is characterized by having.

According to a fourteenth aspect of the present invention, in the method for manufacturing a semiconductor device according to the thirteenth aspect, the capacitor element forming step includes the step of forming the conductive layer formed adjacent to each other on the insulating film; The method includes a step of forming a capacitive element by using a dielectric layer formed in a gap between one side and the other side of the conductor layer.

According to a fifteenth aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the tenth to thirteenth aspects, the capacitive element forming step includes a step of covering a periphery of the capacitive element with a protective film. A method for manufacturing a semiconductor device, comprising:

In the present invention, the first conductor layer, the dielectric layer, and the second conductor layer are laminated on the circuit element formation region and laminated inside the chip to form a capacitance element.
It is possible to mount a capacitor without increasing the chip area. Further, in the present invention, since the capacitor is formed two-dimensionally by sandwiching the dielectric layer between the conductor layers on the circuit element forming region, the capacitor can be mounted without increasing the chip area. become. Furthermore, in the present invention, the capacitor is formed in a planar manner by sandwiching the dielectric layer between the conductor layer and the columnar electrode on the circuit element forming region, so that the capacitor is mounted without increasing the chip area. It becomes possible.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. (1) First Embodiment FIGS. 1 to 10 show a semiconductor device 20 according to a first embodiment.
FIG. 4 is a cross-sectional view for explaining the structure of FIG. The conventional example described above in these figures (see FIG. 24).
The same reference numerals are given to the parts common to and the description thereof will be omitted. The semiconductor device 20 according to the first embodiment is different from the above-described conventional example (see FIG. 24) in that the semiconductor layer 20 has a lower surface connected to the connection pad 2 (hereinafter, referred to as a first conductive layer 5). A conductor layer 10 on which a post 6 is formed on the upper surface (hereinafter, referred to as a conductor layer 10)
A capacitor (capacitor) is formed by providing a dielectric layer 8 between the capacitor and a second conductor layer 10, and a protective film 9 (hereinafter, referred to as a second protective film 9) surrounds the capacitor. Cover and electrically insulate it.

The capacitance of the capacitor formed by such a structure is determined by the relative permittivity, thickness and area of the dielectric forming the dielectric layer 8. As a dielectric material for forming the dielectric layer 8, for example, barium titanate, tantalum titanate, or the like is used. In addition, the capacitive elements formed by being stacked on the circuit element forming area DA can be arranged in various modes. For example, when a large-capacity capacitive element is provided, as shown in FIG. In the case where a plurality of capacitive elements are provided, the mode shown in FIG.

Next, a manufacturing process of the semiconductor device 20 having the above structure will be described with reference to FIGS. In the manufacturing process according to the first embodiment, first, as shown in FIG. 3, the center of each connection pad 2 is formed on the upper surface side of a plurality of connection pads 2 made of aluminum electrodes and the like provided on the circuit surface side of the wafer 1. A passivation 3 made of silicon oxide, silicon nitride, or the like is formed so as to expose the portion. Thereafter, a protective film 4 (hereinafter referred to as a first film) is formed on the upper surface side of the passivation 3 so that a central portion of each connection pad 2 is opened.
Protective film 4) is formed.

The first protective film 4 is formed, for example, by applying and curing a polyimide resin material over the entire circuit surface side of the wafer 1 and then performing resist patterning and protective film patterning using an etchant, and then removing the resist. It is formed by doing. The protective film 4 may be formed by applying a polyimide resin material and applying a spin coating method, as well as a printing method using a squeegee or a coating method using ink ejection from a nozzle. Not limited to the material, an epoxy resin material, PBO (benzaoxide), or the like may be used.

Next, as shown in FIGS. 4 and 5,
A first conductor layer is formed on the connection pad exposed through an opening formed in the protective film. First conductor layer 5
Is UBM on the entire surface of the protective film 4 by UBM sputtering or the like.
After depositing a layer (not shown), applying and curing a photoresist for a conductor layer, performing patterning having an opening of a predetermined shape by a photolithography technique, and applying electrolytic plating to a portion opened by the resist. It is formed by. As a method of forming the first conductor layer 5, there are:
Alternatively, an electroless plating method can be used. As the wiring material, copper, aluminum, gold, or an alloy thereof having good conductive properties is used.

After the formation of the first conductor layer 5, a dielectric layer 8 is formed at a predetermined position on the first conductor layer 5. The dielectric layer 8 is formed by, for example, forming a pattern with a resist and then depositing a dielectric material to a predetermined thickness by sputtering. After the dielectric layer 8 is formed, as shown in FIG. 6, the dielectric layer 8 is electrically insulated from other layers, and a portion where the second conductor layer 10 is provided, or a portion where dicing is cut. A second protective film 9 is formed so as to open a portion where the second protective film 9 is to be formed. Similarly to the above-described first protective film 4, the second protective film 9 is formed, for example, by applying and curing a polyimide resin material over the entire circuit surface side of the wafer 1 and then using an etchant to perform resist patterning and protective film formation. It is formed by stripping the resist after patterning.

Next, when the second protective film 9 is formed,
As shown in FIG. 7, while being electrically connected to the first conductor layer 5 exposed through the opening formed in the second protective film 9, the upper surface of the dielectric layer 8 is electrically connected to the first conductor layer 5. Connect to the second
Is formed. The second conductor layer 10 is formed by patterning with a resist and then performing electrolytic plating similarly to the first conductor layer 5 described above. After the formation of the second conductor layer 10, the posts 6 are provided at predetermined positions on each conductor layer 10, as shown in FIG.

The post 6 is formed by applying and curing a photoresist for forming a post having a thickness of, for example, about 100 to 150 μm, and forming an opening exposing a predetermined portion of the second conductor layer 10. It is formed by subjecting to electrolytic plating. As a method of forming the post 6, other than this, an electroless plating method or a stud bump method can be used. As the post material, copper, solder, gold, nickel, or the like having good conductive properties is used. When solder is used as the post forming material, a spherical electrode can be formed by performing a reflow process thereafter. When the post 6 is formed using solder, a printing method can be used in addition to the above.

After the structure shown in FIG. 8 is thus formed, the entire circuit surface of the wafer 1 is molded with a resin material such as polyimide or epoxy so as to cover the posts 6 as shown in FIG. Thus, a sealing film 7 is formed. The sealing film 7 is preferably made of a resin material whose main component is substantially the same as that of the first protective film 4 and the second protective film 9 described above, in order to secure reliability corresponding to environmental changes. As a method of forming the sealing film 7, a printing method, a dipping method, a spin coating method, and a die coating method can be used in addition to the molding method.

After the resin sealing of the post 6, as shown in FIG. 10, the upper end face of the sealing film 7 is cut and polished to expose the end face 6a of the post 6, and the oxide film on the surface is removed. Perform metallization processing such as solder printing. Thereafter, dicing is performed along a predetermined cut line CL to singulate the wafer 1 into chips. As a result, the semiconductor device 20 having the structure shown in FIG. 1 is generated.

In the semiconductor device 20 having such a structure, the first conductive layer 5, the dielectric layer 8, and the second conductive layer 10 are stacked to form a three-dimensional capacitive element. , The capacitive element in various forms according to the arrangement of the second conductor layer redistribution 10 and the post 6 in an integrated circuit (LSI)
Can be connected to A specific example will be described with reference to FIGS. These figures show the connection form of the capacitor according to the arrangement of the second conductor layer 10 and the post 6 in the semiconductor device 20, and the equivalent circuit corresponding thereto.

FIG. 11 shows one end and the other end of the capacitive element formed by laminating the first conductor layer 5, the dielectric layer 8 and the second conductor layer 10 without drawing out to the outside and connecting pads 2-2, 2 3 illustrates a form of connection to the wafer 1 via the -3. FIG.
FIG. 1 shows a mode in which one end of a capacitive element is connected to connection pads 2-1 and 2-2 connected to the wafer 1, and the other end is connected to terminals T1 and T2. FIG. 13 shows one end of both capacitance elements provided in parallel connected to the connection pad 2-2, and the other end connected to the terminal T.
2 and T3 are illustrated. FIG.
Reference numeral 4 denotes a form in which one end of the capacitive element is connected to the connection pad 2-2 of the connection pads 2-1 to 2-3 connected to the wafer 1, and the other end is connected to the terminal T2.

As described above, according to the first embodiment,
The first conductor layer 5 and the dielectric layer 8 are formed on the circuit element formation area DA.
Since the capacitor is formed three-dimensionally by laminating the second conductor layer 10 and the second conductor layer 10, it is possible to mount the capacitor without increasing the chip area. In addition, when a plurality of capacitance elements are provided on the circuit element formation area DA, it goes without saying that various forms of the capacitance elements shown in FIGS. 11 to 14 may be provided in a mixed manner.

That is, according to the first embodiment, the second
Capacitors can be connected to an integrated circuit (LSI) in various forms in accordance with the arrangement of the conductor layer 10 and the posts 6 of FIG.
When the present invention is applied to a tooth module, a conventionally required external capacitance element can be built in, which can contribute to downsizing of the module.

In the first embodiment described above, the dielectric layer 8 is a single layer. However, the present invention is not limited to this.
A plurality of capacitance elements may be formed in a multilayer structure in which the conductor layers 10 are alternately stacked. In this case, a plurality of capacitive elements can be connected in parallel or in series by the patterns of the plurality of second conductor layers 10 stacked alternately. Further, in the first embodiment, in order to simplify the description, the capacitance element is simply formed by stacking the first conductor layer 5, the dielectric layer 8, and the second conductor layer 10. In order to suppress the effect of the capacitive element on other conductor layers, that is, stray capacitance and parasitic capacitance, for example, the conductor layer 5 or the conductor layer 10
A ground layer made of the same material as the conductor layer 5 or the conductor layer 10 may be provided in the vicinity of the same plane as that of the conductor layer 5. Furthermore, in the first embodiment, the capacitance element is formed by providing the dielectric layer 8. Alternatively, for example, a dielectric material may be mixed in the second protective film 9 to form the dielectric layer 8.
May also be used.

(2) Second Embodiment FIGS. 15 to 18 show a semiconductor device 2 according to a second embodiment.
FIG. 2 is a cross-sectional view for explaining a structure of No. 0 and a manufacturing process thereof. In these figures, the first embodiment (FIG. 1)
The same reference numerals are given to the same parts as those in FIG. In the above-described first embodiment, the first conductor layer 5, the dielectric layer 8, and the second conductor layer 10 are stacked to form a three-dimensional capacitor, whereas in the second embodiment, As shown in FIG. 15, a dielectric layer 8 is formed in a gap between one side and the other side of the conductor layers 5 arranged adjacent to each other on the first protective film 4. That is, the capacitor is formed in a planar manner by sandwiching the dielectric layer 8 between the conductor layers 5.

As in the first embodiment, the capacitance of the capacitor formed by the above structure is determined by the relative permittivity, thickness and area of the dielectric forming the dielectric layer 8. Dielectric layer 8
As a dielectric for forming, for example, barium titanate,
Tantalum titanate or the like is used. Further, the capacitance element thus formed in a plane on the circuit element formation area DA is
For example, when a large-capacity capacitive element is provided, the configuration shown in FIG. 16A is used, and when a plurality of capacitive elements are provided, the configuration shown in FIG. 16B is used.

Next, the manufacturing process of the semiconductor device 20 according to the second embodiment will be described with reference to FIGS. The difference between the manufacturing process according to the second embodiment and the above-described first embodiment is that a dielectric layer is formed in a gap between one side and the other side of the conductor layers 5 arranged on the first protective film 4 so as to be adjacent to each other. The second protective film 9 is provided after the body layer 8 is formed. That is, in the manufacturing process according to the second embodiment, as in the first embodiment, each connection pad 2 is provided on the upper surface side of a plurality of connection pads 2 made of aluminum electrodes and the like provided on the circuit surface side of the wafer 1. Is formed so as to expose the central portion of the passivation layer 3 made of silicon oxide or silicon nitride.
The first protective film 4 is formed on the upper surface side of the substrate so that the central portion of each connection pad 2 opens.

After forming the first protective film 4, as shown in FIG. 17, a conductor layer 5 is formed on the connection pads 2 exposed through the openings formed in the first protective film 4. .
The conductor layer 5 is formed by depositing a UBM layer (not shown) on the entire surface of the protective film 4 by a UBM sputtering process or the like, applying and curing a photoresist for the conductor layer, and performing patterning having an opening of a predetermined shape by a photolithography technique. After giving
It is formed by applying electrolytic plating to a portion opened by the resist. At this time, an opening (gap) for providing the dielectric layer 8 is formed at a predetermined position on the first protective film 4.

After the conductor layer 5 is formed, as shown in FIG. 17, an opening (gap) provided on the first protective film 4 is formed.
Next, a dielectric layer 8 is formed. The dielectric layer 8 is formed by, for example, forming a pattern with a resist and then depositing a dielectric material to a predetermined thickness by sputtering. And the dielectric layer 8
After forming the second protective film 9, as shown in FIG. 18, a second protective film 9 is formed to electrically insulate the dielectric layer 8, and then the opening formed in the second protective film 9 is formed. There is provided a post 6 electrically connected to the conductor layer 5 exposed through the post.

Thereafter, the wafer 1 is covered so as to cover the post 6.
Is molded with a resin material such as polyimide or epoxy to form a sealing film 7. After the formation of the sealing film 7, the upper end surface of the sealing film 7 is cut and polished to expose the end surface 6a of the post 6, the oxide film on the surface is removed, and a metallizing process such as solder printing is performed thereon. Next, the semiconductor device 20 having the structure shown in FIG. 15 is obtained by dicing the wafer 1 into chips by dicing along predetermined cut lines.

In the semiconductor device 20 having such a structure, since the capacitive element is formed two-dimensionally by sandwiching the dielectric layer 8 between the conductor layers 5, the capacitance depends on the arrangement of the conductor layer 5 and the post 6. The device can be integrated into various forms of integrated circuits (LS
I). A specific example will be described with reference to FIGS. These drawings illustrate the connection form of the capacitive element according to the arrangement of the conductor layer 5 and the post 6 in the semiconductor device 20, and the equivalent circuit corresponding thereto.

FIG. 19 shows a form in which one end and the other end of a capacitive element formed by sandwiching a dielectric layer 8 between conductive layers 5 are drawn out without connecting to the wafer 1, that is, a capacitive element to be used as a preliminary is mounted on a chip. FIG. FIG. 20 illustrates a form in which one end and the other end of the capacitive element are connected to the wafer 1 directly through the connection pads 2-1 and 2-2 without being pulled out to the outside. FIG. 21 shows an embodiment in which capacitance elements are connected in parallel to connection pads 2-1 and 2-2 connected to wafer 1.
That is, an embodiment in which a capacitive element used as an auxiliary is mounted on a chip is illustrated.

As described above, according to the second embodiment,
Since the dielectric layer 8 is sandwiched between the conductor layers 5 on the circuit element forming area DA to form the capacitive element in a planar manner, the capacitive element can be mounted without increasing the chip area. Further, according to the second embodiment, since the capacitance element is formed two-dimensionally, the process can be simplified as compared with the first embodiment in which the capacitance element is formed three-dimensionally. Further, when a plurality of capacitance elements are provided on the circuit element formation region DA, it goes without saying that various types of capacitance elements shown in FIGS. 19 to 21 may be provided in a mixed manner.

That is, in the second embodiment, the conductor layer 5
Capacitors can be connected to an integrated circuit (LSI) in various forms according to the arrangement of the posts 6 and the post 6. Therefore, when the present invention is applied to a Bluetooth module as well as a downsizing of a chip area, it is conventionally required. Since the external capacitance element can be built in, it can contribute to downsizing of the module.

In the second embodiment, for the sake of simplicity of explanation, the capacitance element in which the dielectric layer 8 is simply sandwiched between the first conductor layers 5 is used. To suppress the effect on the conductor layer, that is, stray capacitance and parasitic capacitance, for example,
The ground layer made of the same material as the conductor layer 5 may be provided.

(3) Third Embodiment Next, a third embodiment will be described with reference to FIG. FIG. 22 is a sectional view showing the structure of the semiconductor device 20 according to the third embodiment.
Portions common to the embodiment (see FIG. 15) are denoted by the same reference numerals, and description thereof is omitted.

In the second embodiment described above, the dielectric layer 8
Are sandwiched by the first conductor layer 5 to form a capacitive element in a planar manner. In the third embodiment, as shown in FIG. 22, they are arranged adjacent to each other on the first protective film 4. The dielectric layer 8 is formed in the gap between the first conductor layer 5 and the post 6 on one side and the other side. That is, the dielectric element 8 is sandwiched between the first conductor layer 5 and the post 6 to form a planar capacitive element. In this case, the post 6 sandwiching the dielectric layer 8 is formed in a rectangular column shape or a plate shape having a rectangular shape in plan view. Note that the dielectric layer 8 may be sandwiched only between the plate-like posts 6.

The capacitance element formed by the above-described structure
As in the second embodiment, the relative permittivity, the thickness and the area of the dielectric forming the dielectric layer 8 determine its capacitance. As the dielectric forming the dielectric layer 8, for example, barium titanate,
Tantalum titanate or the like is used. The capacitive element formed in this manner can be arranged on the chip in various modes according to the shape of the post 6 that sandwiches the dielectric layer 8. For example, when the post 6 is formed in a plate shape having a rectangular shape in a plan view, the capacitive element is arranged on the chip in a manner shown in FIG.

Further, as shown in FIG. 23 (b), it is also possible to lay the plate-like post 6 around the chip periphery, and thus, the area of the dielectric layer 8 can be increased. Since the size can be increased, a capacitor with a large capacity can be formed. In the semiconductor device 20 having such a structure, since the dielectric element 8 is sandwiched between the conductor layer 5 and the post 6 to form a capacitive element in a plane, the illustration is omitted. Similarly, a capacitor can be connected to an integrated circuit (LSI) in various forms. Further, when a plurality of capacitance elements are provided on the circuit element formation area DA, it goes without saying that these various forms may be provided in a mixed manner.

As described above, according to the third embodiment,
The dielectric layer 8 is formed on the first conductor layer 5 on the circuit element forming area DA.
And the capacitor 6 is sandwiched between the posts 6 to form the capacitive element in a planar manner, without increasing the chip area.
It is possible to mount a larger capacitance element than in the case of the second embodiment. It should be noted that, based on each of the above-described embodiments, when a plurality of capacitance elements are provided on the circuit element formation region DA, it may be configured such that various types of capacitance elements in each embodiment may be provided in a mixed manner. Not even.

[0054]

According to the first and tenth aspects of the present invention, the semiconductor substrate on which the circuit element formation region and the plurality of connection pads are formed, the insulating film formed on the circuit element formation region, A plurality of columnar electrodes connected to the connection pad, wherein a first conductor layer formed on the insulating film, a dielectric layer formed on the first conductor layer, Since the capacitor element is formed by the second conductor layer provided on the dielectric layer and the capacitor element is formed by stacking the capacitor element on the circuit element forming region, the chip area is increased. And a capacitor can be formed and mounted. According to the second and eleventh aspects of the present invention, the semiconductor substrate on which the circuit element formation region and the plurality of connection pads are formed, the insulating film formed on the circuit element formation region, and the connection pad A plurality of columnar electrodes connected to each other, wherein the semiconductor device is formed by a conductor layer adjacent to each other on the insulating film and a dielectric layer formed in a gap between one side and the other side of the conductor layer. Since the capacitance element is provided and the capacitance element is formed in a plane on the circuit element formation region, the capacitance element can be formed and mounted in a simple manufacturing process without increasing the chip area. it can. According to the third and twelfth aspects of the present invention, the semiconductor substrate on which the circuit element formation region and the plurality of connection pads are formed, the insulating film formed on the circuit element formation region, and the connection pad A plurality of columnar electrodes connected to each other, a conductor layer adjacent to each other on the insulating film, and a plate electrode provided on each of the conductor layers, and at least the adjacent plate electrode Since the capacitive element is formed by the dielectric layer formed in the gap between one side and the other side, a large-capacity capacitive element can be formed and mounted without increasing the chip area. it can. According to the invention as set forth in claims 4 to 9, the capacitance element provided on the circuit element formation region via the insulating film can be connected to the integrated circuit in the circuit element formation region in various forms. The area and the module area can be reduced. According to the invention as set forth in claims 13 to 15, a conductor layer is formed on a circuit element formation region of a semiconductor wafer substrate provided with a plurality of chip formation regions having a plurality of circuit element formation regions and a plurality of connection pads via an insulating film. After forming at least one columnar electrode connected to the plurality of connection pads by forming a capacitive element by a dielectric layer, a plurality of chips are formed by dividing into chip forming regions. A plurality of chips each having a capacitor mounted thereon with an insulating film interposed therebetween can be formed over the formation region.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device 20 according to a first embodiment.

FIG. 2 is a plan view for explaining an arrangement form of a capacitor.

FIG. 3 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment;

FIG. 4 is a cross-sectional view for explaining a manufacturing step of the semiconductor device following FIG. 3;

FIG. 5 is a cross-sectional view for explaining a manufacturing step of the semiconductor device following FIG. 4;

FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device following FIG. 5;

FIG. 7 is a cross-sectional view for explaining a manufacturing step of the semiconductor device following FIG. 6;

FIG. 8 is a cross-sectional view for explaining a manufacturing step of the semiconductor device following FIG. 8;

FIG. 9 is a cross-sectional view for explaining a manufacturing step of the semiconductor device following FIG. 9;

FIG. 10 is a cross-sectional view for explaining a manufacturing process of the semiconductor device following FIG. 9, and shows a completed state of the semiconductor device 20 which has been separated;

FIG. 11 is a diagram illustrating a connection mode of a capacitor.

FIG. 12 is a diagram illustrating a connection mode of a capacitor.

FIG. 13 is a diagram illustrating a connection mode of a capacitor.

FIG. 14 is a diagram illustrating a connection mode of a capacitor.

FIG. 15 is a sectional view showing the structure of the semiconductor device 20 according to the second embodiment.

FIG. 16 is a plan view for explaining an arrangement mode of the capacitor.

FIG. 17 is a sectional view for explaining the manufacturing process of the semiconductor device according to the first embodiment;

FIG. 18 is a cross-sectional view for illustrating a manufacturing step of the semiconductor device following FIG. 17;

FIG. 19 is a diagram illustrating a connection mode of a capacitor.

FIG. 20 is a diagram illustrating a connection mode of a capacitor.

FIG. 21 is a diagram illustrating a connection mode of a capacitor.

FIG. 22 is a cross-sectional view illustrating a structure of a semiconductor device 20 according to a third embodiment.

FIG. 23 is a plan view for explaining an arrangement mode of the capacitor.

FIG. 24 is a cross-sectional view showing a structure of a semiconductor device 20 according to a conventional example.

FIG. 25 is a plan view showing a circuit element formation area DA of the wafer 1.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wafer (semiconductor substrate) 2 Connection pad 3 Passivation 4 Protective film 5 First conductive layer 6 Post (columnar electrode) 7 Sealing film 8 Dielectric layer 9 Protective film 10 Second conductive layer 20 Semiconductor device

Continued on the front page (72) Inventor Ichiro Mihara 550 Higashi-Asakawa-cho, Hachioji-shi, Tokyo Inside I-P Technologies Inc. (72) Inventor Yoshitaka Aoki 3-2-1 Sakaemachi, Hamura-shi, Tokyo No. Casio Computer Co., Ltd. Hamura Technical Center F term (reference) 5E082 AB03 BB10 FG03 FG26 FG27 FG42 KK01 5F038 AC05 AC17 BE07 EZ14 EZ15

Claims (15)

[Claims] A semiconductor substrate on which a circuit element formation region and a plurality of connection pads are formed; an insulating film formed on the circuit element formation region; and a plurality of columnar electrodes connected to the connection pads. In the semiconductor device, a first conductive layer formed on the insulating film, a dielectric layer formed on the first conductive layer, and a second conductive layer provided on the dielectric layer A semiconductor device comprising: a capacitance element formed by the first conductor layer, the dielectric layer, and the second conductor layer. 2. A semiconductor substrate having a circuit element formation region and a plurality of connection pads formed thereon, an insulating film formed on the circuit element formation region, and a plurality of columnar electrodes connected to the connection pads. A semiconductor device comprising: a conductor layer adjacent to each other on the insulating film; and a dielectric layer formed in a gap between one side and the other side of the conductor layer,
A semiconductor device comprising a capacitor formed by the adjacent conductor layer and the dielectric layer. 3. A semiconductor substrate having a circuit element formation region and a plurality of connection pads formed thereon, an insulating film formed on the circuit element formation region, and a plurality of columnar electrodes connected to the connection pads. In the semiconductor device provided, a conductor layer adjacent to each other on the insulating film, a plate electrode provided on each of the conductor layers, and a gap between at least one side and the other side of the adjacent plate electrode Comprising a dielectric layer formed on, the adjacent conductor layer and a plate-shaped electrode,
A semiconductor device comprising: a capacitor formed by the dielectric layer. 4. The semiconductor device according to claim 2, wherein a columnar electrode is provided at one end and the other end of the capacitance element. 5. The semiconductor device according to claim 1, wherein a periphery of the capacitor is covered with a protective film. 6. The semiconductor device according to claim 1, wherein one end and the other end of the capacitance element are connected to the connection pad. 7. The semiconductor device according to claim 1, wherein one end of the capacitive element is connected to the connection pad, and a columnar electrode is provided at the other end. 8. The semiconductor device according to claim 1, wherein a plurality of the capacitive elements are provided. 9. The invention according to claim 8, wherein the plurality of capacitors have one end and the other end connected to the connection pad, and one end connected to the connection pad and the other end provided with a columnar electrode. A semiconductor device comprising at least two types of configurations provided, and configurations in which a columnar electrode is provided at one end and the other end. 10. A semiconductor substrate having a circuit element formation region and a plurality of connection pads formed thereon, an insulating film formed on the circuit element formation region, and a plurality of columnar electrodes connected to the connection pads. A method for manufacturing a semiconductor device comprising: a step of forming a first conductor layer on a circuit element formation region of the semiconductor substrate via an insulating film; and forming a dielectric layer on the first conductor layer; Providing a second conductor layer on the dielectric layer and laminating on the circuit element formation region to form a capacitor element. 11. A semiconductor substrate having a circuit element formation region and a plurality of connection pads formed thereon, an insulating film formed on the circuit element formation region, and a plurality of columnar electrodes connected to the connection pads. Forming a conductor layer on one side and a conductor layer on the other side adjacent to each other with a predetermined gap on the insulating film; and forming one side and the other side of the conductor layer on the insulating film. Providing a dielectric layer in the gap and forming a capacitive element on the circuit element forming region in a planar manner. 12. A semiconductor substrate having a circuit element formation region and a plurality of connection pads formed thereon, an insulating film formed on the circuit element formation region of the semiconductor substrate, and a plurality of columnar electrodes connected to the connection pads. Forming a semiconductor layer on one side and a conductor layer on the other side adjacent to each other with a predetermined gap on the insulating film; and each of the adjacent conductor layers. Forming a plate-shaped electrode on the substrate; and forming a capacitive element in a plane on the circuit element formation region by providing a dielectric layer at least in a gap between one side and the other side of the plate-shaped electrode. A method for manufacturing a semiconductor device, comprising: 13. A step of preparing a semiconductor wafer substrate including a plurality of chip forming regions having a circuit element forming region and a plurality of connection pads, and a step of forming an insulating film on the circuit element forming region of each of the chip forming regions. Forming a capacitor element on the insulating film by using a conductor layer and a dielectric layer; forming at least one columnar electrode connected to the plurality of connection pads; Forming a plurality of semiconductor devices by dividing each chip formation region. 14. The invention according to claim 13, wherein, in the capacitive element forming step, the conductive layer formed adjacent to each other on the insulating film and a gap between one side and the other side of the conductive layer Forming a capacitive element using the dielectric layer formed on the semiconductor device. 15. The method for manufacturing a semiconductor device according to claim 10, wherein the step of forming the capacitor includes a step of covering a periphery of the capacitor with a protective film.