JP2008300560A - Semiconductor device, and manufacturing method thereof - Google Patents

Semiconductor device, and manufacturing method thereof Download PDF

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JP2008300560A
JP2008300560A JP2007143896A JP2007143896A JP2008300560A JP 2008300560 A JP2008300560 A JP 2008300560A JP 2007143896 A JP2007143896 A JP 2007143896A JP 2007143896 A JP2007143896 A JP 2007143896A JP 2008300560 A JP2008300560 A JP 2008300560A
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insulating layer
layer
conductive layer
active element
semiconductor device
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Osamu Yamagata
修 山形
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Sony Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which wiring density can be enhanced by constraining an increase in thickness. <P>SOLUTION: The semiconductor device includes a substrate 20, an active element 10 mounted on the substrate 20, a first insulating layer 26 formed on the substrate 20 and not thicker than the active element 10 at a position different from the part where the active element 10 is mounted, a first conductive layer 28 formed on the first insulating layer 26, a second insulating layer 29 formed above the first insulating layer 26 to cover the active element 10 and the first conductive layer 28, and a second conductive layer 32 formed on the second insulating layer 29. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関し、特に半導体チップ等の能動素子をウエハレベルでパッケージ化された半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which active elements such as semiconductor chips are packaged at a wafer level and a manufacturing method thereof.

半導体チップ等の能動素子とコンデンサ等の受動素子とを高密度に内蔵し、パッケージ化された半導体装置として、例えば、図１０に示す構成の半導体装置が提案されている（例えば、特許文献１参照）。   For example, a semiconductor device having a configuration shown in FIG. 10 has been proposed as a packaged semiconductor device in which active elements such as a semiconductor chip and passive elements such as a capacitor are embedded at high density. ).

図１０に示す半導体装置は、基板１００上に形成されたキャパシタ１１０と、基板１００にフェイスアップで搭載された２個の能動素子１３０Ａ，１３０Ｂとを第１の絶縁層１１１で被覆した構造を有する。
また、第１の絶縁層１１１の表面に形成された導電層１２５を第２の絶縁層１２１で被覆し、第２の絶縁層１２１上に形成されたインダクタ１２０及び導電層１２７を第３の絶縁層１４０によって被覆した構造を有する。
また、第１〜第３絶縁層１１１，１２１，１４０に埋め込まれた素子の電極等を絶縁層の表面に引き出すための接続部１１６，１２６，１４３が、絶縁層１１１，１２１，１４０に形成される。また、絶縁層１１１，１２１の表面には、接続部１１６，１２６等に接合し、各素子間を電気的に接続し、若しくは電極位置を再配置するための導電層１２５及び１２７が設けられる。絶縁層１４０の表面には、接続部１４３に接合し、半導体装置と外部機器とを接続するためのバンプ等よりなる外部電極１４５が設けられている。 The semiconductor device shown in FIG. 10 has a structure in which a capacitor 110 formed on a substrate 100 and two active elements 130A and 130B mounted face-up on the substrate 100 are covered with a first insulating layer 111. .
In addition, the conductive layer 125 formed on the surface of the first insulating layer 111 is covered with the second insulating layer 121, and the inductor 120 and the conductive layer 127 formed on the second insulating layer 121 are third-insulated. It has a structure covered by the layer 140.
In addition, connection portions 116, 126, and 143 are formed in the insulating layers 111, 121, and 140 for leading out the electrodes of the elements embedded in the first to third insulating layers 111, 121, and 140 to the surface of the insulating layer. The Conductive layers 125 and 127 are provided on the surfaces of the insulating layers 111 and 121 to join the connection portions 116 and 126, etc., to electrically connect the elements, or to rearrange the electrode positions. On the surface of the insulating layer 140, an external electrode 145 is provided which is bonded to the connection portion 143 and is made of a bump or the like for connecting the semiconductor device and an external device.

特開２００５−５５４８号公報JP 2005-5548 A

上述の半導体装置では、能動素子１３０Ａ，１３０Ｂを埋め込むように第１の絶縁層１１１が形成されている。そして、能動素子１３０Ａ，１３０Ｂの電極の開口部を形成している。
このため、半導体装置の配線密度を向上させるために、装置内に複数の導電層を形成する場合には、導電層を被覆する絶縁層を能動素子の上部に複数設けなければならない。このため、半導体装置全体の厚さが増加してしまう。
また、インダクタ等の受動素子を配線により形成する場合には、能動素子の上部に配線等の導電層を形成しなければならないため、半導体装置全体の厚さが増加してしまう。さらに、インダクタを２以上設ける場合はより層数が増加してしまう。 In the semiconductor device described above, the first insulating layer 111 is formed so as to bury the active elements 130A and 130B. And the opening part of the electrode of active element 130A, 130B is formed.
For this reason, in order to improve the wiring density of the semiconductor device, when a plurality of conductive layers are formed in the device, a plurality of insulating layers covering the conductive layers must be provided on the active elements. For this reason, the thickness of the entire semiconductor device increases.
In addition, when a passive element such as an inductor is formed by wiring, a conductive layer such as wiring must be formed on the active element, which increases the thickness of the entire semiconductor device. Further, when two or more inductors are provided, the number of layers is further increased.

上述した問題の解決のため、本発明においては、半導体装置の厚さの増加を抑え、配線密度を向上させることが可能な半導体装置及びその製造方法を提供するものである。   In order to solve the above-described problems, the present invention provides a semiconductor device capable of suppressing an increase in the thickness of the semiconductor device and improving the wiring density, and a manufacturing method thereof.

本発明の半導体装置は、基板と、基板に搭載される能動素子と、能動素子が搭載された部分とは異なる位置において、基板上に能動素子の厚さ以下に形成される第１の絶縁層と、第１の絶縁層上に形成される第１の導電層と、第１の絶縁層の上部に形成され、能動素子及び第１の導電層を被覆する第２の絶縁層と、第２の絶縁層上に形成される第２の導電層とを備えることを特徴とする。   The semiconductor device of the present invention includes a first insulating layer formed on the substrate at a thickness equal to or less than the thickness of the active element at a position different from the substrate, the active element mounted on the substrate, and the portion where the active element is mounted. A first conductive layer formed on the first insulating layer; a second insulating layer formed on the first insulating layer and covering the active element and the first conductive layer; And a second conductive layer formed on the insulating layer.

本発明半導体装置では、基板上に搭載される能動素子の搭載部分と異なる位置に、能動素子の厚さ以下の第１の絶縁層が形成され、この第１の絶縁層上に第１の導電層が形成される。このような構成により、基板から第１の導電層までの厚さが、基板から能動素子までの厚さよりも薄く形成される。そして、第１の導電層及び能動素子を被覆して第２の絶縁層が形成される。このため、半導体装置の厚さは、搭載された能動素子の厚さのみに依存し、第１の絶縁層及び第１の導電層の厚さの分の増加を抑えることができる。
従って、第１の導電層と第２の導電層との積層構造により、配線密度が向上した場合でも、半導体装置全体の厚さに影響を与えない。 In the semiconductor device of the present invention, a first insulating layer having a thickness equal to or smaller than the thickness of the active element is formed at a position different from the mounting portion of the active element mounted on the substrate, and the first conductive layer is formed on the first insulating layer. A layer is formed. With such a configuration, the thickness from the substrate to the first conductive layer is formed thinner than the thickness from the substrate to the active element. A second insulating layer is then formed covering the first conductive layer and the active element. For this reason, the thickness of the semiconductor device depends only on the thickness of the mounted active element, and an increase in the thicknesses of the first insulating layer and the first conductive layer can be suppressed.
Therefore, even when the wiring density is improved by the laminated structure of the first conductive layer and the second conductive layer, the thickness of the entire semiconductor device is not affected.

本発明の半導体装置の製造方法は、基板上に、能動素子の搭載部分に開口部を設け、能動素子以下の厚さで第１の絶縁層を形成する工程と、第１の導電層上に第１の導電層を形成する工程と、第１の絶縁層の開口部に能動素子を搭載する工程と、第１の絶縁層上に、能動素子及び第１の導電層を被覆する第２の絶縁層を形成する工程と、第２の絶縁層上に第２の導電層を形成する工程とからなることを特徴とする。   According to a method of manufacturing a semiconductor device of the present invention, a step of providing an opening in a mounting portion of an active element on a substrate and forming a first insulating layer with a thickness equal to or less than that of the active element; A step of forming a first conductive layer; a step of mounting an active element in an opening of the first insulating layer; and a second step of covering the active element and the first conductive layer on the first insulating layer. The method includes a step of forming an insulating layer and a step of forming a second conductive layer on the second insulating layer.

半導体装置の製造方法では、能動素子の搭載部分と異なる位置に能動素子以下の厚さで第１の絶縁層を形成し、この第１の絶縁層上に第１の導電層を形成する。第１の絶縁層を能動素子以下の厚さで形成することにより、第１の導電層は、能動素子よりも低い位置に形成される。そして、この第１の絶縁層の上及び第１の導電層上に、能動素子を被覆して第２の絶縁層を形成する。このため、基板から第２の絶縁層までの厚さは、能動素子の厚さによる影響を受けるが、能動素子よりも薄い第１の絶縁層の影響は受けない。
従って、下部導電層と第２の導電層との間に第１の導電層を形成し、半導体装置の配線密度を向上させた場合にも、半導体装置の厚さに影響を与えない。 In the method of manufacturing a semiconductor device, a first insulating layer is formed with a thickness equal to or less than that of the active element at a position different from the mounting portion of the active element, and the first conductive layer is formed on the first insulating layer. By forming the first insulating layer with a thickness equal to or less than that of the active element, the first conductive layer is formed at a position lower than that of the active element. Then, an active element is covered on the first insulating layer and the first conductive layer to form a second insulating layer. Therefore, the thickness from the substrate to the second insulating layer is affected by the thickness of the active element, but is not affected by the first insulating layer thinner than the active element.
Therefore, even when the first conductive layer is formed between the lower conductive layer and the second conductive layer to improve the wiring density of the semiconductor device, the thickness of the semiconductor device is not affected.

本発明によれば、半導体装置の厚さの増加を抑え、半導体装置の配線密度を向上させることができる。   According to the present invention, an increase in the thickness of the semiconductor device can be suppressed and the wiring density of the semiconductor device can be improved.

本発明の実施の形態について図面を用いて説明する。
図１は本発明の一実施形態に係わる半導体装置の断面図である。 Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

本実施の形態の半導体装置は、基板２０上に、例えばトランジスタ等の半導体素子を含む電子回路が形成された能動素子１０が搭載される。
また、基板２０上には、下地絶縁膜２１、電極２２、パッシベーション膜２３が形成される。さらにその上には、第１のシード層２４、下部導電層２５、第１の絶縁層２６、だ２のシード層２７、第１の導電層２８、第２の絶縁層２９、第３のシード層３０、第２の導電層３１、第３の絶縁層３２、及び、外部電極３３が形成される。 In the semiconductor device of the present embodiment, an active element 10 in which an electronic circuit including a semiconductor element such as a transistor is formed is mounted on a substrate 20.
A base insulating film 21, an electrode 22, and a passivation film 23 are formed on the substrate 20. Further thereon, a first seed layer 24, a lower conductive layer 25, a first insulating layer 26, a second seed layer 27, a first conductive layer 28, a second insulating layer 29, and a third seed. The layer 30, the second conductive layer 31, the third insulating layer 32, and the external electrode 33 are formed.

基板２０は、例えば、シリコン等からなる基板上にトランジスタ等の半導体素子を含む電子回路を設けた能動素子ウエハにより構成される。
なお、本実施の形態では基板２０上に能動素子１０等を設けて半導体装置を構成しているが、基板２０に替えて、トランジスタ等の半導体素子を含む電子回路を設けていないシリコン等からなる基体を用いることで半導体装置を構成してもよい。 The substrate 20 is constituted by an active element wafer in which an electronic circuit including a semiconductor element such as a transistor is provided on a substrate made of, for example, silicon.
In the present embodiment, the semiconductor device is configured by providing the active element 10 and the like over the substrate 20, but instead of the substrate 20, it is made of silicon or the like not provided with an electronic circuit including a semiconductor element such as a transistor. You may comprise a semiconductor device by using a base | substrate.

能動素子１０の電子回路等を形成した面にはパッド電極１２が形成される。また、回路面を保護するパッシベーション膜１３がパッド電極１２を露出して形成される。
能動素子１０は、例えば、ダイアタッチフィルム１４によって基板２０上に搭載される。
ダイアタッチフィルム１４は、例えば能動素子１０のパッド電極１２とは反対側の面に設けられる。そして、このダイアタッチフルム１４によって能動素子１０と基板２０とが接着される。 A pad electrode 12 is formed on the surface of the active element 10 on which an electronic circuit or the like is formed. Further, a passivation film 13 for protecting the circuit surface is formed by exposing the pad electrode 12.
The active element 10 is mounted on the substrate 20 by a die attach film 14, for example.
The die attach film 14 is provided, for example, on the surface opposite to the pad electrode 12 of the active element 10. Then, the active element 10 and the substrate 20 are bonded by the die attach film 14.

基板２０上に形成される下地絶縁膜２１は、酸化シリコン等からなる。また、この下地絶縁膜２１上に、電極２２及び電極２２を露出してパッシベーション膜２３が形成される。   The base insulating film 21 formed on the substrate 20 is made of silicon oxide or the like. Further, the passivation film 23 is formed on the base insulating film 21 by exposing the electrode 22 and the electrode 22.

第１のシード層２４は、基板２０の電極２２及びパッシベーション膜２３上に、下部導電層２５が形成される箇所の下地に設けられる。
シード層は、電極上に電解めっきにより導電層を形成する下地層として、また、電極と導電層とを電気的に接続する機能を有する。第１のシード層２４は例えば、厚さ１６０ｎｍのＴｉ膜と厚さ６００ｎｍのＣｕ膜とから形成される。第１のシード層２４は、例えば、基板２０上に電極２２と接続する導電層を電解Ｃｕめっきによって形成するもので、電極２２と導電層とを電気的に接続する。
そして、下部導電層２５がこの第１のシード層２４上に電解めっき等により形成される。下部導電層２５は、例えばＣｕ等により形成される。
下部導電層２５は、基板２０に設けられた電極２２と電気的に接続され、電極位置を再配置するための配線やランド等が形成される。また、基板２０上に、例えば下部導電層２５によって、図示しないインダクタ等を形成することができる。 The first seed layer 24 is provided on the substrate 22 where the lower conductive layer 25 is formed on the electrode 22 and the passivation film 23 of the substrate 20.
The seed layer has a function of electrically connecting the electrode and the conductive layer as a base layer for forming the conductive layer on the electrode by electrolytic plating. The first seed layer 24 is formed of, for example, a 160 nm thick Ti film and a 600 nm thick Cu film. For example, the first seed layer 24 is formed by forming a conductive layer connected to the electrode 22 on the substrate 20 by electrolytic Cu plating, and electrically connects the electrode 22 and the conductive layer.
Then, the lower conductive layer 25 is formed on the first seed layer 24 by electrolytic plating or the like. The lower conductive layer 25 is made of, for example, Cu.
The lower conductive layer 25 is electrically connected to the electrode 22 provided on the substrate 20, and wiring, lands, and the like for rearranging the electrode positions are formed. Further, an inductor or the like (not shown) can be formed on the substrate 20 by using the lower conductive layer 25, for example.

第１の絶縁層２６は、基板２０上において、能動素子１０が搭載された部分とは異なる位置において、能動素子１０以下の厚さで形成される。また、基板２０上において、下部導電層２５等を被覆するようにパターニングされる。
第１の絶縁層２６には、下部導電層２５と第１の導電層２８とを接続する箇所に、導電層同士を導通させるための開口部３４が設けられる。また、能動素子１０を搭載する箇所に、能動素子１０の大きさに第１の絶縁層２６の厚さの半分を加えた面積の開口部３８が設けられる。
第１の絶縁層２６は、例えば、エポキシ樹脂、アクリル樹脂、ポリイミド樹脂、ＰＢＯ（ポリパラフェニレンベンゾビスオキサゾール）樹脂、ＢＣＢ（ベンゾシクロブテン）樹脂等により形成される。 The first insulating layer 26 is formed on the substrate 20 at a thickness different from that of the active element 10 at a position different from the portion where the active element 10 is mounted. Further, the substrate 20 is patterned so as to cover the lower conductive layer 25 and the like.
The first insulating layer 26 is provided with an opening 34 for conducting the conductive layers at a location where the lower conductive layer 25 and the first conductive layer 28 are connected. In addition, an opening 38 having an area obtained by adding half the thickness of the first insulating layer 26 to the size of the active element 10 is provided at a place where the active element 10 is mounted.
The first insulating layer 26 is formed of, for example, an epoxy resin, an acrylic resin, a polyimide resin, a PBO (polyparaphenylene benzobisoxazole) resin, a BCB (benzocyclobutene) resin, or the like.

また、第１の絶縁層２６は、搭載される能動素子１０以下の厚さで形成される。
例えば、能動素子１０の厚さを５０μｍとし、能動素子１０に設けるダイアタッチフィルム１４の厚さが１０μｍであると、基板２０上に搭載される能動素子２０全体の厚さｔ１は６０μｍとなる。この場合、基板２０上に形成される第１の絶縁層２６の厚さｔ２は、５０μｍ以下となる。これにより、第１の絶縁層２６上に形成される導電層が、能動素子１０の上面よりも低い位置に形成される。また、絶縁膜として機能させるためには、第１の絶縁層２６の厚さを少なくとも５μｍ以上とする必要がある。このため、第１の絶縁層２６の厚さｔ２は、５〜５０μｍの厚さとすることが望ましい。 Further, the first insulating layer 26 is formed with a thickness equal to or less than the active element 10 to be mounted.
For example, if the thickness of the active element 10 is 50 μm and the thickness of the die attach film 14 provided on the active element 10 is 10 μm, the total thickness t 1 of the active element 20 mounted on the substrate 20 is 60 μm. . In this case, the thickness t 2 of the first insulating layer 26 formed on the substrate 20 is 50 μm or less. Thereby, the conductive layer formed on the first insulating layer 26 is formed at a position lower than the upper surface of the active element 10. In order to function as an insulating film, the thickness of the first insulating layer 26 needs to be at least 5 μm or more. Therefore, the thickness t 2 of the first insulating layer 26, it is desirable that the thickness of 5 to 50 [mu] m.

上述のように、第１の絶縁層２６が、能動素子１０よりも薄く形成されることにより、能動素子１０の上面よりも低い位置において、第１の絶縁層２６上に第１の導電層により配線等を形成することができる。このため、半導体装置の厚さより厚くすることなく、多層配線を形成することができる。従って、半導体装置に形成する配線密度を向上させることができ、例えば第１の絶縁層２６上に配線によってインダクタ等の受動素子を形成することができる。   As described above, since the first insulating layer 26 is formed thinner than the active element 10, the first conductive layer is formed on the first insulating layer 26 at a position lower than the upper surface of the active element 10. Wiring and the like can be formed. For this reason, multilayer wiring can be formed without making it thicker than the thickness of the semiconductor device. Therefore, the wiring density formed in the semiconductor device can be improved. For example, a passive element such as an inductor can be formed on the first insulating layer 26 by wiring.

また、導電層同士を導通させるために形成される開口部３４は、接続不良を防ぐため、第１の絶縁層２６の厚さと、開口部３４の開口サイズとの比であるアスペクト比が１程度となるように形成される。   In addition, the opening 34 formed for conducting the conductive layers has an aspect ratio of about 1 that is a ratio between the thickness of the first insulating layer 26 and the opening size of the opening 34 in order to prevent poor connection. It is formed to become.

なお、上述の第１の絶縁層は、１層の絶縁層により形成するのみでなく、例えば、複数の絶縁層により形成することもできる。この場合には、複数の絶縁層による合計の厚さが、能動素子１０の厚さよりも薄く構成されていればよい。
第１の絶縁層を、絶縁層を複数層形成することにより、絶縁層上に形成できる導電層の数が増え、より高密度に配線等を形成することができる。
また、能動素子の厚さ以下に複数の絶縁層を形成することにより、半導体装置の厚さを増加することなく構成することができる。 The first insulating layer described above can be formed not only by a single insulating layer but also by a plurality of insulating layers, for example. In this case, the total thickness of the plurality of insulating layers may be configured to be thinner than the thickness of the active element 10.
By forming a plurality of insulating layers as the first insulating layer, the number of conductive layers that can be formed on the insulating layer is increased, and wiring and the like can be formed with higher density.
Further, by forming a plurality of insulating layers below the thickness of the active element, the semiconductor device can be configured without increasing the thickness.

第２のシード層２７は、第１の絶縁層２６上において第１の導電層２８が形成される箇所、及び、第１の絶縁層２６に形成される開口部３４内に下地層として設けられる。第２のシード層２７は、例えば、厚さ１６０ｎｍのＴｉ膜と厚さ６００ｎｍのＣｕ膜とからなる。第２のシード層は、第１の導電層を形成するためのめっき下地層である。そして、下部導電層２５と第１の導電層２８とを電気的に接続する。   The second seed layer 27 is provided as a base layer in the portion where the first conductive layer 28 is formed on the first insulating layer 26 and in the opening 34 formed in the first insulating layer 26. . The second seed layer 27 is made of, for example, a 160 nm thick Ti film and a 600 nm thick Cu film. The second seed layer is a plating base layer for forming the first conductive layer. Then, the lower conductive layer 25 and the first conductive layer 28 are electrically connected.

第１の導電層２８は、第２のシード層２７上に形成される。そして、第１の絶縁層２６の開口部３４の内部において、開口部３４を導電体で埋めることにより接続部２８ａが形成されて、いわゆるフィルドビアが形成される。第１の導電層２８は、例えばＣｕ等により形成される。そして、第１の導電層２８により、能動素子１０を搭載した部分以外において、電極位置を再配置するための配線やランド等が形成される。また、第１の絶縁層２６上に、例えば第１の導電層２８によって、図示しないインダクタ等を形成する。
また、第１の絶縁層内に形成された接続部２８ａを介して、下部導電層２５と第１の導電層２８とが電気的に接続される。 The first conductive layer 28 is formed on the second seed layer 27. And in the opening part 34 of the 1st insulating layer 26, the connection part 28a is formed by filling the opening part 34 with a conductor, and what is called a filled via is formed. The first conductive layer 28 is made of, for example, Cu. The first conductive layer 28 forms wirings, lands, and the like for rearranging electrode positions other than the portion where the active element 10 is mounted. Further, an inductor or the like (not shown) is formed on the first insulating layer 26 by using the first conductive layer 28, for example.
Further, the lower conductive layer 25 and the first conductive layer 28 are electrically connected through a connection portion 28a formed in the first insulating layer.

また、上述のように、能動素子１０は、第１の絶縁層２６に設けられた開口部３８において、ダイアタッチフィルム１４により下部導電層２５及びパッシベーション膜２３上に固定される。   Further, as described above, the active element 10 is fixed on the lower conductive layer 25 and the passivation film 23 by the die attach film 14 in the opening 38 provided in the first insulating layer 26.

第２の絶縁層２９は、基板２０上において、第１の導電層２８を被覆し、また、能動素子１０を被覆するようにパターニングされて形成される。
第２の絶縁層２９には、第１の導電層２８と第２の導電層３１とを接続するための開口部３５、及び、能動素子１０のパッド電極と第２の導電層３１とを接続するための開口部３６が設けられる。また、能動素子１０の上部及び側面を覆い、能動素子１０が封止される。
第２の絶縁層２９は、例えば、エポキシ樹脂、アクリル樹脂、ポリイミド樹脂、ＰＢＯ樹脂、ＢＣＢ樹脂等で形成される。 The second insulating layer 29 is formed on the substrate 20 by patterning so as to cover the first conductive layer 28 and the active element 10.
The second insulating layer 29 is connected to the opening 35 for connecting the first conductive layer 28 and the second conductive layer 31, and the pad electrode of the active element 10 and the second conductive layer 31. An opening 36 is provided for this purpose. Further, the active element 10 is sealed so as to cover an upper portion and a side surface of the active element 10.
The second insulating layer 29 is formed of, for example, an epoxy resin, an acrylic resin, a polyimide resin, a PBO resin, a BCB resin, or the like.

第３のシード層３０は、第２の絶縁層２９上において第２の導電層３１が形成される箇所および、第２の絶縁層２９に形成された開口部３５，３６の内部に下地層として設けられる。第３のシード層３０は、例えば、１６０ｎｍのＴｉ膜と６００ｎｍのＣｕ膜とからなる。第３のシード層３０は、第２の導電層を形成するためのめっき下地層である。そして、第２の導電層３１と第１の導電層２８及びパッド電極１２とを電気的に接続する。   The third seed layer 30 is formed as a base layer on the second insulating layer 29 where the second conductive layer 31 is formed and inside the openings 35 and 36 formed in the second insulating layer 29. Provided. The third seed layer 30 is made of, for example, a 160 nm Ti film and a 600 nm Cu film. The third seed layer 30 is a plating base layer for forming the second conductive layer. Then, the second conductive layer 31 is electrically connected to the first conductive layer 28 and the pad electrode 12.

第２の導電層３１は、第３のシード層３０上に形成される。そして、第２の絶縁層２９の開口部３５，３６の内部において、開口部３５，３６を導電体で埋めることにより接続部３１ａ，３１ｂが形成されて、いわゆるフィルドビアが形成される。また、この第２の導電層３１により、能動素子１０のパッド電極１２と第１の導電層２８が電気的に接続される。第２の導電層３１は、例えばＣｕ等により形成される。そして、この第２の導電層３１により、電極位置を再配置するための配線やランド等が形成される。また、第２の絶縁層２９上に、例えば第２の導電層３２によって、図示しないインダクタ等が形成される。
また、下部導電層２５上に接続部２８ａを介して第１の導電層２８が形成され、第１の導電層２８上に接続部３１ａを介して第２の導電層３１が形成されることにより、複数層の導電層が電気的に接続された、いわゆるスタックビアが形成される。 The second conductive layer 31 is formed on the third seed layer 30. Then, inside the openings 35 and 36 of the second insulating layer 29, the openings 35 and 36 are filled with a conductor to form connection parts 31a and 31b, so-called filled vias are formed. Further, the pad electrode 12 of the active element 10 and the first conductive layer 28 are electrically connected by the second conductive layer 31. The second conductive layer 31 is made of, for example, Cu. The second conductive layer 31 forms wiring, lands, and the like for rearranging electrode positions. Further, an inductor or the like (not shown) is formed on the second insulating layer 29 by, for example, the second conductive layer 32.
In addition, the first conductive layer 28 is formed on the lower conductive layer 25 via the connection portion 28a, and the second conductive layer 31 is formed on the first conductive layer 28 via the connection portion 31a. A so-called stack via in which a plurality of conductive layers are electrically connected is formed.

第３の絶縁層３２は、例えば、エポキシ樹脂、アクリル樹脂、ポリイミド樹脂、ＰＢＯ樹脂、ＢＣＢ樹脂等が、パターニングされてなる。
第３の絶縁層３２には、外部電極３３を形成する箇所に開口部３７が設けられる。
この第３の絶縁層３２は、最上層の導電層である第２の導電層３１を保護するとともに、半導体装置の外形を整えるため、上部が平坦化されて形成される。
そして、この開口部３７に、はんだボール、はんだ印刷、はんだめっき等による、例えばバンプ状の外部電極３３が形成される。外部電極３３は、半導体装置を外部機器に接続するため、外部機器の電極等の配置に合わせて設けられる。 The third insulating layer 32 is formed by patterning, for example, an epoxy resin, an acrylic resin, a polyimide resin, a PBO resin, a BCB resin, or the like.
The third insulating layer 32 is provided with an opening 37 where the external electrode 33 is formed.
The third insulating layer 32 is formed by flattening the upper portion in order to protect the second conductive layer 31 that is the uppermost conductive layer and to adjust the outer shape of the semiconductor device.
Then, for example, bump-shaped external electrodes 33 are formed in the openings 37 by solder balls, solder printing, solder plating, or the like. The external electrode 33 is provided in accordance with the arrangement of the electrodes of the external device in order to connect the semiconductor device to the external device.

上述の実施の形態では、能動素子１０が第２の絶縁膜２９で被覆され、さらに、絶縁層２９がパターニングされることにより、第１の導電層によってパッド電極１２が再配置される構成である。
このため、例えば、能動素子をフェイスアップで搭載した場合であっても、能動素子を搭載するため基板に掘り込みによる凹部を形成せずに、能動素子の厚さによる段差を解消することができる。従って、段差に起因する能動素子電極と下部導電層との接続による開口不良を防ぐことができる。
また、凹部を形成する必要がないため、能動素子を搭載する基板として、表面に電子回路及び電極が形成された能動素子ウエハを用いることができる。 In the above-described embodiment, the active element 10 is covered with the second insulating film 29, and further, the insulating layer 29 is patterned, so that the pad electrode 12 is rearranged by the first conductive layer. .
For this reason, for example, even when the active element is mounted face up, the step due to the thickness of the active element can be eliminated without forming a recess by digging in the substrate to mount the active element. . Accordingly, it is possible to prevent a defective opening due to the connection between the active element electrode and the lower conductive layer due to the step.
Further, since it is not necessary to form a recess, an active element wafer having an electronic circuit and electrodes formed on the surface can be used as a substrate on which an active element is mounted.

また、上述の実施の形態では、能動素子１０以下の厚さで形成される第１の絶縁層が形成される。また、第１の絶縁層に替えて、複数の絶縁層と導電層を、能動素子１０の厚さ以下で形成することができる。
このため、半導体装置全体の厚さを抑えたまま、複数の絶縁層と導電層を形成することができる。そして、配線層を増加させても半導体装置全体の厚さの増加を抑えることができる。
また、能動素子とは異なる部分に能動素子以下の厚さで複数の絶縁層と導電層を形成するため、能動素子の厚さが大きい場合においても、半導体装置における能動素子搭載部以外の厚さを、能動素子の厚さ以下で形成することができる。このため、半導体装置全体の厚さの増加を抑えて多層配線を形成することができる。従って、能動素子を厚くした場合においても、半導体装置全体の厚さを抑えることができ、例えば５０μｍ以上の厚さを有する能動素子を搭載した場合にも、厚さを抑えた半導体装置を構成することができる。 In the above-described embodiment, the first insulating layer formed with a thickness of the active element 10 or less is formed. Further, instead of the first insulating layer, a plurality of insulating layers and conductive layers can be formed with the thickness of the active element 10 or less.
For this reason, a plurality of insulating layers and conductive layers can be formed while suppressing the thickness of the entire semiconductor device. And even if it increases a wiring layer, the increase in the thickness of the whole semiconductor device can be suppressed.
In addition, since a plurality of insulating layers and conductive layers are formed with a thickness equal to or less than that of the active element in a portion different from the active element, even when the thickness of the active element is large, the thickness other than the active element mounting portion in the semiconductor device Can be formed below the thickness of the active element. For this reason, a multilayer wiring can be formed while suppressing an increase in the thickness of the entire semiconductor device. Therefore, even when the active element is thickened, the thickness of the entire semiconductor device can be suppressed. For example, even when an active element having a thickness of 50 μm or more is mounted, a semiconductor device with a reduced thickness is configured. be able to.

次に、本発明の実施の形態に係わる半導体装置の製造方法の一例について説明する。
まず、図２（ａ）に示すように、基板２０は例えば能動素子ウエハより成り、図示しないトランジスタ等の能動素子を含む電子回路を形成する。そして、この電子回路に接続する電極２２と、電極２２を露出して電子回路を被覆する下地絶縁膜２１及びパッシベーション膜２３を形成する。
基板２０には、電子回路（図示省略）、電極２２及び下地絶縁膜２１が形成され、例えばその周囲に後の工程で固片化する大きさに合わせてスクライブライン３９が形成される。パッシベーション膜２３は、電極２２及びスクライブライン３９上を除いて形成される。 Next, an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described.
First, as shown in FIG. 2A, the substrate 20 is made of, for example, an active element wafer to form an electronic circuit including an active element such as a transistor (not shown). Then, an electrode 22 connected to the electronic circuit, and a base insulating film 21 and a passivation film 23 that expose the electrode 22 and cover the electronic circuit are formed.
An electronic circuit (not shown), an electrode 22 and a base insulating film 21 are formed on the substrate 20. For example, a scribe line 39 is formed around the substrate 20 in accordance with a size to be solidified in a later process. The passivation film 23 is formed except on the electrode 22 and the scribe line 39.

次に、図２（ｂ）に示すように、基板２０上に電極２２と接続する導電層を電解Ｃｕめっきによって形成するため、また、電極２２と導電層とを電気的に接続するため、第１のシード層２４を形成する。
第１のシード層２４は、例えば、スパッタリング法により形成され、例えば、Ｔｉを１６０ｎｍ成膜した後、Ｔｉ膜上にＣｕを６００ｎｍ成膜することにより形成する。 Next, as shown in FIG. 2B, in order to form a conductive layer connected to the electrode 22 on the substrate 20 by electrolytic Cu plating, and to electrically connect the electrode 22 and the conductive layer, 1 seed layer 24 is formed.
The first seed layer 24 is formed by, for example, a sputtering method. For example, the first seed layer 24 is formed by depositing Ti with a thickness of 160 nm and then depositing Cu with a thickness of 600 nm on the Ti film.

次に、第１のシード層２４上全面に、スピンコート、真空ラミネート等によりレジスト層４０を形成する。そして、フォトリソグラフィー工程により、レジスト層４０に露光、現像処理を行い、図２（ｃ）に示すように、後の工程で下部導電層２５を形成する部分のレジスト層４０を除去する。
そして、図２（ｄ）に示すように、レジスト層４０が除去された部分に、例えば、電解めっきによりＣｕ層を成長させ、下部導電層２５を形成する。
このときの電解めっきは、例えば、電流密度を１．５Ａ／ｄｍ２で行い、下部導電層２５の導電層厚を７μｍに形成する。 Next, a resist layer 40 is formed on the entire surface of the first seed layer 24 by spin coating, vacuum lamination, or the like. Then, the resist layer 40 is exposed and developed by a photolithography process, and as shown in FIG. 2C, a portion of the resist layer 40 where the lower conductive layer 25 is to be formed is removed in a subsequent process.
Then, as shown in FIG. 2D, the lower conductive layer 25 is formed by growing a Cu layer, for example, by electrolytic plating in the portion where the resist layer 40 has been removed.
The electrolytic plating at this time is performed, for example, at a current density of 1.5 A / dm 2 and the conductive layer thickness of the lower conductive layer 25 is formed to 7 μm.

次に、図３（ｅ）に示すように、溶剤等によりレジスト層４０を除去した後、不要な第１のシード層２４を除去する。第１のシード層２４の除去は、下部導電層２５をマスクとしてウェットエッチング等により行う。まず、上層のＣｕ層を除去し、この後下層のＴｉ層を除去する。   Next, as shown in FIG. 3E, after removing the resist layer 40 with a solvent or the like, the unnecessary first seed layer 24 is removed. The removal of the first seed layer 24 is performed by wet etching or the like using the lower conductive layer 25 as a mask. First, the upper Cu layer is removed, and then the lower Ti layer is removed.

次に、図３（ｆ）に示すように、基板２０の全面に第１の絶縁層２６を塗布する。第１の絶縁層２６は、例えば、スピンコート法、フィルムラミネート法、印刷法、ディスペンス法等の方法を用いて、エポキシ樹脂、アクリル樹脂、ポリイミド樹脂、ＰＢＯ樹脂、ＢＣＢ樹脂等の絶縁膜により形成する。
このとき、第１の絶縁層２６の厚さは、図１において説明したように、後の工程で搭載する能動素子１０の厚さ以下に形成する。例えば、能動素子１０の厚さを５０μｍ、能動素子１０の裏面に設けるダイアタッチフィルムを１０μｍとした場合には、下部導電層２５上の第１の絶縁層２６の厚さは５０μｍ以下に形成する。
また、第１の絶縁層２６が、絶縁膜として機能するためには少なくとも５μｍ以上の厚さを必要とする。このため、第１の絶縁層２６の厚さは、５μｍ以上に形成する。 Next, as shown in FIG. 3F, a first insulating layer 26 is applied to the entire surface of the substrate 20. The first insulating layer 26 is formed of an insulating film such as an epoxy resin, an acrylic resin, a polyimide resin, a PBO resin, or a BCB resin by using a method such as a spin coating method, a film laminating method, a printing method, or a dispensing method. To do.
At this time, as described in FIG. 1, the thickness of the first insulating layer 26 is formed to be equal to or less than the thickness of the active element 10 to be mounted in a later process. For example, when the thickness of the active element 10 is 50 μm and the die attach film provided on the back surface of the active element 10 is 10 μm, the thickness of the first insulating layer 26 on the lower conductive layer 25 is 50 μm or less. .
Further, in order for the first insulating layer 26 to function as an insulating film, a thickness of at least 5 μm or more is required. Therefore, the thickness of the first insulating layer 26 is 5 μm or more.

次に、図３（ｇ）に示すように、能動素子１０を搭載するための開口部３８、接続部２８ａ（図１参照）を形成するための開口部３４、及び、スクライブライン３９の開口部を形成するように第１の絶縁層２６をパターニングする。
開口部３８は、例えば、搭載する能動素子１０の大きさに第１の絶縁層２６の厚さの半分を加えた面積とする。また、開口部３４は、第１の絶縁層２６の厚さと、開口部３４の開口サイズとの比であるアスペクト比が１程度となるように形成する。 Next, as shown in FIG. 3G, the opening 38 for mounting the active element 10, the opening 34 for forming the connection 28a (see FIG. 1), and the opening of the scribe line 39. The first insulating layer 26 is patterned so as to form.
The opening 38 has, for example, an area obtained by adding half the thickness of the first insulating layer 26 to the size of the active element 10 to be mounted. The opening 34 is formed so that the aspect ratio, which is the ratio between the thickness of the first insulating layer 26 and the opening size of the opening 34, is about 1.

次に、図４（ｈ）に示すように、下部導電層２５上に電解Ｃｕめっきにより第１の導電層を形成するため、また、下部導電層２５と第１の導電層との接続のため、第２のシード層２７を形成する。
第２のシード層２７は、例えば、スパッタリング法により形成する。まず、Ｔｉを１６０ｎｍ成膜した後、Ｔｉ膜上にＣｕを６００ｎｍ成膜することにより形成する。 Next, as shown in FIG. 4H, the first conductive layer is formed on the lower conductive layer 25 by electrolytic Cu plating, and the connection between the lower conductive layer 25 and the first conductive layer is performed. Then, the second seed layer 27 is formed.
The second seed layer 27 is formed by, for example, a sputtering method. First, Ti is formed to a thickness of 160 nm, and then Cu is formed to a thickness of 600 nm on the Ti film.

次に、第２のシード層２７上の全面に、スピンコート、真空ラミネート等によりレジスト層４１を形成する。そして、フォトリソグラフィー工程により、レジスト層４１に露光、現像処理を行い、図４（ｉ）に示すように、後の工程で接続部２８ａ及び第１の導電層２８を形成する部分のレジスト層４１を除去する。   Next, a resist layer 41 is formed on the entire surface of the second seed layer 27 by spin coating, vacuum lamination, or the like. Then, the resist layer 41 is exposed and developed by a photolithography process, and as shown in FIG. 4I, the resist layer 41 in a portion where the connection portion 28a and the first conductive layer 28 are formed in the subsequent process. Remove.

次に、図４（ｊ）に示すように、レジスト層４１が除去された部分に、例えば、電解めっきによりＣｕ層を成長させ、接続部２８ａと第１の導電層２８とを形成する。
このときの電解めっきは、例えば、電流密度を１．５Ａ／ｄｍ２で行い、第１の導電層２８の導電層厚を７μｍに形成する。 Next, as shown in FIG. 4J, a Cu layer is grown on the portion from which the resist layer 41 has been removed by, for example, electrolytic plating to form the connection portion 28a and the first conductive layer 28.
The electrolytic plating at this time is performed, for example, at a current density of 1.5 A / dm 2 , and the conductive layer thickness of the first conductive layer 28 is formed to 7 μm.

次に、図５（ｋ）に示すように、溶剤等によりレジスト層４１を剥離した後、不要な第２のシード層２７を除去する。第２のシード層２７の除去は、第１の導電層２８をマスクにしてウェットエッチング等により行い、まず上層のＣｕ層を除去し、この後下層のＴｉ層を除去する。   Next, as shown in FIG. 5K, after the resist layer 41 is peeled off with a solvent or the like, the unnecessary second seed layer 27 is removed. The second seed layer 27 is removed by wet etching or the like using the first conductive layer 28 as a mask. First, the upper Cu layer is removed, and then the lower Ti layer is removed.

次に、図５（ｌ）に示すように、薄固片化した能動素子１０をフェイスアップで基板２０上に搭載する。能動素子１０の薄固片化は、例えば、トランジスタ等の能動素子を含む電子回路を形成したウエハの裏面を研削し、ダイアタッチフィルム１４をラミネートした後、ダイシングすることにより行う。そして、第１の絶縁層２６の開口部３８において、パッシベーション膜２３及び下部導電層２５上に、ダイアタッチフィルム１４を裏面に備えた能動素子１０を搭載する。能動素子１０は、例えば、加重２．５Ｎ、温度２３０℃、押し込み量０．３ｍｍの条件で搭載する。   Next, as shown in FIG. 5L, the thinned active element 10 is mounted on the substrate 20 face up. The thinning of the active element 10 is performed, for example, by grinding the back surface of the wafer on which the electronic circuit including the active element such as a transistor is formed, laminating the die attach film 14, and then dicing. Then, the active element 10 having the die attach film 14 on the back surface is mounted on the passivation film 23 and the lower conductive layer 25 in the opening 38 of the first insulating layer 26. For example, the active element 10 is mounted under the conditions of a load of 2.5 N, a temperature of 230 ° C., and a push-in amount of 0.3 mm.

その後、図５（ｍ）に示すように、能動素子１０を搭載した基板２０の全面に、第２の絶縁層２９を塗布する。第２の絶縁層２９は、例えば、スピンコート法、フィルムラミネート法、印刷法、ディスペンス法等の方法を用いて、エポキシ樹脂、アクリル樹脂、ポリイミド樹脂、ＰＢＯ樹脂、ＢＣＢ樹脂等の絶縁膜により形成する。   Thereafter, as shown in FIG. 5M, a second insulating layer 29 is applied to the entire surface of the substrate 20 on which the active element 10 is mounted. The second insulating layer 29 is formed of an insulating film such as an epoxy resin, an acrylic resin, a polyimide resin, a PBO resin, or a BCB resin using a method such as a spin coating method, a film laminating method, a printing method, or a dispensing method. To do.

次に、図６（ｎ）に示すように、第１の導電層２８と第２の導電層３１とを接合する接続部３１ａ（図１参照）を形成する開口部３５、能動素子１０のパッド電極１２と第２の導電層３１とを接合する接続部３１ｂを形成する開口部３６、及び、スクライブライン３９の開口部を形成するように、第２の絶縁層２９をパターニングする。
開口部３５，３６は、第２の絶縁層２９の厚さと、開口部３５，３６の開口サイズとの比であるアスペクト比が１程度となるように形成する。 Next, as shown in FIG. 6 (n), an opening 35 for forming a connecting portion 31a (see FIG. 1) for joining the first conductive layer 28 and the second conductive layer 31, and a pad of the active element 10 The second insulating layer 29 is patterned so as to form the opening 36 for forming the connection portion 31 b for joining the electrode 12 and the second conductive layer 31 and the opening for the scribe line 39.
The openings 35 and 36 are formed so that the aspect ratio, which is the ratio between the thickness of the second insulating layer 29 and the opening size of the openings 35 and 36, is about 1.

図６（ｏ）に示すように、第１の導電層２８上に電解Ｃｕめっきにより第２の導電層３１を形成するため、また、第１の導電層２８及びパッド電極１２と、第２の導電層３１との電気的な接続のため、第３のシード層３０を形成する。
第３のシード層３０は、例えば、スパッタリング法により形成し、まず、Ｔｉを１６０ｎｍ成膜した後、Ｔｉ膜上にＣｕを６００ｎｍ成膜することにより形成する。 As shown in FIG. 6 (o), the second conductive layer 31 is formed on the first conductive layer 28 by electrolytic Cu plating, and the first conductive layer 28 and the pad electrode 12, A third seed layer 30 is formed for electrical connection with the conductive layer 31.
The third seed layer 30 is formed by, for example, a sputtering method. First, Ti is formed to a thickness of 160 nm, and then Cu is formed to a thickness of 600 nm on the Ti film.

次に、第３のシード層３０上全面に、スピンコート、真空ラミネート等によりレジスト層４２を形成する。そして、フォトリソグラフィー工程により、レジスト層４２に露光、現像処理を行い、図６（ｐ）に示すように、後の工程で導電層及び接続部を形成する部分のレジスト層４２を除去する。   Next, a resist layer 42 is formed on the entire surface of the third seed layer 30 by spin coating, vacuum lamination, or the like. Then, the resist layer 42 is exposed to light and developed by a photolithography process, and as shown in FIG. 6 (p), the resist layer 42 that forms a conductive layer and a connection portion is removed in a subsequent process.

次に、図７（ｑ）に示すように、レジスト層４２が除去された部分に、例えば、電解めっきによりＣｕ層を成長させ、接続部３１ａ，３１ｂと第２の導電層３１とを形成する。
このときの電解めっきは、例えば、電流密度を１．５Ａ／ｄｍ２で行い、第２の導電層３１の導電層厚を７μｍに形成する。 Next, as shown in FIG. 7 (q), a Cu layer is grown on the portion from which the resist layer 42 has been removed, for example, by electrolytic plating, and the connection portions 31a and 31b and the second conductive layer 31 are formed. .
The electrolytic plating at this time is performed, for example, at a current density of 1.5 A / dm 2 , and the conductive layer thickness of the second conductive layer 31 is formed to 7 μm.

次に、図７（ｒ）に示すように、溶剤等によりレジスト層４２を剥離した後、不要な第３のシード層３０を除去する。第３のシード層３０の除去は、第２の導電層３１をマスクにしてウェットエッチング等により行い、まず上層のＣｕ層を除去し、この後下層のＴｉ層を除去する。   Next, as shown in FIG. 7R, after the resist layer 42 is peeled off with a solvent or the like, the unnecessary third seed layer 30 is removed. The third seed layer 30 is removed by wet etching or the like using the second conductive layer 31 as a mask. First, the upper Cu layer is removed, and then the lower Ti layer is removed.

次に、図７（ｓ）に示すように、第２の導電層３１を形成した基板２０の全面に、第３の絶縁層３２を塗布する。第３の絶縁層３２は、例えば、スピンコート法、フィルムラミネート法、印刷法、ディスペンス法等の方法を用いて、エポキシ樹脂、アクリル樹脂、ポリイミド樹脂、ＰＢＯ樹脂、ＢＣＢ樹脂等の絶縁膜により形成する。   Next, as shown in FIG. 7S, a third insulating layer 32 is applied to the entire surface of the substrate 20 on which the second conductive layer 31 is formed. The third insulating layer 32 is formed of an insulating film such as an epoxy resin, an acrylic resin, a polyimide resin, a PBO resin, or a BCB resin by using a method such as a spin coating method, a film laminating method, a printing method, or a dispensing method. To do.

次に、図８（ｔ）に示すように、第２の導電層３１と外部電極３３とを接続するための開口部３７、及び、スクライブライン３９に開口部を形成するように第３の絶縁層３２をパターニングする。   Next, as shown in FIG. 8 (t), the third insulating layer is formed so as to form openings 37 for connecting the second conductive layer 31 and the external electrodes 33 and scribe lines 39. Layer 32 is patterned.

次に、図８（ｕ）に示すように、開口部３７にバンプ状等の外部電極３３を形成する。外部電極３３は、はんだボールの搭載、はんだ印刷、はんだめっきによって行う。例えば、外部電極にはんだボールを搭載する場合には、外部電極３３を形成する箇所に、フラックスを塗布した後にはんだボールを付着させ、リフローで溶融接合を行う。そして、はんだボールの接合後、フラックスを洗浄する。   Next, as shown in FIG. 8 (u), bump-shaped external electrodes 33 are formed in the openings 37. The external electrode 33 is performed by mounting solder balls, solder printing, or solder plating. For example, when a solder ball is mounted on the external electrode, the solder ball is attached to the portion where the external electrode 33 is formed, after the flux is applied, and fusion bonding is performed by reflow. Then, after joining the solder balls, the flux is washed.

次に、基板２０の薄固片化を行うことにより、図８（ｖ）示す半導体装置を形成することができる。
薄固片化は、例えば、基板２０に形成したスクライブライン３９において、基板２０の最終厚さよりも深く、例えば最終厚さからさらに７０μｍ程度深くまでハーフカットを行う。そして、バックグラインドにより基板２０の裏面を研削することにより薄固片化を行うことができる。
また、例えば、基板２０の裏面を完成厚さまでバックグラインドにより研削し、スクライブライン３９においてフルカットダイシングを行うことで、薄固片化を行うことができる。
以上の工程により、本実施の形態の半導体装置を製造することができる。 Next, the semiconductor device shown in FIG. 8V can be formed by thinning the substrate 20 into thin pieces.
Thinning is performed by, for example, half-cutting the scribe line 39 formed on the substrate 20 deeper than the final thickness of the substrate 20, for example, about 70 μm from the final thickness. Then, thinning can be performed by grinding the back surface of the substrate 20 by back grinding.
Further, for example, by grinding the back surface of the substrate 20 to the finished thickness by back grinding and performing full-cut dicing on the scribe line 39, thinning can be performed.
Through the above steps, the semiconductor device of this embodiment can be manufactured.

次に、本発明の他の実施形態に係わる半導体装置の断面図を図９に示す。
図９は、図１において示した半導体装置の第１の絶縁層２６を、能動素子の厚さよりも薄い第４の絶縁層５２及び第５の絶縁層５３による複数の絶縁層によって構成した場合の半導体装置の断面図である。
また、図９に示す半導体装置では、基板５８上に２つの能動素子１０，２０Ａがフェイスアップで搭載され、さらに、この能動素子１０，２０Ａと図示しない配線によって接続される受動素子として、キャパシタ５７及びインダクタ４８，４９，５０，５１が同一の基板５８上に形成されている。
なお、図１に示した半導体装置と同様の構成については、図面に同一の符号を付して説明を省略する。また、図９において、導体層下部に形成されるシード層は図示を省略する。 Next, FIG. 9 shows a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
9 shows a case where the first insulating layer 26 of the semiconductor device shown in FIG. 1 is constituted by a plurality of insulating layers including a fourth insulating layer 52 and a fifth insulating layer 53 which are thinner than the thickness of the active element. It is sectional drawing of a semiconductor device.
In the semiconductor device shown in FIG. 9, two active elements 10 and 20A are mounted face-up on a substrate 58, and a capacitor 57 is used as a passive element connected to the active elements 10 and 20A by wiring (not shown). Inductors 48, 49, 50, 51 are formed on the same substrate 58.
Note that the same components as those of the semiconductor device illustrated in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. In FIG. 9, the illustration of the seed layer formed under the conductor layer is omitted.

図９に示す半導体装置は、能動素子１０，２０Ａを被覆する第２の絶縁層２９の下部において、能動素子１０，２０Ａが搭載される部分と異なる位置に形成される第４の絶縁層５２と第５の絶縁層５３を備える。また、第４の絶縁層５２上には、第３の導電層５４が形成され、第５の絶縁層５３上には、第４の導電層５５が形成される。
また、基板５８上の全面に下部絶縁層５６が形成される。
そして、下部絶縁層５６上には、下部導電層４３、誘電体層４４、誘電体層４４の保護層４５、及び、下部導電層２５の引き出し電極４６と上部電極４７とが順次積層されることにより、キャパシタ５７が形成される。このキャパシタ５７は、例えば、基板５８上において、下部絶縁層５６上の能動素子１０，２０Ａが搭載される部分と異なる位置に形成される。 The semiconductor device shown in FIG. 9 includes a fourth insulating layer 52 formed below the second insulating layer 29 covering the active elements 10 and 20A at a position different from the portion where the active elements 10 and 20A are mounted. A fifth insulating layer 53 is provided. A third conductive layer 54 is formed on the fourth insulating layer 52, and a fourth conductive layer 55 is formed on the fifth insulating layer 53.
A lower insulating layer 56 is formed on the entire surface of the substrate 58.
On the lower insulating layer 56, a lower conductive layer 43, a dielectric layer 44, a protective layer 45 for the dielectric layer 44, and an extraction electrode 46 and an upper electrode 47 for the lower conductive layer 25 are sequentially stacked. Thus, the capacitor 57 is formed. For example, the capacitor 57 is formed on the substrate 58 at a position different from the portion on the lower insulating layer 56 where the active elements 10 and 20A are mounted.

また、下部絶縁層５６上に、導電層のパターニングにより第１のインダクタ４８が形成される。第１のインダクタ４８は、例えば、下部導電層２５の引き出し電極４６と同一層上であり、能動素子１０，２０Ａとキャパシタ５７との間に形成され、第４の絶縁層５２によって被覆埋設される。
さらに、第４の絶縁層５２上に、導電層のパターニングにより第２のインダクタ４９が形成される。第２のインダクタ４９は、第１のインダクタ４８の上方に形成され、第５の絶縁層５３によって被覆埋設される。
同様に、導電層をパターニングすることにより、第５の絶縁層５３上に第３のインダクタ５０が形成され、第２の絶縁層２９によって被覆埋設される。また、第２の絶縁層２９上に第４のインダクタ５１が形成され、第３の絶縁層３２によって被覆埋設される。そして、第３のインダクタ５０及び第４のインダクタ５１は、第１のインダクタ４８及び第２のインダクタ４９の上方に形成される。 A first inductor 48 is formed on the lower insulating layer 56 by patterning the conductive layer. The first inductor 48 is, for example, on the same layer as the extraction electrode 46 of the lower conductive layer 25, is formed between the active elements 10, 20 </ b> A, and the capacitor 57, and is embedded by the fourth insulating layer 52. .
Further, the second inductor 49 is formed on the fourth insulating layer 52 by patterning the conductive layer. The second inductor 49 is formed above the first inductor 48 and is embedded in the fifth insulating layer 53.
Similarly, the third inductor 50 is formed on the fifth insulating layer 53 by patterning the conductive layer, and is covered and buried by the second insulating layer 29. In addition, a fourth inductor 51 is formed on the second insulating layer 29, and is embedded in the third insulating layer 32. The third inductor 50 and the fourth inductor 51 are formed above the first inductor 48 and the second inductor 49.

下部電極４３、第２の導電層３１、第３の導電層５４及び第４の導電層５５によって、電極位置を再配置するための配線やランド等が形成され、キャパシタ５７、インダクタ４８，４９，５０，５１、及び、能動素子１０の電極や、能動素子２０Ａ上の下部導電層２５に電気的に接続される。   The lower electrode 43, the second conductive layer 31, the third conductive layer 54, and the fourth conductive layer 55 form wirings, lands, and the like for rearranging the electrode positions, and capacitors 57, inductors 48, 49, 50, 51 and the electrodes of the active element 10 and the lower conductive layer 25 on the active element 20A are electrically connected.

第４の絶縁層５２及び第５の絶縁層５３は、基板５８上において、能動素子１０及び２０Ａが搭載された部分とは異なる位置に形成される。また、第４の絶縁層５２及び第５の絶縁層５３は、基板５８上に搭載された能動素子１０と能動素子２０Ａと合計の厚さ以下で形成される。また、第４の絶縁層５２は、基板５８上においてキャパシタ５７及び第１のインダクタ４８を被覆するよう形成される。第５の絶縁層５３は、第４の絶縁層５２上において第３の導電層５４等を被覆するように形成される。   The fourth insulating layer 52 and the fifth insulating layer 53 are formed on the substrate 58 at a position different from the portion where the active elements 10 and 20A are mounted. In addition, the fourth insulating layer 52 and the fifth insulating layer 53 are formed with a total thickness or less of the active element 10 and the active element 20A mounted on the substrate 58. The fourth insulating layer 52 is formed on the substrate 58 so as to cover the capacitor 57 and the first inductor 48. The fifth insulating layer 53 is formed on the fourth insulating layer 52 so as to cover the third conductive layer 54 and the like.

上述のように、能動素子を積層して搭載する場合には、積層した能動素子の合計の厚さ以下となるように、第４の絶縁層５２及び第５の絶縁層５３を成膜する。
これにより、半導体装置全体の厚さ増加させずに、複数の絶縁層と導電層が形成され、配線密度を向上させた半導体装置が構成される。 As described above, when the active elements are stacked and mounted, the fourth insulating layer 52 and the fifth insulating layer 53 are formed so as to be equal to or less than the total thickness of the stacked active elements.
Thereby, a plurality of insulating layers and conductive layers are formed without increasing the thickness of the entire semiconductor device, and a semiconductor device with improved wiring density is configured.

キャパシタ５７は、例えば、酸化タンタルＴａ２Ｏ５、ＢＳＴ（チタン酸バリウムストロンチウムＢａｘＳｒ１−ｘＴｉＯ３）、ＰＺＴ（チタン酸ジルコン酸鉛ＰｂＺｒｘＴｉ１−ｘＯ３）、チタン酸バリウムＢａＴｉＯ３、窒化ケイ素ＳｉＮ、ＰＩ（ポリイミド）、又は酸化ケイ素ＳｉＯ２等の誘電体層４４により構成される。これらの材料はキャパシタ５７の容量と耐圧を考慮して選択される。 The capacitor 57 includes, for example, tantalum oxide Ta 2 O 5 , BST (barium strontium titanate Ba x Sr 1-x TiO 3 ), PZT (lead zirconate titanate PbZr x Ti 1-x O 3 ), barium titanate BaTiO 3. 3 , and a dielectric layer 44 such as silicon nitride SiN, PI (polyimide), or silicon oxide SiO 2 . These materials are selected in consideration of the capacity and breakdown voltage of the capacitor 57.

第１から第４のインダクタ４８，４９，５０，５１は、それぞれ配線によって形成される。そして、第１のインダクタ４８は、保護層４５上に形成され、上部電極４７の引き出し電極４６を形成する工程や、下部電極４３を形成する工程と共通の工程によって形成することができる。また、第４の絶縁層５２上に形成される第２のインダクタ４９は、第３の導電層５４を形成する工程と共通の工程によって形成することができる。第５の絶縁層５３上に形成する第３のインダクタ５０は、第４の導電層５５を形成する工程と共通の工程によって形成することができる。第２の絶縁層２９上に形成される第４のインダクタ５１は、第２の導電層３１を形成する工程と共通の工程によって形成することができる。   The first to fourth inductors 48, 49, 50, 51 are each formed by wiring. The first inductor 48 is formed on the protective layer 45 and can be formed by a process common to the process of forming the lead electrode 46 of the upper electrode 47 and the process of forming the lower electrode 43. Further, the second inductor 49 formed on the fourth insulating layer 52 can be formed by a process common to the process of forming the third conductive layer 54. The third inductor 50 formed on the fifth insulating layer 53 can be formed by a process common to the process of forming the fourth conductive layer 55. The fourth inductor 51 formed on the second insulating layer 29 can be formed by a process common to the process of forming the second conductive layer 31.

上述のように、基板５８上に、能動素子１０，２０Ａと共にキャパシタ５７とインダクタ４８，４９，５０，５１とを形成し、それぞれを接続することにより、キャパシタ及びインダクタによるバンドパスフィルタを形成することができる。これにより、必要な周波数成分のみを通過させ、不要な周波数成分を阻止することができる。   As described above, the capacitor 57 and the inductors 48, 49, 50, and 51 are formed on the substrate 58 together with the active elements 10 and 20A, and the bandpass filter including the capacitor and the inductor is formed by connecting each of them. Can do. Thereby, only a necessary frequency component can be passed and an unnecessary frequency component can be blocked.

上述の構成により、第３の導電層５４及び第４の導電層５５を形成した場合でも、半導体装置全体の厚さは、能動素子１０，２０Ａの厚さによる影響を受けるが、第４の絶縁層５２、第５の絶縁層５３、第３の導電層５４及び第４の導電層５５の厚さによる影響を受けない。
このため、導体層を複数設け、半導体装置の配線密度を向上させた場合においても、半導体装置全体の厚さに影響を与えない。
また、上述のように、絶縁層を複数層形成することにより、絶縁層上に形成できる導電層の数が増え、また、搭載可能なインダクタやキャパシタ等の受動素子の数を容易に増加させることができる。このため、半導体装置においてより高密度に配線等を形成することができ、複数のインダクタ等の受動素子を有する半導体装置において小型化を図ることができる。 Even when the third conductive layer 54 and the fourth conductive layer 55 are formed by the above-described configuration, the thickness of the entire semiconductor device is affected by the thickness of the active elements 10 and 20A. The thickness of the layer 52, the fifth insulating layer 53, the third conductive layer 54, and the fourth conductive layer 55 is not affected.
For this reason, even when a plurality of conductor layers are provided and the wiring density of the semiconductor device is improved, the thickness of the entire semiconductor device is not affected.
In addition, as described above, by forming a plurality of insulating layers, the number of conductive layers that can be formed on the insulating layer increases, and the number of passive elements such as inductors and capacitors that can be mounted can be easily increased. Can do. Therefore, wirings and the like can be formed with higher density in the semiconductor device, and the semiconductor device having a plurality of passive elements such as inductors can be reduced in size.

本発明は、上述の構成に限定されるものではなく、各層の材料構成や、能動素子及び受動素子の個数、材料構成等において、本発明の要旨を逸脱しない範囲でその他様々な構成が取り得る。   The present invention is not limited to the above-described configuration, and various other configurations can be employed in the material configuration of each layer, the number of active elements and passive elements, the material configuration, and the like without departing from the spirit of the present invention. .

本発明の一実施の形態による半導体装置の断面図である。It is sectional drawing of the semiconductor device by one embodiment of this invention. （ａ）〜（ｄ）は本発明の一実施の形態による半導体装置の製造工程図である。(A)-(d) is a manufacturing-process figure of the semiconductor device by one embodiment of this invention. （ｅ）〜（ｇ）は本発明の一実施の形態による半導体装置の製造工程図である。(E)-(g) is a manufacturing-process figure of the semiconductor device by one embodiment of this invention. （ｈ）〜（ｊ）は本発明の一実施の形態による半導体装置の製造工程図である。(H)-(j) is a manufacturing-process figure of the semiconductor device by one Embodiment of this invention. （ｋ）〜（ｍ）は本発明の一実施の形態による半導体装置の製造工程図である。(K)-(m) is a manufacturing-process figure of the semiconductor device by one embodiment of this invention. （ｎ）〜（ｐ）は本発明の一実施の形態による半導体装置の製造工程図である。(N)-(p) is a manufacturing-process figure of the semiconductor device by one embodiment of this invention. （ｑ）〜（ｓ）は本発明の一実施の形態による半導体装置の製造工程図である。(Q)-(s) is a manufacturing-process figure of the semiconductor device by one embodiment of this invention. （ｔ）〜（ｖ）は本発明の一実施の形態による半導体装置の製造工程図である。(T)-(v) is a manufacturing-process figure of the semiconductor device by one embodiment of this invention. 本発明の他の実施の形態による半導体装置の断面図である。It is sectional drawing of the semiconductor device by other embodiment of this invention. 従来の半導体装置の断面図である。It is sectional drawing of the conventional semiconductor device.

符号の説明Explanation of symbols

１０，２０Ａ，１３０Ａ，１３０Ｂ 能動素子、１２ パッド電極、１３，２３ パッシベーション膜、２０ 基板、５８，１００ 基板、２１ 下地絶縁膜、２２ 電極、２４ 第１のシード層、２５，４３，１１１ 下部導電層、２６ 第１の絶縁層、２７ 第２のシード層、２８，１２１ 第１の導電層、２８ａ，３１ａ，３１ｂ，１１６，１２６，１４３ 接続部、２９ 第２の絶縁層、３０ 第３のシード層、３１ 第２の導電層、３２，１４０ 第３の絶縁層、３３，１４５ 外部電極、３４，３５，３６，３７，３８ 開口部、３９ スクライブライン、４０，４１，４２ レジスト層、４３ 下部電極、４４ 誘電体層、４５ 保護層、４６ 引き出し電極、４７ 上部電極、４８ 第１のインダクタ、４９ 第２のインダクタ、５０ 第３のインダクタ、５１ 第４のインダクタ、５２ 第４の絶縁層、５３ 第５の絶縁層、５４ 第３の導電層、５５ 第４の導電層、５６ 下部絶縁層、５７ キャパシタ、１２５，１２７ 導電層   10, 20A, 130A, 130B active element, 12 pad electrode, 13, 23 passivation film, 20 substrate, 58, 100 substrate, 21 base insulating film, 22 electrode, 24 first seed layer, 25, 43, 111 lower conductive 26, first insulating layer, 27 second seed layer, 28, 121 first conductive layer, 28a, 31a, 31b, 116, 126, 143 connection portion, 29 second insulating layer, 30 third Seed layer, 31 Second conductive layer, 32, 140 Third insulating layer, 33, 145 External electrode, 34, 35, 36, 37, 38 Opening, 39 Scribe line, 40, 41, 42 Resist layer, 43 Lower electrode, 44 dielectric layer, 45 protective layer, 46 lead electrode, 47 upper electrode, 48 first inductor, 49 second inductor, 50 third inductor Dactor, 51 4th inductor, 52 4th insulating layer, 53 5th insulating layer, 54 3rd conductive layer, 55 4th conductive layer, 56 lower insulating layer, 57 capacitor, 125, 127 conductive layer

Claims (8)

基板と、
前記基板に搭載される能動素子と、
前記能動素子が搭載された部分とは異なる位置において、前記基板上に前記能動素子の厚さ以下に形成される第１の絶縁層と、
前記第１の絶縁層上に形成される第１の導電層と、
前記第１の絶縁層の上部に形成され、前記能動素子及び前記第１の導電層を被覆する第２の絶縁層と、
前記第２の絶縁層上に形成される第２の導電層と、を備える
ことを特徴とする半導体装置。 A substrate,
An active element mounted on the substrate;
A first insulating layer formed on the substrate with a thickness equal to or less than a thickness of the active element at a position different from a portion where the active element is mounted;
A first conductive layer formed on the first insulating layer;
A second insulating layer formed on the first insulating layer and covering the active element and the first conductive layer;
And a second conductive layer formed on the second insulating layer. A semiconductor device comprising: 前記第１の絶縁層上において、前記能動素子の厚さよりも薄い導電層及び絶縁層により受動素子が形成されることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a passive element is formed on the first insulating layer by a conductive layer and an insulating layer that are thinner than the thickness of the active element. 前記受動素子として、インダクタが形成されることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein an inductor is formed as the passive element. 前記受動素子として、前記インダクタと接続されるキャパシタが形成されることを特徴とする請求項３に記載の半導体装置。   The semiconductor device according to claim 3, wherein a capacitor connected to the inductor is formed as the passive element. 前記第１の絶縁層の一部に替えて、複数の絶縁層と導電層とが積層されてなることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a plurality of insulating layers and conductive layers are stacked instead of a part of the first insulating layer. 前記基板が、表面に電子回路及び電極が形成される能動素子からなることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the substrate includes an active element having an electronic circuit and an electrode formed on a surface thereof. 前記能動素子からなる基板の電極と前記第１の導電層とが電気的に接続されることを特徴とする請求項６に記載の半導体装置。   The semiconductor device according to claim 6, wherein an electrode of the substrate made of the active element and the first conductive layer are electrically connected. 基板上に、能動素子の搭載部分に開口部を設けて前記能動素子以下の厚さで第１の絶縁層を形成する工程と、
前記第１の絶縁層上に第１の導電層を形成する工程と、
前記第１の絶縁層の開口部に能動素子を搭載する工程と、
前記第１の絶縁層上に、前記能動素子及び前記第１の導電層を被覆する第２の絶縁層を形成する工程と、
前記第２の絶縁層上に第２の導電層を形成する工程とからなる
ことを特徴とする半導体装置の製造方法。 Forming a first insulating layer on the substrate at a thickness equal to or smaller than the active element by providing an opening in a mounting portion of the active element;
Forming a first conductive layer on the first insulating layer;
Mounting an active element in the opening of the first insulating layer;
Forming a second insulating layer covering the active element and the first conductive layer on the first insulating layer;
Forming a second conductive layer on the second insulating layer. A method of manufacturing a semiconductor device, comprising:
JP2007143896A 2007-05-30 2007-05-30 Semiconductor device, and manufacturing method thereof Ceased JP2008300560A (en)

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JP2015504608A (en) * 2011-11-22 2015-02-12 日本テキサス・インスツルメンツ株式会社 Micro surface mount device packaging

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