JP2011253944A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses an increase in manufacturing cost.SOLUTION: The semiconductor device 1 includes a semiconductor substrate 10, a dielectric film 22, a rewiring part 24, an upper electrode 25, an insulation film 26 and an external connection terminal 28. The semiconductor substrate 10 on which circuits are formed has a lower electrode 15, an upper electrode pad 16 and connection pads 17, 18 on a top face respectively connected to the circuits. The dielectric film 22 covers the lower electrode 15 and has openings reaching top faces of the upper electrode pad 16 and connection pads 17, 18. The rewiring part 24 is electrically connected with some of the connection pads 17, 18. The upper electrode 25 is disposed facing a top face of the lower electrode 15 via the dielectric film 22, connected with the upper electrode pad 16 and includes the rewiring part 24. The insulation film 26 covers the dielectric film 22, the wiring part 24 and the upper electrode 25. The external connection terminal 28 penetrates the insulation film 26 and is connected to the rewiring part 24 and exposed on a top face of the insulation film 16.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  A semiconductor device including a semiconductor integrated circuit or the like is required to be reduced in cost as well as high integration, miniaturization, and thinning.

  In order to achieve high integration, miniaturization, and the like, a semiconductor device has a stacked form of, for example, CoC (Chip on Chip). In CoC, another semiconductor chip, for example, two semiconductor chips having different functions such as a memory and a logic are electrically connected and fixed to the surface of the completed semiconductor chip. The connected semiconductor chips are assembled into, for example, a CSP (Chip size package) that is substantially equal to the size of the larger semiconductor chip to form a higher-performance semiconductor device and mounted on a mounting substrate. In order to electrically connect the two semiconductor chips to each other, that is, to match the connection positions of the two semiconductor chips, rewiring is performed on the surface of at least one of the semiconductor chips to adjust the position of the connection pads.

  Further, in order to reduce the size and thickness of the semiconductor device, rewiring is performed on the surface of the semiconductor chip, and an external connection terminal is connected to the rewiring to obtain a wafer level CSP (WLCSP, WCSP). Is possible. WLCSP rewiring is formed on the surface of a semiconductor chip instead of an interposer as a rewiring substrate. That is, since the WLCSP can use the external connection terminal for connecting another semiconductor chip, it can be used as a technique for forming at least one semiconductor chip constituting the above-mentioned CoC.

  In many semiconductor chips, capacitors necessary for a circuit are provided in the chip, that is, in an interlayer insulating film or a silicon substrate. In a high-frequency circuit such as a PLL (Phase Locked Loop), a VCO (Voltage Controlled Oscillator), etc., a capacitor is often arranged outside the package and connected. If the necessary capacitors can be taken into the package including the semiconductor chip, the semiconductor device can be reduced in size and thickness. However, costs should be kept as low as possible.

JP 2005-108929 A

  The present invention provides a semiconductor device capable of suppressing an increase in manufacturing cost and a manufacturing method thereof.

  The semiconductor device according to the embodiment of the present invention includes a semiconductor substrate portion, a dielectric film, a rewiring, an upper electrode, an insulating film, and an external connection terminal. The semiconductor substrate portion is formed with a circuit and has first to third connection pads connected to the circuit on the upper surface. The dielectric film has an opening that covers at least the first connection pad and reaches the upper surfaces of the second and third connection pads. The rewiring is electrically connected to at least a part of the third connection pads. The upper electrode is disposed to face the upper surface of the first connection pad via the dielectric film, is connected to the second connection pad, and includes the same configuration as the rewiring. The insulating film covers the dielectric film, the rewiring, and the upper electrode. The external connection terminal penetrates the insulating film, is connected to the rewiring, and is exposed from the upper surface of the insulating film.

  In the method of manufacturing a semiconductor device according to the embodiment of the present invention, a dielectric film is formed so as to cover a surface of a semiconductor substrate portion having a circuit formed thereon and first to third connection pads connected to the circuit on the surface. Forming an opening reaching the upper surfaces of the second and third connection pads in the dielectric film, covering the upper surfaces of the second and third connection pads, and the dielectric film. A step of forming a first barrier metal. The method for manufacturing a semiconductor device may also include a region on the first and second connection pads, a part of the third connection pad, a region connecting the first connection pad and the second connection pad, and A first photoresist patterned so as to expose the barrier metal in a region connecting the first to third connection pads is formed on the first barrier metal, and the exposed first first metal is exposed. Forming a rewiring on the barrier metal, removing the first photoresist and the first barrier metal under the first photoresist, the dielectric film, and the rewiring And a step of forming an insulating film so as to cover the third connection pad. The method of manufacturing a semiconductor device also includes a step of providing an opening in the insulating film to selectively expose the rewiring and the third connection pad on the third connection pad, the rewiring, A step of forming a second barrier metal so as to cover the third connection pad and the insulating film; and a second photoresist having an opening selectively so as to cover the second barrier metal. Forming and exposing an external terminal metal on the exposed second barrier metal, and removing the second photoresist and the second barrier metal under the second photoresist. I have.

1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present invention. Sectional drawing which shows typically the manufacturing method of the semiconductor device which concerns on embodiment of this invention. Sectional drawing which shows typically the manufacturing method following FIG. 2 of the semiconductor device which concerns on embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the figure shown below, the same code | symbol is attached | subjected to the same component. The direction in which the rewiring layer is present is on the upper side of the surface of the silicon substrate.

(Embodiment)
A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 1, the semiconductor device 1 schematically includes a semiconductor substrate unit 10 and a rewiring unit 20 provided on an upper surface (also referred to as an upper surface). The semiconductor substrate unit 10 includes a silicon substrate 11, an interlayer insulating film 13 provided on the upper surface of the silicon substrate 11, a multilayer wiring 14 disposed so as to be embedded in the interlayer insulating film 13, and an upper surface of the interlayer insulating film 13. A lower electrode 15 as a first connection pad, an upper electrode pad 16 as a second connection pad, and connection pads 17 and 18 as third connection pads are provided.

  The rewiring unit 20 penetrates through the interlayer insulating film 13, the lower electrode 15, the upper electrode pad 16, and the dielectric film 22 on the upper surface of the connection pads 17 and 18, the upper surface of the dielectric film 22, or the dielectric film 22. The barrier metal 23 and the rewiring 24 which are provided lead electrodes, the dielectric film 22, the side surface of the barrier metal 23, the insulating film 26 covering the rewiring 24, and the insulating film 26 are connected to the rewiring 24. A barrier metal 27 and an external connection terminal 28 are provided. The lower electrode 15, the dielectric film 22 on the lower electrode 15, and the upper electrode 25 made up of the barrier metal 23 and the rewiring 24 facing the lower electrode 15 and connected to the upper electrode pad 16 are MIM (Metal Insulator Metal). A type capacitor 21 is formed.

  In the semiconductor substrate portion 10, a plurality of transistors and the like (not shown) suitable for the function are disposed on the surface region of the silicon substrate 11, and usually a multilayer wiring 14 composed of a plurality of layers and an interlayer between the upper surface of the silicon substrate 11. It has an integrated circuit provided with an insulating film 13. Here, a plug for connecting the upper and lower multilayer wirings 14 is also included in the multilayer wiring 14. The semiconductor substrate unit 10 is an integrated circuit that can ensure reliability if a passivation film (not shown) or a surface protective film (not shown) is formed on the surface. The semiconductor substrate portion 10 is manufactured through a known semiconductor process except for the passivation film or the surface protective film. The semiconductor substrate portion 10 can be configured to have a film corresponding to a passivation film or a surface protective film inside the upper end of the interlayer insulating film 13.

  The lower electrode 15, the upper electrode pad 16, and the connection pads 17 and 18 are terminals for externally connecting the semiconductor substrate unit 10. The lower electrode 15, the upper electrode pad 16, and the connection pads 17 and 18 are made of, for example, aluminum or a metal mainly composed of aluminum. The multilayer wiring 14 including the plug is made of copper or a metal containing copper as a main component, but tungsten, aluminum, a metal containing these as a main component, or the like can also be used.

  In the rewiring unit 20, the dielectric film 22 is a dielectric for accumulating charges in the MIM type capacitor 21 and functions as an insulating film. In order to set the capacitance of the capacitor 21 to a suitable value and to ensure necessary insulation, the material, film thickness, and the like are determined. The dielectric film 22 is, for example, a silicon nitride film, but in addition, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, a titanium oxide film, a barium titanate film, or a laminated film thereof From the above, it is possible to select an appropriate dielectric constant. The dielectric film 22 has a substantially constant film thickness between the lower electrode 15 and the upper electrode 25.

  The barrier metal 23 is made of titanium, but may be titanium, titanium nitride, tantalum, or a laminated film thereof. In addition to the upper electrode of the capacitor 21, the rewiring 24 connects, for example, the connection pad 17 and the external connection terminal 28 in the vertical direction, the connection between the lower electrode 15, the upper electrode pad 16, and the connection pads 17, 18. In addition, the lower electrode 15, the upper electrode pad 16, the connection pad 17 and the external connection terminal 28 are connected. The rewiring 24 is copper formed by electrolytic plating or electroless plating. In addition, the rewiring 24 can use aluminum, gold, or the like.

  The barrier metal 27 is a film made of the same material as the barrier metal 23. The external connection terminal 28 is a tin-copper solder having an upper end formed in a bump shape. As the external connection terminal 28, it is possible to use tin-gold solder, gold or the like in addition to tin-copper solder depending on the connection method. The external connection terminal 28 includes columnar copper or the like extending in the vertical direction between the barrier metal 27 and the rewiring 24, or the lower end portion of the external connection terminal 28 is made of columnar copper or the like, and the upper end portion It is possible to have bump-shaped solder on the surface. The external connection terminal 28 can be a pad whose surface is exposed for connection, and the pad at that time can be, for example, copper or the like.

  The insulating film 26 is a polyimide film, but is composed of an epoxy film, a phenolic resin film, a silicon oxide film, a silicon nitride film, or a laminated film including these. The upper surface of the insulating film 26 can be formed of a solder resist film (not shown).

  A part of the upper surface of the connection pad 18 is connected to the barrier metal 23 and the rewiring 24, and the insulating film 26 is removed and a part is exposed. The connection pad 18 can be connected to the outside, for example, wire bonding.

  Next, a method for manufacturing the semiconductor device 1 will be described. As shown in FIG. 2 (a), an interlayer insulating film 13 made of a TEOS (Tetraethoxysilane) -based silicon oxide film is formed on the upper end, a lower electrode 15 made of aluminum, an upper electrode pad 16 on the interlayer insulating film 13, and The semiconductor substrate portion 10 provided with the connection pads 17 and 18 is prepared. The semiconductor substrate unit 10 is in a wafer state. After the rewiring unit 20 is formed, the semiconductor substrate unit 10 is separated into the semiconductor device 1.

  As shown in FIG. 2B, a dielectric film 22 made of a silicon nitride film is formed by, for example, CVD so as to cover the interlayer insulating film 13, the lower electrode 15, the upper electrode pad 16, and the connection pads 17 and 18. It is formed by (Chemical Vapor Deposition) method.

  As shown in FIG. 2C, an opening 30 is formed in the dielectric film 22 on the upper electrode pad 16 and the connection pads 17 and 18 that require electrical connection by using a photolithography technique.

  As shown in FIG. 2D, a barrier metal 23 made of titanium or titanium nitride is formed by, for example, a sputtering method so as to cover the dielectric film 22 and the opening 30.

  As shown in FIG. 2 (e), on the barrier metal 23, the lower electrode 15, which requires the rewiring 24, the upper electrode pad 16, and the connection pads 17, 18 and the region connecting the pads, etc. A photoresist 31 patterned so as to have the opening 32 is formed by using a photolithography technique.

  As shown in FIG. 2F, a rewiring 24 made of copper is formed on the barrier metal 23 in the opening 32 by electrolytic or electroless plating.

  As shown in FIG. 2G, the photoresist 31 is removed using a release agent or the like. The photoresist 31 can also be removed by a dry etching (ashing) method.

  As shown in FIG. 3A, using the rewiring 24 as a mask, the barrier metal 23 excluding the lower portion of the rewiring 24 is removed by RIE (Reactive Ion Etching). The barrier metal 23 and the rewiring 24 are formed so as to be connected to the upper electrode pad 16 and continuously cover the lower electrode 15 and the upper electrode pad 16. The barrier metal 23 and the rewiring 24 are connected to the connection pads 17 and 18 respectively and cover at least a part thereof.

  As shown in FIG. 3B, an insulating film 26 made of photosensitive polyimide is applied so as to cover the dielectric film 22 and the rewiring 24. The insulating film 26 may be non-photosensitive, and in that case, a patterning photoresist or the like is used in combination.

  As shown in FIG. 3C, the insulating film 26 is patterned by photolithography so as to have an opening reaching the upper surface of the rewiring 24 on the connection pad 17 and the upper surface of the connection pad 18 that require external connection. Thereafter, a barrier metal 27 is formed on the insulating film 26. The barrier metal 27 is formed by the same material and method as the barrier metal 23.

  As shown in FIG. 3D, a photoresist 33 is formed so as to cover the barrier metal 27 and patterned so as to have an opening reaching the upper surface of the barrier metal 27 on the connection pad 17. Thereafter, external connection terminals 28 made of solder are formed by electrolytic or electroless plating.

  As shown in FIG. 1, the photoresist 33 is removed, the barrier metal 27 is removed except for the lower portion of the external connection terminal 28, and a wafer in which regions to be the semiconductor device 1 are arranged is formed. Thereafter, dicing or the like not shown is performed to complete the semiconductor device 1. On the upper surface of the semiconductor device 1, bump-like external connection terminals 28 connected to the connection pads 17, the insulating film 26, and a part of the connection pads 18 are exposed.

  As described above, the semiconductor device 1 includes the barrier metal 23 and the rewiring of the rewiring portion 20 facing the lower electrode 15 as the other electrode and the uppermost lower electrode 15 of the semiconductor substrate portion 10 as a pair of electrodes. The upper electrode 25 is composed of 24. A dielectric film 22 is disposed between the lower electrode 15 and the upper electrode 25 to constitute an MIM type capacitor 21.

  The capacitor 21 is not provided in the semiconductor substrate unit 10, for example, in the region of the interlayer insulating film 13 and the multilayer wiring 14. Therefore, an exposure mask or the like for forming any one of the lower electrode, the upper electrode, and the dielectric film, which is required when the semiconductor substrate unit 10 is provided, is not required.

  The capacitor 21 requires a special exposure mask for forming the lower electrode 15 because the lower electrode 15 is formed of the same conductor as the uppermost connection pads 17 and 18 of the semiconductor substrate portion 10. And not. Since the upper electrode 25 is formed of the barrier metal 23 and the rewiring 24, a special exposure mask or the like for forming the upper electrode 25 is not required. However, although the step of forming the dielectric film 22 is required, an exposure mask for forming the dielectric film 22 of the capacitor 21 is not required.

  As a result, the semiconductor device 1 has a configuration similar to that of the WLCSP, and at the same time, the capacitor 21 can be moved from the semiconductor substrate portion 10 to the boundary portion with the rewiring portion 20. It is. Further, in the semiconductor device 1, a capacitor that is newly required when a plurality of semiconductor devices are housed in one package, such as CoC, may be formed at the boundary between the semiconductor substrate unit 10 and the rewiring unit 20. Is possible. Further, it is possible to take in the capacitor, which was required to be provided outside the package, at the boundary between the semiconductor substrate unit 10 and the rewiring unit 20, that is, into the package. Since the capacitor 21 can be formed at the boundary between the semiconductor substrate unit 10 and the rewiring unit 20 without using an additional exposure mask for forming the capacitor 21, an increase in manufacturing cost can be suppressed. .

  Although the embodiment has been described above, this embodiment is merely shown as an example and is not intended to limit the scope of the present invention. Indeed, the novel semiconductor device described herein and its manufacturing method may be embodied in various other forms, and further, without departing from the spirit of the present invention, the semiconductor device described herein and its manufacture. Various omissions, substitutions and changes in the form of the method may be made. The appended claims and their equivalents or equivalent methods are intended to include such forms or modifications as fall within the scope and spirit of the present invention.

  For example, in the embodiment, in the semiconductor device, a capacitor is formed at the boundary between the semiconductor substrate portion and the rewiring portion, and at the same time, a solder bump or the like is formed as an external connection terminal by connecting to another pad or the like. However, the solder bumps are not necessarily formed on the semiconductor device at the same time. That is, the semiconductor device may have only the connection pads, and the solder bumps may be formed on the other side to be connected, for example. Of course, it is possible to have solder bumps on both the semiconductor device and the other side to be connected, and to connect the solder bumps.

  In the embodiment, an example in which a silicon substrate is used as the semiconductor device has been described. However, it is possible to use a compound semiconductor substrate such as GaAs, GaN, InP, and SiC. The silicon substrate and the compound semiconductor substrate may be thin films.

The present invention can be configured as described in the following supplementary notes.
(Supplementary note 1) A circuit board is formed, and a semiconductor substrate portion having first to third connection pads connected to the circuit on its upper surface, covering at least the first connection pad, and the second and third connections. A dielectric film having an opening reaching the upper surface of the connection pad, a rewiring electrically connected to at least a part of the third connection pad, and the first connection pad via the dielectric film An upper electrode disposed opposite to the upper surface of the substrate and connected to the second connection pad and including the same configuration as the rewiring; an insulating film covering the dielectric film, the rewiring, and the upper electrode; A semiconductor device comprising: an external connection terminal penetrating the insulating film and connected to the rewiring and exposed from an upper surface of the insulating film.

(Appendix 2) The semiconductor device according to appendix 1, wherein the dielectric film is an oxide film of silicon, aluminum, titanium, and tantalum, a silicon nitride film, and a film obtained by stacking these films (Appendix 3). The semiconductor device according to appendix 1, which is one of a polyimide film, a phenol resin film, an epoxy film, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film or a composite film thereof.

(Additional remark 4) The said rewiring is a semiconductor device of Additional remark 1 which mainly has copper, aluminum, gold | metal | money, and the metal which has these as a main component.

(Supplementary note 5) The semiconductor device according to supplementary note 1, wherein the rewiring facing the first connection pad, the dielectric film, and the first connection pad constitutes an MIM type capacitor.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor substrate part 11 Silicon substrate 13 Interlayer insulation film 14 Multilayer wiring 15 Lower electrode 16 Upper electrode pad 17, 18 Connection pad 20 Rewiring part 21 Capacitor 22 Dielectric film 23, 27 Barrier metal 24 Rewiring 25 Upper electrode 26 Insulating film 28 External connection terminals 30, 32, 34 Openings 31, 33 Photoresist

Claims (5)

A semiconductor substrate portion having a circuit formed thereon and first to third connection pads respectively connected to the circuit;
A dielectric film covering at least the first connection pad and having an opening reaching the upper surfaces of the second and third connection pads;
Rewiring electrically connected to at least some of the third connection pads;
An upper electrode disposed opposite to the upper surface of the first connection pad via the dielectric film, connected to the second connection pad, and having the same configuration as the rewiring;
An insulating film covering the dielectric film, the rewiring, and the upper electrode;
An external connection terminal that penetrates through the insulating film and is connected to the rewiring and exposed from the upper surface of the insulating film;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the external connection terminal has bump-shaped solder at a tip portion protruding from the insulating film. Forming a dielectric film so as to cover a surface of the semiconductor substrate portion having a circuit formed and having first to third connection pads respectively connected to the circuit;
Forming an opening in the dielectric film reaching the top surfaces of the second and third connection pads;
Forming a first barrier metal so as to cover the top surfaces of the second and third connection pads and the dielectric film;
On the first and second connection pads, on a part of the third connection pads, a region connecting the first connection pads and the second connection pads, and the first to third connection pads A first photoresist patterned so as to expose the barrier metal in a region connecting the two is formed on the first barrier metal, and rewiring is formed on the exposed first barrier metal. Forming, and
Removing the first photoresist and the first barrier metal under the first photoresist;
Forming an insulating film so as to cover the dielectric film, the rewiring, and the third connection pad;
Providing an opening in the insulating film to selectively expose the rewiring and the third connection pad on the third connection pad;
Forming a second barrier metal so as to cover the rewiring, the third connection pad, and the insulating film;
Forming a second photoresist having an opening selectively so as to cover the second barrier metal, and forming an external terminal metal on the exposed second barrier metal;
Removing the second photoresist and the second barrier metal under the second photoresist;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 3, wherein the rewiring is formed by a plating method.   5. The method of manufacturing a semiconductor device according to claim 3, wherein the external terminal metal is formed by a plating method.

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