JP2009038203A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which an inductive element and a capacitive element are formed on a semiconductor substrate, capable of miniaturizing the device by effectively using a limited area and can curtail a manufacturing process and cost. <P>SOLUTION: The semiconductor device 1 at least comprises: semiconductor substrate 2 having an electrode and an integrated circuit formed on at least one surface; a first insulating resin layer 5 provided covering the one surface of the semiconductor substrate; an inductive element 8a formed on the first insulating resin layer and electrically connected to the electrode; and a capacitive element 9 formed on the one surface of the semiconductor substrate. It is characterized in that the inductive element comprises a conductor part formed in spiral, one end of the capacitive element is electrically connected to an inner edge of the conductor part, and the other end of the capacitive element is electrically connected to the integrated circuit or an external circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device including an inductive element and a capacitive element on one surface side of a semiconductor substrate.

  In mobile communication terminals, particularly portable terminals, it is essential to reduce the size and weight of the terminal, and it is important to reduce the size of components used therefor. As a trend toward miniaturization of components, it is strongly desired to convert high frequency components of portable terminals into MMIC (Monolithic Microwave IC). By integrating the active element and its matching circuit and bias circuit on the same substrate, it is advantageous for miniaturization as compared with a hybrid IC in which the matching circuit, bias feeding circuit and the like are formed by external chip components.

  Even in the case of the MMIC, it is necessary to ground the circuit element. Conventionally, there are two methods used for grounding, that is, a method of wire bonding from a semiconductor substrate and a method of using a via hole. is there. Compared with the method using wire bonding, a method using a via hole is more effective in improving performance and reducing the mounting cost of assembly. Therefore, a method using a via hole is often used in the MMIC.

10A and 10B are diagrams illustrating a configuration example of a conventional semiconductor device, in which FIG. 10A is a plan view, and FIG.
In this semiconductor device, an input matching parallel inductor 814, an input matching series inductor 816, and an input matching parallel capacitor 815 are formed on a GaAs substrate 824 via an insulating film 834 on a semiconductor substrate. Yes.

  The inductor 814 and the inductor 816 use a spiral pattern, and this spiral inductor has a lower wiring metal layer 831 such as gold / titanium deposition and an upper wiring metal layer 830 such as gold plating formed of silicon nitride (SiN) or the like. This structure is connected by a contact hole 833 through the interlayer insulating film 832.

  On the other hand, the capacitor 815 is an MIM (Metal-Insulator-Metal) capacitor pattern, and a titanic acid having a dielectric constant of 100 or more as a high dielectric layer 828 is formed on the tip of the electrode drawn from the lower wiring metal layer 831. In this structure, the upper wiring metal 829 is formed by gold / titanium deposition or the like via strontium (SrTiO3: STO). The electrode drawn from the upper wiring metal 829 is connected to the ground metal layer 826 on the via hole.

  The via hole 821 is formed through the semiconductor substrate, and the inner wall of the via hole 821 is formed with a conductive film electrically connected to the back surface ground metal 829, and is electrically connected to the MIM capacitor upper layer metal 829 through the ground metal layer 826. Connected.

  However, in such a conventional LC resonator, a spiral inductor as an inductive element, a MIM (Metal Insulation Metal) capacitor as a capacitive element, and a via hole for grounding are individually arranged two-dimensionally with respect to the semiconductor substrate. As a result, the area occupied by the circuit increases, which hinders downsizing of the device.

If a semiconductor device similar to the above is realized by a wafer level CSP (chip scale package) technology, it is considered that the configuration is as shown in FIG. 11A is a plan view, and FIG. 11B is a cross-sectional view. Note that the via hole is not shown here.
The semiconductor device 100 includes a first insulating resin layer 102, a first wiring layer 103, a second insulating resin layer 104, and a second wiring layer 105 having a spiral inductor 105a as an inductive element on a semiconductor substrate 101. The capacitor 106 and the sealing resin layer 110 are disposed in order. The capacitor 106 includes an upper electrode layer 107 and a lower electrode layer 108, and a dielectric layer 109 disposed therebetween.

  Usually, it is conceivable to form an LC resonator by adopting a spiral inductor and a MIM capacitor as a capacitor in a copper plating rewiring process of a wafer level CSP. In FIG. 11, the spiral inductor 105a is arranged on the left side and the MIM capacitor 106 is arranged on the right side, and they are connected in series.

However, the semiconductor device configured as shown in FIG. 11 has the following problems.
(1) The area is not effectively used in the internal region of the inductor.
(2) Since the capacitors are arranged in a plane, the occupied area is increased, which hinders downsizing of the element.
(3) It is necessary to obtain a plurality of steps in manufacturing the capacitor, which causes an increase in cost.
(4) Since the capacitor structure uses different materials, there is a concern about reliability.
(5) In order to increase the capacitance of the capacitor, special dielectric materials or measures such as increasing the size are required. However, using special dielectric materials increases costs and increases reliability. Disadvantageous. Further, when the size is increased, the occupied area is increased, which hinders downsizing of the element. In particular, the increase in the occupied area is a problem.
JP 2002-64345 A

  The present invention has been devised in view of such a conventional situation, and in a semiconductor device in which an inductive element and a capacitive element are arranged on a semiconductor substrate, the device can be downsized by effectively utilizing a limited area. An object of the present invention is to provide a highly reliable semiconductor device that can reduce manufacturing processes and costs.

According to a first aspect of the present invention, there is provided a semiconductor device having at least one surface on which an electrode and an integrated circuit are disposed, a first insulating resin layer disposed so as to cover one surface of the semiconductor substrate, and the first An inductive element disposed on an insulating resin layer and electrically connected to the electrode, and a capacitive element disposed on one surface side of the semiconductor substrate, wherein the inductive element comprises: Consists of a spirally formed conductive portion, one end of the capacitive element is electrically connected to the inner end of the conductive portion, and the other end of the capacitive element is electrically connected to the integrated circuit or external circuit It is characterized by being.
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, further comprising a second insulating resin layer disposed so as to cover the inductive element, wherein the capacitive element is on the second insulating resin layer. The capacitive element and the inductive element are electrically connected via a wiring portion that extends through the second insulating resin layer.

  In the present invention, in a semiconductor device in which an inductive element and a capacitive element are arranged on a semiconductor substrate, the inductive element is formed of a conductive portion formed in a spiral shape, and one end of the capacitive element is connected to an inner end of the conductive portion. By electrically connecting the other end of the capacitor to the integrated circuit or the external circuit, the device can be miniaturized by effectively using a limited area. Further, the manufacturing process and cost can be reduced, and a semiconductor device with excellent reliability can be provided.

  Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings.

1A and 1B are views schematically showing an embodiment of a semiconductor device of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view.
A semiconductor device 1 according to the present invention includes a semiconductor substrate 2 having an electrode 3 and an integrated circuit 4 disposed on at least one surface, a first insulating resin layer 5 disposed so as to cover one surface of the semiconductor substrate 2, and the first A first wiring layer 6 disposed on the insulating resin layer 5; a second insulating resin layer 7 disposed so as to cover the first wiring layer 6; and the electrode disposed on the second insulating resin layer 7 3, an inductive element (inductor 8 a) electrically connected to 3, and a capacitive element (capacitor 9) disposed on one surface side of the semiconductor substrate 2.
In the semiconductor device 1 of the present invention, the inductive element includes a second wiring layer (conductive portion) 8 formed in a spiral shape, and one end of the capacitive element is connected to an inner end portion of the second wiring layer 8. It is electrically connected, and the other end of the capacitor is electrically connected to the integrated circuit 4 or an external circuit.

  In the present invention, in the semiconductor device 1 in which the inductive element and the capacitive element are arranged on the semiconductor substrate 2, the inductive element includes the second wiring layer 8 formed in a spiral shape, and one end of the capacitive element is It is electrically connected to the inner end portion of the second wiring layer 8 and the other end of the capacitive element is electrically connected to the integrated circuit 4 or the external circuit, so that a limited area can be effectively used. This can contribute to downsizing of the apparatus. In addition, the manufacturing process and cost can be reduced, and the semiconductor device 1 having excellent reliability can be provided.

The present invention provides an LC resonator comprising a spiral inductor 8a and a chip capacitor (or chip capacitor) 9 using wafer level CSP technology and chip component mounting technology.
That is, in the present invention, the capacitor 9 is mounted as a capacitive element in a region inside the innermost periphery of the spiral inductor 8a created by using the wafer level CSP rewiring (hereinafter referred to as an inner region of the inductor 8a). Thus, a semiconductor device that can effectively use the area and contribute to the miniaturization of the element is configured.

A commercially available chip capacitor is preferably used as the capacitor 9. Thereby, the process for forming a capacitor becomes unnecessary, and a man-hour and cost can be reduced. Further, it is not necessary to use different materials for capacitor formation, and reliability is improved.
As is apparent from FIG. 1A, the present invention can be applied to an inductor 8a having a physical size such that the chip capacitor 9 can be accommodated in the inner region of the inductor 8a.

Here, the inner end portion of the inductor 8a has a pad portion 10 for mounting a chip capacitor. That is, in the second wiring layer 8 constituting the inductor 8a, the part where the chip capacitor 9 is mounted has a larger line width than the other part.
FIG. 2 shows an enlarged view of the vicinity of the portion where the chip capacitor 9 is mounted in the second wiring layer 8. Naturally, the pad portion 10 for mounting the chip capacitor 9 is a region on the second wiring layer 8 avoiding the via portion 11.

When the area of the inner region of the inductor 8a has no margin, the chip capacitor 9 is arranged at the very limit of the inner region, and when there is a relatively large margin, the arrangement shown in FIG. 1 can be performed.
If the area of the internal region of the inductor 8a is sufficient and the influence of the chip capacitor 9 on the inductor 8a is a concern, the chip capacitor 9 may be disposed at the end of the internal region of the inductor 8a. Further, a chip capacitor 9 may be arranged so as to straddle the spiral inductor 8a.

The semiconductor substrate 2 is provided with, for example, an Al pad as an electrode 3 on at least one surface of a base material whose surface layer forms an insulating portion (not shown), and further a passivation film such as SiN or SiO ₂ (insulation by passivation). Film). The passivation film is provided with an opening at a position aligned with the electrode 3, and the electrode 3 is exposed through the opening.

  The semiconductor substrate 2 may be a semiconductor wafer such as a silicon wafer, or may be a semiconductor chip obtained by cutting (dicing) the semiconductor wafer into chip dimensions. When the semiconductor substrate 2 is a semiconductor chip, first, a plurality of sets of various semiconductor elements, ICs, induction elements, etc. are formed on a semiconductor wafer, and then a plurality of semiconductor chips are obtained by cutting into chip dimensions. Can do.

The first insulating resin layer 5 has an opening formed at a position aligned with the electrode 3. The insulating resin layer is made of, for example, polyimide resin, epoxy resin, silicone resin, or the like, and has a thickness of, for example, 1 to 30 μm.
The first insulating resin layer 5 can be formed by, for example, a spin coating method, a printing method, a laminating method, or the like. The opening can be formed by patterning using, for example, a photolithography technique.

The first wiring layer 6 is a rewiring that electrically connects the inductor 8a and the integrated circuit 4 or an external circuit.
For example, Cu or the like is used as the material of the first wiring layer 6, and the thickness thereof is, for example, 1 to 20 μm. Thereby, sufficient electrical conductivity is obtained. The second wiring layer 8 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

The second insulating resin layer 7 has an opening 7 a formed at a position aligned with one end of the first wiring layer 6. The insulating resin layer is made of, for example, polyimide resin, epoxy resin, silicone resin, or the like, and has a thickness of, for example, 1 to 30 μm.
The second insulating resin layer 7 can be formed by, for example, a spin coating method, a printing method, a laminating method, or the like. The opening can be formed by patterning using, for example, a photolithography technique.

The second wiring layer 8 has a spiral inductor 8a as an inductive element.
As the material of the second wiring layer 8, for example, Cu or the like is used, and the thickness thereof is, for example, 1 to 20 μm. Thereby, sufficient electrical conductivity is obtained. The second wiring layer 8 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.
In the example shown in FIG. 1, the spiral inductor 8 a has a quadrangular shape, but is not limited thereto, and may have a circular shape, an octagonal shape, or the like.

The capacitor 9 as a capacitive element is a chip capacitor, and has a structure in which a metal layer-dielectric layer-metal layer, that is, a structure in which a dielectric layer is sandwiched between metal layers, extends over several layers. Such a chip capacitor has a small resistance and enables a high capacity density.
Capacitor 9 includes a plurality of electrode layers made of a metal material such as Ag and a dielectric layer made of perovskite oxide such as barium titanate or strontium titanate provided therebetween.

FIG. 3 is a cross-sectional view showing another configuration example of the semiconductor device of the present invention.
The semiconductor device 1B (1) further includes a third insulating resin layer 12 disposed so as to cover the inductive element, and the capacitive element is disposed on the third insulating resin layer 12, and the capacitor The element and the inductive element are electrically connected via a third wiring layer 13 (wiring portion) disposed through the third insulating resin layer 12.
That is, in the semiconductor device 1B shown in FIG. 3, the third insulating resin layer 12 is disposed on the spiral inductor 8a, and the capacitor 9 is provided thereon. That is, the spiral inductor 8 a and the capacitor 9 are separated from each other by the third insulating resin layer 12.

The third insulating resin layer 12 has an opening 12 a formed at a position aligned with the pad portion 10 in the second wiring layer 8. The third insulating resin layer 12 is made of, for example, a polyimide resin, an epoxy resin, a silicone resin, or the like, and has a thickness of, for example, 1 to 30 μm.
The third insulating resin layer 12 can be formed by, for example, a spin coating method, a printing method, a laminating method, or the like. The opening 12a can be formed by patterning using, for example, a photolithography technique.

  A plan view of the first wiring layer 6 and the second wiring layer 8 in this case is shown in FIG. (A) is the second wiring layer 8, and (b) is the second wiring layer 8 and the chip capacitor 9 mounted on the second wiring layer 8. That is, the second wiring layer 8 forms the inductor 8a, and the pad portion 10 of the second wiring layer 8 becomes the mounting portion and the lead wiring of the chip capacitor 9. With this configuration, the present invention can be applied even when the chip capacitor 9 is larger than the inner region of the inductor 8a. Thus, the semiconductor device of the present invention can be realized without being limited to the relative sizes of the inductor 8a and the chip capacitor 9. A chip capacitor 9 may be mounted so as to straddle the spiral inductor 8a.

  Thus, since the spiral inductor 8a and the capacitor 9 are provided in different layers via the third insulating resin layer 12, the area occupied by the inductor 8a is reduced as compared with the case where they are provided in the same layer. be able to. Further, by arranging the spiral inductor 8a and the capacitor 9 in different layers, a sufficient space for forming the spiral inductor 8a and the capacitor 9 can be secured. Therefore, characteristics such as an inductance value and a capacitance value can be improved.

A semiconductor device 1C (1) shown in FIG. 5 is provided with a structure 20 on one surface side of the semiconductor substrate 2 and arranged around the inductor 8a.
The structure 20 includes a protruding resin post 21 having a flat top, a fourth wiring layer 22, and a solder bump 23 placed on the top.

  The resin post 21 is an approximately frustoconical insulating resin formed at a predetermined position on the insulating resin layer. For example, the resin post 21 has an insulating property such as a polyimide resin, an epoxy resin, a silicon resin (silicone), or a novolac resin. It is preferably made of a positive photosensitive resin. The resin post 21 has, for example, a height of 10 to 100 μm and a diameter of 50 to 500 μm.

The fourth wiring layer 22 is formed on the upper surface of the resin post 21 in order to mount the solder bump 23.
For example, copper, chromium, aluminum, titanium, gold, titanium-tungsten alloy or the like is preferably used for the fourth wiring layer 22, and the thickness is preferably 2 to 40 μm, and more preferably 5 to 20 μm. Thereby, sufficient electrical conductivity is obtained. The fourth wiring layer 22 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.
The fourth wiring layer 22 may be electrically connected to the inductor 8a and the capacitor 9 or the integrated circuit 4 in the semiconductor substrate 2, but is not particularly limited.

  For the solder bump 23, eutectic solder, high-temperature solder not containing lead, or the like can be used. The solder bump 23 can be formed by, for example, a solder ball mounting method, an electrolytic solder plating method, a solder ball mounting method, a solder paste printing method, a solder paste dispensing method, a solder vapor deposition method, or the like.

  Further, as in the semiconductor device 1D (1) shown in FIG. 6, the sealing resin layer 24 disposed on the one surface side of the semiconductor substrate 2 so that the resin post 21 and the chip capacitor 9 are embedded. (Sealing part) may be further provided.

The sealing resin layer 24 is made of, for example, polyimide resin, epoxy resin, silicone resin, or the like, and has a thickness of, for example, 10 to 15 μm. The sealing resin layer 24 is provided with an opening (not shown) for outputting a terminal to the outside.
Such a sealing resin layer 24 can form the sealing resin layer 24 having an opening at a desired position, for example, by patterning a photosensitive resin such as a photosensitive polyimide resin by a photolithography technique. . In addition, the formation method of the sealing resin layer 24 is not limited to this method, For example, the pattern application | coating by a printing method may be sufficient.

  In the semiconductor device 1E (1) shown in FIG. 7, the semiconductor substrate 2 has an integrated circuit 4 (IC), and the integrated circuit 4, the inductor 8a, and the capacitor 9 have electrical connections. At this time, the pad portion 10 of the inductor 8 a is directly connected to the electrode 3 of the integrated circuit 4 in the semiconductor substrate 2.

  Further, as in the semiconductor device 1F (1) shown in FIG. 8, a structure 20 on the one surface side of the semiconductor substrate 2 and disposed around the inductor 8a may be provided. The structure 20 includes a protruding resin post 21 having a flat top, a fourth wiring layer 22, and a solder bump 23 placed on the top.

  Further, as in the semiconductor device 1G (1) shown in FIG. 9, the sealing resin layer 24 disposed on the one surface side of the semiconductor substrate 2 so that the resin post 21 and the chip capacitor 9 are embedded. (Sealing part) may be further provided.

As described above, in the semiconductor device of the present invention, since the chip capacitor is mounted in the inner area of the spiral inductor, the area inside the spiral inductor can be effectively used to prevent an increase in the occupied area. That is, it can contribute to miniaturization of equipment.
Further, in the wafer level CSP technology, since the inductor is formed by thick film copper plating, it is possible to reduce the wiring resistance. As a result, a resonator having a high Q value can be realized.

  A commercially available chip capacitor is used as the capacitor (C) of the LC resonator. As a result, it is sufficient to mount the chip, and the capacitor forming step is not necessary. As a result, man-hours and manufacturing costs can be reduced. Also, reliability is improved.

  As described above, in the present invention, by applying the wafer level CSP technology and the chip component mounting technology, it is possible to reduce the size of the apparatus by effectively using the area. Further, the manufacturing process and cost can be reduced, and a semiconductor device with excellent reliability can be provided.

Although the semiconductor device of the present invention has been described above, the present invention is not limited to this, and can be appropriately changed without departing from the spirit of the invention.
For example, in the above-described embodiment, the case where the capacitor is arranged on the upper side of the inductor has been described as an example. However, the inductor may be arranged on the upper side of the capacitor. That is, a capacitor disposed on one surface side of the semiconductor substrate may be sealed with a resin layer, and an inductor may be formed on the resin layer.
1 to 9 show only a portion corresponding to one inductive element and one capacitive element on the semiconductor substrate, the present invention is applied to a semiconductor device having a plurality of inductive elements and capacitive elements. You can also.

  The present invention can be applied to a semiconductor device including an inductive element and a capacitive element. In particular, the present invention is particularly effective in semiconductor devices used for wireless communication devices, consumer devices (radio tuners, tuning in wireless devices, oscillation circuits, etc.) and the like.

2A and 2B are a plan view and a cross-sectional view illustrating an example of a semiconductor device according to the present invention. The top view which expands and shows the mounting part vicinity of an inductor in FIG. Sectional drawing which shows other embodiment of the semiconductor device which concerns on this invention. FIG. 4 is a plan view showing a first wiring layer and a second wiring layer in FIG. 3. Sectional drawing which shows another example of the semiconductor device which concerns on this invention. Sectional drawing which shows another example of the semiconductor device which concerns on this invention. Sectional drawing which shows another example of the semiconductor device which concerns on this invention. Sectional drawing which shows another example of the semiconductor device which concerns on this invention. Sectional drawing which shows another example of the semiconductor device which concerns on this invention. The top view (a) and sectional drawing (b) which show an example of the conventional semiconductor device. The top view (a) and sectional drawing (b) which show another example of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Semiconductor substrate, 3 Electrode, 4 Integrated circuit, 5 1st insulating resin layer, 6 1st wiring layer, 7 2nd insulating resin layer, 8 2nd wiring layer, 8a Inductive element (inductor), 9 capacity | capacitance Element (capacitor), 10 pad portion, 11 via portion, 12 third insulating resin layer.

Claims (2)

A semiconductor substrate having an electrode and an integrated circuit disposed on at least one surface;
A first insulating resin layer disposed to cover one surface of the semiconductor substrate;
An inductive element disposed on the first insulating resin layer and electrically connected to the electrode;
A semiconductor device comprising at least a capacitive element disposed on one surface side of the semiconductor substrate,
The inductive element includes a conductive portion formed in a spiral shape,
One end of the capacitor element is electrically connected to an inner end portion of the conductive portion, and the other end of the capacitor element is electrically connected to the integrated circuit or an external circuit. A second insulating resin layer disposed so as to cover the inductive element,
The capacitive element is disposed on the second insulating resin layer,
2. The semiconductor device according to claim 1, wherein the capacitive element and the inductive element are electrically connected via a wiring portion that extends through the second insulating resin layer.

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