JP2003283284A - Flat filter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique of building up a filter on a laminate board which is superior in productivity and manufacturable at a low cost. <P>SOLUTION: A plurality of board layers 11-14 are laminated to form a laminate board 1. Chip capacitors C1-C6 are disposed on one layer of the board 1. Spiral inductors L1-L3 composed of striplines 21 are formed on another layer and connected to the chip capacitors through through-holes H1-H4 extending through the plurality of board layers. A board layer having a ground plane 22 is disposed between the board layer having the chip capacitors and that having the spiral inductors. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a filter used in a wireless module such as a VHF or UHF band,
In particular, it relates to a filter constructed on a laminated substrate.

[0002]

2. Description of the Related Art As a filter element constructed on a laminated substrate, for example, Japanese Patent Laid-Open No. 2000-31651 discloses
By forming a conductor between each layer of a laminated substrate in which three layers of dielectric substrates are laminated and by short-circuiting a predetermined end of each conductor to a through hole in which copper or gold plating is embedded,
A filter element is disclosed in which a capacitance C is created between conductors formed in different layers, and an inductance L is created in a conductor short-circuited to a through hole. that time,
By continuously providing the through holes in the conductor peripheral region excluding the input portion and the output portion, the shield effect for the filter element is enhanced.

[0003]

In the case of the filter element as described above, it is necessary to use a high dielectric material such as ceramic, which is relatively expensive and has poor workability, as a material of the dielectric substrate, and is inexpensive as a laminated substrate. It is difficult to use the glass-epoxy-based material generally used in. In particular, when a conductor is three-dimensionally electromagnetically coupled to construct a filter element, it is not realistic to use a material other than a high-dielectric material such as ceramics because it is necessary to increase the area of the conductor. Further, the use of a substrate having a high dielectric constant results in a large wavelength shortening rate, which causes a problem that the characteristics are significantly changed even with a slight pattern size deviation. Further, in order to improve the shielding effect of the filter element, continuously providing a large number of through holes in which copper or gold plating must be embedded later becomes a factor of increasing the manufacturing cost. In view of the above situation, an object of the present invention is to provide a technique for constructing a filter, which has excellent productivity and can be manufactured at low cost, on a laminated substrate, and at that time, the shield effect can be enhanced with a simple structure. That is also important.

[0004]

In order to solve the above problems, in a filter according to the present invention constructed on a laminated substrate in which a plurality of substrate layers are laminated, a chip capacitor is provided on one layer of the laminated substrate. At the same time, an inductor constituted by a strip line is formed in another layer, and the chip capacitor and the inductor are connected by a through hole extending over the plurality of substrate layers.

In this structure, since the inductor by the strip line is formed on the substrate layer different from the substrate layer on which the chip capacitor is mounted, the chip capacitor and the inductor can be arranged so as to overlap each other in the vertical direction. The density can be improved. In addition, the inductor flattened by the strip line can be formed in a very small size and can be manufactured with high accuracy, so that its electrical characteristics are stable.

Further, since the circuit elements such as the capacitor and the inductor are connected through the through hole, the inductor can be physically connected in the shortest distance, and unnecessary resonance current and eddy current can be prevented from flowing out to other circuits. In particular, if this through hole is provided as a through through hole that penetrates the laminated substrate, this connection line can be formed at a very low cost.

A preferred formation pattern of a stripline inductor is a spiral, and such a planarized spiral inductor contributes to miniaturization of the shape. At that time, if a structure in which the formation pattern of the spiral inductor is short-circuited is adopted, as a result, some electric resonance modes are combined and the frequency bandwidth is widened.

As a preferred embodiment for improving the shielding property, a substrate layer having a ground plane is arranged between the substrate layer having the chip capacitor and the substrate layer having the inductor. Be proposed.

Further, by forming the inductor on the intermediate substrate layer and arranging the chip capacitor on the front substrate layer, it becomes easy to adjust the frequency characteristic of the externally attached capacitor, and it is easy to repeat the trial manufacture. The desired frequency characteristic can be obtained. Other features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the drawings.

[0010]

1 (a) and 1 (b) are a perspective view and a longitudinal sectional view of a laminated substrate 1 in a region in which an embodiment of a flattening filter according to the present invention is constructed, respectively. . The laminated substrate 1 includes a first substrate layer 11 located on the front surface side (upper side), a fourth substrate layer 14 located on the back surface side (lower side), and a glass layer between the first substrate layer 11 and the fourth substrate layer 14. Second substrate layer 1 as an intermediate layer, which is arranged with a dielectric layer 2 made of an epoxy material (dielectric constant of about 4.6) interposed.
It is a laminated substrate having a four-layer structure including 2 and a third substrate layer 13. These first, second, third and fourth substrate layers 11, 1
A flattening filter is constructed over 2, 13, 14 and its exploded perspective view is shown in FIG. 2, and the plan views thereof are (a), (b), (c), (in FIG. 3). d).

The first substrate layer 11 functions as a mounting surface on which the C1 to C6 chip capacitors are arranged, and the second substrate layer 12 and the fourth substrate layer 14 have a ground plate 22 formed almost all over the ground. It functions as a surface. Third
The substrate layer 13 functions as an inductor pattern surface on which three rectangular spiral inductors L1 to L3 composed of strip lines 21 are formed. The input port P1 is the fourth
The substrate layer 14 is formed so as to be surrounded by the ground plate 22, and the output port P2 is formed in the first substrate layer 11.

The chip capacitors C1 to C6 arranged on the first substrate layer 11 and the spiral inductors L1 to L3 formed on the third substrate layer 13 are connected by through through holes H1 to H4 provided in the laminated substrate 1. ing. Further, similar through through holes H5 to H8 are provided to connect each circuit element and the ground plate 22.

The circuit configuration of the flattening filter constructed on the laminated substrate 1 will be described in detail with reference to FIGS. 1 to 3.
First, the input port P1 formed as a strip line on the fourth substrate layer 14 is connected to one end of the first spiral inductor L1 formed on the third substrate layer 13 via the first through-hole H1. First substrate layer 1
It is also connected to one end of the first chip capacitor C1 mounted on No. 1. The other end of the first chip capacitor C1 is connected to the ground plates 22 of the second substrate layer 12 and the fourth substrate layer 14 via the sixth through hole H6. First
The other end of the spiral inductor L1 is also the same as the third substrate layer 1
It is connected to one end of the second spiral inductor L2 formed in 1. Further, the second through-hole H2 is connected at the connection point between the first spiral inductor L1 and the second spiral inductor L2.

The second through-hole H2 is formed in the first substrate layer 1
In No. 1, it is connected to one end of the second chip capacitor C2 and one end of the third chip capacitor C3. The other end of the second chip capacitor C2 is connected to the ground plates 22 of the second substrate layer 12 and the fourth substrate layer 14 via the seventh through hole H7. The other end of the third chip capacitor C3 is similarly connected to one end of the fifth chip capacitor C5 mounted on the first substrate layer 11. The connection point between the third chip capacitor C3 and the fifth chip capacitor C5 is connected to the third through hole H3. Also, the first
The fourth chip capacitor C4 mounted on the substrate layer 11 has one end connected to the third through hole H3 and the other end second through the eighth through hole H8.
Ground plate 22 of substrate layer 12 and fourth substrate layer 14
Connected to.

The above-mentioned third through-hole H3 is the third
The substrate layer 13 is connected to the other end of the second spiral inductor L2. Further, one end of the third spiral inductor L3 formed on the third substrate layer 13 is connected to the fourth through hole H4, and the other end of the third spiral inductor L3 is connected through the fifth through hole H5. Ground plate 2 of second substrate layer 12 and fourth substrate layer 14
Connected to 2.

The fourth through hole H4 is formed in the first substrate layer 1
In No. 1, it is connected to the other end of the fifth chip capacitor C5 and also to one end of the sixth chip capacitor C6. The other end of the sixth chip capacitor C6 is connected to the strip line forming the output port P2.

As mentioned above, this planarizing filter
The chip capacitors C1 to C6 are mounted on the first substrate layer 11,
The rectangular spiral inductors L1 to L3 are formed on the third substrate layer 13, and the dielectric layer 2 is interposed between the first substrate layer 11 and the third substrate layer 13 and below the third substrate layer 13. A second substrate layer 12 and a fourth substrate layer 14, which are substantially ground plate layers, are arranged on the substrate. The required connection between the chip capacitor and the spiral inductor is made by the first, second, third and fourth through-holes H1 to H4, and the required chip capacitor and the spiral inductor are grounded at the fifth. It is realized by connecting to the ground plate 22 of the second substrate layer 12 and the fourth substrate layer 14 through the sixth, seventh and eighth through holes H5 to H8. Of course, this ground can also be connected to the ground plate 22 of either the second substrate layer 12 or the fourth substrate layer 14.

FIG. 4 shows an equivalent circuit of the flattening filter obtained by the above-mentioned structure, and its simulation result concerning the frequency characteristic is shown in FIG. 5. The actual measurement result for the actually manufactured sample is shown in FIG. It is shown in FIG. From the comparison between FIG. 5 and FIG. 6, it can be seen that the planarization filter according to the present invention agrees well with the simulation result. This is because this flattening filter is composed of chip capacitors and spiral inductors arranged on different substrate layers which are stacked, and they are connected to each other by through-holes so that the electrical and physical lengths are the shortest. Is a major factor.

The formation pattern of the inductor composed of the strip line is not limited to the rectangular spiral, and various formation patterns for producing inductance can be adopted. It is also possible to form a short-circuited portion in the inductor formation pattern.

[Brief description of drawings]

FIG. 1 is a perspective view and a vertical sectional view showing a laminated substrate on which a flattening filter as an example of the present invention is constructed.

FIG. 2 is an exploded perspective view showing each substrate layer on which a flattening filter is constructed.

FIG. 3 is a plan view of each substrate layer on which a planarization filter is constructed.

FIG. 4 is an equivalent circuit of the flattening filter treated in the embodiment.

5 is a frequency characteristic graph as a result of simulation based on the equivalent circuit shown in FIG.

FIG. 6 is a frequency characteristic graph as an actual measurement result of the flattening filter treated in the embodiment.

[Explanation of symbols]

1 Laminated board 2 Dielectric layer 11 First substrate layer 12 Second substrate layer 13 Third substrate layer 14 Fourth substrate layer 21 strip line 22 Grand plate C1 to C6 chip capacitors L1-L3 spiral inductor H1 to H8 through-holes P1 input port P2 output port

Claims (6)

[Claims] 1. A laminated substrate in which a plurality of substrate layers are laminated.
A chip capacitor is disposed on one layer and an inductor constituted by a strip line is formed on another layer, and the chip capacitor and the inductor are connected by through holes extending over the plurality of substrate layers. A flattening filter. 2. The flattening filter according to claim 1, wherein the inductor is a spiral inductor. 3. The flattening filter according to claim 2, wherein the formation pattern of the spiral inductor is short-circuited midway. 4. A substrate layer on which a ground plane is formed is arranged between a substrate layer on which the chip capacitor is arranged and a substrate layer on which the inductor is formed. The flattening filter according to any one of 1. 5. The flattening filter according to claim 1, wherein the chip capacitor is arranged on a front substrate layer and the inductor is formed on an intermediate substrate layer. 6. The flattening filter according to claim 1, wherein the through hole is provided as a through through hole penetrating the laminated substrate.