JP5067056B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, particularly relates to a semiconductor device active element is packaged on a wafer level, such as a semiconductor chip.

In a conventional semiconductor device, when a thin active element is mounted face-up on a substrate, for example, the active element is mounted on the substrate and a photosensitive insulating film is sealed so as to seal the active element. Is formed. Then, the connecting portion between the lower wiring on the substrate and the electrode of the active element is embedded in the conductive layer by opening the insulating layer by exposure and development.
However, in this method, since there is a difference between the thickness of the mounted active element and the thickness of the lower wiring, a step is formed on the surface of the formed insulating layer. In the state where there is a step on the surface of the insulating layer, an opening failure occurs in the insulating layer that opens to connect the lower wiring layer and the electrode of the active element.

  For this reason, in a semiconductor device in which fine-pitch wiring is re-wired to wiring with a wider pitch, the step portion is separated in a separate step in the step of the insulating layer between the wiring layer on the substrate and the active element mounted on the substrate. Then, the insulating layer is planarized, and the active element and the substrate-buried portion are connected (for example, see Non-Patent Document 1).

IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL.23, NO.2, MAY 2000

  In a semiconductor device using a photosensitive insulating film as an insulating film, when a thick insulating layer for embedding an active element is formed, the thickness of the resin insulating film to be exposed is set in an exposure process for forming an opening in the insulating layer. Accordingly, the amount of exposure must be increased. As a result, pattern collapse occurs due to an increase in exposure amount, and it becomes difficult to perform stable patterning.

In the semiconductor device described in Non-Patent Document 1, a conductive post is formed on a substrate, an insulating layer for protecting the post is used, and a solid insulating resin is used in upper and lower molds. The insulating layer is formed and flattened by heating and pressurizing.
However, in this method, the resin must be pressed and molded in a mold while heating the resin to the melting temperature, and the process becomes complicated and the manufacturing cost increases.

  In order to solve the above-described problems, the present invention provides a semiconductor device that can be manufactured with a small number of steps regardless of the thickness of an active element mounted on a substrate, and a manufacturing method thereof.

The semiconductor device of the present invention is formed by covering a semiconductor substrate on which an electronic circuit including a semiconductor element and an electrode are formed, a first conductive layer formed on the substrate, and the semiconductor substrate and the first conductive layer. A first insulating layer, an active element mounted on the semiconductor substrate , a second conductive layer formed on the first insulating layer and connected to an electrode of the active element, and on the first conductive layer It is formed, comprising a conductive post connecting the first conductive layer and a second conductive layer, a second insulating layer formed to cover the active element and the second conductive layer, the active element A printing plate in which the height and the height of the conductive posts are substantially the same, and the first insulating layer has a pattern in which the positions of the active elements and the conductive posts are masked, an epoxy resin, an acrylic resin, a polyimide resin, and PBO (Polyparaphenylene benzobisoxazole) resin, and , BCB by (benzocyclobutene) printing method using at least one or more liquid insulating resin selected from resins, it is formed in a region excluding a portion on the on the active element and the conductive post, the first An opening is formed in a portion where the conductive post and the second conductive layer are connected to the insulating layer, and the area of the opening is smaller than the area of the upper surface of the conductive post.

The above-described method for manufacturing a semiconductor device includes a step of forming a first conductive layer on a substrate, a step of forming a conductive post on the first conductive layer, and a step of mounting an active element on the substrate. And a step of covering the first conductive layer on the substrate, providing an opening on the upper surface of the conductive post, and forming the insulating layer by a printing method, and forming a second conductive layer on the insulating layer. you.

  As described above, in the semiconductor device of the present invention, the height of the active element mounted on the substrate and the height of the conductive post are formed substantially the same, that is, their upper surfaces are arranged on the substantially same surface. Then, a first insulating layer is formed between the active element and the conductive post and excluding the central portion of the upper surface of the conductive post. Further, the first insulating layer is formed without covering the upper part of the active element. With such a configuration of the semiconductor device, the first insulating layer is formed without covering the entire top surface of the conductive post. For this reason, the step of the insulating layer due to the thickness of the active element does not occur, and the flattening of the insulating layer becomes unnecessary. In addition, a process for exposing the conductive posts from the first insulating layer is not necessary. Therefore, the number of steps for manufacturing a semiconductor device can be reduced.

In the semiconductor device manufacturing method described above , the first insulating layer is formed by a printing method using, for example, a liquid insulating resin. In this manner, since the first insulating layer is formed by a printing method, an insulating layer with excellent flatness can be formed without performing planarization in another step. Further, when the first insulating layer is formed by the printing method, it is not necessary to expose the conductive post in another step by providing an opening on the upper surface of the conductive post. For this reason, the process for manufacturing a semiconductor device can be reduced.

  According to the present invention, the number of steps for manufacturing a semiconductor device can be reduced regardless of the thickness of the active element mounted on the substrate.

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

In the semiconductor device of the present embodiment, an active element 10 in which an electronic circuit including a semiconductor element such as a transistor is formed is mounted on a substrate 20.
In addition, a base insulating film 21 is formed on the substrate 20, and a first conductive layer 22 is formed in addition to a portion where the active element 10 is mounted, and is covered with a passivation film 23. Further, a first seed layer 24 and a conductive post 25 are formed on the first conductive layer 22, and a first insulating layer 26 is formed by embedding them. A second conductive layer 28 is formed on the conductive post 25 through a second seed layer 27 in a pattern connected to the pad electrode 12 of the active element 10, for example, and a second insulating layer 29 and an external electrode 33 are formed. Is formed.

The substrate 20 is constituted by an active element wafer in which an electronic circuit including a semiconductor element such as a transistor is provided on a substrate made of, for example, silicon.
In the present embodiment, the semiconductor device is configured by providing the active element 10 and the like over the substrate 20, but instead of the substrate 20, it is made of silicon or the like not provided with an electronic circuit including a semiconductor element such as a transistor. You may comprise a semiconductor device by using a base | substrate.

A pad electrode 12 is formed on the surface of the active element 10 on which an electronic circuit or the like is formed. Further, a passivation film 13 for protecting the circuit surface is formed by exposing the pad electrode 12.
The active element 10 is mounted on the substrate 20 by a die attach film 14, for example.
The die attach film 14 is provided, for example, on the surface opposite to the pad electrode 12 of the active element 10. Then, the active element 10 and the substrate 20 are bonded by the die attach film 14.

  The base insulating film 21 formed on the substrate 20 is made of, for example, silicon oxide. Further, a passivation film 23 is formed on the base insulating film 21 by exposing the first conductive layer 22 and a part of the first conductive layer 22.

  The first conductive layer 22 is made of, for example, Cu. The first conductive layer 22 forms wiring, lands, and the like for rearranging electrode positions on the substrate 20. Further, a passive element such as an inductor or a conductor (not shown) can be formed on the substrate 20 by using, for example, the first conductive layer 22.

The first seed layer 24 is provided as a base layer on the first conductive layer 22 and the passivation film 23 of the substrate 20 where the conductive posts 25 are formed.
The seed layer has a function of electrically connecting the electrode and the conductive layer as a base layer for forming the conductive layer on the electrode by electrolytic plating. The first seed layer 24 is formed of, for example, a 160 nm thick Ti film and a 600 nm thick Cu film. The first seed layer 24 is, for example, for forming a conductive layer connected to the first conductive layer 22 on the substrate 20 by electrolytic Cu plating. The first seed layer 24 is electrically conductive by electrolytic Cu plating. Electrically connect the layers.
Then, the conductive post 25 is formed on the first seed layer 24 by electrolytic plating or the like. The conductive post 25 is made of, for example, Cu.

The conductive post 25 is electrically connected to the first conductive layer 22 provided on the substrate 20. Then, in order to draw the first conductive layer 22 formed on the substrate to the upper part of the semiconductor device, the first conductive layer 22 is formed so as to penetrate vertically.
The conductive post 25 is formed to have substantially the same height as the height of the active element 10 and the thickness of the die attach film 14. For this reason, in this example, if the thickness of the active element 10 is 25 μm and the thickness of the die attach film 14 is 10 μm, the conductive post 25 has substantially the same height when formed with a thickness of 35 μm. In addition, the conductive post 25 is formed with an aspect ratio of 1 or more in order to prevent connection failure.

The first insulating layer 26 is formed on the substrate 20 except for the upper surface of the active element 10.
In addition, the first insulating layer 26 is formed in the upper part of the conductive post 25 with an opening 30 having an area smaller than the upper surface of the conductive post 25.
The first insulating layer 26 is formed thicker than the active element 10 and the conductive post 25. A slight step is provided between the active element 10 and the conductive post 25 and the first insulating layer 26. Further, the first insulating layer 26 is formed flat.
The first insulating layer 26 is formed on the substrate 20 with a width of 50 μm or more from the side surface of the active element 10 and the side surface of the conductive post 25, for example.
The first insulating layer 26 is formed of, for example, an epoxy resin, an acrylic resin, a polyimide resin, a PBO (polyparaphenylene benzobisoxazole) resin, a BCB (benzocyclobutene) resin, or the like.

The first insulating layer 26 is formed by a printing method, for example, by screen printing using a printing plate. Therefore, the first insulating layer 26 is formed by applying a liquid insulating resin to a pattern determined by a printing method and then curing the insulating resin.
By forming the first insulating layer 26 as described above, it is not necessary to use a photosensitive resin as a material for forming the first insulating layer 26. For this reason, the cost at the time of manufacturing a semiconductor device can be reduced. Further, since it is not necessary to perform a photolithography process for patterning the photosensitive resin, the number of processes for manufacturing a semiconductor device can be reduced.

Further, for example, by using a printing plate having a predetermined pattern in which the positions of the active elements and the conductive posts are masked, an insulating layer having openings provided on the active elements and the conductive posts can be formed.
In the case of the printing method, the insulating layer can be formed flat in one step regardless of the thickness of the active element without forming the insulating layer on the active element. For this reason, the work of planarizing the insulating layer becomes unnecessary, and the number of steps for manufacturing a semiconductor device can be reduced.
Furthermore, since the opening is provided in the upper part of the conductive post, an operation for exposing the upper part of the conductive post becomes unnecessary. For this reason, the number of processes for manufacturing a semiconductor device can be reduced.

  The second seed layer 27 is provided as a plating base layer on the first insulating layer 26 where the second conductive layer 28 is formed. The second seed layer 27 is made of, for example, a 160 nm thick Ti film and a 600 nm thick Cu film. The second seed layer 27 electrically connects the conductive post 25 and the second conductive layer 28.

The second conductive layer 28 is formed on the second seed layer 27. Then, the opening 30 of the first insulating layer 26 is filled with a conductor, so that the conductive post 25 and the second conductive layer 28 are electrically connected via the second seed layer 27. Also. By the second conductive layer 28, the pad electrode 12 of the active element 10 and the first conductive layer 22 are electrically connected via the conductive post 25.
The second conductive layer 28 forms wirings, lands, and the like for rearranging the electrode positions on the first insulating layer 26. Further, a passive element such as an inductor or a conductor (not shown) can be formed on the first insulating layer 26 by using, for example, the second conductive layer 28.

The second insulating layer 29 is formed on the substrate 20 so as to cover the second conductive layer 28 and the active element 10. As a material of the second insulating layer 29, for example, an epoxy resin, an acrylic resin, a polyimide resin, a PBO resin, a BCB resin, or the like is used.
The second insulating layer 29 is provided with an opening 31 where the external electrode 33 is formed. A bump-like external electrode 33 is formed in the opening 31 by, for example, solder balls, solder printing, solder plating, or the like. The external electrode 33 is provided in accordance with the arrangement of electrodes and the like of the external device in order to connect the semiconductor device and the external device.

In the above-described embodiment, the active element 10 is covered with the second insulating layer 29, and the insulating layer 29 is further patterned so that the pad electrode 12 is rewired by the second conductive layer 28. is there.
For this reason, for example, even when the active element is mounted face up, the step due to the thickness of the active element can be eliminated without forming a recess by digging in the substrate to mount the active element. . Therefore, it is possible to prevent an opening defect, for example, pattern crushing, caused by a step difference between the active element electrode and the lower conductive layer.

In the above example, the sum of the thickness of the active element and the die attach film and the thickness of the conductive post are substantially the same, and the height of the active element and the conductive post are substantially the same. The heights do not have to be exactly the same, as long as they do not cause a defective opening or pattern collapse due to the step corresponding to the thickness of the active element described above. Specifically, if the range of variation in the height direction between the active element and the conductive post is within 15 μm, the opening defect and the pattern collapse due to the difference in height do not occur. For this reason, the active element and the conductive post need only have substantially the same height with an error of about 7.5 μm or less.
Further, since it is not necessary to form a recess, an active element wafer having an electronic circuit and electrodes formed on the surface can be used as a substrate on which an active element is mounted.

Next, an example of a method for manufacturing a semi-conductor device.
First, as shown in FIG. 2A, a substrate 20 is formed of, for example, an active element wafer, and an electronic circuit including an active element such as a transistor (not shown) and a base insulating film 21 are formed. And it forms with the 1st conductive layer 22 connected to this electronic circuit.
In addition, a scribe line 39 is formed around the electronic circuit (not shown), the first conductive layer 22, and the base insulating film 21 formed on the substrate 20 in accordance with the size to be separated in a later process.
Further, a passivation film 23 is formed to cover the electronic circuit except on the first conductive layer 22 and the scribe line 39.

Next, as shown in FIG. 2B, a conductive post connected to the first conductive layer 22 is formed on the substrate 20 by electrolytic Cu plating. Also, the first conductive layer 22 and the conductive post are formed. Are electrically connected to each other, a first seed layer 24 is formed.
The first seed layer 24 is formed, for example, by sputtering, for example, by forming a Ti film with a thickness of 160 nm and then forming a Cu film thereon with a thickness of 600 nm.

  Next, a resist layer 40 is formed on the entire surface of the first seed layer 24 by spin coating, vacuum lamination, or the like. Then, the resist layer 40 is exposed and developed by a photolithography process, and as shown in FIG. 2C, a portion of the resist layer 40 where the conductive post 25 is formed is removed in a subsequent process.

Then, as shown in FIG. 3D, a conductive layer 25 is formed by growing a Cu layer on the portion where the resist layer 40 has been removed, for example, by electrolytic plating.
The electrolytic plating at this time is performed at a current density of 1.5 A / dm ² , for example.
The conductive post 25 is formed to have a thickness substantially the same as the total thickness of the active element 10 and the die attach film 14 to be mounted on the substrate 20 in a later step. For example, if the thickness of the active element 10 is 25 μm and the thickness of the die attach film 14 is 10 μm, the conductive post 25 is formed with a thickness of about 35 μm so that the height is substantially the same as that of the active element 10. . The conductive post 25 is formed with an aspect ratio of 1 or more in order to prevent poor connection.

  Next, as shown in FIG. 3E, after removing the resist layer 40 with a solvent or the like, the unnecessary first seed layer 24 is removed. The removal of the first seed layer 24 is performed by wet etching or the like using the conductive post 25 as a mask. First, the upper Cu layer is removed, and then the lower Ti layer is removed.

Next, as shown in FIG. 3F, the thinned active element 10 is mounted on the substrate 20 face up. The thinning of the active element 10 is performed, for example, by grinding the back surface of the wafer on which the electronic circuit including the active element such as a transistor is formed, laminating the die attach film 14, and then dicing. Then, the active element 10 provided with the die attach film 14 on the back surface is mounted on the passivation film 23 of the substrate 20 except the portion where the conductive post 25 is formed. The active element 10 is mounted, for example, under the conditions of a weight of 2.5 N, a temperature of 230 ° C., and a push amount of 0.3 mm.
Here, for example, when the thickness of the active element 10 is 25 μm or more and the thickness of the die attach film 14 is 10 μm or more, the active element 10 is mounted at a height of 35 μm or more from the surface of the substrate 20.
This mounting can be performed with an accuracy of ± 2.5 μm by positioning, for example, a characteristic pattern of the active element wafer, the conductive post 25, or the like. Thereby, displacement of the active element 10 can be prevented, and poor connection with the conductive layer can be prevented.

Next, as shown in FIG. 4G, after mounting the active element 10, the printing plate 42 is aligned on the substrate 20. A pattern for forming the first insulating layer 26 is formed on the printing plate 42 by a printing method.
The alignment between the substrate 20 and the printing plate 42 is performed by, for example, forming an alignment mark for printing on the active element 10 in advance and aligning the printing plate 42 with the alignment mark. Alternatively, the characteristic pattern of the active element 10 may be used as an alignment for printing, and the active element 10 and the printing plate 42 may be aligned. The alignment accuracy of the printing plate 42 at this time is, for example, about ± 10 μm.
The aligned printing plate 42 is adhered to the upper surface of the active element 10 and the upper surface of the conductive post.

  The pattern formed on the printing plate 42 has a configuration in which portions other than between the active element 10 and the conductive post 25 and between the conductive post 25 and the scribe line 39 are masked. Further, the masking of the printing plate 42 on the conductive post 25 is a pattern having an opening with an area smaller than the area of the upper surface of the conductive post 42.

Further, the printing plate 42 is formed with a stopper portion 43 having a thickness different from that of other portions on the printing plate 42 located on the scribe line 39 so that the resin printed on the scribe line 39 does not flow. Has been.
When the printing plate 42 is brought into close contact with the substrate 20, the stopper portion 43 covers the scribe line 39 and comes into close contact therewith. For this reason, it is possible to prevent the resin from flowing into the scribe line 39. Furthermore, an insulating resin by printing can be formed between the stopper portion 43 and the conductive post 25.

  Next, as shown in FIG. 4H, the first insulating layer 26 is formed by a printing method. As the material of the first insulating layer 26, for example, an epoxy resin, an acrylic resin, a polyimide resin, or a PBO resin is used. The first insulating layer 26 is formed by using a liquid insulating resin 45 with, for example, a metal squeegee 44 at an attack angle of 60 ° to 70 °, a speed of 10 to 20 mm / s, and a printing pressure of 0.25 Mpa. In addition, the first insulating layer 26 takes into consideration the active element 10 and the detachment of the printing resin 26 to the back side of the printing plate 42 when the printing plate 42 is separated from the substrate 20. The conductive post 25 is formed with a width of 50 μm or more.

Further, by printing the insulating resin by bringing the printing plate 42 into close contact with the active element 10 and the conductive post, the first insulating resin is more than the active element 10 and the conductive post 25 by the thickness of the printing plate 42. Is formed thick.
Then, the printing plate 42 on the conductive post 25 is masked with an area smaller than the area of the upper surface of the conductive post 25, so that the opening of the first insulating layer 26 is formed at the center on the conductive post 25. Part 30 is formed. Here, when the opening area of the masking on the conductive post 25 is larger than the upper surface of the conductive post 25, the liquid resin does not flow around the back side of the masked printing plate 42, and the conductive post 25. The side of will be exposed. In this case, a step is formed in the first insulating layer 26 near the side surface of the conductive post 25.
However, as shown in FIGS. 4G and 4H, the masking area of the printing plate 42 on the conductive post 25 is made smaller than the area of the upper surface of the conductive post 25, so that the conductive post 25 is formed. The first insulating layer 26 can be formed without generating a step on the side surface. Further, the conductive post 25 can be covered and protected by an insulating resin.

As described above, by printing with the printing plate 42 in close contact with the upper surfaces of the active element 10 and the conductive posts 25, the first insulating layer 26 having a flat upper surface can be formed by a simple method. . For this reason, it is not necessary to planarize the insulating layer in another process.
Further, by making the masking of the printing plate 42 on the conductive post 25 smaller than the area of the upper surface of the conductive post 25, the opening 30 can be reliably formed on the conductive post 25. For this reason, it is not necessary to remove the insulating layer for exposing the surface of the conductive post.
Therefore, it is possible to reduce the number of processes when manufacturing a semiconductor device.

  Further, according to this method, for example, if the height of the active element and the height of the conductive post are formed substantially the same, the insulating layer can be formed by a printing method regardless of the thickness of the active element. For this reason, for example, when the insulating layer is formed thick using a photosensitive resin, the semiconductor device can be stably manufactured without causing adverse effects such as pattern collapse that occurs during exposure. .

  Next, the liquid insulating resin pattern formed by the printing method is cured to remove the upper surface of the active element 10, the conductive post 25, and the scribe line 39 as shown in FIG. 4 (i). Thus, the first insulating layer 26 is formed.

Next, as shown in FIG. 5 (j), the second conductive layer is formed on the conductive post 25 by electrolytic Cu plating, and the conductive post 25 is connected to the second conductive layer. Then, the second seed layer 27 is formed.
The second seed layer 27 is formed by, for example, forming a Ti film with a thickness of 160 nm, for example, by sputtering, and then forming a Cu film with a thickness of, for example, 600 nm on the Ti film.

  Next, a resist layer 41 is formed on the entire surface of the second seed layer 27 by spin coating, vacuum lamination, or the like. Then, the resist layer 41 is exposed and developed by a photolithography process, and, as shown in FIG. 5K, patterning is performed to remove a portion where the second conductive layer is to be formed in a later process.

Next, as shown in FIG. 5L, a Cu layer is grown on the portion from which the resist layer 41 has been removed, for example, by electroplating to form the second conductive layer 28.
The electrolytic plating at this time is performed, for example, at a current density of 1.5 A / dm ² and the thickness of the second conductive layer 28 is set to 7 μm, for example.

  Next, as shown in FIG. 6 (m), the resist layer 41 is removed with a solvent or the like. Further, as shown in FIG. 6 (n), the unnecessary second seed layer 27 is removed. The second seed layer 27 is removed by wet etching or the like using the second conductive layer 28 as a mask. First, the upper Cu layer or the like is removed, and then the lower Ti layer or the like is removed.

  Next, as shown in FIG. 6O, a second insulating layer 29 is applied to the entire surface of the substrate 20 on which the second conductive layer 28 is formed. The second insulating layer 29 is formed of an insulating film such as an epoxy resin, an acrylic resin, a polyimide resin, a PBO resin, or a BCB resin using a method such as a spin coating method, a film laminating method, a printing method, or a dispensing method. To do.

  Next, as shown in FIG. 7 (p), the second insulating layer 28 is formed so as to form openings in the opening 31 for connecting the second conductive layer 28 and the external electrode 33 and the scribe line 39. Layer 29 is patterned. For example, when the second insulating layer 29 is formed of a photosensitive material, as shown in FIG. 6 (o), the insulating material is applied to the entire surface of the substrate 20 and then aligned with the opening. Exposure is performed using a photomask on which a pattern is formed. Then, the second insulating layer 29 can be formed by removing an unnecessary portion of the insulating layer by development.

  Next, as shown in FIG. 7 (q), bump-shaped external electrodes 33 are formed in the openings 31. The external electrode 33 is performed by mounting solder balls, solder printing, or solder plating. For example, when a solder ball is mounted as the external electrode 33, a flux is applied to the opening 31, and then the solder ball is attached and fusion bonding is performed by reflow. Then, after the solder balls are joined, the flux is washed.

Next, the semiconductor device shown in FIG. 7R can be formed by thinning the substrate 20 into pieces.
Thinning is performed by, for example, half-cutting the scribe line 39 formed on the substrate 20 deeper than the final thickness of the substrate 20, for example, about 70 μm from the final thickness. Then, thinning can be performed by grinding the back surface of the substrate 20 by back grinding.
Further, for example, by grinding the back surface of the substrate 20 to the finished thickness by back grinding and performing full-cut dicing on the scribe line 39, thinning can be performed.
Through the above steps, the semiconductor device of this embodiment can be manufactured.

As described above, according to the method for manufacturing a semiconductor device , an insulating layer having a flat upper surface can be formed by forming the first insulating layer by a printing method. Therefore, an insulating layer with excellent flatness can be formed without planarizing the insulating layer in another step.
In addition, when the first insulating layer is formed by a printing method, a liquid insulating resin is used. Since the liquid resin has viscosity, the pattern formed by printing does not collapse even after the printing plate is removed, and the insulating layer can be stably formed.

  In the semiconductor device of the present invention, the conductive post is formed at a height substantially the same as the height of the active element mounted on the substrate. For this reason, when forming the first insulating layer by the printing method, it is not necessary to expose the conductive post in another step by providing the opening on the upper surface of the conductive post. Therefore, the number of steps for manufacturing a semiconductor device can be reduced.

In addition, by using an active element having an electronic circuit and an electrode formed on the surface as a substrate and stacking the active elements, the semiconductor device can have multiple functions.
In addition, since the second insulating layer is formed so as to cover the active element and the second conductive layer, the second conductive layer can be protected and the external shape of the semiconductor device can be adjusted.

  The present invention is not limited to the above-described configuration, and various other configurations can be employed without departing from the gist of the present invention.

It is sectional drawing of the semiconductor device by one embodiment of this invention. (A) ~ (c) is a manufacturing process drawing of the semi-conductor device. (D) ~ (f) is a manufacturing process drawing of the semi-conductor device. (G) ~ (i) is a manufacturing process drawing of the semi-conductor device. (J) ~ (l) is a manufacturing process drawing of the semi-conductor device. (M) ~ (o) is a manufacturing process drawing of the semi-conductor device. (P) ~ (r) is a manufacturing process drawing of the semi-conductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Active element, 12 Pad electrode, 13, 23 Passivation film | membrane, 14 Die attach film, 20 Substrate, 21 Base insulating layer, 22 1st conductive layer, 24 1st seed layer, 25 Conductive post, 26 1st Insulating layer, 27 Second seed layer, 28 Second conductive layer, 29 Second insulating layer, 30, 31 opening, 33 External electrode, 39 Scribe line, 40, 41 Resist layer, 42 Printing plate, 43 Stopper Part, 44 squeegee, 45 liquid insulating resin

Claims (1)

A semiconductor substrate on which an electronic circuit including a semiconductor element and an electrode are formed ;
A first conductive layer formed on the semiconductor substrate ;
A first insulating layer formed to cover the semiconductor substrate and the first conductive layer;
An active element mounted on the semiconductor substrate ;
A second conductive layer formed on the first insulating layer and connected to an electrode of the active element;
A conductive post formed on the first conductive layer and connecting the first conductive layer and the second conductive layer;
A second insulating layer formed to cover the active element and the second conductive layer,
The height of the active element and the height of the conductive post are substantially the same,
A printing plate having a pattern in which the position of the active element and the conductive post is masked by the first insulating layer , an epoxy resin, an acrylic resin, a polyimide resin, a PBO (polyparaphenylene benzobisoxazole) resin, and Formed in a region excluding a part on the active element and the conductive post by a printing method using at least one kind of liquid insulating resin selected from BCB (benzocyclobutene) resin ,
An opening is formed in a portion where the conductive post and the second conductive layer are connected to the first insulating layer, and the area of the opening is smaller than the area of the upper surface of the conductive post apparatus.

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