CN103579168B - Substrate structure and packaging piece with same - Google Patents
Substrate structure and packaging piece with same Download PDFInfo
- Publication number
- CN103579168B CN103579168B CN201210275824.0A CN201210275824A CN103579168B CN 103579168 B CN103579168 B CN 103579168B CN 201210275824 A CN201210275824 A CN 201210275824A CN 103579168 B CN103579168 B CN 103579168B
- Authority
- CN
- China
- Prior art keywords
- opening
- substrate body
- semiconductor chip
- metal level
- packaging part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 title claims abstract description 46
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims description 23
- 239000010410 layer Substances 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 3
- 230000032798 delamination Effects 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 7
- 239000003292 glue Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- -1 Poly(phenyleneether) Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 229920002521 macromolecule Polymers 0.000 description 2
- 241000531908 Aramides Species 0.000 description 1
- 241000969130 Atthis Species 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229920006231 aramid fiber Polymers 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
A substrate structure and a package with the substrate structure are provided, the substrate structure includes a substrate body, a metal layer, an insulating protection layer and a chip placement area, the metal layer is formed on a surface of the substrate body, the insulating protection layer is formed on the surface of the substrate body and has an opening exposing the metal layer, the chip placement area is defined on the surface of the substrate body for connecting a semiconductor chip on the surface, wherein one chip placement area corresponds to one opening, the scope of the chip placement area covers the whole of the opening, or the metal layer does not exceed the scope of the chip placement area. The invention can effectively reduce the delamination phenomenon of the packaging piece so as to improve the yield.
Description
Technical field
The present invention has about a kind of board structure and packaging part, espespecially a kind of for chip packageBoard structure and packaging part.
Background technology
General flip chip comprises that covering geode grid array (FCBGA) encapsulates (as shown in Figure 1)And crystal covered chip size encapsulation (flipchipchipscalepackage, FCCSP) two kinds, itsBoth are difference: cover the large and thickness of the base plate for packaging of geode grid array (FCBGA) encapsulationHeight, therefore rigidity is stronger, and uses at CPU (CPU) and GPU more(GPU) carrying and be electrically connected above, covers geode grid array (FCBGA) encapsulation conventionallyMethod for making first connects semiconductor chip 11 to be placed on base plate for packaging 10, and in semiconductor chip 11 with10 of base plate for packaging are filled with protection glue material 12 with capillary bottom (CUF) technology of filling, to protectProtect soldered ball 13 and make non-active of this semiconductor chip 11 111 exposed so that this is non-activeFace 111 is as connecing the use of putting radiating piece (not icon).
Relatively, as shown in Fig. 2 A and Fig. 2 B, be respectively existing crystal covered chip size encapsulation(FCCSP) cutaway view of packaging part and the top view of base plate for packaging, crystal covered chip size envelopeDress (FCCSP), for the less and thin base plate for packaging 20 of area, is generally used for mobile electronicsIn product, its packaged type adopts so-called molding bottom to fill (MUF) technology, namelyNeed not be if aforementioned geode grid array (FCBGA) the encapsulation ground that covers be in semiconductor chip and base plate for packagingBetween be filled with protection glue material, but directly straight with encapsulating material (Moldingcompound) 22Connect semiconductor chip 21 is coated on base plate for packaging 20 completely, and this encapsulating material 22 is filled outFill between semiconductor chip 21 and base plate for packaging 20. Crystal covered chip size encapsulation (FCCSP)Without filling protection glue material between semiconductor chip and base plate for packaging in the another end of filling, with save man-hour andCost, can directly be coated semiconductor chip 21 with protection semiconductor with encapsulating material 22 again completelyChip 21 is not destroyed by external environment, and the rigidity of this encapsulating material 22 is stronger, so can makeObtain whole flip chip and be difficult for warpage, and then improve reliability issues.
In some situation, the base plate for packaging 20 of crystal covered chip size encapsulation (FCCSP) useThe copper layer 201 of middle section need partly be revealed in outside insulating protective layer 23, for heat radiation, electricalThe purposes such as conduction or ground connection.
But the semiconductor chip 21 in crystal covered chip size encapsulation (FCCSP) is projected to copperThe marginal position A place of layer 201 has larger stress, therefore in the time of temperature reliability test, shouldOften can there is the problem that encapsulating material 22 and copper layer 201 are peeled off in marginal position A, and cause wholeBase plate for packaging 20 cannot pass through reliability test.
Therefore, how to avoid above-mentioned variety of problems of the prior art, become at present and desire most ardently in factThe problem solving.
Summary of the invention
Because the defect of above-mentioned prior art, main purpose of the present invention is to provide a kind of baseThe packaging part of plate structure and this board structure of tool, can effectively reduce the delamination of packaging part, withPromote yield.
Board structure of the present invention comprises: board structure, and it comprises: substrate body; Metal level,It is formed on a surface of this substrate body; Insulating protective layer, it is formed at this substrate bodyThis surface on, and there is at least one opening that exposes this metal level; And at least one crystalline setting area,It is defined in this surface of this substrate body, puts semiconductor chip for connecing on this surface,Wherein, this crystalline setting area corresponding this opening, the scope of this crystalline setting area contains this openingAll, or this metal level does not exceed the scope of this crystalline setting area.
The present invention also provides a kind of packaging part, and it comprises: substrate body; Metal level, its formationOn a surface of this substrate body; Insulating protective layer, it is formed at this table of this substrate bodyOn face, and there is at least one opening that exposes this metal level; And at least one semiconductor chip,It connects and is placed on this metal level, wherein, corresponding this opening of this semiconductor chip, one should be partlyConductor chip is contained the whole of this opening in this surperficial drop shadow spread of this substrate body, orPerson, this metal level does not exceed this semiconductor chip this surperficial drop shadow spread in this substrate body.
As from the foregoing, because making semiconductor chip be projected to substrate body surface, the present invention do not depositThere iing the metal level exposing, and reducing the overall exposed area of metal level, so follow-up in this goldBelong to after the upper covering of layer encapsulating material, be difficult for occurring the heterogeneous of existing encapsulating material and metal interlevel(principle is that metal and encapsulating material are heterogeneous, and its adherence is compared with homogeneity for the delamination at junction placeAdherence between macromolecule for example, for poor: encapsulating material, insulating protective layer or substrate body tableAdherence between the dielectric layer (homogeneity class) of face is good), and then promote overall yield.
Brief description of the drawings
That shown in Figure 1 is the existing cutaway view that covers brilliant BGA packages.
Fig. 2 A and Fig. 2 B those shown are respectively the cuing open of packaging part of existing crystal covered chip size encapsulationThe top view of view and base plate for packaging.
That shown in Figure 3 is the cutaway view of the first embodiment of board structure of the present invention and packaging part.
That shown in Figure 4 is the cutaway view of the second embodiment of board structure of the present invention and packaging part.
Primary clustering symbol description
10,20 base plate for packaging
11,21,33 semiconductor chips
111 non-active
12 protection glue materials
13,36 soldered balls
22,34 encapsulating materials
201 bronze medal layers
23,32 insulating protective layers
A marginal position
30 substrate body
30a, 30b surface
300 crystalline setting areas
31 metal levels
320 openings
35 solder ball pads.
Detailed description of the invention
Below by particular specific embodiment explanation embodiments of the present invention, art technologyPersonnel can understand other advantage of the present invention and merit easily by content disclosed in the present specificationEffect.
Notice, appended graphic the illustrated structure of this description, ratio, size etc., all only useTo coordinate the content that description was disclosed, for those skilled in the art's understanding and reading, andNon-in order to limit the enforceable qualifications of the present invention, therefore the technical essential meaning of tool is not appointedThe adjustment of the modification of what structure, the change of proportionate relationship or size, is not affecting institute of the present invention energyUnder the effect producing and the object that can reach, all should still drop in disclosed technologyIn the scope that Rong get Neng is contained. Meanwhile, in this description, quote as " on ", " central authorities ",The term such as " drop shadow spread " and " one ", also only for ease of understanding of narrating, but not in order to limitDetermine the enforceable scope of the present invention, the change of its relativeness or adjustment, changing skill without essenceIn art, hold, when being also considered as the enforceable category of the present invention.
The first embodiment
That shown in Figure 3 is analysing and observe of the first embodiment of board structure of the present invention and packaging partFigure. It first provides a kind of board structure, and this board structure comprises: substrate body 30, its materialCan be ABF (AjinomotoBuild-upFilm), BCB (Benzocyclo-buthene),LCP(LiquidCrystalPolymer)、PI(Poly-imide)、PPE(Poly(phenyleneether))、PTFE(Poly(tetra-fluoroethylene))、FR4、FR5、BT(BismaleimideTriazine), aramid fiber (Aramide) or blending epoxy glass fibre (Glassfiber);Metal level 31, it is formed at a surperficial 30a of this substrate body 30; Insulating protective layer 32 (asAnti-welding green paint), its this surface 30a that is formed at this substrate body 30 is upper, and has and expose this goldBelong to the opening 320 of layer 31; And crystalline setting area 300, it is defined in this table of this substrate body 30Face 30a, for connecing and put semiconductor chip 33 on the 30a of this surface, wherein, one this put crystalline substanceCorresponding this opening 320 in district 300, the scope of this crystalline setting area 300 contains the complete of this opening 320Portion, and better this opening 320 central authorities that are positioned in this crystalline setting area 300.
The packaging part of the present embodiment connects and puts semiconductor core in 300 places, crystalline setting area of aforesaid base plate structureSheet 33, makes this semiconductor chip 33 be positioned at this opening 320 central authorities, wherein, and this semiconductorCorresponding this opening 320 of chip 33, this semiconductor chip 33 is at this table of this substrate body 30The whole of this opening 320 are contained in the drop shadow spread of face 30a, and this semiconductor chip 33 is flatFace size is greater than the size of this opening 320.
In aforesaid packaging part, also comprise encapsulating material 34, it is formed at this substrate body 30This surface 30a upper, to be coated this semiconductor chip 33.
In described packaging part, this semiconductor chip 33 connects and is placed in this metal level 31 to cover crystal typeUpper, and the material of this metal level 31 is copper.
In the packaging part of the present embodiment, another surperficial 30b of this substrate body 30 also has multipleSolder ball pad 35, and also comprise soldered ball 36, it connects and is placed in respectively on this solder ball pad 35.
The second embodiment
That shown in Figure 4 is analysing and observe of the second embodiment of board structure of the present invention and packaging partFigure. It first provides a kind of board structure, and this board structure comprises: substrate body 30; Metal level31, it is formed at a surperficial 30a of this substrate body 30; Insulating protective layer 32, it is formed atThis surface 30a of this substrate body 30 is upper, and has the opening 320 that exposes this metal level 31;And crystalline setting area 300, it is defined in this surface 30a of this substrate body 30, in this tableOn face 30a, connect and put semiconductor chip 33, wherein, this metal level 31 does not exceed this crystalline setting area 300Scope, and better this opening 320 central authorities that are positioned in this crystalline setting area 300.
The packaging part of the present embodiment connects and puts semiconductor core in 300 places, crystalline setting area of aforesaid base plate structureSheet 33, makes this semiconductor chip 33 be positioned at this opening 320 central authorities, wherein, and this metal level31 do not exceed the drop shadow spread of this semiconductor chip 33 at this surface of this substrate body 30 30a.
The further feature of the present embodiment is roughly identical with last embodiment, therefore do not repeated at this.
Be noted that in board structure of the present invention and packaging part, this opening 320 also canExpose the dielectric layer (not icon) on these substrate body 30 surfaces, and this metal level 31 also can wrapVinculum road (not icon) and cooling pad (not icon).
In sum, than prior art, because making semiconductor chip, the present invention is projected to basePlate body surface place does not have the metal level exposing, and reduces the overall exposed area of metal level,Cover after encapsulating material on this metal level so follow-up, be difficult for occur existing encapsulating material withThe delamination at the heterojunction place of metal interlevel (principle is that metal and encapsulating material are heterogeneous, itsAdherence is poor compared with the adherence between the macromolecule of homogeneity, for example: encapsulating material, insulation protectionAdherence between the dielectric layer (homogeneity class) on layer or substrate body surface is good), and then promote wholeBody yield.
Above-described embodiment is only in order to illustrative principle of the present invention and effect thereof, but not forRestriction the present invention. Any those skilled in the art all can be without prejudice to spirit of the present invention and categoryUnder, above-described embodiment is modified. Therefore the scope of the present invention, should be as rightClaim is listed.
Claims (12)
1. a board structure, comprising:
Substrate body;
Metal level, it is formed on a surface of this substrate body;
Insulating protective layer, it is formed on this surface of this substrate body, and has and expose this goldBelong at least one opening of layer; And
At least one crystalline setting area, it is defined in this surface of this substrate body, on this surfaceConnect and put semiconductor chip, and for forming coated this semiconductor chip on this surface and inserting thisEncapsulating material in opening, wherein, corresponding this opening in this crystalline setting area, this crystalline setting areaScope contains the whole of this opening, or this metal level does not exceed the scope of this crystalline setting area.
2. board structure according to claim 1, is characterized in that, this crystalline setting area is positioned at thisOpening central authorities.
3. board structure according to claim 1, is characterized in that, this opening also exposes thisThe dielectric layer on substrate body surface.
4. board structure according to claim 1, is characterized in that, this metal level also comprisesCircuit and cooling pad.
5. a packaging part, comprising:
Substrate body;
Metal level, it is formed on a surface of this substrate body;
Insulating protective layer, it is formed on this surface of this substrate body, and has and expose this goldBelong at least one opening of layer;
At least one semiconductor chip, it connects and is placed on this metal level, wherein, this semiconductor coreCorresponding this opening of sheet, this semiconductor chip is in this surperficial drop shadow spread of this substrate bodyContain the whole of this opening, or this metal level does not exceed this semiconductor chip at this substrateThis surperficial drop shadow spread of body; And
Encapsulating material, it is formed on this surface of this substrate body and in this opening, to be coatedThis semiconductor chip.
6. packaging part according to claim 5, is characterized in that, this semiconductor chip is to coverCrystal type connects and is placed on this metal level.
7. packaging part according to claim 5, is characterized in that, the material of this metal level isCopper.
8. packaging part according to claim 5, is characterized in that, another of this substrate bodySurface also has multiple solder ball pads.
9. packaging part according to claim 8, is characterized in that, this packaging part also comprises welderingBall, it connects and is placed in respectively on this solder ball pad.
10. packaging part according to claim 5, is characterized in that, this semiconductor chip positionIn these opening central authorities.
11. packaging parts according to claim 5, is characterized in that, this opening also exposes thisThe dielectric layer on substrate body surface.
12. packaging parts according to claim 5, is characterized in that, this metal level also comprisesCircuit and cooling pad.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101125980 | 2012-07-19 | ||
| TW101125980A TWI463610B (en) | 2012-07-19 | 2012-07-19 | Substrate structure and die package integrating the substrate structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103579168A CN103579168A (en) | 2014-02-12 |
| CN103579168B true CN103579168B (en) | 2016-05-04 |
Family
ID=50050618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210275824.0A Active CN103579168B (en) | 2012-07-19 | 2012-08-03 | Substrate structure and packaging piece with same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103579168B (en) |
| TW (1) | TWI463610B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI569339B (en) * | 2015-01-06 | 2017-02-01 | 矽品精密工業股份有限公司 | Method of fabricating a package structure and a package substrate thereof |
| TWI629756B (en) * | 2017-08-14 | 2018-07-11 | 矽品精密工業股份有限公司 | Package structure and its package substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101064259A (en) * | 2006-04-25 | 2007-10-31 | 矽品精密工业股份有限公司 | Semiconductor package and its chip bearing structure and production method |
| JP4052237B2 (en) * | 2003-12-12 | 2008-02-27 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291268B1 (en) * | 2001-01-08 | 2001-09-18 | Thin Film Module, Inc. | Low cost method of testing a cavity-up BGA substrate |
| JP2004063770A (en) * | 2002-07-29 | 2004-02-26 | Fujitsu Ltd | Method of forming connection structure between electrodes |
| JP4528062B2 (en) * | 2004-08-25 | 2010-08-18 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| CN100485894C (en) * | 2005-09-20 | 2009-05-06 | 全懋精密科技股份有限公司 | Flip chip packaging method and packaging structure thereof |
| DE102005055280B3 (en) * | 2005-11-17 | 2007-04-12 | Infineon Technologies Ag | Connecting elements for semiconductor components have mushroom shape with first metal area filling out indentations on top of insulating layer and with second metal area on containing refractory inter-metallic phases of metals of solder |
| CN101364582A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Loading board construction embedded with chip and preparation thereof |
| TWI389220B (en) * | 2007-10-22 | 2013-03-11 | 矽品精密工業股份有限公司 | Semiconductor package and method for fabricating the same |
| TWI349994B (en) * | 2008-01-30 | 2011-10-01 | Advanced Semiconductor Eng | Package process for embedded semiconductor device |
-
2012
- 2012-07-19 TW TW101125980A patent/TWI463610B/en active
- 2012-08-03 CN CN201210275824.0A patent/CN103579168B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4052237B2 (en) * | 2003-12-12 | 2008-02-27 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| CN101064259A (en) * | 2006-04-25 | 2007-10-31 | 矽品精密工业股份有限公司 | Semiconductor package and its chip bearing structure and production method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103579168A (en) | 2014-02-12 |
| TW201405718A (en) | 2014-02-01 |
| TWI463610B (en) | 2014-12-01 |
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