TW202103271A - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

Info

Publication number
TW202103271A
TW202103271A TW108123412A TW108123412A TW202103271A TW 202103271 A TW202103271 A TW 202103271A TW 108123412 A TW108123412 A TW 108123412A TW 108123412 A TW108123412 A TW 108123412A TW 202103271 A TW202103271 A TW 202103271A
Authority
TW
Taiwan
Prior art keywords
encapsulation layer
electronic component
electronic package
scope
patent application
Prior art date
Application number
TW108123412A
Other languages
Chinese (zh)
Other versions
TWI690039B (en
Inventor
唐紹祖
馬伯豪
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW108123412A priority Critical patent/TWI690039B/en
Priority to CN201910624358.4A priority patent/CN112185903A/en
Application granted granted Critical
Publication of TWI690039B publication Critical patent/TWI690039B/en
Publication of TW202103271A publication Critical patent/TW202103271A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

This invention provides an electronic package and a manufacturing method thereof, in which an electronic component is disposed on a carrier by the manner of flip chip, and the electronic component is covered by an encapsulation layer. In addition, part of the material of the encapsulation layer, part of the material of the electronic component, and part of the material of the carrier are removed by the leveling operation to reduce the overall thickness of the electronic package.

Description

電子封裝件及其製法 Electronic package and its manufacturing method

本發明係有關一種半導體封裝製程，尤指一種電子封裝件及其製法。 The present invention relates to a semiconductor packaging manufacturing process, in particular to an electronic packaging component and its manufacturing method.

目前應用於晶片封裝領域之技術繁多，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型封裝製程、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊製程。 There are many technologies currently used in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA), or Multi-Chip Module (Multi-Chip Module). MCM) and other flip-chip packaging processes, or the three-dimensional stacking and integration of chips into a three-dimensional integrated circuit (3D IC) chip stacking process.

如第1圖所示，習知四方平面無引腳(Quad Flat No leads，簡稱QFN)型式之半導體封裝件1，係將半導體晶片11藉由複數銲錫凸塊110以覆晶方式接置於一導線架10上，再以封裝膠體12包覆該半導體晶片11、導線架10及銲錫凸塊110，之後進行切割，以令該導線架10之各導腳100的側面(Side Surface)及底面(Bottom Surface)外露出該封裝膠體12，並使各該導腳100之底面與該封裝膠體12之底面齊平。 As shown in Figure 1, the conventional Quad Flat No leads (QFN) type semiconductor package 1 has a semiconductor chip 11 connected by flip-chip through a plurality of solder bumps 110. On the lead frame 10, the semiconductor chip 11, the lead frame 10, and the solder bumps 110 are covered with the encapsulant 12, and then cut to make the side surface and bottom surface of each lead 100 of the lead frame 10 The Bottom Surface) exposes the encapsulation compound 12, and makes the bottom surface of each lead 100 and the bottom surface of the encapsulation body 12 flush.

另一方面，為符合薄化需求，需先降低該半導體晶片11之厚度d，再將該半導體晶片11接置於該導線架10上。 On the other hand, in order to meet the thinning requirement, the thickness d of the semiconductor chip 11 needs to be reduced first, and then the semiconductor chip 11 is placed on the lead frame 10.

惟，在多接點(I/O)數量且尺寸微小的封裝體積之需求下，尤其是該半導體封裝件1之整體厚度t小於0.3mm，該半導體晶片11所需之厚度d極小，故當該半導體晶片11接置於該導線架10上時，容易受壓而產生碎裂(crack)的狀況，造成該半導體封裝件1之信賴性不佳。 However, under the requirement of a multi-contact (I/O) number and a small size package, especially the overall thickness t of the semiconductor package 1 is less than 0.3mm, the required thickness d of the semiconductor chip 11 is extremely small, so when When the semiconductor chip 11 is connected to the lead frame 10, it is easy to be pressed and cracked, which causes the reliability of the semiconductor package 1 to be poor.

因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the above-mentioned problems of the conventional technology has become an urgent problem to be solved at present.

鑑於上述習知技術之缺失，本發明係提供一種電子封裝件，係包括：承載件，係具有複數導腳；電子元件，係結合於該承載件上且電性連接該複數導腳；以及封裝層，係形成於該承載件上且包覆該電子元件，其中，該封裝層係定義有相對之第一表面與第二表面，該電子元件之一表面係齊平該封裝層之第一表面，且該導腳係齊平該封裝層之第二表面。 In view of the lack of the above-mentioned conventional technology, the present invention provides an electronic package, which includes: a carrier having a plurality of leads; an electronic component coupled to the carrier and electrically connected to the plurality of leads; and a package The layer is formed on the carrier and covers the electronic component, wherein the encapsulation layer is defined with a first surface and a second surface opposite to each other, and one surface of the electronic component is flush with the first surface of the encapsulation layer And the lead pin is flush with the second surface of the encapsulation layer.

本發明亦提供一種電子封裝件之製法，係包括：結合電子元件於一具有複數導腳之承載件上，且令該電子元件係電性連接該複數導腳；形成封裝層於該承載件上，使該封裝層包覆該電子元件；以及移除該封裝層之部分材質、該電子元件之部分材質及該承載件之部分材質，使該封裝層定義出相對之第一表面與第二表面，以令該電子元件之一表面齊平該封裝層之第一表面，且該導腳之一表面齊平該封裝層之第二表面。 The present invention also provides a method for manufacturing an electronic package, which includes: combining an electronic component on a carrier with a plurality of leads, and electrically connecting the electronic component with the plurality of leads; forming an encapsulation layer on the carrier , The packaging layer covers the electronic component; and removing part of the material of the packaging layer, part of the material of the electronic component and part of the material of the carrier, so that the packaging layer defines a first surface and a second surface opposite to each other , So that a surface of the electronic component is flush with the first surface of the encapsulation layer, and a surface of the lead pin is flush with the second surface of the encapsulation layer.

前述之製法中，係採用研磨方式移除該封裝層之部分材質、該電子元件之部分材質及該承載件之部分材質。 In the aforementioned manufacturing method, a grinding method is used to remove part of the material of the packaging layer, part of the material of the electronic component, and part of the material of the carrier.

前述之製法中，復包括進行切單作業。 In the aforementioned manufacturing method, multiple operations include cutting orders.

前述之電子封裝件及其製法中，該承載件係為導線架。 In the aforementioned electronic package and its manufacturing method, the carrier is a lead frame.

前述之電子封裝件及其製法中，該電子元件係具有相對之作用面與非作用面，該電子元件以該作用面藉由複數導電凸塊設於該導腳上，且該非作用面齊平該封裝層之第一表面。 In the aforementioned electronic package and its manufacturing method, the electronic component has an opposite active surface and a non-active surface, the electronic component is provided on the lead pin with the active surface through a plurality of conductive bumps, and the non-active surface is flush The first surface of the encapsulation layer.

前述之電子封裝件及其製法中，該封裝層係定義有鄰接該第一表面與第二表面之側面，且令該導腳之部分表面外露出該封裝層之側面。 In the aforementioned electronic package and its manufacturing method, the encapsulation layer is defined with side surfaces adjacent to the first surface and the second surface, and part of the surface of the lead pin is exposed to the side surface of the encapsulation layer.

前述之電子封裝件及其製法中，該電子元件係外露於該封裝層之第一表面。 In the aforementioned electronic package and its manufacturing method, the electronic component is exposed on the first surface of the package layer.

前述之電子封裝件及其製法中，復包括配置於該封裝層之第二表面上的絕緣層，其具有複數外露該導腳之開孔。 The aforementioned electronic package and its manufacturing method further include an insulating layer disposed on the second surface of the package layer, which has a plurality of openings exposing the lead pins.

前述之電子封裝件及其製法中，復包括配置於該電子元件與該封裝層之第一表面上的作用件。又包括配置於該封裝層之第二表面上的絕緣層，其具有複數外露該導腳之開孔，例如，該作用件之材質與該絕緣層之材質相同。或者，該作用件之材質係採用聚合物，以作為保護層。 In the aforementioned electronic package and its manufacturing method, it also includes active components arranged on the first surface of the electronic component and the package layer. It also includes an insulating layer disposed on the second surface of the encapsulation layer, which has a plurality of openings exposing the lead pins. For example, the material of the active part is the same as the material of the insulating layer. Alternatively, the material of the active part is made of polymer as a protective layer.

由上可知，本發明之電子封裝件及其製法中，主要藉由該電子元件上表面齊平該封裝層之第一表面，且該導腳下表面齊平該封裝層之第二表面，以縮小該承載件之厚度與該封裝層之厚度，故相較於習知技術，本發明之製法所得之電子封裝件之整體厚度能符合薄化需求，且能避免該電子元件產生碎裂的狀況。 It can be seen from the above that in the electronic package and the manufacturing method of the present invention, the upper surface of the electronic component is flush with the first surface of the encapsulation layer, and the lower surface of the lead pin is flush with the second surface of the encapsulation layer to reduce the size. The thickness of the carrier and the thickness of the packaging layer, compared with the prior art, the overall thickness of the electronic package obtained by the manufacturing method of the present invention can meet the thinning requirements, and can prevent the electronic component from being broken.

1‧‧‧半導體封裝件 1‧‧‧Semiconductor package

10‧‧‧導線架 10‧‧‧Wire frame

100,200‧‧‧導腳 100,200‧‧‧Guide foot

11‧‧‧半導體晶片 11‧‧‧Semiconductor chip

110‧‧‧銲錫凸塊 110‧‧‧Solder bump

12‧‧‧封裝膠體 12‧‧‧Packaging gel

2‧‧‧電子封裝件 2‧‧‧Electronic package

20‧‧‧承載件 20‧‧‧Carrier

20a‧‧‧第一側 20a‧‧‧First side

20b‧‧‧第二側 20b‧‧‧Second side

21‧‧‧電子元件 21‧‧‧Electronic components

21a‧‧‧作用面 21a‧‧‧working surface

21b‧‧‧非作用面 21b‧‧‧Inactive surface

210‧‧‧電極墊 210‧‧‧Electrode pad

211‧‧‧導電凸塊 211‧‧‧Conductive bump

22‧‧‧封裝層 22‧‧‧Encapsulation layer

22a‧‧‧第一表面 22a‧‧‧First surface

22b‧‧‧第二表面 22b‧‧‧Second surface

22c‧‧‧側面 22c‧‧‧Side

23‧‧‧絕緣層 23‧‧‧Insulation layer

230‧‧‧開孔 230‧‧‧Opening

24‧‧‧作用件 24‧‧‧action piece

A‧‧‧置晶部 A‧‧‧Crystal Placement Department

B‧‧‧外接部 B‧‧‧External part

d,h,h1,h2,r,t‧‧‧厚度 d,h,h1,h2,r,t‧‧‧thickness

第1圖係為習知半導體封裝件之剖面示意圖。 Figure 1 is a schematic cross-sectional view of a conventional semiconductor package.

第2A至2D圖係為本發明之電子封裝件之製法的剖面示意圖。 2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“第一”、“第二”、“上”、“下”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It should be noted that the structure, ratio, size, etc. shown in the drawings in this manual are only used to match the content disclosed in the manual for the understanding and reading of those who are familiar with the art, and are not intended to limit the implementation of the present invention. Therefore, it does not have any technical significance. Any structural modification, proportional relationship change or size adjustment, without affecting the effects and objectives that can be achieved by the present invention, should still fall within the scope of the present invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "first", "second", "upper", "lower" and "one" cited in this specification are only for ease of description and are not intended to limit the scope of the present invention. The scope of implementation, the change or adjustment of the relative relationship, shall be regarded as the scope of the implementation of the present invention without substantive changes to the technical content.

第2A至2D圖係為本發明之電子封裝件2之製法的剖面示意圖。 2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

如第2A圖所示，提供一具有相對之第一側20a與第二側20b的承載件20。 As shown in FIG. 2A, a carrier 20 having a first side 20a and a second side 20b opposite to each other is provided.

於本實施例中，該承載件20係為導線架，其包含複數相分離之導腳200，其中，該些導腳200係定義有相鄰接之置晶部A與外接部B，且該置晶部A較該外接部B靠近中間區域。 In this embodiment, the carrier 20 is a lead frame, which includes a plurality of separated lead pins 200, wherein the lead pins 200 are defined with adjacent crystal placement part A and external part B, and the The crystal placement part A is closer to the middle area than the external part B.

如第2B圖所示，結合至少一電子元件21於該承載件20之第一側20a上。接著，形成一封裝層22於該承載件20之第一側20a上，以包覆該電子元件21，並外露出該承載件20之第二側20b。 As shown in FIG. 2B, at least one electronic component 21 is combined on the first side 20a of the carrier 20. Next, an encapsulation layer 22 is formed on the first side 20a of the carrier 20 to cover the electronic component 21 and expose the second side 20b of the carrier 20 to the outside.

該電子元件21係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。於本實施例中，該電子元件21係為半導體晶片，其具有相對之作用面21a與非作用面21b，且該作用面21a具有複數電極墊210，使該電子元件21藉由複數接合該些電極墊210之導電凸塊211(如銲錫材料或其它導電材)，而採用覆晶方式設於該些導腳200之置晶部A上，以令該電子元件21電性連接該些導腳200。 The electronic component 21 is an active component, a passive component, or a combination of the two, etc., wherein the active component is a semiconductor chip, and the passive component is a resistor, a capacitor, and an inductor. In this embodiment, the electronic component 21 is a semiconductor chip, which has an active surface 21a and a non-active surface 21b opposite to each other, and the active surface 21a has a plurality of electrode pads 210, so that the electronic component 21 is connected to the plurality of electrode pads. The conductive bumps 211 (such as solder material or other conductive materials) of the electrode pad 210 are arranged on the chip placement portion A of the lead pins 200 by flip chip, so that the electronic component 21 is electrically connected to the lead pins 200.

再者，形成該封裝層22之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)或其它適當絕緣材。 Furthermore, the material forming the encapsulation layer 22 is polyimide (PI), dry film, epoxy or molding compound or other suitable insulating materials.

如第2C圖所示，移除該封裝層22之部分材質、該電子元件21之部分材質及該承載件20(第二側20b)之部分材質，以令該電子元件21之非作用面21b外露於該封裝層22，且該承載件20之第二側20b仍外露於該封裝層22。 As shown in Figure 2C, part of the material of the encapsulation layer 22, part of the material of the electronic component 21 and part of the material of the carrier 20 (second side 20b) are removed to make the non-active surface 21b of the electronic component 21 It is exposed on the packaging layer 22, and the second side 20 b of the carrier 20 is still exposed on the packaging layer 22.

於本實施例中，藉由整平作業(如研磨方式)沿如第2B圖所示之上方與下方之預定移除區域L移除該封裝層22之部分材質、該電子元件21之非作用面21b之部分材質及該承載件20之第二側20b之部分材質，使該封裝層22定義出相對之第一表面22a與第二表面22b，以令該電子元件21之非作用面21b齊平該封裝層22之第一表面22a，且該些導腳200(或該承載件20之第二側20b)係齊平該封裝層22之第二表面22b。 In this embodiment, a leveling operation (such as a grinding method) is used to remove part of the material of the encapsulation layer 22 and the non-functioning of the electronic component 21 along the upper and lower predetermined removal regions L as shown in FIG. 2B. Part of the material of the surface 21b and part of the material of the second side 20b of the carrier 20 allows the encapsulation layer 22 to define a first surface 22a and a second surface 22b opposite to each other, so that the non-active surface 21b of the electronic component 21 is aligned. The first surface 22 a of the encapsulation layer 22 is flat, and the lead pins 200 (or the second side 20 b of the carrier 20) are flush with the second surface 22 b of the encapsulation layer 22.

如第2D圖所示，沿如第2C圖所示之切割路徑S進行切單作業，以製得電子封裝件2，其導腳200係外露於該封裝層22之側面22c。 As shown in FIG. 2D, the slicing operation is performed along the cutting path S shown in FIG. 2C to produce the electronic package 2, the lead 200 of which is exposed on the side surface 22c of the package layer 22.

於本實施例中，該電子封裝件2係為四方平面無引腳(QFN)型式，且該些導腳200之底面及側面係齊平該封裝層22之第二表面22b與側面22c，俾供後續於該些導腳200之外露表面上形成如銲球之銲錫材料(圖略)，以接置於如電路板或另一線路板之電子裝置(圖略)。 In this embodiment, the electronic package 2 is of a quadrilateral plane no-lead (QFN) type, and the bottom and side surfaces of the lead pins 200 are flush with the second surface 22b and the side surface 22c of the package layer 22, so that For the subsequent formation of solder materials such as solder balls on the exposed surfaces of the lead pins 200 (the figure is omitted) to be connected to an electronic device such as a circuit board or another circuit board (the figure is omitted).

再者，可依需求於該承載件20之第二側20b與該封裝層22之第二表面22b上形成一絕緣層23，如防銲材，其形成有複數外露部分該導腳200之開孔230，以於外露出該些開孔230中之導腳200上形成如銲球之銲錫材料(圖略)。 Furthermore, an insulating layer 23, such as a solder mask, can be formed on the second side 20b of the carrier 20 and the second surface 22b of the encapsulation layer 22 as required, which is formed with a plurality of exposed portions of the lead pins 200 The holes 230 are used to expose the lead pins 200 in the openings 230 to form solder materials such as solder balls (the figure is omitted).

又，可依需求於該封裝層22之第一表面22a與該電子元件21之非作用面21b上配置一作用件24，如薄膜、散熱材或其它構造，以保護該電子元件21或提供該電子元件21之散熱。例如，該作用件24之材質可採用聚合物(Polymer)，以作為保護層；或者，該作用件24之材質與該絕緣層23之材質可相同。 In addition, an active member 24, such as a film, heat dissipation material, or other structure, can be arranged on the first surface 22a of the encapsulation layer 22 and the non-active surface 21b of the electronic component 21 as required to protect the electronic component 21 or provide the The heat dissipation of the electronic component 21. For example, the material of the active member 24 can be a polymer (Polymer) as a protective layer; or, the material of the active member 24 and the material of the insulating layer 23 can be the same.

因此，本發明之製法係藉由整平作業，以移除該封裝層22之部分材質、該電子元件21之部分材質及該承載件20之第二側20b之部分材質，以縮小該承載件20之厚度h1與該封裝層22之厚度h2(如第2C圖所示)，故相較於習知技術，本發明之製法所得之電子封裝件2之整體厚度h(如第2D圖所示)能符合薄化需求，例如整體厚度h僅為0.135mm。 Therefore, the manufacturing method of the present invention uses a leveling operation to remove part of the material of the packaging layer 22, part of the material of the electronic component 21, and part of the material of the second side 20b of the carrier 20 to reduce the carrier. The thickness h1 of 20 and the thickness h2 of the encapsulation layer 22 (as shown in Fig. 2C), so compared with the prior art, the overall thickness h of the electronic package 2 obtained by the method of the present invention (as shown in Fig. 2D) ) Can meet thinning requirements, for example, the overall thickness h is only 0.135mm.

再者，本發明之製法係先將該電子元件21設於該承載件20上，再以該封裝層22包覆該電子元件21，以於移除該封裝層22之部分材質及該電子元件21之非作用面21b之部分材質時，該封裝層22能分散應 力，故相較於習知技術，本發明之製法不僅能薄化該電子元件21之厚度r，且能避免該電子元件21破裂之問題。 Furthermore, the manufacturing method of the present invention is to first set the electronic component 21 on the carrier 20, and then cover the electronic component 21 with the encapsulation layer 22 to remove part of the material of the encapsulation layer 22 and the electronic component When part of the material of the non-acting surface 21b of 21, the encapsulation layer 22 can disperse the application Therefore, compared with the prior art, the manufacturing method of the present invention can not only reduce the thickness r of the electronic component 21, but also avoid the problem of cracking of the electronic component 21.

本發明復提供一種電子封裝件2，其包括：一承載件20、一電子元件21以及一封裝層22。 The present invention further provides an electronic package 2, which includes: a carrier 20, an electronic component 21, and an encapsulation layer 22.

所述之承載件20係為導線架，其包含複數相分離之導腳200。 The carrier 20 is a lead frame, which includes a plurality of separated lead legs 200.

所述之電子元件21係結合於該承載件20上且電性連接該導腳200。 The electronic component 21 is combined on the carrier 20 and electrically connected to the lead 200.

所述之封裝層22係形成於該承載件20上且包覆該電子元件21，其中，該封裝層22係定義有相對之第一表面22a與第二表面22b，且該電子元件21之上表面係齊平該封裝層22之第一表面22a，而該導腳200之下表面係齊平該封裝層22之第二表面22b，以令該電子元件21與該導腳200外露於該封裝層22。 The encapsulation layer 22 is formed on the carrier 20 and covers the electronic component 21, wherein the encapsulation layer 22 is defined with a first surface 22a and a second surface 22b opposite to each other, and on the electronic component 21 The surface is flush with the first surface 22a of the encapsulation layer 22, and the lower surface of the lead 200 is flush with the second surface 22b of the encapsulation layer 22, so that the electronic component 21 and the lead 200 are exposed to the package Layer 22.

於一實施例中，該電子元件21係具有相對之作用面21a與非作用面21b，且該作用面21a藉由複數導電凸塊211設於該導腳200上，而該非作用面21b齊平該封裝層22之第一表面22a。 In one embodiment, the electronic component 21 has an active surface 21a and a non-active surface 21b opposite to each other, and the active surface 21a is provided on the lead 200 by a plurality of conductive bumps 211, and the non-active surface 21b is flush. The first surface 22a of the encapsulation layer 22.

於一實施例中，該封裝層22係定義有鄰接該第一與第二表面22a,22b之側面22c，以令該導腳200外露於該封裝層22之側面22c。 In one embodiment, the encapsulation layer 22 is defined with a side surface 22c adjacent to the first and second surfaces 22a, 22b, so that the lead 200 is exposed on the side surface 22c of the encapsulation layer 22.

於一實施例中，該電子元件21係外露於該封裝層22之第一表面22a。 In one embodiment, the electronic component 21 is exposed on the first surface 22 a of the encapsulation layer 22.

於一實施例中，所述之電子封裝件2復包括配置於該封裝層22之第二表面22b上的絕緣層23，其具有複數外露該導腳200之開孔230。 In one embodiment, the electronic package 2 further includes an insulating layer 23 disposed on the second surface 22b of the encapsulation layer 22, which has a plurality of openings 230 exposing the lead pins 200.

於一實施例中，所述之電子封裝件2復包括配置於該電子元件21與該封裝層22之第一表面22a上的作用件24。例如，該作用件24之材 質與該絕緣層23之材質相同。或者，該作用件24之材質係採用聚合物，以作為保護層。 In one embodiment, the electronic package 2 further includes an active member 24 disposed on the first surface 22 a of the electronic component 21 and the encapsulation layer 22. For example, the material of the acting member 24 The quality is the same as that of the insulating layer 23. Alternatively, the material of the acting member 24 is made of polymer as a protective layer.

綜上所述，本發明之電子封裝件及其製法係藉由上、下方向研磨之整平過程，以縮小該電子封裝件之整體厚度，因而能符合薄化之需求，且能避免該電子元件破裂之問題。 To sum up, the electronic package and its manufacturing method of the present invention reduce the overall thickness of the electronic package through the leveling process of grinding in the upper and lower directions, so that it can meet the needs of thinning, and can avoid the electronic The problem of component cracking.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone who is familiar with this technique can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

2‧‧‧電子封裝件 2‧‧‧Electronic package

20‧‧‧承載件 20‧‧‧Carrier

20b‧‧‧第二側 20b‧‧‧Second side

200‧‧‧導腳 200‧‧‧Guide foot

21‧‧‧電子元件 21‧‧‧Electronic components

21b‧‧‧非作用面 21b‧‧‧Inactive surface

22‧‧‧封裝層 22‧‧‧Encapsulation layer

22a‧‧‧第一表面 22a‧‧‧First surface

22b‧‧‧第二表面 22b‧‧‧Second surface

22c‧‧‧側面 22c‧‧‧Side

23‧‧‧絕緣層 23‧‧‧Insulation layer

230‧‧‧開孔 230‧‧‧Opening

24‧‧‧作用件 24‧‧‧action piece

h‧‧‧厚度 h‧‧‧Thickness

Claims (20)

一種電子封裝件，係包括：承載件，係具有複數導腳；電子元件，係結合於該承載件上且電性連接該複數導腳；以及封裝層，係形成於該承載件上且包覆該電子元件，其中，該封裝層係定義有相對之第一表面與第二表面，該電子元件之一表面係齊平該封裝層之第一表面，且該導腳之一表面係齊平該封裝層之第二表面。 An electronic package includes: a carrier with a plurality of lead pins; an electronic element coupled to the carrier and electrically connected to the plurality of leads; and an encapsulation layer formed on the carrier and covered The electronic component, wherein the encapsulation layer is defined with a first surface and a second surface opposite to each other, a surface of the electronic component is flush with the first surface of the encapsulation layer, and a surface of the lead pin is flush with the The second surface of the encapsulation layer. 如申請專利範圍第1項所述之電子封裝件，其中，該承載件係為導線架。 The electronic package described in item 1 of the scope of patent application, wherein the carrier is a lead frame. 如申請專利範圍第1項所述之電子封裝件，其中，該電子元件係具有相對之作用面與非作用面，該電子元件以該作用面藉由複數導電凸塊設於該導腳上，且該非作用面齊平該封裝層之第一表面。 The electronic package described in item 1 of the scope of patent application, wherein the electronic component has an opposite active surface and a non-active surface, and the electronic component is provided on the lead pin with the active surface through a plurality of conductive bumps, And the inactive surface is flush with the first surface of the encapsulation layer. 如申請專利範圍第1項所述之電子封裝件，其中，該封裝層係定義有鄰接該第一表面與第二表面之側面，且令該導腳之部分表面外露出該封裝層之側面。 According to the electronic package described in claim 1, wherein the encapsulation layer is defined with side surfaces adjacent to the first surface and the second surface, and a part of the surface of the lead pin exposes the side surface of the encapsulation layer. 如申請專利範圍第1項所述之電子封裝件，復包括配置於該封裝層之第二表面上的絕緣層，其具有複數外露該導腳之開孔。 The electronic package described in item 1 of the scope of patent application includes an insulating layer disposed on the second surface of the encapsulation layer, which has a plurality of openings exposing the lead pins. 如申請專利範圍第1項所述之電子封裝件，復包括配置於該電子元件與該封裝層之第一表面上的作用件。 The electronic package as described in item 1 of the scope of the patent application includes functional elements arranged on the first surface of the electronic component and the encapsulation layer. 如申請專利範圍第6項所述之電子封裝件，復包括配置於該封裝層之第二表面上的絕緣層，其具有複數外露該導腳之開孔。 The electronic package described in item 6 of the scope of patent application includes an insulating layer disposed on the second surface of the encapsulation layer, which has a plurality of openings exposing the lead pins. 如申請專利範圍第7項所述之電子封裝件，其中，該作用件之材質與該絕緣層之材質相同。 The electronic package described in item 7 of the scope of patent application, wherein the material of the active part is the same as the material of the insulating layer. 如申請專利範圍第6項所述之電子封裝件，其中，該作用件之材質係採用聚合物，以作為保護層。 For the electronic package described in item 6 of the scope of patent application, the material of the active member is a polymer as a protective layer. 一種電子封裝件之製法，係包括：結合電子元件於一具有複數導腳之承載件上，且令該電子元件係電性連接該複數導腳；形成封裝層於該承載件上，使該封裝層包覆該電子元件；以及移除該封裝層之部分材質、該電子元件之部分材質及該承載件之部分材質，使該封裝層定義出相對之第一表面與第二表面，以令該電子元件之一表面齊平該封裝層之第一表面，且該導腳之一表面齊平該封裝層之第二表面。 A method for manufacturing an electronic package includes: combining an electronic component on a carrier with a plurality of leads, and electrically connecting the electronic component with the plurality of leads; forming an encapsulation layer on the carrier to make the package Layer covering the electronic component; and removing part of the material of the encapsulation layer, part of the material of the electronic component, and part of the material of the carrier, so that the encapsulation layer defines a first surface and a second surface opposite to each other, so that the A surface of the electronic component is flush with the first surface of the encapsulation layer, and a surface of the lead pin is flush with the second surface of the encapsulation layer. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該承載件係為導線架。 The manufacturing method of the electronic package as described in item 10 of the scope of patent application, wherein the carrier is a lead frame. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該電子元件係具有相對之作用面與非作用面，該電子元件以該作用面藉由複數導電凸塊設於該導腳上，且該非作用面齊平該封裝層之第一表面。 The method for manufacturing an electronic package as described in item 10 of the scope of patent application, wherein the electronic component has an opposite active surface and a non-active surface, and the electronic component is provided on the lead pin with the active surface through a plurality of conductive bumps And the inactive surface is flush with the first surface of the encapsulation layer. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該封裝層係定義有鄰接該第一表面與第二表面之側面，且令該導腳之部分表面外露出該封裝層之側面。 The method for manufacturing an electronic package as described in claim 10, wherein the encapsulation layer is defined as a side surface adjacent to the first surface and the second surface, and part of the surface of the lead pin is exposed outside of the encapsulation layer side. 如申請專利範圍第10項所述之電子封裝件之製法，復包括配置絕緣層於該封裝層之第二表面上，其中，該絕緣層具有複數外露該導腳之開孔。 As described in item 10 of the scope of patent application, the method for manufacturing an electronic package includes disposing an insulating layer on the second surface of the encapsulating layer, wherein the insulating layer has a plurality of openings exposing the lead pins. 如申請專利範圍第10項所述之電子封裝件之製法，復包括配置作用件於該電子元件與該封裝層之第一表面上。 The method for manufacturing an electronic package as described in item 10 of the scope of the patent application includes arranging an active element on the first surface of the electronic component and the package layer. 如申請專利範圍第15項所述之電子封裝件之製法，復包括配置絕緣層於該封裝層之第二表面上，且該絕緣層具有複數外露該導腳之開孔。 As described in item 15 of the scope of patent application, the method for manufacturing an electronic package includes disposing an insulating layer on the second surface of the encapsulating layer, and the insulating layer has a plurality of openings exposing the lead pins. 如申請專利範圍第16項所述之電子封裝件之製法，其中，該作用件之材質與該絕緣層之材質相同。 The manufacturing method of the electronic package as described in item 16 of the scope of patent application, wherein the material of the active part is the same as the material of the insulating layer. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該作用件之材質係採用聚合物，以作為保護層。 For example, the method for manufacturing an electronic package described in item 15 of the scope of the patent application, wherein the material of the active member is a polymer as a protective layer. 如申請專利範圍第10項所述之電子封裝件之製法，其中，係採用研磨方式移除該封裝層之部分材質、該電子元件之部分材質及該承載件之部分材質。 For example, the manufacturing method of the electronic package described in the scope of the patent application, wherein a grinding method is used to remove part of the material of the packaging layer, part of the material of the electronic component, and part of the material of the carrier. 如申請專利範圍第10項所述之電子封裝件之製法，復包括進行切單作業。 For example, the manufacturing method of the electronic package described in item 10 of the scope of patent application includes the operation of cutting orders.
TW108123412A 2019-07-03 2019-07-03 Electronic package and manufacturing method thereof TWI690039B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW108123412A TWI690039B (en) 2019-07-03 2019-07-03 Electronic package and manufacturing method thereof
CN201910624358.4A CN112185903A (en) 2019-07-03 2019-07-11 Electronic package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW108123412A TWI690039B (en) 2019-07-03 2019-07-03 Electronic package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TWI690039B TWI690039B (en) 2020-04-01
TW202103271A true TW202103271A (en) 2021-01-16

Family

ID=71134348

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108123412A TWI690039B (en) 2019-07-03 2019-07-03 Electronic package and manufacturing method thereof

Country Status (2)

Country Link
CN (1) CN112185903A (en)
TW (1) TWI690039B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113675102A (en) * 2021-10-22 2021-11-19 深圳新声半导体有限公司 Method for chip packaging and chip particles
US11616044B2 (en) 2021-10-20 2023-03-28 Shenzhen Newsonic Technologies Co., Ltd. Chip packaging method and particle chips

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW463342B (en) * 2000-08-18 2001-11-11 Siliconware Precision Industries Co Ltd Flip-chip quad-flat nolead package
TWI316749B (en) * 2006-11-17 2009-11-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
CN101335216A (en) * 2007-06-27 2008-12-31 矽品精密工业股份有限公司 Heat radiating type package construction and manufacturing method thereof
TWI490988B (en) * 2012-03-21 2015-07-01 Chipmos Technologies Inc Semiconductor package structure
CN102683230B (en) * 2012-05-30 2015-06-17 天水华天科技股份有限公司 Quad flat no-lead multi-circle-arranged integrated circuit (IC) chip packaging part and production method thereof
TWI480989B (en) * 2012-10-02 2015-04-11 矽品精密工業股份有限公司 Semiconductor package and fabrication method thereof
CN103094240A (en) * 2012-12-15 2013-05-08 华天科技（西安）有限公司 High-density etched lead frame FCAAQFN package part and manufacture process thereof
CN106328545A (en) * 2015-07-02 2017-01-11 万国半导体(开曼)股份有限公司 Ultrathin chip double-surface exposed package structure of and manufacturing method thereof
WO2017011246A1 (en) * 2015-07-10 2017-01-19 Adventive Technology Ltd. Universal surface-mount semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11616044B2 (en) 2021-10-20 2023-03-28 Shenzhen Newsonic Technologies Co., Ltd. Chip packaging method and particle chips
CN113675102A (en) * 2021-10-22 2021-11-19 深圳新声半导体有限公司 Method for chip packaging and chip particles
US11683020B2 (en) 2021-10-22 2023-06-20 Shenzhen Newsonic Technologies Co., Ltd. Chip packaging method and particle chips

Also Published As

Publication number Publication date
CN112185903A (en) 2021-01-05
TWI690039B (en) 2020-04-01

Similar Documents

Publication Publication Date Title
JP5215605B2 (en) Manufacturing method of semiconductor device
US20200335447A1 (en) Method for fabricating electronic package
KR101076537B1 (en) Multiple chip package module having inverted package stacked over die
JP5280014B2 (en) Semiconductor device and manufacturing method thereof
JP5215587B2 (en) Semiconductor device
TWI671861B (en) Semiconductor package structure and method of making the same
TWI496270B (en) Semiconductor package and method of manufacture
TWI614848B (en) Electronic package and method of manufacture thereof
US9548220B2 (en) Method of fabricating semiconductor package having an interposer structure
TW201501226A (en) Semiconductor packages and methods of packaging semiconductor devices
TW201926588A (en) Electronic package and method of manufacture
TWI635585B (en) Semiconductor package and method of manufacture
TWI611542B (en) Electronic package structure and the manufacture thereof
KR20100005112A (en) Flip chip with interposer, and methods of making same
TWI488270B (en) Semiconductor package and method of forming the same
TWI690039B (en) Electronic package and manufacturing method thereof
TWI534965B (en) Semiconductor package and fabrication method thereof
US20230395571A1 (en) Electronic package and manufacturing method thereof
TW202220151A (en) Electronic packaging and manufacturing method thereof
TWI798952B (en) Electronic package and manufacturing method thereof
TW201637139A (en) Electronic package structure and method of fabricating the same
TWI766271B (en) Electronic package and method for fabricating the same
TW201911500A (en) Electronic package and its manufacturing method
TWI718801B (en) Electronic package manufacturing method
TWM537303U (en) 3D multi-chip module packaging structure