TWI490988B - Semiconductor package structure - Google Patents

Description

Semiconductor package structure

This invention relates to a semiconductor component, and more particularly to a semiconductor package structure.

Semiconductor packaging technology includes many package types. The quad flat no-lead package belonging to the quad flat package series has a short signal transmission path and relatively fast signal transmission speed, so the quad flat no-lead package is suitable for high-frequency transmission. A chip package (eg, a radio frequency band) and one of the mainstream of the low pin count package type.

In a quad flat no-lead package process, multiple wafers are first placed on a leadframe. Then, the wafers are electrically connected to the lead frame by a plurality of bonding wires or a plurality of flip-chip bumps. Thereafter, the lead frame, the bonding wires or the flip chip and the wafers are covered by an encapsulant. Finally, a plurality of quad flat no-lead package structures are obtained by singulating the above structure by a dicing process.

However, as technology advances and the size of components is miniaturized, the size of wafers is gradually shrinking. Therefore, when the size of the wafer is reduced, the distance between the wafer and the pin of the lead frame is relatively increased. As a result, the conventional lead frame cannot directly carry the wafer during the flip chip bonding process, and needs to be additionally designed. The lead frame is used to match the reduced size of the wafer; or the wafer with the central electrical contact is to be flip-chip bonded to the lead, and a redistribution layer is formed on the wafer to make the wafer electrically The contacts can be electrically connected to the leads, which will result in increased packaging costs.

The present invention provides a semiconductor package structure that solves the problem that the conventional wafer size becomes small and cannot be directly flipped on the lead frame.

The invention provides a semiconductor package structure comprising an interposer substrate, a lead frame, a wafer and an encapsulant. The interposer substrate has a surface and a patterned wiring layer. A patterned wiring layer is formed on the surface and has a first end and a second end opposite the first end. The lead frame is disposed on the surface of the interposer substrate and defines a receiving recess with the surface of the interposer substrate. The lead frame includes a plurality of pins, each of which has a cantilever portion and an outer portion, and the cantilever portion of the pin is electrically connected to the second end of the patterned circuit layer of the interposer substrate. The wafer is disposed on the surface of the interposer substrate and is located in the accommodating recess, wherein the lead surrounds the periphery of the wafer, and the wafer has a plurality of conductive bumps. The wafer is electrically connected to the first end of the patterned circuit layer of the interposer through the conductive bumps. The encapsulant covers the interposer substrate, the leadframe and the wafer, and fills the receiving recess and fills the pins.

The invention also provides a semiconductor package structure comprising an interposer substrate, a lead frame, a wafer and an encapsulant. The interposer substrate has a first surface and a second surface opposite to each other, a plurality of first pads and a plurality of second pads. The first pad is disposed at a central region of the first surface, and the second pad is located at a peripheral region of the second surface. The lead frame includes a wafer holder and a plurality of pins disposed around the wafer holder. Each pin has a cantilever portion and an outer portion, and the cantilever portion of the pin is electrically connected to the second pad of the interposer substrate. The wafer is disposed on the first surface of the interposer substrate and above the wafer holder. The wafer has a plurality of conductive bumps and is electrically connected to the first pads on the first surface of the interposer substrate through the conductive bumps. The encapsulant covers the wafer, the interposer substrate, and the leadframe and is filled between the pins.

Based on the above, since the semiconductor package structure of the present invention has an interposer substrate, the wafer can be electrically connected to the lead frame through the interposer substrate, and the conventional chip can be used even if the chip size is reduced to a conventional pin frame. The leadframe is flip-chip bonded without changing the design. Moreover, the wafer can be placed in the receiving groove between the pins, which can effectively reduce the thickness of the package.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a cross-sectional view showing a semiconductor package structure according to an embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the semiconductor package structure 100 a includes an interposer substrate 110 a , a lead frame 120 a , a wafer 130 , and an encapsulant 140 . In detail, the interposer substrate 110a has a surface 112a and a patterned wiring layer 113. The patterned wiring layer 113 is formed on the surface 112a and has a first end 113a and a second end opposite to the first end 113a. 113b, wherein the patterned wiring layer 113 may be buried within the surface 112a of the interposer substrate 110a. In other embodiments not shown, the patterned wiring layer 113 may also be disposed on the surface 112a of the interposer substrate 110a, which is not limited herein. In addition, the interposer substrate 110a of the present embodiment is, for example, a single-layer circuit substrate or a film reel, which is not limited herein.

The lead frame 120a is disposed on the surface 112a of the interposer substrate 110a, and the lead frame 120a defines a receiving recess C with the surface 112a of the interposer substrate 110a. The lead frame 120a includes a plurality of pins 122a, wherein each of the pins 122a has a cantilever portion 122a1 and an outer portion 122a2. The cantilever portion 122a1 of the pin 122a is electrically connected to the second end 113b of the patterned wiring layer 113 of the interposer substrate 110a. The wafer 130 is disposed on the surface 112a of the interposer substrate 110a and is located in the accommodating recess C, wherein the pin 122a surrounds the periphery of the wafer 130. The wafer 130 has a plurality of conductive bumps 150, and the wafer 130 is electrically connected to the first end 113a of the patterned wiring layer 113 of the interposer substrate 110a through the conductive bumps 150. Therefore, the wafer 130 can pass through the interposer substrate 110a and The foot 122a is electrically conductive. The encapsulant 140 covers the interposer substrate 110a, the lead frame 120a and the wafer 130, and fills the receiving recess C and fills between the pins 122a.

More specifically, the lead frame 120a and the wafer 130 of the present embodiment are disposed under the interposer substrate 110a, and the lead frame 120a and the wafer 130 are located on the same surface 112a of the interposer substrate 110a, wherein each pin 122a The cantilever portion 122a1 and the outer portion 122a2 have a common upper surface 123a2. A first lower surface 121a of the cantilever portion 122a1 has a concave receiving space S with respect to the second lower surface 123a1 of the outer portion 122a2. The colloid 140 is filled in the accommodating space S. In addition, the semiconductor package structure 100a further includes a conductive element 160, wherein the conductive element 160 is disposed between the cantilever portion 122a1 of the pin 122a of the lead frame 120a and the surface 112a of the interposer substrate 110a, and the cantilever portion 122a1 is transmitted through the conductive member 160. The second end 113b of the patterned wiring layer 113 of the interposer substrate 110a is electrically connected. Here, the material of the conductive member 160 is, for example, a solder, an anisotropic conductive paste (ACP), an anisotropic conductive film (ACF), or other suitable conductive material.

In addition, the second lower surface 123a1 of the external portion 122a2 of each pin 122a and a back surface 132 of the wafer 130 are substantially flush with a bottom surface 142 of the encapsulant 140. In this way, the heat generated by the wafer 130 can be directly transmitted to the outside through the back surface 132, so that the semiconductor package structure 100a has a better heat dissipation effect. In addition, the semiconductor package structure 100a can be electrically connected to an external circuit (not shown) through the second lower surface 123a1 of the external portion 122a2 of the pin 122a exposed outside the encapsulant 140, thereby effectively expanding the semiconductor package structure 100a. Application range. Moreover, the upper surface 123a2 of each of the pins 122a can form a plurality of groove portions 126, the encapsulant 140 fills the groove portions 126, and the groove portions 126 can increase the contact area of the pins 122a with the encapsulant 140. The bonding strength makes the pin 122a hard to fall off. In addition, the semiconductor package structure 100a of the present embodiment is a quad flat non-leaded (QFN) type package structure.

Since the semiconductor package structure 100a of the present embodiment has the interposer substrate 110a, the wafer 130 can be electrically connected to the interposer substrate 110a through the conductive bumps 150 by means of flip chip bonding, and then through the patterned circuit layer of the interposer substrate 110a. 113 is electrically connected to pin 122a of lead frame 120a. That is, the wafer 130 can sequentially transmit electrical signals to the lead frame 120a via the conductive bumps 150 and the interposer substrate 110a. In this way, the problem that the wafer size becomes small and the flip chip cannot be directly bonded to the lead frame can be effectively solved. In addition, since the wafer 130 of the present embodiment is disposed in the accommodating recess C defined by the surface 112a of the lead 122a and the interposer substrate 110a, the package thickness of the semiconductor package structure 100a can be effectively reduced to conform to the current thinning. the trend of.

It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

2 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention. Referring to FIG. 2, the semiconductor package structure 100b of the present embodiment is similar to the semiconductor package structure 100a of FIG. 1, but the main difference is that the lead frame 120b and the wafer 130 of the semiconductor package structure 100b of the present embodiment are both configured. Above the interposer substrate 110b, and on the same surface 112b of the interposer substrate 110b, the encapsulant 140 covers the interposer substrate 110b, the wafer 130 and the lead frame 120b, and is filled between the leads 122b. More specifically, the second end 113b of the patterned circuit layer 113 of the intermediate substrate 110b is connected to the first lower surface 121b of the cantilever portion 122b1, wherein the intermediate substrate 110b is partially located in the accommodating space S' of the cantilever portion 122b1. The wafer 130 is electrically connected to the first end 113a of the patterned wiring layer 113 of the interposer substrate 110b through the conductive bumps 150 in a flip chip manner. In addition, a second lower surface 123b1 of the external portion 122b of each of the pins 122b is substantially flush with the bottom surface 142 of the encapsulant 140, so that the semiconductor package structure 100b can pass through the external portion of the pin 122b exposed outside the encapsulant 140. The second lower surface 123b1 of the 122b2 is electrically connected to an external circuit (not shown), which can effectively expand the application range of the semiconductor package structure 100b.

It should be noted that the present invention does not limit the type of the pin 122b, although the upper surface 123b2 of the pin 122b mentioned herein is substantially a plane, but in other embodiments not shown, The upper surface 123b2 of the leg 122b can also form a plurality of groove portions, wherein the groove portion can be used to increase the bonding strength between the pin 122b and the encapsulant 140, so that the pin 122b is not easily peeled off. In short, the type of the pin 122b shown in FIG. 2 is merely an example and is not limited thereto.

3 is a cross-sectional view showing a semiconductor package structure according to still another embodiment of the present invention. Referring to FIG. 3, the semiconductor package structure 100c of the present embodiment is similar to the semiconductor package structure 100a of FIG. 1, but the main difference is that the interposer substrate 110c of the semiconductor package structure 100c of the present embodiment has one opposite to each other. The first surface 112c and the second surface 114c, the plurality of first pads 115 and the plurality of second pads 116, wherein the first pads 115 are disposed on a central region P1 of the first surface 112c, and the second pads 116 is located in a peripheral region P2 of one of the second surfaces 114c. In particular, the first pads 115 and the second pads 116 are electrically connected to the conductive vias, for example, by conductive traces formed in the interposer substrate 110c. The wafer 130 is located on the first surface 112c of the interposer substrate 110c, and the lead frame 120c is located on the second surface 114c of the interposer substrate 110c, and the cantilever portion 122c1 of the pin 122c and the second pad 116 of the interposer substrate 110c. Electrical connection. That is, the lead frame 120c and the wafer 130 are respectively located on opposite side surfaces of the interposer substrate 110c. The lead frame 120c further includes a wafer holder 124 in which the pins 122c are disposed around the wafer holder 124 and the wafer holder 124 is located directly below the wafer 130. A first lower surface 121c of the cantilever portion 122c1 of each of the pins 122c has a concave receiving space S" with respect to the second lower surface 123c1 of the external portion 122c2, and the encapsulant 140 is filled in the accommodating space S" Inside. In addition, the wafer 130 has a plurality of conductive bumps 150, and the wafer 130 is electrically connected to the first pads 115 on the first surface 112c of the interposer substrate 110c through the conductive bumps 150.

In this embodiment, a third lower surface 125 of the wafer holder 124 of each of the pins 122c and a second lower surface 123c1 of the external portion 122c2 are substantially flush with a bottom surface 142 of the encapsulant 140. In this way, the heat generated by the wafer 130 can be transmitted to the outside through the conductive bumps 150, the interposer substrate 110c, and the wafer holder 124, thereby effectively increasing the heat dissipation performance of the semiconductor encapsulant 100c. In addition, the semiconductor package structure 100c can be electrically connected to an external circuit (not shown) through the second surface 123c1 of the external portion 122c2 of the pin 122c exposed outside the package adhesive 140, thereby effectively expanding the application range of the semiconductor package structure 100c. . In addition, the semiconductor package structure 100c further includes a conductive element 160' disposed between the cantilever portion 122c1 of each of the pins 122c and the second surface 114c of the interposer substrate 110c. The cantilever portion 122c1 and the outer portion 122c2 of each of the pins 122c have a common upper surface 123c2, and the second pads 116 of the intermediate substrate 110c are connected to the cantilever portion 122c1 of the conductive member 160' and the pin 122c. The surface 123c2 is electrically connected. Here, the material of the conductive member 160' is, for example, a solder, an anisotropic conductive paste (ACP), an anisotropic conductive film (ACF), or other suitable conductive material.

It should be noted that, in other unillustrated embodiments, a plurality of passive components may also be disposed on the interposer substrate, wherein the passive components are, for example, one of a resistor, an inductor, a capacitor, or a combination thereof, which may be used to add a semiconductor. The functionality of the package structure. In addition, the present invention does not limit the type of the pin 122c, although the upper surface 123c2 of the pin 122c mentioned herein is substantially a flat surface, but in other embodiments not shown, the upper side of the pin 122c The surface 123c2 may also form a plurality of groove portions, wherein the groove portion may be used to increase the bonding strength between the pin 122c and the encapsulant 140, so that the pin 122c is not easily peeled off. In short, the type of the pin 122c shown in FIG. 3 is merely an example and is not limited thereto.

In summary, since the semiconductor package structure of the present invention has an interposer substrate, the wafer can be electrically connected to the interposer through the conductive bumps by means of flip chip bonding, and the conductive bumps can pass through the interposer substrate and the leads. The frame is electrically connected, that is, the wafer can sequentially transmit electrical signals to the lead frame via the conductive bumps and the interposer substrate. In this way, the problem that the wafer size becomes small and the flip chip cannot be directly bonded to the lead frame can be effectively solved. Moreover, the wafer can be placed in the receiving groove between the pins, which can effectively reduce the thickness of the package.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100a, 100b, 100c‧‧‧ semiconductor package structure

110a, 110b, 110c‧‧‧Intermediate substrate

112a, 112b‧‧‧ surface

112c‧‧‧ first surface

113‧‧‧ patterned circuit layer

113a‧‧‧ first end

113b‧‧‧ second end

114c‧‧‧ second surface

115‧‧‧First mat

116‧‧‧second mat

120a, 120b, 120c‧‧‧ lead frame

121a, 121b, 121c‧‧‧ first lower surface

122a, 122b, 122c‧‧‧ pins

122a1, 122b1, 122c1‧‧‧ cantilever

122a2, 122b2, 122c2‧‧‧ External Department

123a1, 123b1, 123c1‧‧‧ second lower surface

123a2, 123b2, 123c2‧‧‧ upper surface

124‧‧‧ Wafer holder

125‧‧‧ Third lower surface

126‧‧‧ Groove

130‧‧‧ wafer

132‧‧‧Back

140‧‧‧Package colloid

142‧‧‧ bottom

150‧‧‧conductive bumps

160, 160'‧‧‧ conductive elements

C‧‧‧ accommodating grooves

S, S’, S”‧‧‧ accommodating space

P1‧‧‧Central Area

P2‧‧‧ surrounding area

1 is a cross-sectional view showing a semiconductor package structure according to an embodiment of the present invention.

2 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention.

3 is a cross-sectional view showing a semiconductor package structure according to still another embodiment of the present invention.

100a. . . Semiconductor package structure

110a. . . Intermediary substrate

112a. . . surface

113. . . Patterned circuit layer

113a. . . First end

113b. . . Second end

120a. . . Pin frame

121a. . . First lower surface

122a. . . Pin

122a1. . . Cantilever

122a2. . . External unit

123a1. . . Second lower surface

123a2. . . Upper surface

126. . . Groove

130. . . Wafer

132. . . back

140. . . Encapsulant

142. . . Bottom

150. . . Conductive bump

160. . . Conductive component

C. . . Locating groove

S. . . Housing space

Claims (10)

A semiconductor package structure comprising: an interposer substrate having a surface and a patterned circuit layer, the patterned circuit layer being formed on the surface, and the patterned circuit layer having a first end opposite to the first a second end of the end; a lead frame disposed on the surface of the interposer substrate and defining a receiving recess with the surface of the interposer substrate, the lead frame comprising a plurality of pins, wherein Each of the leads has a cantilever portion and an outer portion, and the cantilever portions of the pins are electrically connected to the second end of the patterned circuit layer of the interposer substrate; a wafer is disposed in the medium The surface of the substrate is located in the accommodating recess, wherein the pins surround the periphery of the wafer, and the wafer has a plurality of conductive bumps, and the wafer passes through the conductive bumps and the interposer substrate The first end of the patterned circuit layer is electrically connected; and an encapsulant covers the interposer substrate, the lead frame and the wafer, and fills the receiving recess and fills the pins The cantilever portion of each of the pins and the external connection Having a common upper surface, a first lower surface of the cantilever portion has a concave receiving space with respect to a second lower surface of the outer portion, and the encapsulant is filled in the accommodating space, the intermediate The second end of the patterned circuit layer of the substrate is connected to the first lower surface of the cantilever portions, and the intermediate substrate portion is located in the accommodating space of the cantilever portions. The semiconductor package structure of claim 1, wherein the cantilever portions of the pins are a conductive member and the intermediate substrate The second end of the patterned circuit layer is electrically connected. The semiconductor package structure of claim 2, wherein the material of the conductive element comprises solder, an anisotropic conductive paste or an anisotropic conductive film. The semiconductor package structure of claim 1, wherein the interposer substrate comprises a single layer circuit substrate or a film web. The semiconductor package structure of claim 1, wherein the upper surface of each of the pins is formed with a plurality of groove portions, and the encapsulant fills the groove portions. The semiconductor package structure of claim 1, wherein the wafer sequentially transmits an electrical signal to the lead frame via the conductive bumps and the interposer substrate. A semiconductor package structure comprising: an interposer substrate having a first surface and a second surface opposite to each other, a plurality of first pads, and a plurality of second pads, wherein the first pads are disposed on the a central region of the first surface, the second pads are located in a peripheral region of the second surface, the first pads are directly connected to the second pads, and each of the first pads is electrically conductive Traces, and each of the second pads is a conductive via; a lead frame includes a wafer holder and a plurality of pins disposed around the wafer holder, wherein each of the pins has a cantilever portion and an external portion And the cantilever portions of the pins are electrically connected to the second pads of the interposer substrate; a wafer is disposed on the first surface of the interposer substrate and located at Above the wafer holder, the wafer has a plurality of conductive bumps, and the wafer is electrically connected to the first pads on the first surface of the interposer through the conductive bumps; and an encapsulant Covering the wafer, the interposer substrate, and the lead frame, and filling between the pins. The semiconductor package structure of claim 7, wherein a first lower surface of the wafer holder of each of the pins and a second lower surface of the external portion are flush with a bottom surface of the encapsulant. The semiconductor package structure of claim 7, wherein the cantilever portion of each of the pins and the external portion have a common upper surface, and the second pads of the intermediate substrate are a conductive member The upper surface of the cantilever portions of the pins are electrically connected. The semiconductor package structure of claim 9, wherein the material of the conductive element comprises solder, an anisotropic conductive paste or an anisotropic conductive film.