TW463342B - Flip-chip quad-flat nolead package - Google Patents

Flip-chip quad-flat nolead package Download PDF

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Publication number
TW463342B
TW463342B TW089116723A TW89116723A TW463342B TW 463342 B TW463342 B TW 463342B TW 089116723 A TW089116723 A TW 089116723A TW 89116723 A TW89116723 A TW 89116723A TW 463342 B TW463342 B TW 463342B
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TW
Taiwan
Prior art keywords
chip
flip
patent application
scope
item
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Application number
TW089116723A
Other languages
Chinese (zh)
Inventor
Shiau-Yu Luo
Ji-Chiuan Wu
Original Assignee
Siliconware Precision Industries Co Ltd
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Priority to TW089116723A priority Critical patent/TW463342B/en
Application granted granted Critical
Publication of TW463342B publication Critical patent/TW463342B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Wire Bonding (AREA)

Abstract

A flip-chip quad-flat nolead package is disclosed, which comprises: plural leads, each lead having the first surface and the corresponding second surface, respectively; a chip having an active surface and the corresponding back side, the active surface having plural bonding pads, each bonding pad having a bump, each bump corresponding to one of the leads, and being connected to the first surface of the lead, and molding compound encapsulating the lead and chip, and exposing the second surface of the lead.

Description

經濟部智慧財產局員工消費合泎达印製 6049twf.doc/006 pj ___B7 五、發明說明（丨） 本發明是有關於一種四方扁平無接腳構裝，且特別 是有關於一種利用覆晶方式接合的覆晶式四方扁平無接腳 構裝。 現今積體電路元件發展的趨勢，無不朝向高積集 度、高密度、小體積、多功能等發展，而這些需求不但反 應於半導體製程的技術發展，同時也呈現於後段半導體封 裝的技術硏發。就半導體製程而言，0,18微米線寬的半導 體元件已進入量產，而系統整合晶片（System on Chip, SOC) 也陸續硏發出來；相對地，諸多高密度的封裝結構也因應 而生，比如：晶片尺寸構裝（Chip Scale Package, CSP)、 多晶片模組（Multi Chip Module, MCM)等。 四方扁平無接腳構裝（Quad Flat Nolead Package, QFN)，由MatsuS1ta公司所開發，是常見以導線架爲構裝 基材之晶片尺寸構裝（lead frame based CSP)。而無接腳 型（leadless)的晶片尺寸構裝具有訊號傳遞路徑（trace) 短，降低訊號衰減的優點，一直是低腳位（1 ow p i n coun t) 半導體元件常用的構裝結構。 請參照第1圖，其繪示習知四方扁平無接腳構裝的 剖面示意圖。習知四方扁平無接腳構裝100的導線架係由 晶片座l〇2(die pad)及其周緣多個接腳104(Uad)所組 成；晶片108以其背面丨08b藉由銀膠106(silver paste) 與晶片座102之頂面102a貼合。晶片108主動表面 108a(active surface)上的焊墊 114(bonding pad)則透過 金線110(gold wire)，分別與接腳104的頂面104a連接， 3 本紙張尺度適用中國國家標準（CNS〉A4規格（210 X 297公釐） I I I. I I — I — In--*------Γ 11 I ----I III r (請先Μ讀背面之注意事項再填寫本頁) 4633 4 2 6 04 9twf * doc /0 06 A7 B7 經濟部智慧財產咼員工消費合泎杜印製 五、發明說明（1) 形成電丨生導通。而封裝材料l〗2(molding compourui)包覆 晶片108 '金線110、晶片座ι〇2的頂面1〇2a及接腳104 的頂面l〇4a，而暴露出晶片座1〇2的底面1〇2b及接腳1〇4 的底面l〇4b。透過接腳1〇4的底面i〇4b與外部的印刷電 路扳（未繪示）連接。 習知四方扁平無接腳構裝係利用金線連接焊墊與接 腳’因此接腳必須配置於晶片之外圍，並保持一適當距離， 約15~30密爾’所以將使得構裝之面積變大。而且封裝材 料爲了包覆金線，因此需要與金線頂端保持一定距離，所 以亦造成構裝的厚度增加。同時，利用金線連接，使得訊 號傳遞路徑變長，使得構裝中訊號傳遞效能降低，可能導 致訊號延遲及衰減。 因此本發明的目的之一就是在提供一種覆晶式四方 扁平無接腳構裝，可以縮小構裝之面積及厚度，提高構裝 密度。 本發明的另一目的在於提供一種覆晶式四方扁平無 接腳構裝，改善構裝的電性，提高構裝的訊號傳遞效能。 本發明的再一目的在於提供一種覆晶式四方扁平無 接腳構裝，改善構裝的散熱效果’提高產品品質。 爲達成本發明之上述和其他目的’提出一種覆晶式 四方扁平無接腳構裝，包括：多個接腳’每一接腳分別具 有第一表面及對應之第二表面。一晶片，具有主動表面及 對應之背面，主動表面具有多個焊墊’每一焊墊分別具有 一凸塊，而每一凸塊分別對應接腳其中之一，並分別與接 4 本紙張尺度適用中國國家標準（CNS)A4規格（2〗〇 X 297公« ) 11-嚴---— l·--- 訂*--1-----線 (請先閲讀背面之注恚事項再填寫本頁) 經濟郎眢慧財產笱員工消費合阼法印製 4633 4 2 6 04 9twf .d〇C/0 〇 6 a? 五、發明說明（> ) 腳之第一表面連接。而封裝材料，包覆接腳及晶片，且暴 露出接腳的第二表面。 依照本發明的一較佳實施例，其中封裝材料可以選 擇性暴露出晶片的背面，而晶片的背面亦可以選擇性配置 一散熱片以改善散熱效能。另外，在晶片的主動表面上亦 可以配置散熱片，並使其—面暴露於封裝材料外，同樣地 可以改善產品散熱效能。 由於本發明晶片與接腳之間的連接係採用覆晶的方 式，僅透過一凸塊形成連接，而且接腳直接與晶片之焊墊 位置重合，更無須晶片座，因此可以縮減封裝之面積及厚 度。另外’晶片係以導電凸塊與接腳形成電性連接，因此 可以縮短訊號傳遞路徑，改善構裝的電性。而在晶片背面 或主動表面增設散熱片，可以改善構裝的散熱效果，提升 產品品質。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂’下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖繪示習知四方扁平無接腳構裝的剖面示意 圖。 第2圖繪示依照本發明第一較佳實施例的一種覆晶 式四方扁平無接腳構裝的剖面示意圖. 第3圖繪示對應於第2圖之仰視圖。 第4圖繪示對應於第2圖之立體透視圖。 - -----I I I ---i I 丨 l· ί I 訂·！ I ---. (請先閱讀背面之注意事項再填寫本頁)Consumption of employees of Intellectual Property Bureau of the Ministry of Economic Affairs printed 6049twf.doc / 006 pj ___B7 V. Description of the invention (丨) The present invention relates to a quadrangular flat, non-pin structure, and in particular to a method of using flip chip Bonded flip-chip square flat pinless structure. At present, the development trend of integrated circuit components is all in the direction of high accumulation, high density, small size, and multi-function. These requirements not only reflect the technological development of semiconductor manufacturing processes, but also present the technology of semiconductor packaging in the later stage. hair. As far as the semiconductor process is concerned, semiconductor components with a line width of 0,18 microns have entered mass production, and System on Chip (SOC) has also been launched. In contrast, many high-density packaging structures have also emerged in response. For example: Chip Scale Package (CSP), Multi Chip Module (MCM), etc. Quad Flat Nolead Package (QFN), developed by MatsuS1ta Corporation, is a lead frame based CSP that is commonly used with a lead frame as the substrate. The leadless chip size structure has the advantages of short signal traces and reduced signal attenuation, and has always been a common structure for low pin (1 ow p i n coun t) semiconductor devices. Please refer to FIG. 1, which shows a schematic cross-sectional view of a conventional square flat no-pin structure. The conventional leadframe of the square flat pinless structure 100 is composed of a die pad 10 (die pad) and a plurality of pins 104 (Uad) on its periphery; the wafer 108 is on its back 丨 08b by silver glue 106 (silver paste) is attached to the top surface 102a of the wafer holder 102. The bonding pads 114 on the active surface 108a (active surface) of the chip 108 are connected to the top surface 104a of the pins 104 through gold wires 110, respectively. 3 This paper size applies to Chinese national standards (CNS> A4 specification (210 X 297 mm) II I. II — I — In-* ------ Γ 11 I ---- I III r (Please read the precautions on the back before filling this page) 4633 4 2 6 04 9twf * doc / 0 06 A7 B7 Intellectual property of the Ministry of Economic Affairs, employee consumption, printed by Du. V. Description of the invention (1) Forming electrical conduction, and packaging material l 2 (molding compourui) coating The wafer 108 ′ gold wire 110, the top surface 102a of the wafer holder 102 and the top surface 104a of the pin 104, and the bottom surface 102b of the wafer holder 102 and the bottom surface of the pin 104 are exposed. l〇4b. Connected to the external printed circuit board (not shown) through the bottom surface of the pin 104, i04b. The conventional square flat, pinless structure uses gold wires to connect the pads to the pins. The feet must be placed on the periphery of the chip and maintain a proper distance, about 15 ~ 30 mil 'so it will make the area of the structure larger. And the packaging material is used to cover the gold wire, because It needs to keep a certain distance from the top of the gold wire, which also causes the thickness of the structure to increase. At the same time, the use of gold wire connection makes the signal transmission path longer, which reduces the signal transmission performance during the construction, which may cause signal delay and attenuation. One of the objects of the invention is to provide a flip-chip tetragonal flat contactless structure, which can reduce the area and thickness of the structure and increase the density of the structure. Another object of the present invention is to provide a flip-chip quadrilateral flat contactless structure. The foot structure improves the electrical properties of the structure and improves the signal transmission efficiency of the structure. Another object of the present invention is to provide a flip-chip tetragonal flat pinless structure to improve the heat dissipation effect of the structure and improve the product quality. In order to achieve the above and other objectives of the present invention, a flip-chip tetragonal flat pinless structure is proposed, including: a plurality of pins. Each pin has a first surface and a corresponding second surface respectively. A chip has Active surface and corresponding back, the active surface has a plurality of pads, each pad has a bump, and each bump corresponds to the pin One of them, and the four paper sizes are applicable to the Chinese National Standard (CNS) A4 specifications (2) 〇X 297 public «） 11-strict ----- l · --- order *-1 --- --Line (please read the notes on the back before filling this page) Economy Lang, Hui Property, Employee Consumption Co-printing Method 4633 4 2 6 04 9twf .d〇C / 0 〇6 a? V. Description of Invention (>) The first surface of the foot is connected. The packaging material covers the pins and the chip, and exposes the second surface of the pins. According to a preferred embodiment of the present invention, the packaging material may selectively expose the back surface of the chip, and the back surface of the chip may be optionally provided with a heat sink to improve heat dissipation performance. In addition, a heat sink can be arranged on the active surface of the chip and its surface is exposed to the packaging material, which can also improve the heat dissipation performance of the product. Because the connection between the chip and the pins of the present invention is a flip-chip method, the connection is formed only through a bump, and the pins directly coincide with the position of the solder pads of the chip, and there is no need for a chip holder, so the area of the package can be reduced and thickness. In addition, the chip is electrically connected to the pins with conductive bumps, so the signal transmission path can be shortened and the electrical properties of the structure can be improved. Adding a heat sink on the back of the chip or on the active surface can improve the heat dissipation effect of the structure and the product quality. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: FIG. 1 A schematic cross-sectional view of a conventional square flat no-pin structure is shown. FIG. 2 is a schematic cross-sectional view of a flip-chip tetragonal flat contactless structure according to the first preferred embodiment of the present invention. FIG. 3 is a bottom view corresponding to FIG. 2. FIG. 4 is a perspective view corresponding to FIG. 2. ------ I I I --- i I 丨 l · I order! I ---. (Please read the notes on the back before filling this page)

463342 6049twf ,d〇c / 006 A7 B7 五、發明說明（ψ) 第5圖繪示對應於第2圖中接腳202的局部放大立 體圖。 第6圖繪示本發明第二較佳實施例，一種覆晶式四 方扁平無接腳構裝剖面示意圖。 第7圖繪示本發明第三較佳實施例，一種覆晶式四 方扁平無接腳構裝剖面示意圖。 第8圖繪示本發明第四較佳實施例，一種覆晶式四 方扁平無接腳構裝剖面示意圖。 第9圖繪示本發明第五較佳實施例，一種覆晶式四 方扁平無接腳構裝剖面示意圖 弟10圖繪不本發明第六較佳實施例，一種覆晶式 四方扁平無接腳構裝剖面不意圖。 第11圖繪不本發明第七較佳實施例，一種覆晶式 四方扁平無接腳構裝剖面斤;意圖。 第12圖繪不本發明桌八較佳實施例，一種覆晶式 四方扁平無接腳構裝剖面示意圖。 圖式之標示說明： 100 :四方扁平無接腳構裝 102 :晶片座 102a、丨04a、232、244 :頂面 102b、104b、234、246 :底面 104、202 :接腳 106 :銀膠 108、210 :晶片 6 本紙張尺度適用中國國家標率（CNS)A4規格（210 X 297公釐） II Ϊ - - I I 1 L--- I 訂·！ (請先閲讀背面之注意事項再填寫本頁> 6 334 2 6049twf, doc/006 幻 __ _ B7 " ------ 五、發明說明（f) 108a、212 :主動表面 108b、214 :背面 110 :金線 {請先閱讀背面之注意事項再填窝本頁) 112、224、226、228、240、248、250 :封裝材料 114、216 :焊墊 200 :覆晶式四方扁平無接腳構裝 204 :第一表面 206 :第二表面 218 :凸塊 220 :焊罩層 222 :開□ 230、238、242 :散熱片 236 :導熱材料 富施例 請同時參照第2圖、第3圖及第4圖，其中第2圖 繪示依照本發明第一較佳實施例的一種覆晶式四方扁平無 接腳構裝的剖面示意圖；第3圖繪示對應於第2圖之仰視 圖；而第4圖繪示對應於第2圖之立體透視圖。 經濟郎智慧財產局員^消費合阼达印製 本發明的覆晶式四方扁平無接腳構裝200採用導線 架型承載器，其係由多個接腳202所構成，每一接腳202 分別具有第一表面204(頂面）及對應之第二表面206(底 面）。晶片210具有主動表面212( active surface)及對應 之背面214(backside)，主動表面212具有多個焊墊 216(bonding pad)，其上分別形成有凸塊218(bump)。其 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 痤齊郎智慧时4局員X消費合怍ii印製 6 33 4 2 6 0 4 9 twf . doc /0 0 6 ^ _____B7__ 五、發明說明（6) 中凸塊218的製程還包括：球底金屬層（under bump metai， UBM)的形成，及凸塊的形成等，在此不再贅述，而凸塊218 之材質包括錫鉛合金，金或導電高分子材料（conductive polymer)等。晶片210以主動表面212面對接腳202配置， 並使得每一凸塊218對應一接腳202的第一表面204，晶 片210則透過凸塊218分別與接腳202形成電性連接。而 封裝材料224包覆晶片210及接腳202的第一表面204， 而暴露出接腳202的第二表面206及側面，以作爲構裝對 外的接點，其中封裝材料224的材質比如是環氧樹脂 (epoxy) 〇 然而，爲了確保覆晶製程的良率，較佳是在接腳202 的第一表面204進行防焊處理（solder res i s t ance) ^請 同時參照第5圖，其繪示對應於第2圖中接腳202的局部 放大立體圖。較佳的防焊處理是在接腳202的第一表面204 形成一焊罩層 220(solder mask or solder resistor)， 其材質爲絕緣材料，包括紫外線型綠漆及熱硬化型綠漆 等，形成焊罩層220之方法則包括滾筒塗佈法（Roller Coating)、簾幕塗佈法（Curtain Coating)、網版印刷法 (Screen Printing)、浸染法（Di p)以及乾膜（Dry Fi lm) 形成方法等。然後定義焊罩層220，使其對應欲接合凸塊 的位置形成一開口 222，藉由開口 222可以使得後續覆晶 製程中，凸塊在接合時會侷限其附著範圍，確保其順利接 合。 上述實施例中凸塊218對於錫鉛凸塊而言，其直徑 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 11 1---------- 裝·----^*"··訂------— I ·線 (請先閲讀背面之注意事項再填寫本頁) Α7 Β7 4633 4 2 6049twf . doc/006 五、發明說明（夕） 大約100-200微米，而對金凸塊而言，其直徑大約25微 米。相對於習知打線的接合結構，其金線之長度大約介於 500〜3000微米，因此本發明的覆晶式四方扁平無接腳構裝 可以縮短訊號傳遞路徑，可以大幅改善構裝的電性。另外 覆晶的結構，亦可以縮減構裝的面積及厚度，提高構裝的 密度。另外，對於錫鈴凸塊而言，其形成方法可以藉由電 鍍（plating)或網版印刷（screen printing)的方式，形成 一錫鉛材料於對應的球底金屬層表面，再經過迴銲（refl〇w) 而形成錫錯凸塊。 然而’爲了提高構裝的散熱效果，本發明的構裝結 構可以有下面幾種變化： 首先請參照第6圖，其繪示本發明第二較佳實施例， 一種覆晶式四方扁平無接腳構裝剖面示意圖。有別於第一 實施例在於本實施例的封裝材料226在進行封膠 (encapsulating)時，將晶片210的背面214裸露出來， 使得晶片210所產生的熱可以直接發散至外界。 請再參照第7圖，其繪示本發明第三較佳實施例， 一種覆晶式四方扁平無接腳構裝剖面示意圖。還可以在晶 片 210 的同面 214 配置一散熱片 23〇(heat sink，heat slug 〇r heat spreader)，其具有一頂面232及對應之一底面 234，散熱片23〇以其底面234面對晶片21〇背面214配 置。散熱片23〇可以連接晶片21〇或保持一定距離配置， 而封裝材料228將暴露出散熱片230之頂面232。晶片210 可以藉由散熱片230將所產生之熱能發散至外界。 ----.11! ^--11------ («·先閲讀背面之注$項再填寫本頁) 經濟部智慧財產局員X消費合阼ti印製 公 y/ N X 1υ Νϊ «L 4 Λ / 0 4 6 33 4 2 t w f . doc /0 0 6 A7 B7 五、發明說明（i>) 請參照第8圖，其繪示本發明第四較佳實施例，一 種壤晶式四方扁平無接腳構裝剖面示意圖。本實施例中， 類似第二實施例之結構，然而可以選擇性地在暴露出的晶 片210背面214配置一散熱片238，而散熱片238係以一 導熱性材料236固定於晶片210背面214。如此，可以進 〜歩提高構裝的散熱效果。 請參照第9圖，其繪示本發明第五較佳實施例，一 種複晶式四方扁平無接腳構裝剖面示意圖。散熱片除了如 上述實施例可以配置於晶片的背面外，亦可以選擇性地配 置於晶片主動表面的一側。如第9圖所示，在晶片210之 主動表面212的一側，配置一散熱片242(heat s ink)，其 具有一頂面244及一底面246。散熱片242則置於各接腳 202的中間，亦即接腳202位於散熱片242的周緣，而封 裝材料240在封膠時會暴露出散熱片242之底面246，使 得晶片210所產生之熱能藉由散熱片242發散至外界。而 在後續組裝時，接腳202藉由表面焊接技術（surface mount technology，SMT)與電路板（PCB)連接的同時，散熱片亦 可以其底面246與電路板連接，藉由電路板散熱。 請參照弟10圖，其繪不本發明第六較佳實施例， 一種覆晶式四方扁平無接腳構裝剖面示意圖。上述第五實 施例的結構可以與前述第二、三、四實施例結合應用。本 實施例即是將第五實施例與第二實施例結合，將第五實施 例中，晶片210的背面214在封裝材料248封膠時暴露出 來0 本紙張尺度適用中闺闺家標準（CNS)A4規格（21〇 X 297公釐） ----* 裝-----^! — 訂 -------線 (請先閱讀背面之注意事項再填寫本頁) 4 633 4 2 6049twf.doc/006 八7 _B7_ 五、發明說明（1 ) 請參照第11圖，其繪示本發明第七較佳實施例， 一種覆晶式四方扁平無接腳構裝剖面示意圖。此實施例則 是將第五實施例與第三實施例結合，在晶片210背面214 配置一散熱片230。散熱片230具有一頂面232及對應之 一底面234，散熱片230以其底面234面對晶片210背面 214配置。散熱片230可以連接晶片210或保持一定距離 配置，而封裝材料250暴露出散熱片230之頂面232。 請參照第U圖，其繪示本發明第八較佳實施例， 一種覆晶式四方扁平無接腳構裝剖面示意圖。此實施例係 將第六實施例與第四實施例結合，將裸露的晶片210背面 214連接一散熱片238,而散熱片238藉由一導熱性材料236 固定於晶片210背面214。 綜上所述，本發明至少具有下列優點： 1. 本發明之覆晶式四方扁平無接腳構裝，由於本發 明晶片與接腳之間的連接係採用覆晶的方式，僅透過一凸 塊形成連接，而且接腳直接與晶片之焊墊位置重合，而承 載器無須晶片座之設置，因此可以縮小構裝之面積及厚 度，提高構裝密度。 2. 本發明之覆晶式四方扁平無接腳構裝中，另外， 晶片係以導電凸塊與接腳形成電性連接，因此可以縮短訊 號傳遞路徑，避免訊號之衰減及延遲，改善構裝的電性， 提高構裝的訊號傳遞效能。 3. 本發明之覆晶式四方扁平無接腳構裝，可以裸露 晶片背面，而在晶片背面或主動表面可以選擇性增設散熱 (請先閱讀背面之注意事項再填寫本1) 裝-----..---—訂--------線. 痤齊郎智慧时產局貝X消費合泎fi印製 本紙張尺度適用中0 0家標準（CNS)A4規格（210 X 297公釐） 33 Λ ? 6049twf . doc/006 A7 B7 五、發明說明U〇) 片，以改善構裝的散熱效果，提升產品品質。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 (锖先IW讀背面之注意事項再填寫本頁) 裝----l·---tr-i-------線. 絰濟郎智慧財產局員工消費合阼杜印裂 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐）463342 6049twf, doc / 006 A7 B7 V. Description of the invention (ψ) Figure 5 shows a partially enlarged perspective view corresponding to the pin 202 in Figure 2. FIG. 6 is a schematic cross-sectional view of a flip-chip tetragonal flat contactless structure according to a second preferred embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of a flip-chip tetragonal flat contactless structure according to a third preferred embodiment of the present invention. FIG. 8 shows a fourth preferred embodiment of the present invention, a schematic cross-sectional view of a flip-chip tetragonal flat no-pin structure. FIG. 9 shows a fifth preferred embodiment of the present invention, a schematic cross-sectional view of a flip-chip tetragonal flat non-pin structure. The construction profile is not intended. FIG. 11 illustrates a seventh preferred embodiment of the present invention, a flip-chip type, square flat, non-pin structured cross section; FIG. 12 is a schematic cross-sectional view of a flip-chip tetragonal flat, non-pin structure according to a preferred embodiment of the eighth table of the present invention. Description of the drawing: 100: square flat without pin structure 102: wafer holder 102a, 04a, 232, 244: top surface 102b, 104b, 234, 246: bottom surface 104, 202: pin 106: silver glue 108 210: Wafer 6 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) II Ϊ--II 1 L --- I Order ·! (Please read the notes on the back before filling in this page> 6 334 2 6049twf, doc / 006 Magic __ _ B7 " ------ V. Description of the invention (f) 108a, 212: Active surface 108b, 214: back 110: gold wire (please read the precautions on the back before filling this page) 112, 224, 226, 228, 240, 248, 250: packaging materials 114, 216: solder pads 200: flip-chip tetragonal flat Pinless structure 204: First surface 206: Second surface 218: Bump 220: Welding cover layer 222: Open 230, 238, 242: Heat sink 236: For examples of thermally conductive materials, please refer to Figure 2 at the same time. 3 and 4, wherein FIG. 2 is a schematic cross-sectional view of a flip-chip tetragonal flat contactless structure according to the first preferred embodiment of the present invention; and FIG. 3 is a diagram corresponding to FIG. 2. Bottom view; and Figure 4 shows a perspective perspective view corresponding to Figure 2. The member of the Economic Property Bureau of Intellectual Property ^ Consumption Heda printed the flip-chip tetragonal flat pinless structure 200 of the present invention using a leadframe type carrier, which is composed of a plurality of pins 202, each of which is respectively 202 It has a first surface 204 (top surface) and a corresponding second surface 206 (bottom surface). The chip 210 has an active surface 212 (active surface) and a corresponding backside 214 (active side). The active surface 212 has a plurality of bonding pads 216 (bumps) formed thereon. The 7 paper sizes are in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm). Achilles' Wisdom 4 Bureaux X Consumption Printing ii 6 33 4 2 6 0 4 9 twf .doc / 0 0 6 ^ _____B7__ 5. The process of the bump 218 in the description of the invention (6) also includes the formation of an under bump metai (UBM), and the formation of bumps, which will not be repeated here. Materials include tin-lead alloy, gold, or conductive polymer. The chip 210 is configured with the active surface 212 facing the pin 202, and each bump 218 corresponds to the first surface 204 of a pin 202. The chip 210 is electrically connected to the pin 202 through the bump 218, respectively. The packaging material 224 covers the chip 210 and the first surface 204 of the pin 202, and exposes the second surface 206 and the side surface of the pin 202 as the external contacts for the structure. The material of the packaging material 224 is, for example, a ring. Epoxy resin 〇 However, in order to ensure the yield of the flip-chip process, it is preferable to perform solder resistance on the first surface 204 of the pin 202 ^ Please refer to FIG. 5 at the same time, which is shown in FIG. A partially enlarged perspective view corresponding to the pin 202 in FIG. 2. A preferred solder masking process is to form a solder mask layer 220 (solder mask or solder resistor) on the first surface 204 of the pin 202. The material is an insulating material, including ultraviolet-type green paint and thermosetting green paint. The method of the solder mask layer 220 includes a roller coating method, a curtain coating method, a screen printing method, a dip method, and a dry film. Formation method, etc. Then, the solder mask layer 220 is defined so that an opening 222 is formed corresponding to the position where the bumps are to be joined. The openings 222 can make the bumps limit the attachment range of the bumps during the subsequent flip-chip manufacturing process to ensure smooth joining. For the tin-lead bumps in the above embodiment, the diameter of the bumps 218 is 8. The paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 11 1 ---------- · ---- ^ * " ·· Order ------— I · Line (please read the notes on the back before filling this page) Α7 Β7 4633 4 2 6049twf .doc / 006 V. Description of the invention ( (Even) about 100-200 microns, and for gold bumps, its diameter is about 25 microns. Compared with the conventional bonding structure of wire bonding, the length of the gold wire is about 500 ~ 3000 microns, so the flip-chip tetragonal flat no-pin structure of the present invention can shorten the signal transmission path and greatly improve the electrical properties of the structure. . In addition, the flip-chip structure can also reduce the area and thickness of the structure, and increase the density of the structure. In addition, for the tin bell bump, the formation method can be formed by plating or screen printing to form a tin-lead material on the surface of the corresponding ball-bottom metal layer, and then re-soldering ( refl0w) to form tin bumps. However, in order to improve the heat dissipation effect of the structure, the structure of the present invention may have the following changes: First, please refer to FIG. 6, which shows a second preferred embodiment of the present invention Schematic cross-section of foot structure. The difference from the first embodiment lies in that the encapsulating material 226 of this embodiment exposes the back surface 214 of the chip 210 during encapsulating, so that the heat generated by the chip 210 can be directly radiated to the outside. Please refer to FIG. 7 again, which illustrates a third preferred embodiment of the present invention, a schematic cross-sectional view of a flip-chip tetragonal flat, non-pin structure. A heat sink 23o (heat sink, heat slug or heat spreader) can also be arranged on the same surface 214 of the chip 210. The heat sink 23o has a top surface 232 and a corresponding bottom surface 234, and the heat sink 23 is faced by the bottom surface 234. The wafer 21 and the back surface 214 are arranged. The heat sink 23 can be connected to the chip 21 or can be arranged at a certain distance, and the packaging material 228 will expose the top surface 232 of the heat sink 230. The chip 210 can radiate the generated heat energy to the outside through the heat sink 230. ----. 11! ^-11 ------ («· Please read the note on the back of the page before filling in this page) Member of the Intellectual Property Bureau of the Ministry of Economic Affairs X Consumption and Printing y / NX 1υ Νϊ «L 4 Λ / 0 4 6 33 4 2 twf. Doc / 0 0 6 A7 B7 V. Description of the invention (i >) Please refer to FIG. 8, which shows the fourth preferred embodiment of the present invention, a soil crystal form Schematic cross-section view of a square flat no-pin structure. In this embodiment, the structure is similar to that of the second embodiment, however, a heat sink 238 can be selectively disposed on the exposed back surface 214 of the wafer 210, and the heat sink 238 is fixed to the back surface 214 of the wafer 210 with a thermally conductive material 236. In this way, the heat dissipation effect of the structure can be improved. Please refer to FIG. 9, which is a schematic cross-sectional view of a fifth preferred embodiment of the present invention. The heat sink can be arranged on the back side of the wafer as in the above embodiment, or can be selectively arranged on one side of the active surface of the wafer. As shown in FIG. 9, a heat sink 242 (heat ink) is disposed on one side of the active surface 212 of the chip 210 and has a top surface 244 and a bottom surface 246. The heat sink 242 is placed in the middle of each pin 202, that is, the pin 202 is located on the periphery of the heat sink 242, and the sealing material 240 will expose the bottom surface 246 of the heat sink 242 during the sealing, so that the thermal energy generated by the chip 210 It is emitted to the outside through the heat sink 242. During subsequent assembly, while the pin 202 is connected to the circuit board (PCB) by surface mount technology (SMT), the heat sink can also be connected to the circuit board at its bottom surface 246 to dissipate heat through the circuit board. Please refer to FIG. 10, which illustrates a schematic cross-sectional view of a flip-chip tetragonal flat, no-pin structure according to a sixth preferred embodiment of the present invention. The structure of the fifth embodiment described above can be applied in combination with the foregoing second, third, and fourth embodiments. This embodiment is a combination of the fifth embodiment and the second embodiment. In the fifth embodiment, the back surface 214 of the chip 210 is exposed when the sealing material 248 is sealed. ) A4 specification (21〇X 297 mm) ---- * Packing ----- ^! — Order ------- line (Please read the precautions on the back before filling this page) 4 633 4 2 6049twf.doc / 006 8 7 _B7_ 5. Description of the invention (1) Please refer to FIG. 11, which shows a seventh preferred embodiment of the present invention, a schematic cross-sectional view of a flip-chip tetragonal flat no-pin structure. In this embodiment, the fifth embodiment is combined with the third embodiment, and a heat sink 230 is disposed on the back surface 214 of the chip 210. The heat sink 230 has a top surface 232 and a corresponding bottom surface 234, and the heat sink 230 is disposed with its bottom surface 234 facing the back surface 214 of the chip 210. The heat sink 230 may be connected to the chip 210 or disposed at a certain distance, and the packaging material 250 exposes the top surface 232 of the heat sink 230. Please refer to FIG. U, which illustrates an eighth preferred embodiment of the present invention, a schematic cross-sectional view of a flip-chip tetragonal flat contactless structure. In this embodiment, the sixth embodiment is combined with the fourth embodiment, and the exposed back surface 214 of the chip 210 is connected to a heat sink 238, and the heat sink 238 is fixed to the back surface 214 of the wafer 210 by a thermally conductive material 236. To sum up, the present invention has at least the following advantages: 1. The flip-chip tetragonal flat pinless structure of the present invention, because the connection between the wafer and the pins of the present invention is a flip-chip method, only through a convex The blocks form a connection, and the pins directly coincide with the positions of the pads of the wafer, and the carrier does not need to be provided with a wafer holder, so the area and thickness of the structure can be reduced, and the density of the structure can be increased. 2. In the flip-chip tetragonal flat pinless structure of the present invention, in addition, the chip is electrically connected to the pins with conductive bumps, so the signal transmission path can be shortened, signal attenuation and delay can be avoided, and the structure can be improved. Electrical performance, improve the signal transmission performance of the structure. 3. The flip-chip tetragonal flat pinless structure of the present invention can expose the back of the chip, and can optionally add heat dissipation on the back of the chip or the active surface (please read the precautions on the back before filling in this 1). Installation --- --..----- Order -------- line. Acqilang Wisdom Time Production Bureau X Consumption Fi Fi Printed This paper is applicable in 0 0 standards (CNS) A4 specifications (210 X 297 mm) 33 Λ? 6049twf.doc / 006 A7 B7 V. Description of the invention U0) film, in order to improve the heat dissipation effect of the structure and the product quality. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (I first read the precautions on the back of IW before filling out this page) Install ---- l · --- tr-i ------- line. 绖 Jilang Intellectual Property Bureau Staff Consumption Du Yinye 12 This paper size applies to China National Standard (CNS) A4 (210 * 297 mm)

Claims (1)

4 Ϊ33 4 2 €049twf.doc/006 A8B8C8D8 六、申請專利範圍 六、申請專利範圍 1. 一種覆晶式四方扁平無接腳構裝，包括： 複數個接腳，每一該些接腳分別具有一第一表面及 對應之一第二表面； 一晶片，具有一主動表面及對應之一背面，該主動 表面具有複數個焊墊，每一該些焊墊分別具有一凸塊，每 一該些凸塊分別對應該些接腳之一，並分別與該些接腳之 該第一表面連接；以及 一封裝材料，包覆該些接腳及該晶片，且暴露出該 些接腳的該第二表面。 2. 如申請專利範圍第1項所述之覆晶式四方扁平無 接腳構裝，其中該些接腳呈四方形排列。 3. 如申請專利範圍第1項所述之覆晶式四方扁平無 接腳構裝，其中該些接腳的該第一表面分別具有一防焊 層，且該防焊層對應該些凸塊連接的位置分別具有一開 □。 4. 如申請專利範圍第1項所述之覆晶式四方扁平無 接腳構裝，其中該些凸塊包括錫鉛凸塊。 5. 如申請專利範圍第1項所述之覆晶式四方扁平無 接腳構裝，其中該些凸塊包括金凸塊。 6. 如申請專利範圍第4項所述之覆晶式四方扁平無 接腳構裝，其中該些錫鉛凸塊係藉由電鍍及迴銲形成。 7. 如申請專利範圍第4項所述之覆晶式四方扁平無 接腳構裝，其中該些錫鉛凸塊係藉由網版印刷及迴銲形 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) Γ—-------線一 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 33 4 2 A8 B8 6049twf . doc/ 006 C8 D8 六、申請專利範圍 成。 8. 如申請專利範圍第5項所述之覆晶式四方扁平無 接腳構裝，其中該些金凸塊係藉由一打線機，在每一焊墊 分別打上該些金凸塊而形成。 9. 如申請專利範两第1項所述之覆晶式四方扁平無 接腳構裝，其中該封裝材料還可暴露出該晶片之該背面。 10. 如申請專利範圍第1項所述之覆晶式四方扁平 無接腳構裝，其中該封裝材料包括環氧樹脂。 11. 如申請專利範圍第9項所述之覆晶式四方扁平 無接腳構裝，其中該晶片之該背面更配置有一散熱片，且 該散熱片藉由一導熱性材料與該晶片之該背面連接。 12. 如申請專利範圍第1項所述之覆晶式四方扁平 無接腳構裝，其中該晶片之該背面配置有一散熱片，該散 熱片具有一底面及對應之一頂面，而該散熱片以該底面面 對該晶片之該背面配置，且該封裝材料暴露出該散熱片之 該頂面。 13. —種覆晶式四方扁平無接腳構裝，包括： 一第一散熱片，具有一第一頂面及對應之一第一底 面； 複數個接腳，配置於該第一散熱片之周緣，每一該 些接腳分別具有一第一表面及對應之一第二表面； 一晶片，具有一主動表面及對應之一背面，該主動 表面具有複數個焊墊，每一該些焊墊分別具有一凸塊，該 晶片以該主動表面面對該第一散熱片之第一頂面配置，而 I 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I------------裝 -------訂---11 ---線 (請先閱讀背面之注意事項再填寫本頁) 6 8 8 S ASSCD Q Q /1 Ο 。j 1 “ 6049twf . doc/006 六、申請專利範圍 每一該些凸塊分別對應該些接腳之一，並分別與該些接腳 之該第一表面連接；以及 一封裝材料，包覆該些接腳、該第一散熱片及該晶 片’且暴露出該些接腳的該第二表面與該散熱片之該底 面。 14.如申請專利範圍第13項所述之覆晶式四方扁平 無接腳構裝，其中該些接腳的該第一表面分別具有一防焊 層，且該防焊層對應該些凸塊連接的位置分別具有一開 □。 15·如申請專利範圍第13項所述之覆晶式四方扁平 無接腳構裝，其中該些凸塊包括錫鉛凸塊。 16·如申請專利範圍第13項所述之覆晶式四方扁平 無接腳構裝，其中該些凸塊包括金凸塊。 Π.如申請專利範圍第13項所述之覆晶式四方扁平 無接腳構裝，其中該封裝材料還可暴露出該晶片之該背 面。 18. 如申請專利範圍第13項所述之覆晶式四方扁平 無接腳構裝，其中該封裝材料包括環氧樹脂。 19. 如申請專利範圍第17項所述之覆晶式四方扁平 無接腳構裝，其中該晶片之該背面更配置有一第二散熱 片，且該第二散熱片藉由一導熱性材料與該晶片之該背面 連接。 20. 如申請專利範圍第13項所述之覆晶式四方扁平 無接腳構裝，其中該晶片之該背面配置有一第二散熱片， 15 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I J 11--- ----------訂-- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 633 4 2 A8 B8 6049twf,doc/006 C8 D8 六、申請專利範圍 該第二散熱片具有一第二底面及對應之一第二頂面，而該 散熱片以該第二底面連接該晶片之該背面，且該封裝材料 暴露出該散熱片之該第二頂面。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）4 Ϊ33 4 2 € 049twf.doc / 006 A8B8C8D8 6. Scope of patent application 6. Scope of patent application 1. A flip-chip tetragonal flat non-pin structure, including: a plurality of pins, each of which has A first surface and a corresponding second surface; a wafer having an active surface and a corresponding back surface, the active surface having a plurality of pads, each of which has a bump, each of which The bumps respectively correspond to one of the pins and are respectively connected to the first surfaces of the pins; and a packaging material covering the pins and the chip, and exposing the first pins of the pins. Two surfaces. 2. The flip-chip tetragonal flat non-pin structure described in item 1 of the scope of patent application, wherein the pins are arranged in a square shape. 3. The flip-chip tetragonal flat no-pin structure described in item 1 of the scope of the patent application, wherein the first surfaces of the pins each have a solder resist layer, and the solder resist layer corresponds to the bumps. The position of the connection has an opening □. 4. The flip-chip tetragonal flat contactless structure described in item 1 of the scope of patent application, wherein the bumps include tin-lead bumps. 5. The flip-chip tetragonal flat contactless structure described in item 1 of the scope of patent application, wherein the bumps include gold bumps. 6. The flip-chip tetragonal flat contactless structure described in item 4 of the scope of patent application, wherein the tin-lead bumps are formed by electroplating and reflow. 7. The flip-chip tetragonal flat no-pin structure as described in item 4 of the scope of the patent application, wherein the tin-lead bumps are screen-printed and re-soldered. 13 This paper size applies to Chinese national standards (CNS ) A4 size (210 X 297 mm) (Please read the precautions on the back before filling out this page) Γ ——------- Employee Cooperative of Line 1 Ministry of Economic Affairs Intellectual Property Bureau Consumer Cooperative Printed by Ministry of Economic Affairs Intellectual Property Bureau employees Printed by the Consumer Cooperative 33 4 2 A8 B8 6049twf.doc / 006 C8 D8 6. The scope of patent application is completed. 8. The flip-chip tetragonal flat pinless structure as described in item 5 of the scope of the patent application, wherein the gold bumps are formed by a wire bonding machine, and the gold bumps are formed on each pad separately. . 9. The flip-chip tetragonal flat contactless structure described in item 1 of the patent application, wherein the packaging material can also expose the back of the wafer. 10. The flip-chip tetragonal flat pinless structure described in item 1 of the scope of patent application, wherein the packaging material includes epoxy resin. 11. The flip-chip tetragonal flat pinless structure described in item 9 of the scope of the patent application, wherein the back surface of the chip is further provided with a heat sink, and the heat sink is made of a thermally conductive material and the chip. Back connection. 12. The flip-chip tetragonal flat pinless structure described in item 1 of the scope of patent application, wherein the back surface of the chip is provided with a heat sink, the heat sink has a bottom surface and a corresponding top surface, and the heat dissipation The sheet is arranged with the bottom surface facing the back surface of the chip, and the packaging material exposes the top surface of the heat sink. 13. —Flip-chip type tetragonal flat pinless structure, including: a first heat sink with a first top surface and a corresponding first bottom surface; a plurality of pins arranged on the first heat sink On the periphery, each of the pins has a first surface and a corresponding second surface; a wafer having an active surface and a corresponding back surface, the active surface has a plurality of pads, and each of the pads Each has a bump, the chip is arranged with the first top surface of the active surface facing the first heat sink, and the paper size of I 4 is applicable to China National Standard (CNS) A4 (210 X 297 mm) I- ----------- install ------- order --- 11 --- line (please read the precautions on the back before filling this page) 6 8 8 S ASSCD QQ / 1 Ο . j 1 “6049twf. doc / 006 VI. The scope of the patent application corresponds to one of the pins for each of the bumps, and is connected to the first surface of the pins respectively; and a packaging material covering the The pins, the first heat sink and the chip, and the second surface of the pins and the bottom surface of the heat sink are exposed. 14. The flip-chip tetragonal flat as described in item 13 of the scope of patent application No-pin structure, wherein the first surfaces of the pins are provided with a solder resist layer, and the solder resist layer has an opening corresponding to the position where the bumps are connected. 15 · If the scope of application for patent No. 13 The flip-chip tetragonal flat non-pin structure described in item 1, wherein the bumps include tin-lead bumps. 16. The flip-chip quadrilateral flat no-pin structure described in item 13 of the patent application scope, wherein The bumps include gold bumps. Π. The flip-chip tetragonal flat pinless structure described in item 13 of the scope of patent application, wherein the packaging material can also expose the back surface of the chip. Flip-chip tetragonal flat contactless structure as described in item 13 of the patent The packaging material includes epoxy resin. 19. The flip-chip tetragonal flat pinless structure described in item 17 of the scope of patent application, wherein the back surface of the chip is further provided with a second heat sink, and the first The two heat sinks are connected to the back surface of the chip through a thermally conductive material. 20. The flip-chip tetragonal flat pinless structure described in item 13 of the scope of the patent application, wherein the back surface of the chip is provided with a second Heat sink, 15 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) IJ 11 --- ---------- Order-(Please read the precautions on the back before (Fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 633 4 2 A8 B8 6049twf, doc / 006 C8 D8 VI. Scope of patent application The second heat sink has a second bottom surface and a corresponding second top surface And the heat sink is connected to the back surface of the chip with the second bottom surface, and the packaging material exposes the second top surface of the heat sink. (Please read the precautions on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperative Zhang scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm)
TW089116723A 2000-08-18 2000-08-18 Flip-chip quad-flat nolead package TW463342B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7312105B2 (en) 2004-06-29 2007-12-25 Advanced Semiconductor Engineering, Inc. Leadframe of a leadless flip-chip package and method for manufacturing the same
CN105047636A (en) * 2014-04-17 2015-11-11 恩智浦有限公司 Single inline no-lead semiconductor package
TWI690039B (en) * 2019-07-03 2020-04-01 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7312105B2 (en) 2004-06-29 2007-12-25 Advanced Semiconductor Engineering, Inc. Leadframe of a leadless flip-chip package and method for manufacturing the same
US7602053B2 (en) 2004-06-29 2009-10-13 Advanced Semiconductor Engineering, Inc. Leadframe of a leadless flip-chip package and method for manufacturing the same
CN105047636A (en) * 2014-04-17 2015-11-11 恩智浦有限公司 Single inline no-lead semiconductor package
TWI690039B (en) * 2019-07-03 2020-04-01 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof

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