JPH03214763A - Lead frame for semiconductor integrated circuit device and the device using the same - Google Patents
Lead frame for semiconductor integrated circuit device and the device using the sameInfo
- Publication number
- JPH03214763A JPH03214763A JP970990A JP970990A JPH03214763A JP H03214763 A JPH03214763 A JP H03214763A JP 970990 A JP970990 A JP 970990A JP 970990 A JP970990 A JP 970990A JP H03214763 A JPH03214763 A JP H03214763A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- lead frame
- circuit device
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 230000017525 heat dissipation Effects 0.000 claims description 15
- 239000008188 pellet Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011889 copper foil Substances 0.000 abstract description 2
- 238000000465 moulding Methods 0.000 abstract 2
- 238000005476 soldering Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置のリードフレーム及びこれ
を用いた半導体集積回路装置に関し、特に熱抵抗を低減
する半導体集積回路装置のリードフレーム及びこれを用
いた半導体集積回路装置に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor integrated circuit device and a semiconductor integrated circuit device using the same, and particularly to a lead frame for a semiconductor integrated circuit device that reduces thermal resistance and the same. The present invention relates to a semiconductor integrated circuit device using.
従来、この種の技術としては、モールド封入のパッケー
ジで、第４図に示すＤＩＰタイプの放熱フィン１２付半
導体集積回路装置のリードフレーム（以下リードフレー
ムと記す）や第５図に示すＳＩＰタイプの放熱フィン２
２付リードフレームがある程度で、モールド封入のフラ
ットパッケージやＳＯＰタイプのパッケージは、特に、
放熱フィンのように構造的に熱をにがす技術はないのが
現状である。Conventionally, as this type of technology, molded packages are used, such as the DIP type lead frame (hereinafter referred to as lead frame) of a semiconductor integrated circuit device with heat dissipation fins 12 shown in FIG. 4, and the SIP type shown in FIG. 5. Heat dissipation fin 2
In particular, molded flat packages and SOP type packages with lead frames with 2 attachments,
Currently, there is no technology that structurally dissipates heat like heat dissipation fins.
上述した従来のＤＩＰタイプのＩＣパッケージの放熱フ
ィン付リードフレームでは、ＱＦＰなどのＦｌａｔ系Ｉ
Ｃパッケージでは実施することが不可能で、又、ＤＩＰ
タイプのＩＣパッケージでも実施面積が大きくなる欠点
がある。In the lead frame with heat dissipation fins of the conventional DIP type IC package mentioned above, Flat type I such as QFP
It is impossible to implement with C package, and DIP
Even with this type of IC package, there is a drawback that the implementation area is large.
又、リードフレームの材質を変える等の対策では、熱抵
抗低減には限度があり、最近の大規模回路のモノリジッ
ク化の傾向に対してＩＣパッケージのもつ熱抵抗で集積
化できないという欠点がある。Furthermore, there is a limit to the reduction in thermal resistance with measures such as changing the material of the lead frame, and there is a drawback that the thermal resistance of the IC package prevents integration with the recent trend toward monolithic large-scale circuits.
本発明の目的は、実装面積を拡大することなく熱抵抗を
低減でき、大規模回路のモノリシック化に対応できるＩ
Ｃパッケージのリードフレームとこれを用いた半導体集
積回路装置を提供することにある。An object of the present invention is to reduce thermal resistance without expanding the mounting area and to adapt to monolithic large-scale circuits.
An object of the present invention is to provide a C package lead frame and a semiconductor integrated circuit device using the lead frame.
１．本発明の半導体集積回路装置のリードフレームは、
ペレットを搭載するアイランドの裏面側に前記アイラン
ドと同一材質の放熱用ピンが突出している。1. The lead frame of the semiconductor integrated circuit device of the present invention includes:
A heat dissipation pin made of the same material as the island protrudes from the back side of the island on which the pellets are mounted.
２，本発明のＱＦＰタイプＩＣパッケージの半導体集積
回路装置は、第１項記載の半導体集積回路装置のリード
フレームのアイランドにペレッ１〜を搭載しモールド樹
脂封止されている，，３．本発明のＤＩＰタイプＩＣパ
ッケージの半導体集積回路装置は、第１−項記載の半導
体集積回路装置のリードフレームのアイランドにペレッ
１〜を搭載しモールド樹脂封止されている。2. In the semiconductor integrated circuit device of the QFP type IC package of the present invention, the pellets 1 to 1 are mounted on the island of the lead frame of the semiconductor integrated circuit device described in item 1 and sealed with mold resin. In the semiconductor integrated circuit device of the DIP type IC package of the present invention, pellets 1 to 1 are mounted on the islands of the lead frame of the semiconductor integrated circuit device described in section 1-1 and sealed with mold resin.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ），（１））は本発明の第１の実施例のリー
ドフレームを遡用した４８ｐ ｉ ｎＱＦＰタイプのＩ
Ｃパッケージの底面図及びＡ−Ａ′線断面図、第２図は
第］−図（ａ＞，（ｂ）のＩＣパッケージをプリント基
板に実装した断面図である。Figure 1 (a), (1)) shows a 48 pin QFP type I which uses the lead frame of the first embodiment of the present invention.
FIG. 2 is a bottom view and a cross-sectional view taken along the line A-A' of the C package, and FIG. 2 is a cross-sectional view of the IC package shown in FIGS.
第１の実施例は、第１図（ａ），（ｂ）に示すように、
４８ｐ ｉ ｎＱＦＰタイフ゜の丁Ｃパ・ンケージに適
用した例で、放熱ピン２は、アイラン１・６と一体構造
となっており、モールド樹脂１の底面より突出している
。The first embodiment, as shown in FIGS. 1(a) and (b),
In this example, the heat dissipation pin 2 is integrated with the eyelins 1 and 6, and protrudes from the bottom surface of the molded resin 1.
第２図に示すように、プリント基板８にＩＣパッケージ
を実装するときには、放熱ピン２はプリント基板８を貫
通してプリント基板８の裏側の銅はく９の面にはんだ層
７にて接合される。As shown in FIG. 2, when an IC package is mounted on a printed circuit board 8, the heat dissipation pins 2 pass through the printed circuit board 8 and are bonded to the surface of the copper foil 9 on the back side of the printed circuit board 8 using a solder layer 7. Ru.
第３図は本発明の第２の実施例のリードフレームを適用
したＤＩＰタイプのＩＣパッケージの断面図である。FIG. 3 is a sectional view of a DIP type IC package to which the lead frame of the second embodiment of the present invention is applied.
第２の実施例は、第３図に示すように、ＤＩＰタイプの
ＩＣパッケージに適用した例である。放熱ピン２が下方
に出ている為、第４図に示す放熱フィン１２付ＤＴＰの
ＩＣパッケージよりも実装面積が小さくなるという利点
がある。The second embodiment is an example in which the present invention is applied to a DIP type IC package, as shown in FIG. Since the heat dissipation pins 2 protrude downward, there is an advantage that the mounting area is smaller than that of the DTP IC package with heat dissipation fins 12 shown in FIG.
以上説明したように本発明は、熱源に接しているアイラ
ンドから裏面方向に突起する放熱ピンを出しプリント基
板実装時にグランドプレーンにはんだ付けすることによ
り、実質的に放熱板が付いたことになり、熱かにげやす
くできる効果がある。すなわち、ケースと周囲との間の
熱抵抗が低減でき、大規模回路のモノリシック化に対応
できる効果がある。As explained above, in the present invention, a heat dissipation pin that protrudes toward the back side from an island in contact with a heat source is taken out and soldered to a ground plane when mounted on a printed circuit board, so that a heat dissipation plate is essentially attached. It has the effect of making it easier to get hot. That is, the thermal resistance between the case and the surroundings can be reduced, and this has the effect of making it possible to make a large-scale circuit monolithic.
５5
第１図（ａ），（１））は本発明の第１の実施例のリー
ドフレームを適用した４８ｐ ｉ ｎＱＦＰタイプのＩ
Ｃパッケージの底面図及びＡ−Ａ’線断面図、第２図は
第１図（ａ），（ｂ）のＩＣパッケージをプリント基板
に実装した断面図、第３図は本発明の第２の実施例のリ
ードフレームを適用したＤＩＰタイプのＩＣパッケージ
の断面図、第４図は従来の放熱フィン付ＤＩＰタイプの
ＩＣパッケージの斜視図、第５図は従来の放熱フィン付
ＳＩＰタイプのＩＣパッケージの斜視図である。
１・・・モールド樹脂、２・・・放熱ピン、３・・・ピ
ン、４・・・ペレット、５・・・ボンディングワイヤ、
６・アイランド、７・・・はんだ層、８・・・プリント
基板、１２．２２・・・放熱フィン。Figures 1(a) and (1)) show a 48pin QFP type I to which the lead frame of the first embodiment of the present invention is applied.
A bottom view and a sectional view taken along the line A-A' of the C package, FIG. 2 is a sectional view of the IC package of FIGS. 1(a) and (b) mounted on a printed circuit board, and FIG. FIG. 4 is a cross-sectional view of a DIP type IC package to which the lead frame of the embodiment is applied, FIG. 4 is a perspective view of a conventional DIP type IC package with heat dissipation fins, and FIG. 5 is a cross-sectional view of a conventional SIP type IC package with heat dissipation fins. FIG. DESCRIPTION OF SYMBOLS 1... Mold resin, 2... Heat dissipation pin, 3... Pin, 4... Pellet, 5... Bonding wire,
6. Island, 7. Solder layer, 8. Printed circuit board, 12.22. Radiation fin.
Claims (1)
ランドと同一材質の放熱用ピンが突出していることを特
徴とする半導体集積回路装置のリードフレーム。 ２、第１項記載の半導体集積回路装置のリードフレーム
のアイランドにペレットを搭載しモールド樹脂封止した
ことを特徴とするＱＦＰタイプＩＣパッケージの半導体
集積回路装置。 ３、第１項記載の半導体集積回路装置のリードフレーム
のアイランドにペレットを搭載しモールド樹脂封止した
ことを特徴とするＤＩＰタイプＩＣパッケージの半導体
集積回路装置。[Scope of Claims] 1. A lead frame for a semiconductor integrated circuit device, characterized in that a heat dissipation pin made of the same material as the island projects from the back side of the island on which a pellet is mounted. 2. A semiconductor integrated circuit device in a QFP type IC package, characterized in that a pellet is mounted on the island of the lead frame of the semiconductor integrated circuit device according to item 1 and sealed with a mold resin. 3. A semiconductor integrated circuit device in a DIP type IC package, characterized in that a pellet is mounted on an island of a lead frame of the semiconductor integrated circuit device according to item 1 and sealed with a mold resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP970990A JPH03214763A (en) | 1990-01-19 | 1990-01-19 | Lead frame for semiconductor integrated circuit device and the device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP970990A JPH03214763A (en) | 1990-01-19 | 1990-01-19 | Lead frame for semiconductor integrated circuit device and the device using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03214763A true JPH03214763A (en) | 1991-09-19 |
Family
ID=11727779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP970990A Pending JPH03214763A (en) | 1990-01-19 | 1990-01-19 | Lead frame for semiconductor integrated circuit device and the device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03214763A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0650373U (en) * | 1992-06-12 | 1994-07-08 | 八重洲無線株式会社 | Laser diode mounting structure |
| US5444025A (en) * | 1991-10-23 | 1995-08-22 | Fujitsu Limited | Process for encapsulating a semiconductor package having a heat sink using a jig |
| US5563773A (en) * | 1991-11-15 | 1996-10-08 | Kabushiki Kaisha Toshiba | Semiconductor module having multiple insulation and wiring layers |
| KR19980039675A (en) * | 1996-11-28 | 1998-08-17 | 황인길 | Structure of Semiconductor Package |
| US6455348B1 (en) | 1998-03-12 | 2002-09-24 | Matsushita Electric Industrial Co., Ltd. | Lead frame, resin-molded semiconductor device, and method for manufacturing the same |
| KR100352119B1 (en) * | 1996-12-13 | 2002-12-31 | 앰코 테크놀로지 코리아 주식회사 | Structure of ball grid array semiconductor package having heatsink and fabricating method thereof |
| JP2009532912A (en) * | 2006-04-06 | 2009-09-10 | フリースケール セミコンダクター インコーポレイテッド | Molded semiconductor package with integral through-hole heat dissipation pins |
-
1990
- 1990-01-19 JP JP970990A patent/JPH03214763A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444025A (en) * | 1991-10-23 | 1995-08-22 | Fujitsu Limited | Process for encapsulating a semiconductor package having a heat sink using a jig |
| US5659200A (en) * | 1991-10-23 | 1997-08-19 | Fujitsu, Ltd. | Semiconductor device having radiator structure |
| US5563773A (en) * | 1991-11-15 | 1996-10-08 | Kabushiki Kaisha Toshiba | Semiconductor module having multiple insulation and wiring layers |
| JPH0650373U (en) * | 1992-06-12 | 1994-07-08 | 八重洲無線株式会社 | Laser diode mounting structure |
| KR19980039675A (en) * | 1996-11-28 | 1998-08-17 | 황인길 | Structure of Semiconductor Package |
| KR100352119B1 (en) * | 1996-12-13 | 2002-12-31 | 앰코 테크놀로지 코리아 주식회사 | Structure of ball grid array semiconductor package having heatsink and fabricating method thereof |
| US6455348B1 (en) | 1998-03-12 | 2002-09-24 | Matsushita Electric Industrial Co., Ltd. | Lead frame, resin-molded semiconductor device, and method for manufacturing the same |
| JP2009532912A (en) * | 2006-04-06 | 2009-09-10 | フリースケール セミコンダクター インコーポレイテッド | Molded semiconductor package with integral through-hole heat dissipation pins |
| JP2014013908A (en) * | 2006-04-06 | 2014-01-23 | Freescale Semiconductor Inc | Molded semiconductor package with integrated through hole technology (tht) heat spreader pin and method of manufacturing the same |
| US8659146B2 (en) | 2006-04-06 | 2014-02-25 | Freescale Semiconductor, Inc. | Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing |
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