KR100352119B1 - Structure of ball grid array semiconductor package having heatsink and fabricating method thereof - Google Patents
Structure of ball grid array semiconductor package having heatsink and fabricating method thereof Download PDFInfo
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- KR100352119B1 KR100352119B1 KR1019960065236A KR19960065236A KR100352119B1 KR 100352119 B1 KR100352119 B1 KR 100352119B1 KR 1019960065236 A KR1019960065236 A KR 1019960065236A KR 19960065236 A KR19960065236 A KR 19960065236A KR 100352119 B1 KR100352119 B1 KR 100352119B1
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- semiconductor chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
본 발명은 히트싱크가 부착된 볼 그리드 어레이(Ball Grid Array ; BGA) 반도체 패키지의 구조 및 제조방법에 관한 것으로, 더욱 상세하게는 열방출 특성을 향상시키기 위한 외부로 노출된 히트싱크를 반도체 칩의 저면에 부착할 수 있도록 PCB 기판상에 반도체 칩이 실장되는 부분에 개방형 관통슬롯을 형성하고, 이 관통슬롯을 통하여 히트싱크를 반도체 칩의 저면에 부착시킴으로서 열방출 특성을 향상시킨 히트싱크가 부착된 볼 그리드 어레이(Ball Grid Array ; BGA) 반도체 패키지의 구조 및 제조방법에 관한 것이다.The present invention relates to a structure and a manufacturing method of a ball grid array (BGA) semiconductor package having a heat sink, and more particularly, to an externally exposed heat sink for improving heat dissipation characteristics of a semiconductor chip. An open through slot is formed in a portion where the semiconductor chip is mounted on the PCB substrate so that it can be attached to the bottom, and the heat sink is attached to improve heat dissipation by attaching the heat sink to the bottom of the semiconductor chip through the through slot. The present invention relates to a structure and a manufacturing method of a ball grid array (BGA) semiconductor package.
최근에 다핀화의 추세에 따른 기술적 요구를 해결하기 위해서 등장한 볼 그리드 어레이(BGA)반도체 패키지는 입출력 수단으로서 반도체 패키지의 일면에 솔더볼을 융착하며 이를 입출력 수단으로 사용함으로서 많은 수의 입출력 신호를 수용할 수 있음은 물론, 그 크기도 작게 형성된 것이다.Recently, the ball grid array (BGA) semiconductor package, which has been introduced to solve the technical demands of the multi-pinning trend, is used to fuse solder balls on one surface of a semiconductor package as an input / output means and use it as an input / output means to accommodate a large number of input / output signals. Of course, the size is also formed small.
이러한 볼 그리드 어레이 반도체 패키지는 인쇄회로기판의 일면에 하나 또는 그 이상의 반도체 칩이 실장되고, 상기의 반도체 칩과 인쇄회로기판이 전기적 접속을 이루도록 와이어로 연결되며, 상기 반도체 칩이 부착된 인쇄회로기판의 대향면 표면상에 솔더볼이 어레이 형태로 융착되는 구조의 반도체 패키지이다.In the ball grid array semiconductor package, one or more semiconductor chips are mounted on one surface of a printed circuit board, and the wires are connected by wires to form an electrical connection between the semiconductor chip and the printed circuit board, and the printed circuit board to which the semiconductor chips are attached. The semiconductor package has a structure in which solder balls are fused in an array form on opposite surfaces of the substrate.
이러한 볼 그리드 어레이 반도체 패키지는 반도체 칩의 회로 동작시에 많은 열이 발생되는데, 이와같이 발생되는 열을 외부로 효과적으로 방출시키지 못하면 반도체 패키지의 성능을 저하시킴으로서 본 발명자는 반도체 칩의 회로동작시 발생되는 열을 효과적으로 방출시킬 수 있는 구조의 볼 그리드 어레이 반도체 패키지를 특허출원 제95-19582호(1995. 7. 5출원)와 특허출원 제95-25172호(1995 8. 16 출원)에서 출원한 바 있다.The ball grid array semiconductor package generates a large amount of heat during the circuit operation of the semiconductor chip. If the heat generated in this way is not effectively discharged to the outside, the performance of the semiconductor package is degraded. A ball grid array semiconductor package having a structure capable of effectively emitting the same has been filed in Patent Application Nos. 95-19582 (July 5, 1995) and Patent Application Nos. 95-25172 (filed Aug. 16, 1995).
상기의 특허출원 제95-19582호의 구조는 도 1에 도시된 바와같이 전자회로가 집적되어 있는 반도체 칩(11)과, 상기 반도체 칩(11)이 실장되는 부위에 개방형 관통슬롯(12a)이 형성되는 인쇄회로기판(12)과, 상기 반도체 칩(11)과 인쇄회로기판(12)을 전기적 연결시키는 와이어(13)와, 상기의 반도체 칩(11)을 외부환경으로 부터 부호하기 위하여 반도체 칩(11)이 실장된 인쇄회로기판(12)의 일면을 몰딩하는 수지봉지재(14)와, 상기 수지봉지재(14)가 몰딩된 인쇄회로기판(12)의 반대면에 용착되는 솔더볼(15)로 구성되며, 상기의 반도체 칩(11)은 상기 인쇄회로기판(12)상의 개방형 관통슬롯(12a) 주연부 인접 상면에 에폭시(12b)로 접착 고정되어 상기 반도체 칩(11)이 저면 일부가 개방형 관통슬롯(12a)을 통해 외부로 직접 노출되는 것이다.As shown in FIG. 1, the structure of the patent application No. 95-19582 has a semiconductor chip 11 in which an electronic circuit is integrated, and an open through slot 12a is formed in a portion where the semiconductor chip 11 is mounted. The printed circuit board 12, the wire 13 for electrically connecting the semiconductor chip 11 and the printed circuit board 12, and the semiconductor chip 11 to code the semiconductor chip 11 from an external environment. 11) a resin encapsulant 14 for molding one surface of the printed circuit board 12 mounted thereon, and a solder ball 15 welded to the opposite surface of the printed circuit board 12 in which the resin encapsulation material 14 is molded. The semiconductor chip 11 is adhesively fixed to the upper surface adjacent to the open through slot 12a on the printed circuit board 12 with an epoxy 12b so that a part of the bottom surface of the semiconductor chip 11 is open through. It is directly exposed to the outside through the slot 12a.
이러한 구조의 볼 그리드 어레이 반도체 패키지는 반도체 칩(11)의 회로동작시 발생되는 열이 반도체 칩(11)의 저면으로 상기 인쇄회로기판(12)의 개방형 관통슬롯(12a)을 통하여 외부로 직접 방출되도록 되어 있는 것으로, 이는 열 방출을 자연 대류 상태 또는 강제 공기 송풍에 의해서 방출시킴으로서 열 방출에 대한 효율성이 저하되는 단점이 발생되는 것이었다.In the ball grid array semiconductor package having such a structure, heat generated during the circuit operation of the semiconductor chip 11 is directly discharged to the outside through the open through slot 12a of the printed circuit board 12 to the bottom of the semiconductor chip 11. In this case, the disadvantage is that the efficiency of heat release is lowered by releasing heat by natural convection or forced air blowing.
또한, 특허출원 제95-25172호의 구조는 도 2에 도시된 바와같이 전자회로가 집적되어 있는 반도체 칩(21)과, 상기 반도체 칩(21)이 실장되는 부위에 개방형 관통슬롯(22a)이 형성되는 인쇄회로기판(22)과, 상기 반도체 칩(21)과 인쇄회로기판(22)을 전기적 연결시키는 와이어(23)와, 상기의 반도체 칩(21)을 외부환경으로 부터 부호하기 위하여 반도체 칩(21)이 실장된 인쇄회로기판(22)의 일면을 몰딩하는 수지봉지재(24)와, 상기 수지봉지재(24)가 몰딩된 인쇄회로기판(22)의 반대면에 용착되는 솔더볼(25)과, 상기의 인쇄회로기판(22)에 형성되는 개방형 관통슬롯(22a) 보다 큰 면적을 갖는 히트싱크(26)로 구성되며, 상기한 히트싱크(26)는 상기의 인쇄회로기판(22)에 형성되는 개방형 관통슬롯(22a) 주연부에 인접 밑면에 에폭시(22b)에 의해 접착 고정되며, 상기 반도체 칩(21)이 상기 인쇄회로기판(22)에 고정된 히트싱크(26)의 상면 중앙부에 에폭시(22c)로 접착 고정되어 상기 인쇄회로기판(22)의 개발형 관통슬롯 중앙부에 내장되는 것이다.In addition, the structure of Patent Application No. 95-25172 has a semiconductor chip 21 in which an electronic circuit is integrated as shown in FIG. 2, and an open through slot 22a is formed in a portion where the semiconductor chip 21 is mounted. The printed circuit board 22, the wire 23 for electrically connecting the semiconductor chip 21 and the printed circuit board 22, and the semiconductor chip 21 to code the semiconductor chip 21 from an external environment. A resin encapsulant 24 for molding one surface of the printed circuit board 22 on which 21 is mounted and a solder ball 25 welded to the opposite surface of the printed circuit board 22 on which the resin encapsulant 24 is molded. And a heat sink 26 having an area larger than that of the open through slot 22a formed on the printed circuit board 22, and the heat sink 26 is formed on the printed circuit board 22. The semiconductor chip 21 is adhesively fixed to the bottom surface adjacent to the open through-slot 22a formed by an epoxy 22b. Is bonded with an epoxy (22c) fixed to the upper surface center portion of the heat sink 26 is fixed to the printed circuit board 22 is embedded in the through-slot gaebalhyeong central portion of the printed circuit board (22).
이와같은 구조의 볼 그리드 어레이 반도체 패키지는 개방형 관통슬롯(22a)이 형성된 인쇄회로기판(22)의 밑면에 개방형 관통슬롯(22a) 보다 더 큰 면적을 갖는 히트싱크(26)를 접착 고정시키고, 개방형 관통슬롯(22a) 내의 중앙부 위치에서 히트싱크(26) 상면에 반도체 칩(21)을 실장시킴으로서, 반도체 칩(21)에서 발생되는 열이 열전도율이 높은 히트싱크(26)를 통하여 직접 마더보드로 효과적으로 방출될 수 있도록 한 것이다.The ball grid array semiconductor package having such a structure adhesively fixes the heat sink 26 having a larger area than the open through slot 22a to the bottom of the printed circuit board 22 on which the open through slot 22a is formed. By mounting the semiconductor chip 21 on the top surface of the heat sink 26 at the central position in the through slot 22a, heat generated in the semiconductor chip 21 can be effectively transferred directly to the motherboard through the heat sink 26 having high thermal conductivity. It can be released.
이러한 구조의 볼 그리드 어레이 반도체 패키지는 인쇄회로기판(22)의 저면에 히트싱크(26)를 부착하는 방식이므로, 이 경우 고접착력 및 고신뢰성을 요하는 에폭시(22b)를 필요로 하며, 아울러 인쇄회로기판(22)에 히트싱크(26)를 부착시 정확한 얼라이먼트(Alignment)가 요구되며, 특히 반도체 칩(21)의 크기에 따라 인쇄회로기판(22)의 개방형 관통슬롯(22a)의 크기가 달라짐으로 특정한 반도체 칩(21)에 특정한 인쇄회로기판(22)을 사용하여야 함으로서 비용이 고가인 단점이 있었던것이다.Since the ball grid array semiconductor package having such a structure attaches the heat sink 26 to the bottom surface of the printed circuit board 22, in this case, an epoxy 22b requiring high adhesion and high reliability is required. When the heat sink 26 is attached to the circuit board 22, accurate alignment is required. In particular, the size of the open through slot 22a of the printed circuit board 22 varies according to the size of the semiconductor chip 21. As a specific printed circuit board 22 to be used for a specific semiconductor chip 21 has a disadvantage that the cost is expensive.
본 발명의 목적은 이와같은 문제점을 해결하기 위하여 발명된 것으로서, 인쇄회로기판에 개방형 관통슬롯을 형성하고, 이 관통슬롯을 통하여 반도체 칩의 저면이 외부로 노출되는 볼 그리드 어레이 반도체 패키지를 구성한 후, 상기의 관통슬롯을 통해 히트싱크의 상면을 반도체 칩의 저면에 부착시킴으로서, 반도체 칩에서 발생기는 열이 열전도율이 높은 히트싱크를 통하여 직접 마더보드로 효과적으로 방출될 수 있도록 한 히트싱크가 부착된 볼 그리드 어레이(Ball Grid Array ; BGA) 반도체 패키지의 구조 및 제조방법를 제공함에 있다.An object of the present invention has been invented to solve such a problem, after forming an open through slot on a printed circuit board, and through the through slot to form a ball grid array semiconductor package that the bottom surface of the semiconductor chip is exposed to the outside, By attaching the top surface of the heat sink to the bottom surface of the semiconductor chip through the through slot, the generator in the semiconductor chip has a heat sink-attached ball grid so that heat can be effectively discharged directly to the motherboard through the heat sink having high thermal conductivity. To provide a structure and a manufacturing method of a ball grid array (BGA) semiconductor package.
도 1은 종래의 볼 그리드 어레이 반도체 패키지를 도시한 단면도1 is a cross-sectional view showing a conventional ball grid array semiconductor package.
도 2는 종래의 히트싱크가 부착된 볼 그리드 어레이 반도체 패키지의 단면도2 is a cross-sectional view of a ball grid array semiconductor package with a conventional heat sink.
도 3은 본 발명에 따른 볼 그리드 어레이 반도체 패키지를 나타낸 단면도3 is a cross-sectional view showing a ball grid array semiconductor package according to the present invention.
도 4는 본 발명에 따른 볼 그리드 어레이 반도체 패키지를 마더보드에 실장한 상태를 나타낸 단면도4 is a cross-sectional view showing a state in which a ball grid array semiconductor package is mounted on a motherboard according to the present invention;
도 5의 (가) 내지 (라)는 본 발명의 볼 그리드 어레이 반도체 패키지에 부착되는 히트싱크의 여러 형상을 나타낸 사시도5A to 5D are perspective views showing various shapes of a heat sink attached to a ball grid array semiconductor package according to the present invention.
도 6의 (가)(나)는 본 발명의 볼 그리드 어레이 반도체 패키지에 부착되는 히트싱크의 단면을 도시한 도면6A and 6B are cross-sectional views of a heat sink attached to a ball grid array semiconductor package of the present invention.
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
31 - 반도체 칩 32 - 인쇄회로기판31-Semiconductor Chip 32-Printed Circuit Board
32a - 개방형 관통슬롯 33 - 와이어32a-open through slot 33-wire
34 - 수지봉지재 35 - 솔더볼34-Resin Encapsulant 35-Solder Ball
36 - 히트싱크 37 - 마더보드36-Heatsink 37-Motherboard
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 볼 그리드 어레이 반도체 패키지의 구성을 나타낸 단면도로서, 그 구조는 전자회로가 집적되어 있는 반도체 칩(31)과, 상기 반도체 칩(31)이 실장되는 부위에 개방형 관통슬롯(32a)이 형성되는 인쇄회로기판(32)과, 상기 반도체 칩(31)과 인쇄회로기판(32)을 전기적으로 연결시키는 와이어(33)와, 상기의 반도체 칩(31)을 외부환경으로 부터 부호하기 위하여 반도체 칩(31)이 실장된 인쇄회로기판(32)의 일면을 몰딩하는 수지봉지재(34)와, 상기 수지봉지재(34)가 몰딩된 인쇄회로기판(32)의 반대면에 용착되는 솔더볼(35)과, 상기 반도체 칩(31)의 열을 효과적으로 외부로 방출시키는 히트싱크(36)로 구성되며, 상기의 반도체 칩(31)은 상기 인쇄회로기판(32)상의 개방형 관통슬롯(32a) 주연부 인접 상면에 에폭시(32b)로 접착 고정되어 상기 반도체 칩(31)의 저면 일부가 개방형 관통슬롯(32a)을 통해 외부로 직접 노출되고, 상기한 히트싱크(36)는 상기의 인쇄회로기판(32)에 형성되는 개방형 관통슬롯(32a)을 통해 저면 일부가 노출된 반도체 칩(31)에 히트싱크(36)의 상면 중앙부가 에폭시(32c)에 의해 접착 고정되어 있는 것이다.3 is a cross-sectional view showing the configuration of a ball grid array semiconductor package according to the present invention, the structure of which is a semiconductor chip 31 in which an electronic circuit is integrated, and an open through slot in a portion where the semiconductor chip 31 is mounted. A printed circuit board 32 having 32a formed thereon, a wire 33 electrically connecting the semiconductor chip 31 and the printed circuit board 32 to the printed circuit board 32, and the semiconductor chip 31 are coded from an external environment. To this end, the resin encapsulant 34 molding one surface of the printed circuit board 32 on which the semiconductor chip 31 is mounted and the opposite side of the printed circuit board 32 on which the resin encapsulant 34 is molded are welded. And a heat sink 36 for effectively dissipating heat from the semiconductor chip 31 to the outside, wherein the semiconductor chip 31 has an open through slot on the printed circuit board 32. 32a) The semiconductor chip 31 is adhesively fixed to the upper surface adjacent to the periphery by epoxy 32b. A portion of the bottom of the bottom surface is directly exposed to the outside through the open through slot (32a), the heat sink 36 is a portion of the bottom through the open through slot (32a) formed on the printed circuit board (32). The center portion of the upper surface of the heat sink 36 is adhesively fixed to the semiconductor chip 31 by the epoxy 32c.
도 4는 이와같은 구성을 갖는 본 발명의 볼 그리드 어레이 반도체 패키지를 마더보드에 실장시킨 상태를 도시한 도면으로서, 상기의 히트싱크(36)가 마더보드(37)에 직접 부착되도록 함으로서 반도체 칩(31)에서 발생되는 열의 방출효과를 극대화 시킬 수 있는 것이다 즉, 상기 히트싱크(36)는 반도체 칩(31)의 저면에 부착되어 솔더볼(35)이 용착되는 인쇄회로기판(32) 표면으로 돌출되며, 반도체 칩(31)에서 발생되는 열이 열전도율이 높은 히트싱크(36)를 통하여 마더보드(37)로 직접 방출되도록 함으로서, 전달 경로가 단축되고, 열 전달이 효율적으로 이루어짐으로서 열방출 효과를 극대화 할 수 있는 것이다.4 is a view showing a state in which the ball grid array semiconductor package of the present invention having such a configuration is mounted on a motherboard, wherein the heat sink 36 is directly attached to the motherboard 37 so that the semiconductor chip ( The heat sink 36 may be attached to the bottom surface of the semiconductor chip 31 to protrude to the surface of the printed circuit board 32 on which the solder balls 35 are welded. In addition, the heat generated from the semiconductor chip 31 is directly discharged to the motherboard 37 through the heat sink 36 having high thermal conductivity, thereby shortening the transfer path and maximizing the heat dissipation effect by efficient heat transfer. You can do it.
또한, 도 5의 (가) 내지 (라)는 본 발명의 볼 그리드 어레이 반도체 패키지에 사용되는 히트싱크(36)의 여러 실시예를 도시한 것으로서, 상기 히트싱크(36)의 재질은 열 전도율이 양호한 구리, 구리합금, Al 등의 금속재 소재가 사용되며, 이러한 히트싱크(36)는 밑판(36a)과, 이 밑판(36a)의 중앙부위가 돌출된 돌출부(36b)를 갖는 구조로 되어 있는 것이다.5A to 5D illustrate various embodiments of the heat sink 36 used in the ball grid array semiconductor package of the present invention, wherein the heat sink 36 has a material having thermal conductivity. Metallic materials such as copper, copper alloy, and Al are used, and the heat sink 36 has a structure having a base plate 36a and a protrusion 36b on which a central portion of the base plate 36a protrudes. .
상기 히트싱크(36)의 형상으로 바람직한 예로는 원형, 사각형, 타원형 및 이들이 조합된 형상으로 열 전달에 용이한 표면적이 넓은 형상으로 형성되는 것으로, 이러한 히트싱크(36)의 밑판(36a)은 인쇄회로기판(32)의 관통슬롯(32a) 보다 큰 면적을 갖고, 히트싱크(36)의 돌출부(36b)는 인쇄회로기판(32)의 관통슬롯(32a) 보다 작은 면적을 갖는 것이다.Preferred examples of the shape of the heat sink 36 are circular, square, oval, and combinations thereof. The heat sink 36 is formed in a shape having a wide surface area for easy heat transfer. The bottom plate 36a of the heat sink 36 is printed. It has an area larger than the through slot 32a of the circuit board 32, and the protrusion 36b of the heat sink 36 has an area smaller than the through slot 32a of the printed circuit board 32.
또한, 상기 히트싱크(36)의 상면 즉, 돌출부(36b)의 상면에는 에폭시(32c)를 매개체로. 반도체 칩(31)과의 접착강도를 높이기 위하여 그 표면을 거칠게 하거나, CuO와 같은 흑색 또는 Cu2O와 같은 갈색 산화물로 처리하고, 상기 히트싱크(36)의 밑면 즉, 밑판(36a)의 저면에는 패키지를 마더보드(37)에 실장시 히트싱크(36)가 마더보드(37)와 직접 솔더링이 용이하도록 하기 위하여 솔더(Solder), 팔라디움(Pd), 니켈(Ni) 등으로 플레이팅 하거나, 또는 베어 카퍼(Bare Copper)를 사용하되, 이 경우 공정 중 발생되는 산화를 방지하기 위하여 오르개니크(Organic ; 유기체의, 탄소를 함유한) 코팅을 하는 것이 바람직하다.In addition, the upper surface of the heat sink 36, that is, the upper surface of the protrusion 36b, is epoxy 32c as a medium. In order to increase the adhesion strength with the semiconductor chip 31, the surface is roughened or treated with black oxide such as CuO or brown oxide such as Cu 2 O, and the bottom surface of the heat sink 36, that is, the bottom surface of the base plate 36a. When the package is mounted on the motherboard 37, the heat sink 36 is plated with solder, palladium (Pd), nickel (Ni), etc. in order to facilitate soldering directly with the motherboard 37, Alternatively, bare copper may be used, in which case it is preferable to apply an organic coating (organic, carbon-containing) to prevent oxidation during the process.
그리고, 상기 히트싱크(36)의 돌출부(36b) 두께는 인쇄회로기판(32)의 두께와 유사하고, 밑판(36a)의 두께는 인쇄회로기판(32)에 융착되는 솔더볼(35)의 높이보다 낮게 형성하되, 본 발명의 '볼 그리드 어레이 반도체 패키지를 마더보드(37)에 실장시 밑판(36a)의 저면이 마더보드(37)의 상면에 접촉될 수 있는 높이로 하는 것이 가장 바람직하다. 즉, 본 발명의 볼 그리드 어레이 반도체 패키지가 마더보드(37)에 실장될 때 솔더볼(35)이 죠인트되는 높이를 넘지 않도록 하여야 한다.The thickness of the protrusion 36b of the heat sink 36 is similar to that of the printed circuit board 32, and the thickness of the bottom plate 36a is greater than the height of the solder ball 35 fused to the printed circuit board 32. It is most preferable to form a low level so that the bottom surface of the base plate 36a may be in contact with the top surface of the motherboard 37 when the ball grid array semiconductor package of the present invention is mounted on the motherboard 37. That is, when the ball grid array semiconductor package of the present invention is mounted on the motherboard 37, the solder ball 35 should not exceed the height of the joint.
또한, 도 6의 (가)(나)에 도시된 바와같이 밑판(36a)과 돌출부(36b)로 이루어지는 히트싱크(36)는 그 내부가 채워지거나, 또는 돌출부(36b)의 저면에 공간이 형성되도록 제작가능한 것이다.In addition, as shown in (a) and (b) of FIG. 6, the heat sink 36 including the bottom plate 36a and the protrusion 36b may be filled with an interior thereof, or a space may be formed at the bottom of the protrusion 36b. It is possible to manufacture.
상기와 같이 구성되는 본 발명의 볼 그리드 어레이 반도체 패키지의 제조 방법은 집전회로가 내장된 반도체 칩(31)이 실장되는 부위에 개방형 관통슬롯(32a)이 형성되는 인쇄회로기판(32)을 제작하는 단계와, 상기 인쇄회로기판(32)의 개방형 관통슬롯(32a) 주연부 인접 상면에 에폭시(32b)로 도포하여 반도체 칩(31)을 부착하는 단체와, 상기의 반도체 칩(31)과 인쇄회로기판(32)을 전기적 연결시키기 위하여 와이어(33)로 본딩하는 단계와, 상기의 반도체 칩(31)을 외부환경으로 부터 부호하기 위하여 반도체 칩(31)이 부착되는 인쇄회로기판(32)의 일면을 수지봉지재로 몰딩하는 단계와, 상기 수지봉지재(34)가 몰딩되는 인쇄회로기판(32)의 반대면에 솔더볼(35)을 융착시키는 단계와, 인쇄회로기판(32)의 관통슬롯(32a)을 통해 외부로 노출되는 반도체 칩(31)의 저면에 에폭시(32c)를 도포한 후, 히트싱크(36)를 인쇄회로기판(32)의 관통슬롯(32a)을 통하여 반도체 칩(31)의 저면에 부착시키는 단계로 이루어지는 것이다.The manufacturing method of the ball grid array semiconductor package of the present invention configured as described above is to produce a printed circuit board 32 in which an open through slot 32a is formed at a portion where a semiconductor chip 31 having a current collector circuit is mounted. And applying the epoxy chip 32 to the upper surface adjacent to the open through slot 32a of the printed circuit board 32 with an epoxy 32b to attach the semiconductor chip 31, and the semiconductor chip 31 and the printed circuit board. Bonding the wires 33 to electrical connections 32, and attaching one surface of the printed circuit board 32 to which the semiconductor chips 31 are attached to code the semiconductor chips 31 from an external environment. Molding with a resin encapsulation material, fusing the solder balls 35 to opposite sides of the printed circuit board 32 on which the resin encapsulation material 34 is molded, and through slots 32a of the printed circuit board 32. On the bottom of the semiconductor chip 31 exposed to the outside through After applying the foxy 32c, the heat sink 36 is attached to the bottom surface of the semiconductor chip 31 through the through slot 32a of the printed circuit board 32.
이와같이 이루어지는 본 발명의 제조공정에 있어서, 상기 반도체 칩(31)의 저면에 히트싱크(S6)를 부착하기 위해서는 인쇄회로기판(32)의 관통슬롯(32a)을 통하여 노출되는 반도체 칩(31)의 저면에 에폭시(32c)를 도포하여 히트싱크(36)를 가압하면서 부착하는 것이다. 이때, 본 발명의 볼 그리드 어레이 반도체 패키지를 마더보드(37)에 실장시 상기 히트싱크(36)의 밑판(36a)이 마더보드(37)에 접촉될 수 있는 높이로 부착하는 것으로, 이러한 높이의 조절은 반도체 칩(31)의 저면에 도포되는 에폭시(32c) ; 유동성이 있음)에 의해서 조절되는 것이다. 즉, 히트싱크(36)를 과다하게 가압하면 에폭시(32c)가 히트싱크(36)의 돌출부(36b)와 인쇄회로기판(32)의 관통슬롯(32a)의 사이로 많이 흘러나와 밑판(36a)의 높이를 낮게할 수 있고, 히트싱크(36)를 약하게 누르면 에폭시(32c)가 히트싱크(36)의 돌출부(36b)와 인쇄회로기판(32)의 관통슬롯(32a)의 사이로 적게 흘러나와 밑판(36a)의 높이를 높게 할 수 있는 것이다. 이와같이 히트싱크(36)를 반도체 칩(31)의 저면에 부착할때 히트싱크(36)를 가압하는 힘에 의하여 히트싱크(36)의 밑판(36a)의 높이를 조절할 수 있는 것이다.In the manufacturing process of the present invention as described above, in order to attach the heat sink S6 to the bottom surface of the semiconductor chip 31, the semiconductor chip 31 exposed through the through slot 32a of the printed circuit board 32. Epoxy 32c is applied to the bottom surface to attach the heat sink 36 while pressing. At this time, when the ball grid array semiconductor package of the present invention is mounted on the motherboard 37, the bottom plate 36a of the heat sink 36 is attached to a height that can be in contact with the motherboard 37, Adjustment is carried out by the epoxy 32c applied to the bottom of the semiconductor chip 31; Fluidity). That is, when the heat sink 36 is excessively pressurized, the epoxy 32c flows out a lot between the protrusion 36b of the heat sink 36 and the through slot 32a of the printed circuit board 32, so that It is possible to lower the height and press the heat sink 36 lightly so that the epoxy 32c flows less between the protrusion 36b of the heat sink 36 and the through slot 32a of the printed circuit board 32. The height of 36a) can be increased. As such, when the heat sink 36 is attached to the bottom surface of the semiconductor chip 31, the height of the bottom plate 36a of the heat sink 36 may be adjusted by a force for pressing the heat sink 36.
상기와 같은 본 발명의 볼 그리드 어레이 반도체 패키지는 반도체 칩(31)의 크기에 관계없이 인쇄회로기판(32)의 관통형 관통슬롯(32a)을 일정한 크기로 형성하고, 이 관통슬롯(32a)에 알맞는 크기의 히트싱크(36)를 선택적으로 사용할 수 있음으로서 반도체 칩(31)의 크기와 무관하게 범용적으로 적용가능한 것이다.The ball grid array semiconductor package of the present invention as described above forms a through type through slot 32a of the printed circuit board 32 to a predetermined size regardless of the size of the semiconductor chip 31, By appropriately using the heat sink 36 having a suitable size, it is universally applicable regardless of the size of the semiconductor chip 31.
이상의 설명에서와 같이 본 발명에 따른 히트싱크가 부착된 볼 그리드 어레이 반도체 패키지는 반도체 칩에서 방출되는 열이 열전도율이 높은 히트싱크를 통해 직접 마더보드로 효율적으로 방출될 수 있는 고열방출특성을 가져 반도체 패키지의 성능을 향상시키고, 신뢰성을 확보할 수 있는 효과가 있다.As described above, the ball grid array semiconductor package to which the heat sink is attached according to the present invention has a high heat dissipation property in which heat emitted from a semiconductor chip can be efficiently discharged directly to the motherboard through a heat sink having high thermal conductivity. The performance of the package can be improved and reliability can be ensured.
Claims (9)
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| KR1019960065236A KR100352119B1 (en) | 1996-12-13 | 1996-12-13 | Structure of ball grid array semiconductor package having heatsink and fabricating method thereof |
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| KR1019960065236A KR100352119B1 (en) | 1996-12-13 | 1996-12-13 | Structure of ball grid array semiconductor package having heatsink and fabricating method thereof |
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| KR100352119B1 true KR100352119B1 (en) | 2002-12-31 |
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| KR20210017857A (en) * | 2019-08-09 | 2021-02-17 | 삼성전기주식회사 | Electronic component module and manufacturing method thereof |
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| KR100649878B1 (en) * | 2000-12-29 | 2006-11-24 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| KR100471413B1 (en) * | 2002-03-27 | 2005-02-21 | 주식회사 칩팩코리아 | Tape ball grid array package |
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| JPH03256351A (en) * | 1990-03-06 | 1991-11-15 | Nec Corp | Semiconductor device |
| JPH05211247A (en) * | 1992-01-30 | 1993-08-20 | Nec Corp | Semiconductor device |
| US5583377A (en) * | 1992-07-15 | 1996-12-10 | Motorola, Inc. | Pad array semiconductor device having a heat sink with die receiving cavity |
| KR950021441A (en) * | 1993-12-09 | 1995-07-26 | 황인길 | Semiconductor BGA (BALL GRID ARRAY) Package |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20210017857A (en) * | 2019-08-09 | 2021-02-17 | 삼성전기주식회사 | Electronic component module and manufacturing method thereof |
| US11191150B2 (en) | 2019-08-09 | 2021-11-30 | Samsung Electro-Mechanics Co., Ltd. | Electronic component module and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980046821A (en) | 1998-09-15 |
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